WO2020107664A1 - 阵列基板和显示面板 - Google Patents
阵列基板和显示面板 Download PDFInfo
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- WO2020107664A1 WO2020107664A1 PCT/CN2019/071072 CN2019071072W WO2020107664A1 WO 2020107664 A1 WO2020107664 A1 WO 2020107664A1 CN 2019071072 W CN2019071072 W CN 2019071072W WO 2020107664 A1 WO2020107664 A1 WO 2020107664A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
Definitions
- the present application relates to an array substrate and a display panel.
- GOA gate on array
- the drive circuit generates a clock signal and sends it to the gate drive circuit.
- the gate drive circuit passes the clock
- the signal line provides a clock signal to each gate drive circuit for line scanning.
- the purpose of the present application is to provide an array substrate and a display panel.
- first electrode layer Forming a first electrode layer on the second passivation layer, the first electrode layer covering part of the first conductive layer, the first passivation layer, the second conductive layer and the second passivation layer;
- the first conductive layer includes multiple first traces, and the second conductive layer includes multiple second traces, wherein each first trace is connected to multiple second traces through corresponding traces of the first electrode layer;
- the projection of each first trace on the first substrate is inside the projection of the non-conductive material layer on the first substrate.
- the non-conductive material layer includes: a color resist material layer formed on the first electrode layer, the color resist material layer covering part of the second passivation layer; and a liquid crystal layer formed on the color resist material layer.
- the non-conductive material layer further includes:
- the projection of each first trace on the first substrate is inside the projection of the color resist material layer on the first substrate.
- the projection of each first trace on the first substrate is inside the projection of the resin material layer on the first substrate.
- the first trace extends in the first direction
- the second trace extends in the second direction crossing the first direction
- a target area is provided on each first trace, the target area includes a cross-over area formed by the first trace and each second trace, and the target area is used to reduce the first trace and the second trace.
- the target area further includes a cross-connected area of the first trace and the second trace.
- the first passivation layer covers part of the first substrate in the target area.
- the liquid crystal layer has a dielectric coefficient.
- the dielectric coefficient includes the dielectric coefficient of the parallel vector and the dielectric coefficient of the vertical vector.
- a display panel includes a color filter substrate, a driving circuit and an array substrate;
- the array substrate includes:
- first electrode layer Forming a first electrode layer on the second passivation layer, the first electrode layer covering part of the first conductive layer, the first passivation layer, the second conductive layer and the second passivation layer;
- the first conductive layer includes multiple first traces, and the second conductive layer includes multiple second traces, wherein each first trace is connected to multiple second traces through corresponding traces of the first electrode layer;
- the projection of each first trace on the first substrate is inside the projection of the non-conductive material layer on the first substrate.
- the non-conductive material layer includes: a color resist material layer formed on the first electrode layer, the color resist material layer covering part of the second passivation layer; and a liquid crystal layer formed on the color resist material layer.
- the non-conductive material layer further includes:
- the projection of each first trace on the first substrate is inside the projection of the color resist material layer on the first substrate.
- the projection of each first trace on the first substrate is inside the projection of the color resist material layer on the first substrate.
- FIG. 2 is a schematic diagram of a capacitive load circuit in an exemplary technology
- FIG. 3 is a schematic structural diagram of an array substrate in an embodiment
- FIG. 5 is a schematic structural diagram of an array substrate in yet another embodiment
- FIG. 6 is a cross-sectional view of an array substrate in still another embodiment
- FIG. 7 is a schematic structural diagram of an array substrate in still another embodiment
- FIG. 8 is a schematic structural view of an array substrate in one embodiment
- FIG. 10 is a cross-sectional view of an array substrate in still another embodiment.
- a display panel with gate array driving using GOA technology includes a color filter substrate 10, an array substrate 20, a driving circuit 30, and a gate driving circuit 40.
- the gate driving circuit 40 is used to make On the array substrate 20, a driving chip made of an external silicon chip is replaced to drive on and off of the thin film transistor. Because the GOA technology can directly set the gate drive circuit 40 around the display area of the display panel, the manufacturing process is simplified, the integration degree of the display panel is improved, and the display panel can realize an ultra-thin design.
- the capacitive load circuit is shown in Figure 2.
- the clock voltage signal 100 sent by the drive circuit is sent to the active switch through the signal line.
- the signal resistance 200 generated by the signal line 200, the signal capacitor 300 and the parallel connection A parallel capacitor 400 between the control terminal b of the active switch and the first terminal a of the active switch 500.
- the signal resistor 200, the signal capacitor 300 and the parallel capacitor 400 all fall on the first terminal a and the control terminal b.
- the circuit load is too heavy, which affects the clock signal transmission effect.
- the array substrate includes: a first substrate 1; a first conductive layer 2 formed on the first substrate 1; A first passivation layer 3 formed on the first conductive layer 2, and the first passivation layer 3 covers part of the first substrate 1; a second conductive layer 4 formed on the first passivation layer 3; formed on the second The second passivation layer 5 on the conductive layer 4, and the second passivation layer 5 covers part of the first passivation layer 3; the first electrode layer 6 formed on the second passivation layer 5 is covered with the first electrode layer 6 Part of the first conductive layer 2, the first passivation layer 3, the second conductive layer 4 and the second passivation layer 5; a non-conductive material layer 7 formed on the first electrode layer 6, the non-conductive material layer 7 covers part of the Two passivation layers 5; a liquid crystal layer 8 formed on the non-conductive material layer 7, the liquid crystal layer 8 covering part of the second passivation layer 5;
- a non-conductive material layer 7 is provided on the first electrode layer 6 so that part or all of the area where the first trace 21 is opposed to the second electrode layer 9 is performed through the non-conductive material layer 7 Isolation, that is, minimizing or avoiding the relative area between the two layers of metal, thereby reducing the capacitance between the first conductive layer 2 and the second electrode layer 9, reducing the capacitance between the plates, and reducing the load of the gate drive circuit
- the signal attenuation caused by the transmission of small signals through the clock signal line improves the quality and reliability of signal transmission.
- the non-conductive material layer 7 may include resin material and/or color resist material.
- the projection of each first trace 21 on the first substrate 1 is inside the projection of the non-conductive material layer 7 on the first substrate 1.
- the projection of the first trace 21 on the non-conductive material layer 7 is located in the non-conductive material coverage area of the non-conductive material layer 7 to ensure that each first trace 21 and its corresponding second electrode layer 9
- the non-conductive material layer 7 can be used for isolation to reduce the capacitance between the plates.
- the array substrate includes: a first substrate 1; a first conductive layer 2 formed on the first substrate 1; a first conductive layer 2 formed on the first conductive layer 2 A passivation layer 3, and the first passivation layer 3 covers part of the first substrate 1; the second conductive layer 4 formed on the first passivation layer 3; the second passivation layer formed on the second conductive layer 4 5, and the second passivation layer 5 covers part of the first passivation layer 3; formed with the first electrode layer 6 on the second passivation layer 5, the first electrode layer 6 covers part of the first conductive layer 2, the first passivation Color layer 3, second conductive layer 4 and second passivation layer 5; a color resist material layer 71 formed on the first electrode layer 6, the color resist material layer 71 covers part of the second passivation layer 5; formed in the color resist Liquid crystal layer 8 of material layer 71, liquid crystal layer 8 covering part of second passivation layer 5; second electrode layer 9 formed on liquid crystal layer 8; second substrate
- the color resist material layer 71 is provided on the first electrode layer 6 so that part or all of the area where the first trace 21 is opposed to the second electrode layer 9 passes through the color resist material layer 71 Isolation, that is, minimizing or avoiding the relative relative area between the two layers of metal, thereby reducing the capacitance between the first conductive layer 2 and the second electrode layer 9 and reducing the capacitance between the plates. Therefore, the load of the gate driving circuit is reduced to reduce the signal attenuation during the transmission of the signal via the clock signal line, and the signal transmission quality and reliability are improved.
- the array substrate includes: a first substrate 1; a first conductive layer 2 formed on the first substrate 1; a first conductive layer 2 formed on the first conductive layer 2 A passivation layer 3, and the first passivation layer 3 covers part of the first substrate 1; the second conductive layer 4 formed on the first passivation layer 3; the second passivation layer formed on the second conductive layer 4 5, and the second passivation layer 5 covers part of the first passivation layer 3; formed with the first electrode layer 6 on the second passivation layer 5, the first electrode layer 6 covers part of the first conductive layer 2, the first passivation Color layer 3, second conductive layer 4 and second passivation layer 5; a color resist material layer 71 formed on the first electrode layer 6, the color resist material layer 71 covers part of the second passivation layer 5; formed in the color resist The resin material layer 72 on the material layer 71; the liquid crystal layer 9 formed on the resin material layer 72, and the liquid crystal layer 9 covers part of the second passivation
- the first trace 21 and the second electrode layer 91 by providing a color resist material layer 71 on the first electrode layer 6 and a resin material layer 72 on the color resist material layer 71, the first trace 21 and the second electrode layer 91
- the opposite partial area or all areas are separated by the color resist material layer 71 and the resin material layer 72, that is, the relative relative area between the two metal layers is minimized or avoided, thereby reducing the first conductive layer 2 and the second electrode layer 91
- the capacitance between the plates reduces the capacitance between the plates and the load of the gate drive circuit to reduce the signal attenuation caused by the signal transmission through the clock signal line and improve the quality and reliability of signal transmission.
- the projection of each first trace 21 on the first substrate 1 is inside the projection of the color resist material layer 71 on the first substrate 1.
- the projection of the first trace 21 on the color resist material layer 71 is located in the RGB color resist material coverage area of the color resist material layer 71 to ensure that each first trace 21 and its corresponding second electrode layer 9 Both can be isolated by the color resist material layer 71 to reduce the capacitance between the plates.
- the first trace 21 extends in the first direction
- the second trace 41 extends in the second direction crossing the first direction.
- each second trace 41 is connected to the corresponding first trace 21, spans the remaining first traces 21 on the second direction side of the corresponding first trace 21, and extends in the second direction.
- each first trace 21 is provided with a target area 92, and the target area 92 includes a cross-over area formed by the first trace 21 and each second trace 41 921, the target area 92 is an area for reducing the capacitance between the first trace 21 and the second electrode layer 9.
- the target area 92 of the first trace 21 refers to an area for reducing the capacitance between the first trace 21 and the second electrode layer 9.
- the first trace 21 in the target area 92 may be in a hollow state.
- the first trace 21 in the target area 92 may also be provided with a groove, and the groove is filled with a non-conductive material to reduce the capacitance between the plates. That is, the capacitance C1 formed between the portion of the first trace 21 (which may be a solid metal, a hollowed portion on the first trace 21, etc.) and the pair of second electrode layers 9 in the target area 92 is smaller than the target The capacitance formed between the first trace 21 and the second electrode layer 9 outside this region.
- the specific implementation is not limited to the two examples given here.
- the cross-over area 921 refers to a portion on the first trace 21 that does not connect with the second trace 41.
- a target area 92 is provided in the cross-over area of the first trace 21 and each second trace 41 to effectively reduce the capacitance value of the gate drive circuit trace, reduce the gate drive circuit trace load and reduce Tablet power.
- the target area 92 further includes a cross connection area 922 of the first trace 21 and the second trace 41.
- the cross-connected area 922 refers to an area where the projection of the second trace 41 on the correspondingly connected first trace 21 has an intersection.
- Cross-connecting regions 921 on the first trace 21 with the second trace 41 are filled with non-conductive materials such as holes or filled with resin to reduce capacitance, thereby reducing the circuit load of the gate drive circuit.
- a conductive bridge hole 93 is formed on the first conductive layer, and the first electrode layer 9 covers the first conductive layer 2 and the second conductive On layer 3.
- the conductive bridge hole 93 connects the first trace 21 on the first conductive layer 2 and the second trace 41 on the second conductive layer 4 to reduce the capacitance value of the gate driving circuit.
- the first passivation layer 3 covers part of the first substrate 1 in the target area 92.
- the first passivation layer 3 covers a part of the first substrate 1 in the target area 92, that is, a hole is dug in the first trace 21, and there is no conductive material at the hole.
- the first passivation layer 3 fills this part of the area, and The contact of the first substrate 1 reduces the capacitance of the panel, thereby reducing the capacitance of the gate drive circuit wiring.
- the liquid crystal layer 8 has a dielectric coefficient.
- the dielectric coefficient includes the dielectric coefficient of the parallel vector and the dielectric coefficient of the vertical vector.
- a first-type conductive bridge hole is formed on each first trace 21, and at the same time, the first electrode layer 6 is covered on the first conductive layer 2, and a voltage signal is transmitted to the first electrode layer 6 and the second through the conductive bridge hole The electrode layer 9, so that the dielectric coefficient of the liquid crystal layer 8 tends to be the dielectric coefficient of the parallel vector (for example: the inclination of the dielectric coefficient direction is controlled by the magnitude of the voltage signal), which effectively reduces the gate drive circuit wiring Of the capacitor.
- the clock signal generated by the driving circuit 30 is given to the first trace 21 and the second trace 41 on the array substrate 20 to drive the thin film transistor
- a target area 92 is set on the first trace 21 corresponding to the second trace 41, so that the projection of the second trace 41 on the first trace 21 falls within the target area 92, that is, the second trace 41 is connected to it
- the capacitance at the intersection of the first traces 21 is minimized, thereby reducing the capacitance of the gate drive circuit 40 traces and reducing the tablet power.
- An array substrate manufacturing method includes:
- the non-conductive material layer includes a color resist material layer formed on the first electrode layer 6, and the array substrate manufacturing method includes:
- the non-conductive material layer further includes a resin material layer disposed on the color resist material layer
- the array substrate manufacturing method includes: providing a first substrate; forming a first conductive layer on the first substrate; Forming a first passivation layer on the conductive layer, and making the first passivation layer cover part of the first substrate; forming a second conductive layer on the first passivation layer; forming a second passivation layer on the second conductive layer, and Making the second passivation layer cover part of the first passivation layer; forming the first electrode layer on the second passivation layer, and making the first electrode layer cover part of the first conductive layer, the first passivation layer, and the second conductive layer And a second passivation layer; forming a color resist material layer on the first electrode layer, the color resist material layer covering part of the second passivation layer; forming a resin material layer on the color resist material layer; forming a liquid crystal layer on the resin material layer , The liquid crystal layer covers part of the second passivation
- the display panel may include a liquid crystal panel, the liquid crystal panel may include a switch array substrate, the color filter layer substrate and the liquid crystal layer 8 formed between the two substrates, the display panel may also be an OLED ( Organic Light-Emitting Diode (organic electric laser display) panel or QLED (Quantum Dot Light Emitting Diodes) panel.
- OLED Organic Light-Emitting Diode (organic electric laser display) panel
- QLED Quadantum Dot Light Emitting Diodes
Abstract
Description
Claims (20)
- 一种阵列基板,包括:第一基板;形成于所述第一基板上的第一导电层;形成于所述第一导电层上的第一钝化层,且所述第一钝化层覆盖部分所述第一基板;形成于所述第一钝化层上的第二导电层;形成于所述第二导电层上的第二钝化层,且所述第二钝化层覆盖部分所述第一钝化层;形成与所述第二钝化层上的第一电极层,所述第一电极层覆盖部分所述第一导电层、所述第一钝化层、所述第二导电层和所述第二钝化层;形成于所述第一电极层上的非导电材料层,所述非导电材料层覆盖部分所述第二钝化层;形成于所述非导电材料层的液晶层,所述液晶层覆盖部分所述第二钝化层;形成于所述液晶层上的第二电极层;形成于所述第二电极层上的第二基板;所述第一导电层包括多条第一走线,所述第二导电层包括多条第二走线,其中,各所述第一走线通过对应的第一电极层的走线连接多个所述第二走线;所述非导电材料层在所述第一基板上的投影与所述第一走线在所述第一基板上的投影存在重叠区域。
- 根据权利要求1所述的阵列基板,其中,各所述第一走线在所述第一基板上的投影位于所述非导电材料层在所述第一基板上的投影里面。
- 根据权利要求1所述的阵列基板,其中,所述非导电材料层包括:形成于所述第一电极层上的色阻材料层,所述色阻材料层覆盖部分所述第二钝化层;所述液晶层形成于所述色阻材料层上。
- 根据权利要求3所述的阵列基板,其中,所述非导电材料层还包括:形成于所述色阻材料层上的树脂材料层;所述液晶层形成于所述树脂材料层上。
- 根据权利要求3所述的阵列基板,其中,各所述第一走线在所述第一基板上的投影位于所述色阻材料层在所述第一基板上的投影里面。
- 根据权利要求4所述的阵列基板,其中,各所述第一走线在所述第一基板上的投影位于所述色阻材料层在所述第一基板上的投影里面。
- 根据权利要求6所述的阵列基板,其中,各所述第一走线在所述第一基板上的投影位于所述色阻材料层在所述第一基板上的投影里面。
- 根据权利要求1所述的阵列基板,其中,所述第一走线沿第一方向延伸,所述第二走线沿与所述第一方向交叉的第二方向延伸。
- 根据权利要求8所述的阵列基板,其中,各所述第一走线上设置有目标区域,所述目标区域包括所述第一走线与各所述第二走线形成的跨线区域,所述目标区域是用于降低第一走线与第二电极层之间电容的区域。
- 根据权利要求9所述的阵列基板,其中,所述目标区域还包括所述第一走线与所述第二走线的交叉连接区域。
- 根据权利要求1所述的阵列基板,其中,所述第一导电层上形成有导电桥接洞,所述第一电极层覆盖于所述第一导电层和所述第二导电层上。
- 根据权利要求11所述的阵列基板,其中,所述导电桥接洞至少为两个。
- 根据权利要求9所述的阵列基板,其中,所述第一钝化层在所述目标区域覆盖部分所述第一基板。
- 根据权利要求1所述阵列基板,其中,所述液晶层具有一介质系数,所述介质系数包括平行向量的介电系数与垂直向量的介电系数。
- 一种显示面板,包括彩色滤光片基板、驱动电路和阵列基板;所述阵列基板包括:第一基板;形成于所述第一基板上的第一导电层;形成于所述第一导电层上的第一钝化层,且所述第一钝化层覆盖部分所述第一基板;形成于所述第一钝化层上的第二导电层;形成于所述第二导电层上的第二钝化层,且所述第二钝化层覆盖部分所述第一钝化 层;形成与所述第二钝化层上的第一电极层,所述第一电极层覆盖部分所述第一导电层、所述第一钝化层、所述第二导电层和所述第二钝化层;形成于所述第一电极层上的非导电材料层,所述非导电材料层覆盖部分所述第二钝化层;形成于所述非导电材料层的液晶层,所述液晶层覆盖部分所述第二钝化层;形成于所述液晶层上的第二电极层;形成于所述第二电极层上的第二基板;所述第一导电层包括多条第一走线,所述第二导电层包括多条第二走线,其中,各所述第一走线通过对应的第一电极层的走线连接多个所述第二走线;所述非导电材料层在所述第一基板上的投影与所述第一走线在所述第一基板上的投影存在重叠区域。
- 根据权利要求15所述的显示面板,其中,各所述第一走线在所述第一基板上的投影位于所述非导电材料层在所述第一基板上的投影里面。
- 根据权利要求15所述的显示面板,其中,所述非导电材料层包括:形成于所述第一电极层上的色阻材料层,所述色阻材料层覆盖部分所述第二钝化层;所述液晶层形成于所述色阻材料层上。
- 根据权利要求17所述的显示面板,其中,所述非导电材料层还包括:形成于所述色阻材料层上的树脂材料层;所述液晶层形成于所述树脂材料层上。
- 根据权利要求17所述的显示面板,其中,各所述第一走线在所述第一基板上的投影位于所述色阻材料层在所述第一基板上的投影里面。
- 根据权利要求18所述的显示面板,其中,各所述第一走线在所述第一基板上的投影位于所述色阻材料层在所述第一基板上的投影里面。
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CN201811445530.1A CN109491161A (zh) | 2018-11-29 | 2018-11-29 | 阵列基板和显示面板 |
CN201811445573.X | 2018-11-29 | ||
CN201811447456.7A CN109298576A (zh) | 2018-11-29 | 2018-11-29 | 阵列基板和显示面板 |
CN201811445530.1 | 2018-11-29 | ||
CN201811445573.XA CN109407435A (zh) | 2018-11-29 | 2018-11-29 | 阵列基板和显示面板 |
CN201811447456.7 | 2018-11-29 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1517751A (zh) * | 2003-01-08 | 2004-08-04 | ���ǵ�����ʽ���� | 上基底及具有该基底的液晶显示装置 |
US7288726B2 (en) * | 2004-10-13 | 2007-10-30 | Chang Gung University | Hollow wire and method for making the same |
CN103472606A (zh) * | 2013-09-27 | 2013-12-25 | 京东方科技集团股份有限公司 | 一种液晶显示面板及显示装置 |
CN104765174A (zh) * | 2014-01-07 | 2015-07-08 | 三星显示有限公司 | 具有积分电容器以及缩小的尺寸的显示设备 |
US20180052364A1 (en) * | 2016-08-18 | 2018-02-22 | Samsung Display Co., Ltd. | Liquid crystal display |
CN108363248A (zh) * | 2018-03-08 | 2018-08-03 | 惠科股份有限公司 | 显示面板及其降低电容负载的方法 |
-
2019
- 2019-01-10 WO PCT/CN2019/071072 patent/WO2020107664A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1517751A (zh) * | 2003-01-08 | 2004-08-04 | ���ǵ�����ʽ���� | 上基底及具有该基底的液晶显示装置 |
US7288726B2 (en) * | 2004-10-13 | 2007-10-30 | Chang Gung University | Hollow wire and method for making the same |
CN103472606A (zh) * | 2013-09-27 | 2013-12-25 | 京东方科技集团股份有限公司 | 一种液晶显示面板及显示装置 |
CN104765174A (zh) * | 2014-01-07 | 2015-07-08 | 三星显示有限公司 | 具有积分电容器以及缩小的尺寸的显示设备 |
US20180052364A1 (en) * | 2016-08-18 | 2018-02-22 | Samsung Display Co., Ltd. | Liquid crystal display |
CN108363248A (zh) * | 2018-03-08 | 2018-08-03 | 惠科股份有限公司 | 显示面板及其降低电容负载的方法 |
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