WO2021107145A1 - 表示装置 - Google Patents

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Publication number
WO2021107145A1
WO2021107145A1 PCT/JP2020/044372 JP2020044372W WO2021107145A1 WO 2021107145 A1 WO2021107145 A1 WO 2021107145A1 JP 2020044372 W JP2020044372 W JP 2020044372W WO 2021107145 A1 WO2021107145 A1 WO 2021107145A1
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WIPO (PCT)
Prior art keywords
region
electrode pads
display device
power supply
supply voltage
Prior art date
Application number
PCT/JP2020/044372
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English (en)
French (fr)
Inventor
弘晃 伊藤
鈴木　隆信
Original Assignee
京セラ株式会社
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Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP2021561577A priority Critical patent/JP7326470B2/ja
Priority to US17/779,381 priority patent/US20220399380A1/en
Priority to CN202080082479.1A priority patent/CN114746927A/zh
Publication of WO2021107145A1 publication Critical patent/WO2021107145A1/ja

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    • H—ELECTRICITY
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Definitions

  • This disclosure relates to a display device.
  • Patent Document 1 An example of the prior art is described in Patent Document 1.
  • the display device of the present disclosure includes a substrate having a first surface and a second surface opposite to the first surface.
  • a plurality of pixel portions located on the first surface and A power supply voltage supply unit located on the second surface and outputting a first power supply voltage applied to the plurality of pixel units and a second power supply voltage having a potential lower than the first power supply voltage is provided.
  • the first wiring conductor that electrically connects the power supply voltage supply unit and the plurality of pixel units and applies the first power supply voltage to the plurality of pixel units and the second power supply voltage are applied to the plurality of pixel units.
  • Has a second wiring conductor to apply At least one of the first wiring conductor and the second wiring conductor includes a planar conductor portion that covers the first surface.
  • the planar conductor portion has a connection portion with the power supply voltage supply portion on at least two sides of the substrate.
  • FIG. 1A It is a figure which shows the voltage distribution in the 1st plane of the 1st power supply voltage in the display device which concerns on one Embodiment of this disclosure. It is a figure which shows the voltage distribution in the 1st plane of the 2nd power supply voltage in the display device which concerns on one Embodiment of this disclosure. It is a figure which shows the voltage distribution in the 1st plane of the 1st power supply voltage in the display device of the comparative example.
  • FIG. 4A It is a figure which shows the voltage distribution in the 1st plane of the 2nd power supply voltage in the display device of the comparative example. It is a top view which shows the schematic structure of the 1st side conductor, the 1st electrode pad and the 2nd electrode pad in the display device which concerns on one Embodiment of this disclosure. It is sectional drawing which cut at the cut plane line AA of FIG. 4A. It is sectional drawing which shows the structure of the 1st side conductor, 1st electrode pad and 2nd electrode pad in the display device which concerns on one Embodiment of this disclosure. It is a top view which shows the pixel part in the display device which concerns on one Embodiment of this disclosure. It is sectional drawing which cut at the cut plane line BB of FIG.
  • a display device that is the basis of the display device of the present disclosure, a display device having a plurality of pixel units including a light emitting diode, an organic EL, and the like is known (see, for example, Patent Document 1).
  • a terminal portion for supplying a power supply voltage signal to the pixel portion is arranged on a peripheral edge portion along one side of the substrate.
  • the potential difference between the high potential side power supply voltage and the low potential side power supply voltage fluctuates in the display surface, resulting in deterioration of display quality such as luminance unevenness and color unevenness.
  • the display device according to the embodiment of the present disclosure will be described with reference to the drawings. It should be noted that each figure referred to below shows the main constituent members and the like of the display device according to the embodiment of the present disclosure. Therefore, the display device according to the embodiment of the present disclosure may have well-known configurations such as a circuit board, a wiring conductor, a control IC, and an LSI (not shown).
  • FIG. 1A is a plan view seen from the first surface side showing a schematic configuration of the display device according to the embodiment of the present disclosure
  • FIG. 1B is a schematic view of the display device according to the embodiment of the present disclosure. It is a top view seen from the 2nd surface side which shows the structure.
  • FIG. 2A is a diagram showing the distribution of the first power supply voltage in the first plane of the display device according to the embodiment of the present disclosure
  • FIG. 2B is a diagram showing the distribution of the first power supply voltage in the display device according to the embodiment of the present disclosure. It is a figure which shows the distribution in the 1st plane of a power supply voltage.
  • FIG. 1A is a plan view seen from the first surface side showing a schematic configuration of the display device according to the embodiment of the present disclosure
  • FIG. 1B is a schematic view of the display device according to the embodiment of the present disclosure. It is a top view seen from the 2nd surface side which shows the structure.
  • FIG. 2A is a diagram showing the distribution of the
  • FIG. 3A is a diagram showing the distribution of the first power supply voltage in the first plane of the display device of the comparative example
  • FIG. 3B is a diagram showing the distribution of the second power supply voltage in the first plane of the display device of the comparative example. It is a figure which shows.
  • the display device 1 includes a substrate 2, a plurality of pixel units 3, a power supply voltage supply unit 4, a first wiring conductor 5, and a second wiring conductor 6.
  • the substrate 2 is, for example, a transparent or opaque glass substrate, a plastic substrate, a ceramic substrate, or the like.
  • the substrate 2 has a rectangular plate shape, and has a first surface 2a and a second surface 2b opposite to the first surface 2a. Further, the substrate 2 includes the first side 2aa of the first surface 2a, and the third surface 2c and the third surface 2c in which the first surface 2a and the second surface 2b are connected on the first side 2aa It has a fourth surface 2d on the opposite side.
  • the substrate of the present invention may be a polygonal plate, not limited to a rectangle, and may be a hexagon or an octagon.
  • the substrate 2 has a first region 21 located from the edge of the first surface 2a along the first side 2aa to the third surface 2c and the second surface 2b. Further, the substrate 2 has a second region 22 located on the first surface 2a from the edge portion along the second side 2ab facing the first side 2aa to the fourth surface 2d and the second surface 2b.
  • the first wiring conductor 5 is arranged in the first region 21 and the second region 22. As will be described later, the first wiring conductor 5 is a conductor that connects the power supply voltage supply unit 4 and each pixel unit 3, and applies a high voltage first power supply voltage to each pixel unit 3.
  • the substrate 2 has a third region 23 located from the edge of the first surface 2a along the first side 2aa to the third surface 2c and the second surface 2b. Further, the substrate 2 has a fourth region 24 located from the edge of the first surface 2a along the second side 2ab to the fourth surface 2d and the second surface 2b.
  • the second wiring conductor 6 is arranged in the third region 23 and the fourth region 24.
  • the second wiring conductor 6 is a conductor that connects the power supply voltage supply unit 4 and each pixel unit 3, and applies a second power supply voltage, which is a voltage lower than the first power supply voltage, to each pixel unit 3.
  • the first surface 2a of the substrate 2 has a rectangular shape, and the first side 2aa and the second side 2ab are short sides of the first surface 2a. ing.
  • the plurality of pixel portions 3 are located on the first surface 2a of the substrate 2.
  • the plurality of pixel portions 3 are arranged in a matrix when viewed in a direction orthogonal to the first surface 2a.
  • Each pixel unit 3 includes at least one light emitting element 31.
  • each pixel unit 3 includes a thin film transistor (TFT) as a switch element, a TFT as a driving element, a capacitive element, and the like.
  • TFT thin film transistor
  • the light emitting element 31 is, for example, a self-luminous element such as a micro light emitting diode (LED) element, an organic EL element, an inorganic EL element, or a semiconductor laser element.
  • a micro LED element is used as the light emitting element 31.
  • the micro LED element may have a rectangular shape when viewed in a plan view, that is, when viewed from a direction orthogonal to the first surface 2a. In this case, the micro LED element may have a side length of about 1 ⁇ m or more and about 100 ⁇ m or less, or may be about 3 ⁇ m or more and about 10 ⁇ m or less.
  • Each pixel unit 3 may have a single light emitting element 31.
  • Each pixel unit 3 includes a sub-pixel unit having a light emitting element 31R that emits red light, a sub-pixel unit having a light emitting element 31G that emits green light, and a sub-pixel unit having a light emitting element 31B that emits blue light.
  • Each pixel portion 3 includes a sub-pixel portion having a light emitting element that emits orange light, red-orange light, magenta light, or purple light, instead of the sub-pixel portion having a light emitting element 31R that emits red light.
  • Each pixel unit 3 may include a sub-pixel unit having a light emitting element that emits yellow-green light, instead of the sub-pixel unit having a light emitting element 31G that emits green light.
  • the power supply voltage supply unit 4 is located on the second surface 2b of the substrate 2.
  • the power supply voltage supply unit 4 has a first power supply voltage terminal and a second power supply voltage terminal.
  • the power supply voltage supply unit 4 outputs the first power supply voltage VDD applied to the plurality of pixel units 3 from the first power supply voltage terminal. Further, the power supply voltage supply unit 4 outputs the second power supply voltage VSS, which is applied to the plurality of pixel units 3 and has a potential lower than that of the first power supply voltage VDD, from the second power supply voltage terminal.
  • the first power supply voltage VDD which is the high potential side power supply voltage
  • the second power supply voltage VSS which is the low potential side power supply voltage
  • VDD is the high potential side power supply voltage
  • VSS is the low potential side power supply voltage
  • the power supply voltage supply unit 4 includes a control circuit for controlling light emission, non-light emission, light emission intensity, etc. of the light emitting element 31.
  • the power supply voltage supply unit 4 may be, for example, a thin film circuit formed on the second surface 2b of the substrate 2.
  • the semiconductor layer constituting the thin film circuit may be, for example, a semiconductor layer made of LTPS (Low Temperature Poly Silicon) directly formed by a thin film forming method such as a CVD method.
  • an IC chip may be mounted as a control circuit.
  • the display device 1 has a plurality of scanning signal lines 7 arranged for each row of the plurality of pixel units 3 arranged in a matrix. Further, the display device 1 has a plurality of light emission control signal lines 8 arranged for each row of the plurality of pixel units 3 arranged in a matrix.
  • the plurality of scanning signal lines 7 and the plurality of light emission control signal lines 8 are driven by the power supply voltage supply unit 4.
  • a plurality of electrode pads 71 electrically connected to the plurality of scanning signal lines 7 are arranged in the fifth region 25 located at the edge of the first surface 2a along the first side 2aa. Further, in the sixth region 26 located at the edge along one long side of the first surface 2a, a plurality of electrode pads 81 electrically connected to the plurality of light emission control signal lines 8 are arranged. ..
  • the first wiring conductor 5 is made of a conductive material, and electrically connects the first power supply voltage terminal of the power supply voltage supply unit 4 and the plurality of pixel units 3.
  • the first wiring conductor 5 includes a plurality of first side surface conductors 51 and a plurality of second side surface conductors 52.
  • the first side conductor 51 is located in the first region 21 of the substrate 2.
  • the first side surface conductor 51 is coated with a conductive paste containing conductive particles such as Ag, Cu, Al, and stainless steel, an uncured resin component, an alcohol solvent, water, and the like on a desired portion in the first region 21. After that, it can be formed by a heating method, a photocuring method of curing by irradiation with light such as ultraviolet rays, a photocuring heating method, or the like.
  • the first side surface conductor 51 can also be formed by a thin film forming method such as a plating method, a vapor deposition method, or a CVD method.
  • a groove may be provided in advance at a portion of the third surface 2c where the first side surface conductor 51 is formed.
  • the conductive paste serving as the first side surface conductor 51 can be easily arranged at a desired portion on the third surface 2c.
  • the second side conductor 52 is located in the second region 22 of the substrate 2.
  • the material for forming the second side surface conductor 52 and the method for forming the second side surface conductor 52 are the same as the material for forming the first side surface conductor 51 and the method for forming the first side surface conductor 51, respectively. Omit.
  • the second wiring conductor 6 is made of a conductive material, and electrically connects the second power supply voltage terminal of the power supply voltage supply unit 4 and the plurality of pixel units 3.
  • the second wiring conductor 6 includes a plurality of third side conductors 61 and a plurality of fourth side conductors 62.
  • the third side conductor 61 is located in the third region 23 of the substrate 2.
  • the material for forming the third side conductor 61 and the method for forming the third side conductor 61 are the same as the material for forming the first side conductor 51 and the method for forming the first side conductor 51, respectively. Omit.
  • the fourth side conductor 62 is located in the fourth region 24 of the substrate 2.
  • the material for forming the fourth side surface conductor 62 and the method for forming the fourth side surface conductor 62 are the same as the material for forming the first side surface conductor 51 and the method for forming the first side surface conductor 51. Omit.
  • the first wiring conductor 5 is located on the second side 2ab side of the substrate 2 and the plurality of first side conductors 51 arranged in the first region 21 located on the first side 2aa side of the substrate 2. It includes a plurality of second side conductors 52 arranged in the second region 22. By disposing it on both sides, it is possible to suppress fluctuations in the first power supply voltage VDD in the first surface 2a.
  • the second wiring conductor 6 has a plurality of third side conductors 61 arranged in the third region 23 located on the first side 2aa side of the substrate 2, and the second side 2ab side of the substrate 2. Includes a plurality of fourth side conductors 62 arranged in a fourth region 24 located in.
  • the display device 1 By disposing it on both sides, it is possible to suppress fluctuations in the second power supply voltage VSS in the first surface 2a. Therefore, according to the display device 1, the fluctuation of the potential difference between the first power supply voltage VDD and the second power supply voltage VSS in the first surface 2a can be reduced, so that the luminance unevenness and the display unevenness can be suppressed. As a result, the display quality can be improved.
  • the voltage distributions of the first power supply voltage VDD and the second power supply voltage VSS in the first surface 2a in the display device 1 of the present embodiment were confirmed by computer simulation.
  • the substrate 2 a substrate having a diagonal length of 9 inches on the first surface 2a was used.
  • the first region 21 has 100 first side conductors 51
  • the second region 22 has 100 second side conductors 52
  • the third region 23 has 100 third side conductors 61
  • the fourth region 24 has a fourth side surface.
  • 100 conductors 62 were arranged.
  • 15 V was applied as the first power supply voltage VDD and 3 V was applied as the second power supply voltage VSS, and the voltage distribution on the substrate was confirmed.
  • a display device similar to the display device 1 used in the embodiment is prepared except that the second side surface conductor 52 and the fourth side surface conductor 62 are not provided, and the display device in the display device is prepared.
  • the voltage distributions of the first power supply voltage VDD and the second power supply voltage VSS in the first surface 2a were confirmed by simulation.
  • FIG. 2A shows the voltage distribution of the first power supply voltage VDD in the display device 1 of the embodiment
  • FIG. 2B shows the voltage distribution of the second power supply voltage VSS in the display device 1 of the embodiment
  • FIG. 3A shows the voltage distribution of the first power supply voltage VDD in the display device of the comparative example
  • FIG. 3B shows the voltage distribution of the second power supply voltage VSS in the display device of the comparative example.
  • the voltage distribution is shown by the shade of color, and the shade level of the color is shown by the voltage range shown on the left side of the figure.
  • the high level of the voltage value was 15.00V and the low level was 14.68V, and the distribution varied by 0.32V.
  • FIG. 2A the high level of the voltage value was 15.00V and the low level was 14.68V, and the distribution varied by 0.32V.
  • FIG. 2A the high level of the voltage value was 15.00V and the low level was 14.68V, and the distribution varied by 0.32V.
  • FIG. 1A shows the high level of the voltage
  • FIG. 2B is a diagram showing a variation of 0.951 V with a high level of 3.959 V and a low level of 3.08 V.
  • FIG. 3A showing a comparative example shows a variation of 0.88 V
  • FIG. 3B shows a variation of 2.924 V.
  • the display device 1 of the embodiment suppresses the fluctuation of the first power supply voltage VDD in the first surface 2a as compared with the display device of the comparative example. Further, from the simulation results of FIGS. 2B and 3B, it can be seen that the display device 1 of the embodiment suppresses the fluctuation of the second power supply voltage VSS in the first surface 2a as compared with the display device of the comparative example. Understand. Therefore, in the display device 1 of the embodiment, the fluctuation of the potential difference between the first power supply voltage VDD and the second power supply voltage VSS in the first surface 2a is reduced as compared with the display device of the comparative example. Understand.
  • FIG. 4A is a plan view showing a schematic configuration of the first side conductor 51, the first electrode pad 53, and the second electrode pad 54 in the display device according to the embodiment of the present disclosure
  • FIG. 4B is a plan view showing the schematic configuration of FIG. 4A.
  • It is a cross-sectional view cut along the cut surface line AA
  • FIG. 4C shows the configuration of the first side conductor 51, the first electrode pad 53, and the second electrode pad 54 in the display device according to the embodiment of the present disclosure.
  • 5A is a plan view showing a pixel portion in the display device according to the embodiment of the present disclosure
  • FIG. 5B is a cross-sectional view cut along the cut plane line BB of FIG. 5A
  • FIG. 5C is a present.
  • FIG. 5D is a plan view showing a first wiring pattern in the display device according to the embodiment of the disclosure
  • FIG. 5D is a plan view showing a third wiring pattern in the display device according to the
  • the first wiring conductor 5 includes a plurality of first electrode pads 53, a plurality of second electrode pads 54, a plurality of third electrode pads 55, and a plurality of fourth electrodes.
  • the electrode pad 56, the first wiring pattern 57, and the second wiring pattern 58 are included.
  • the first wiring pattern 57 is formed on the first surface 2a side, and is formed in the first region 21, the second region 22, the third region 23, the fourth region 24, the fifth region 25, and the sixth region. It is a planar conductor portion formed entirely in a pixel forming region other than 26.
  • the second wiring pattern 58 is a linear conductor portion formed on the second surface side.
  • the plurality of first electrode pads 53 are located in the first region 21 on the first surface 2a.
  • the plurality of first electrode pads 53 are arranged along the first side 2aa, for example, as shown in FIG.
  • the plurality of second electrode pads 54 are located in the first region 21 on the second surface 2b, and overlap with the plurality of first electrode pads 53 in a plan view.
  • a first electrode pad 53 arranged on the first surface 2a and a second electrode pad 54 arranged on the second surface 2b and overlapping the first electrode pad 53 in a plan view. are electrically connected by a first side conductor 51.
  • the first electrode pad 53 is pulled out inward of the first surface 2a (to the right in FIGS. 4B and 4C) and is connected to the first wiring pattern 57.
  • the second electrode pad 54 is pulled out inward of the second surface 2b and connected to the second wiring pattern 58.
  • a lower insulating layer 10 made of SiO 2 , Si 3 N 4, or the like is arranged between the substrate 2 and the first electrode pad 53.
  • a control element, a wiring conductor, or the like for controlling the pixel portion 3 may be arranged inside the lower layer insulating layer 10 or between the substrate 2 and the lower layer insulating layer 10.
  • the first electrode pad 53 and the second electrode pad 54 are made of a conductive material.
  • the first electrode pad 53 and the second electrode pad 54 may be a single metal layer, or a plurality of metal layers may be laminated.
  • FIG. 4C shows an example in which the first electrode pad 53 is composed of two metal layers 53a and 53b in which the first electrode pads 53 are laminated on each other, and the second electrode pad 54 is composed of a single metal layer.
  • the first electrode pad 53 and the second electrode pad 54 are made of, for example, Al, Al / Ti, Ti / Al / Ti, Mo, Mo / Al / Mo, MoNd / AlNd / MoNd, Cu, Cr, Ni, Ag and the like. Become.
  • Al / Ti indicates a laminated structure in which a Ti layer is laminated on an Al layer. The same applies to others.
  • the insulating layer 11 may be arranged in a part of the layers between the metal layers, for example, as shown in FIG. 4C. .. Further, as shown in FIG. 4C, for example, insulation is provided on the inner end of the first surface 2a of the first electrode pad 53 and the inner end of the first surface 2a of the second electrode pad 54. Layers 12 and 13 may be arranged. As a result, it is possible to prevent the first electrode pad 53 and the second electrode pad 54 from being short-circuited with the wiring conductor arranged inside the first surface 2a.
  • the insulating layers 11, 12, and 13 are made of SiO 2 , Si 3 N 4 , a polymer material, or the like.
  • the surface of the first electrode pad 53 and the surface of the second electrode pad 54 may be coated with a transparent conductive layer 17 made of indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
  • the plurality of third electrode pads 55 are located in the second region 22 on the first surface 2a.
  • the plurality of fourth electrode pads 56 are located in the second region 22 on the second surface 2b, and overlap with the plurality of third electrode pads in a plan view.
  • the third electrode pad 55 arranged on the first surface 2a and the fourth electrode pad 56 arranged on the second surface 2b and overlapping the third electrode pad 55 in a plan view are electrically connected by the second side conductor 52. It is connected to the. Since the configurations of the second side conductor 52, the third electrode pad 55, and the fourth electrode pad 56 are the same as the configurations of the first side conductor 51, the first electrode pad 53, and the fourth electrode pad 56, respectively, the second side surface is used. Detailed description of the configuration of the conductor 52, the third electrode pad 55, and the fourth electrode pad 56 will be omitted.
  • the plurality of pixel portions 3 are electrically connected to the plurality of first electrode pads 53 and the plurality of third electrode pads 55.
  • the first wiring pattern 57 is, for example, as shown in FIG. 5C, a wiring pattern in which a conductor portion at a specific portion is not formed and is composed of a planar conductor portion formed substantially on the first surface 2a. is there. However, as shown in FIG. 5C, an opening is formed in the region where the pad 33 described later is formed.
  • the positive electrode anode electrode
  • the negative electrode cathode electrode
  • the second wiring pattern 58 electrically connects the power supply voltage supply unit 4 to the plurality of second electrode pads 54 and the plurality of fourth electrode pads 56.
  • the second wiring pattern 58 is, for example, as shown in FIG. 1B, a wiring pattern composed of linear conductive portions formed on the second surface 2b.
  • the first wiring pattern 57 and the second wiring pattern 58 are composed of, for example, a single layer of Al and Ag, multiple layers of Mo / Al / Mo, and MoNd / AlNd / MoNd.
  • the resistance distribution is reduced by the wiring pattern composed of the planar conductor portion, and the voltage can be input to the planar conductor portion from both sides, so that the first wiring conductor 5 in the first surface 2a is formed. 1 Fluctuations in the power supply voltage VDD can be suppressed. This makes it possible to suppress uneven brightness and uneven display and improve display quality.
  • the second wiring conductor 6 includes a plurality of fifth electrode pads 63, a plurality of sixth electrode pads 64, a plurality of seventh electrode pads 65, and a plurality of eighth electrodes.
  • the electrode pad 66, the third wiring pattern 67, and the fourth wiring pattern 68 are included.
  • the third wiring pattern 67 is formed on the first surface 2a side, and is a pixel forming region other than the first region 21, the second region 22, the third region 23, the fourth region 24, the fifth region 25, and the sixth region 26. It is a planar conductor portion formed in.
  • the fourth wiring pattern 68 is a linear conductor portion formed on the second surface side.
  • the third wiring pattern 67 is formed in a layer different from the first wiring pattern on the first surface 2a via an insulating film.
  • the plurality of fifth electrode pads 63 are located in the third region 23 on the first surface 2a.
  • the plurality of fifth electrode pads 63 are arranged along the first side 2aa, for example, as shown in FIG.
  • the plurality of sixth electrode pads 64 are located in the third region 23 on the second surface 2b, and overlap with the plurality of fifth electrode pads 63 in a plan view.
  • the fifth electrode pad 63 arranged on the first surface 2a and the sixth electrode pad 64 arranged on the second surface 2b and overlapping the fifth electrode pad 63 in a plan view are electrically connected by a third side conductor 61. It is connected to the. Since the configurations of the third side conductor 61, the fifth electrode pad 63, and the sixth electrode pad 64 are the same as the configurations of the first side conductor 51, the first electrode pad 53, and the fourth electrode pad 56, respectively, the third side surface is formed. Detailed description of the configuration of the conductor 61, the fifth electrode pad 63, and the sixth electrode pad 64 will be omitted.
  • the plurality of seventh electrode pads 65 are located in the fourth region 24 on the first surface 2a.
  • the plurality of seventh electrode pads 65 are arranged along the second side 2ab, for example, as shown in FIG.
  • the plurality of eighth electrode pads 66 are located in the fourth region 24 on the second surface 2b, and overlap with the plurality of seventh electrode pads 65 in a plan view.
  • the seventh electrode pad 65 arranged on the first surface 2a and the eighth electrode pad 66 arranged on the second surface 2b and overlapping the seventh electrode pad 65 in a plan view are electrically connected by the fourth side conductor 62. It is connected to the. Since the configurations of the fourth side conductor 62, the seventh electrode pad 65, and the eighth electrode pad 66 are the same as the configurations of the first side conductor 51, the first electrode pad 53, and the fourth electrode pad 56, respectively, the fourth side surface is Detailed description of the configuration of the conductor 62, the seventh electrode pad 65, and the eighth electrode pad 66 will be omitted.
  • the third wiring pattern 67 is a wiring pattern composed of a planar conductor portion formed on substantially the entire surface 2a of the first surface. However, an opening is formed in the region where the light emitting element 31 is mounted. Further, the third wiring pattern 67 is located on the first surface 2a side of the lower layer than the first wiring pattern 57.
  • the first wiring pattern 57 and the third wiring pattern 67 are insulated from each other by the insulating layers 14 and 15.
  • the insulating layers 14 and 15 are made of SiO 2 , Si 3 N 4 , a polymer material, or the like.
  • the power supply voltage supply unit 4 is electrically connected to the plurality of sixth electrode pads 64 and the plurality of eighth electrode pads 66.
  • the second wiring pattern 58 is, for example, as shown in FIG. 1B, a wiring pattern composed of a linear conductor portion formed on the second surface 2b.
  • the third wiring pattern 67 and the fourth wiring pattern 68 are composed of, for example, a single layer of Al and Ag, multiple layers of Mo / Al / Mo, and MoNd / AlNd / MoNd.
  • the resistance distribution is reduced by the wiring pattern composed of the planar conductor portion, and the voltage can be input to the planar conductor portion from both sides, so that the second wiring conductor 6 in the first surface 2a is formed.
  • 2 Fluctuations in the power supply voltage VSS can be suppressed. This makes it possible to suppress uneven brightness and uneven display and improve display quality.
  • Each of the plurality of pixel units 3 has a light emitting element 31R that emits red light, a light emitting element 31G that emits green light, and a light emitting element 31B that emits blue light, as shown in FIG. 5A, for example. As a result, each pixel unit 3 can display color gradation.
  • the light emitting elements 31R, 31G, and 31B may be arranged in an L shape when viewed in a plan view, for example, as shown in FIG. 5A.
  • the area of the pixel unit 3 in the plan view can be reduced, and the shape of the pixel unit 3 in the plan view can be made into a compact square shape or the like.
  • the pixel density of the display device 1 can be improved, and high-quality image display becomes possible.
  • the positive electrode (anode electrode) 31a of the light emitting element 31 is electrically connected to the anode pad 32 which is a part of the first wiring pattern 57.
  • the negative electrode (cathode electrode) 31b of the light emitting element 31 is electrically connected to the cathode pad 33 on the same layer as the first wiring pattern 57.
  • the anode pad 32 and the cathode pad 33 are insulated from each other by an opening (notch) of the first wiring pattern 57 formed around the cathode pad 33.
  • the cathode pad 33 is electrically connected to one end 34a of the routing wiring conductor 34 via a contact hole.
  • the routing wiring conductor 34 is in the same layer as the third wiring pattern 67.
  • the third wiring pattern 67 and the routing wiring conductor 34 are insulated from each other in the same layer by a notch formed around the routing wiring conductor 34.
  • the other end 34b of the routing wiring conductor 34 is electrically connected to the source electrode of the TFT that currently drives the light emitting element 31 as described later.
  • the third wiring pattern 67 is electrically connected to the source electrode of the TFT via a contact hole formed in the insulating film 10, and a power supply voltage VSS is applied to each pixel portion 3. It becomes.
  • the surfaces of the anode pad 32 and the cathode pad 33 may be covered with a transparent conductive layer 17 made of ITO, IZO, or the like. Further, for example, as shown in FIG. 5B, an insulating layer 16 made of SiO 2 , Si 3 N 4 , a polymer material, or the like may be arranged around the anode pad 32 and the cathode pad 33.
  • the display device 1 has a lower insulating layer 10 made of an insulating material such as SiO 2 , Si 3 N 4 or the like on the first surface 2a of the substrate 2.
  • the lower insulating layer 10 may be composed of a single insulating layer, or may be formed by laminating a plurality of insulating layers.
  • a TFT 35 is arranged between the substrate 2 and the lower insulating layer 10 as shown in FIG. 5B, for example.
  • the TFT 35 is, for example, an n-channel TFT, and is used as a drive element for driving a light emitting element with a current.
  • the TFT 35 is a three-terminal element having a gate electrode 35a which is a gate end, a source electrode 35b which is a source end, and a drain electrode 35c which is a drain end.
  • the source electrode 35b is electrically connected to the cathode pad 33 via a conductive connecting member 36 such as a through hole.
  • the gate electrode 35a is electrically connected to the pixel node
  • the drain electrode 35c is electrically connected to the other end 34b of the routing wiring conductor 34 via a conductive connecting member such as a through hole.
  • the display device 1 has a configuration in which the first region 21 is separated from the third region 23 and the second region 22 is separated from the fourth region 24. As a result, it is possible to prevent the first wiring conductor 5 and the second wiring conductor 6 from being short-circuited, so that it is possible to provide a display device with improved reliability.
  • the display device 1 when viewed in a direction orthogonal to the third surface 2c, the first region 21 and the fourth region 24 are separated from each other, and the third region 23 and the third region 23 and the third region 23 The two regions 22 are separated from each other.
  • the third surface 2c of one display device 1 is used.
  • the first region 21 overlaps the second region 22 and the third region 23 overlaps the fourth region 24.
  • It may be a configuration. According to such a configuration, the second wiring pattern 58 and the fourth wiring pattern 68 can be easily routed on the second surface 2b of the substrate 2.
  • the substrate 2 is located at the edge of the first surface 2a along the first side 2aa, and the first region 21 and the display device 1 are located in the direction along the first side 2aa.
  • a pair of fifth regions 25 sandwiching a third region 23 are provided, and a plurality of electrode pads 71 electrically connected to a plurality of scanning signal lines 7 are arranged in the pair of fifth regions 25. It may be.
  • the first wiring conductor 5 and the second wiring conductor 6 apply the first power supply voltage VDD and the second power supply voltage VSS to the pixel unit 3, respectively. Therefore, the first electrode pad 53 of the first wiring conductor 5 and the fifth electrode pad 63 of the second wiring conductor 6 generate heat in the first electrode pad 53 and the fifth electrode pad 63, and disconnection due to the heat generation.
  • the surface area may be larger than the surface area of the electrode pad 71 electrically connected to the scanning signal line 7. In this case, the first region 21 where the first electrode pad 53 is arranged and the third region 23 where the fifth electrode pad 63 is arranged and the fifth region 25 where the electrode pad 71 is arranged are separated from each other.
  • the 1-electrode pad 53, the 5th electrode pad 63, and the electrode pad 71 can be efficiently arranged.
  • FIG. 6 is a plan view showing a schematic configuration of a display device according to another embodiment of the present disclosure.
  • the display device 1A of the present embodiment has a different configuration of the first to fourth regions from the display device 1 of the above embodiment, and the other components have the same configuration. Illustrations and detailed description will be omitted.
  • the first region 21 and the third region 23 are separated from each other, and the second region 22 and the fourth region 24 are separated from each other.
  • the first region 21 overlaps with the second region 22 and is separated from the fourth region 24 when viewed in a direction orthogonal to the third surface 2c. ..
  • the third region 23 overlaps with the fourth region 24 and is separated from the second region 22. ..
  • the display device 1A has a configuration in which the length of the second region 22 along the second side 2ab is longer than the length of the first region 21 along the first side 2aa.
  • the number of the third electrode pads is made larger than the number of the first electrode pads, or the distance between the adjacent third electrode pads is wider than the distance between the adjacent first electrode pads. Therefore, the fluctuation of the first power supply voltage VDD in the first surface 2a can be effectively suppressed. Further, the size of the electrode pad itself can be increased. This makes it possible to suppress uneven brightness and uneven display and improve display quality.
  • the display device 1 has a configuration in which the length along the second side 2ab of the fourth region 24 is longer than the length along the first side 2aa of the third region 23. ..
  • the number of the 7th electrode pads is made larger than the number of the 5th electrode pads, or the distance between the adjacent 7th electrode pads is wider than the distance between the adjacent 5th electrode pads. Therefore, fluctuations in the second power supply voltage VSS in the first surface 2a can be effectively suppressed. Further, the size of the electrode pad itself can be increased. This makes it possible to suppress uneven brightness and uneven display and improve display quality.
  • FIG. 7 is a plan view showing a schematic configuration of a display device according to another embodiment of the present disclosure.
  • the display device 1B of the present embodiment has a different configuration of the first to fourth regions from the display device 1 of the above embodiment, and the other components have the same configuration. Illustrations and detailed description will be omitted.
  • the first region 21 and the third region 23 are separated from each other, and the second region 22 and the fourth region 24 are separated from each other. Further, when the display device 1B is viewed in the direction orthogonal to the third surface 2c as in the display device 1, the first region 21 overlaps with the second region 22 and is separated from the fourth region 24. .. Further, when the display device 1B is viewed in the direction orthogonal to the third surface 2c as in the display device 1, the third region 23 overlaps with the fourth region 24 and is separated from the second region 22. ..
  • the display device 1B has a configuration in which the first region 21 is composed of a plurality of first partial regions 21a and 21b, and the third region 23 is composed of a plurality of third partial regions 23a and 23b. There may be.
  • the first electrode pad 53 and the fifth electrode pad 63 can be dispersedly arranged in the direction along the first side 2aa, so that the first power supply voltage in the first surface 2a Fluctuations in VDD and second power supply voltage VSS can be effectively suppressed.
  • the first partial regions 21a and 21b and the third partial regions 23a and 23b may be alternately arranged in the direction along the first side 2aa, for example, as shown in FIG.
  • the second region 22 is composed of a plurality of second partial regions 22a and 22b
  • the fourth region 24 is composed of a plurality of fourth partial regions 24a and 24b.
  • the third electrode pad 55 and the seventh electrode pad 65 can be distributed and arranged in the direction along the second side 2ab, so that the first power supply voltage in the first surface 2a Fluctuations in VDD and second power supply voltage VSS can be effectively suppressed.
  • the second partial regions 22a and 22b and the fourth partial regions 24a and 24b may be arranged alternately in the direction along the second side 2ab, for example, as shown in FIG.
  • FIG. 8 is a plan view showing a schematic configuration of a display device according to another embodiment of the present disclosure.
  • the display device 1C of the present embodiment has a different configuration of the first to fourth regions from the display device 1 of the above embodiment, and has the same configuration for the others. Illustrations and detailed description will be omitted.
  • the first region 21 and the third region 23 are separated from each other, and the second region 22 and the fourth region 24 are separated from each other. Further, in the display device 1C, similarly to the display device 1, when viewed in the direction orthogonal to the third surface 2c, the first region 21 is separated from the fourth region 24, and the third region 23 is the second. It is separated from the area 22.
  • the first region 21 and the second region 22 are separated from each other, and the third region 23 and the third region 23 and the third region 23 are separated from each other. It has a configuration in which the four regions 24 are separated from each other. According to such a configuration, the first electrode pad 53 and the fifth electrode pad 63 are dispersedly arranged in the direction along the first side 2aa, and the third electrode pad and the seventh electrode pad are arranged on the second side. It can be distributed and arranged in the direction along 2ab.
  • FIG. 9 is a plan view showing a schematic configuration of a multi-display according to an embodiment of the present disclosure.
  • the multi-display 100 of the present embodiment includes a plurality of display devices 1.
  • the plurality of display devices 1 are arranged vertically and horizontally on the same surface so that the first surface 2a faces the same direction, and the side surfaces of the adjacent display devices 1 are connected to each other by an adhesive or the like. Further, the plurality of display devices 1 include a first display device 1 and a second display device 1, and include a third surface 1c of the first display device 1 and a fourth surface 1d of the second display device 1. Are combined.
  • the multi-display 100 by providing a plurality of display devices 1, it is possible to realize a large-scale multi-display in which uneven brightness and uneven display are suppressed and display quality is improved. Further, according to the multi-display 100, the first side conductor 51 or the second side conductor 52 of the first display device 1 and the third side conductor 61 or the fourth side conductor 62 of the second display device 1 are short-circuited. Since this can be suppressed, it is possible to provide a highly reliable multi-display.
  • the multi-display 100 may include a plurality of display devices 1A or may include a plurality of display devices 1B. , Or a plurality of display devices 1C may be provided.
  • the display device of the present disclosure includes a plate-shaped substrate having a first surface and a second surface opposite to the first surface.
  • a plurality of pixel portions located on the first surface and A power supply voltage supply unit located on the second surface and outputting a first power supply voltage applied to the plurality of pixel units and a second power supply voltage having a potential lower than the first power supply voltage is provided. It ’s a display device,
  • the first wiring conductor that electrically connects the power supply voltage supply unit and the plurality of pixel units and applies the first power supply voltage to the plurality of pixel units and the second power supply voltage are applied to the plurality of pixel units.
  • Has a second wiring conductor to apply At least one of the first wiring conductor and the second wiring conductor includes a planar conductor portion that covers the first surface.
  • the planar conductor portion has a connection portion with the power supply voltage supply portion on at least two sides of the substrate.
  • the display device of the present disclosure can be applied to various electronic devices.
  • the electronic device include a complex and large display device (multi-display), an automobile route guidance system (car navigation system), a ship route guidance system, an aircraft route guidance system, a smartphone terminal, a mobile phone, a tablet terminal, and a personal computer.
  • Digital assistants video cameras, digital still cameras, electronic notebooks, electronic dictionaries, personal computers, copiers, game equipment terminals, televisions, product display tags, price display tags, commercial regramable display devices, cars There are audio, digital audio players, facsimiles, printers, automatic cash deposit / payment machines (ATMs), vending machines, digital display watches, smart watches, etc.
  • ATMs automatic cash deposit / payment machines

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Abstract

本開示の表示装置は、第１面と第１面とは反対側の第２面とを有する板状の基板と、第１面上に位置する複数の画素部と、第２面上に位置し、複数の画素部に印加される第１電源電圧、および第１電源電圧よりも低電位である第２電源電圧を出力する電源電圧供給部と、を備える。表示装置は、電源電圧供給部と複数の画素部とを電気的に接続し、第１電源電圧を複数の画素部に印加する第１配線導体と第２電源電圧を複数の画素部に印加する第２配線導体とを有し、第１配線導体と第２配線導体との少なくとも一方が、第１面を覆う面状導体部を含んでおり、面状導体部は基板のうち少なくとも２つの辺において電源電圧供給部との接続部を有する。

Description

表示装置
　本開示は、表示装置に関する。
　従来技術の一例は、特許文献１に記載されている。
特開２０１６－１８６６４９号公報
　本開示の表示装置は、第１面と前記第１面とは反対側の第２面とを有する基板と、
　前記第１面上に位置する複数の画素部と、
　前記第２面上に位置し、前記複数の画素部に印加される第１電源電圧、および前記第１電源電圧よりも低電位である第２電源電圧を出力する電源電圧供給部と、を備え、
　前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第１電源電圧を前記複数の画素部に印加する第１配線導体と前記第２電源電圧を前記複数の画素部に印加する第２配線導体とを有し、
　前記第１配線導体と前記第２配線導体との少なくとも一方が、前記第１面を覆う面状導体部を含んでおり、
　前記面状導体部は前記基板のうち少なくとも２つの辺において前記電源電圧供給部との接続部を有する。
　本開示の目的、特色、および利点は、下記の詳細な説明と図面とからより明確になるであろう。　
本開示の一実施形態に係る表示装置の概略的構成を示す平面図である。 本開示の一実施形態に係る表示装置の概略的構成を示す、図１Ａとは異なる方向から見た平面図である。 本開示の一実施形態に係る表示装置における第１電源電圧の第１面内での電圧分布を示す図である。 本開示の一実施形態に係る表示装置における第２電源電圧の第１面内での電圧分布を示す図である。 比較例の表示装置における第１電源電圧の第１面内での電圧分布を示す図である。 比較例の表示装置における第２電源電圧の第１面内での電圧分布を示す図である。 本開示の一実施形態に係る表示装置における第１側面導体、第１電極パッドおよび第２電極パッドの概略的構成を示す平面図である。 図４Ａの切断面線Ａ－Ａで切断した断面図である。 本開示の一実施形態に係る表示装置における第１側面導体、第１電極パッドおよび第２電極パッドの構成を示す断面図である。 本開示の一実施形態に係る表示装置における画素部を示す平面図である。 図５Ａの切断面線Ｂ－Ｂで切断した断面図である。 本開示の一実施形態に係る表示装置における第１配線パターンを示す平面図である。 本開示の一実施形態に係る表示装置における第３配線パターンを示す平面図である。 本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。 本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。 本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。 本開示の一実施形態に係るマルチディスプレイの概略的構成を示す平面図である。
　本開示の表示装置の基礎となる表示装置として、発光ダイオード、有機ＥＬ等を含む画素部を複数備えた表示装置が知られている（例えば、特許文献１を参照）。そのような表示装置では、基板の一辺に沿う周縁部に、画素部に電源電圧信号を供給するための端子部が配置されている。
　本開示の表示装置の基礎となる表示装置では、高電位側電源電圧と低電位側電源電圧との電位差が表示面内で変動することにより、輝度ムラ、色ムラ等表示品位の低下が発生することがある。
　以下、図面を用いて本開示の実施形態に係る表示装置について説明する。なお、以下で参照する各図は、本開示の実施形態に係る表示装置の主要な構成部材等を示している。したがって、本開示の実施形態に係る表示装置は、図示されていない回路基板、配線導体、制御ＩＣ，ＬＳＩ等の周知の構成を備えていてもよい。
　図１Ａは、本開示の一実施形態に係る表示装置の概略的構成を示す、第１面側から見た平面図であり、図１Ｂは、本開示の一実施形態に係る表示装置の概略的構成を示す、第２面側から見た平面図である。図２Ａは、本開示の一実施形態に係る表示装置における第１電源電圧の第１面内での分布を示す図であり、図２Ｂは、本開示の一実施形態に係る表示装置における第２電源電圧の第１面内での分布を示す図である。図３Ａは、比較例の表示装置における第１電源電圧の第１面内での分布を示す図であり、図３Ｂは、比較例の表示装置における第２電源電圧の第１面内での分布を示す図である。
　表示装置１は、基板２、複数の画素部３、電源電圧供給部４、第１配線導体５および第２配線導体６を備える。
　基板２は、例えば、透明または不透明なガラス基板、プラスチック基板、セラミック基板等である。基板２は、矩形板状であり、第１面２ａ、および第１面２ａとは反対側の第２面２ｂを有している。さらに、基板２は、第１面２ａの第１辺２ａａを含み、第１辺２ａａにおいて第１面２ａと第２面２ｂとが接続している第３面２ｃ、および第３面２ｃとは反対側の第４面２ｄを有している。なお、本発明の基板は、多角形の板状であればよく、長方形だけに限定されず、六角形、八角形であってもよい。
　基板２は、第１面２ａにおける第１辺２ａａに沿った縁部から第３面２ｃおよび第２面２ｂにかけて位置する第１領域２１を有する。さらに、基板２は、第１面２ａにおける、第１辺２ａａに対向する第２辺２ａｂに沿った縁部から第４面２ｄおよび第２面２ｂにかけて位置する第２領域２２を有する。第１領域２１および第２領域２２には、第１配線導体５が配置される。なお、後述するが、第１配線導体５は、電源電圧供給部４と各画素部３とを接続する導体であって、高電圧である第１電源電圧を各画素部３に印加する。
　基板２は、第１面２ａにおける第１辺２ａａに沿った縁部から第３面２ｃおよび前記第２面２ｂにかけて位置する第３領域２３を有する。さらに、基板２は、第１面２ａにおける第２辺２ａｂに沿った縁部から第４面２ｄおよび第２面２ｂにかけて位置する第４領域２４を有する。第３領域２３および第４領域２４には、第２配線導体６が配置される。第２配線導体６は、電源電圧供給部４と各画素部３とを接続する導体であって、第１電源電圧よりも低い電圧である第２電源電圧を各画素部３に印加する。
　本実施形態では、例えば図１に示すように、基板２の第１面２ａは、長方形状とされており、また第１辺２ａａおよび第２辺２ａｂは、第１面２ａの短辺とされている。
　複数の画素部３は、基板２の第１面２ａ上に位置している。複数の画素部３は、第１面２ａに直交する方向に見たときに、マトリクス状に配列されている。各画素部３は、少なくとも１つの発光素子３１を含んでいる。さらに、各画素部３は、スイッチ素子としての薄膜トランジスタ（Thin Film Transistor：ＴＦＴ）、駆動素子としてのＴＦＴ、容量素子等を含んでいる。
　発光素子３１は、例えば、マイクロ発光ダイオード（ＬＥＤ）素子、有機ＥＬ素子、無機ＥＬ素子、半導体レーザ素子等の自発光型の素子である。本実施形態では、発光素子３１として、マイクロＬＥＤ素子を用いる。マイクロＬＥＤ素子は、平面視、すなわち第１面２ａに直交する方向から見たときに、矩形状の形状であってもよい。この場合、マイクロＬＥＤ素子は、一辺の長さが１μｍ程度以上１００μｍ程度以下であってもよく、３μｍ程度以上１０μｍ程度以下であってもよい。
　各画素部３は、単一の発光素子３１を有していてもよい。各画素部３は、赤色光を発光する発光素子３１Ｒを有する副画素部、緑色光を発光する発光素子３１Ｇを有する副画素部および青色光を発光する発光素子３１Ｂを有する副画素部を含んでいてもよい。各画素部３は、赤色光を発光する発光素子３１Ｒを有する副画素部の代わりに、橙色光、赤橙色光、赤紫色光、または紫色光を発光する発光素子を有する副画素部を含んでいてもよい。各画素部３は、緑色光を発光する発光素子３１Ｇを有する副画素部の代わりに、黄緑色光を発光する発光素子を有する副画素部を含んでいてもよい。
　電源電圧供給部４は、基板２の第２面２ｂ上に位置している。電源電圧供給部４は、第１電源電圧端子および第２電源電圧端子を有する。電源電圧供給部４は、複数の画素部３に印加される第１電源電圧ＶＤＤを第１電源電圧端子から出力する。また、電源電圧供給部４は、複数の画素部３に印加される、第１電源電圧ＶＤＤよりも低電位である第２電源電圧ＶＳＳを第２電源電圧端子から出力する。高電位側電源電圧である第１電源電圧ＶＤＤは、例えば１０Ｖ～１５Ｖ程度のアノード電圧であり、低電位側電源電圧である第２電源電圧ＶＳＳは、例えば０Ｖ～３Ｖ程度のカソード電圧である。
　電源電圧供給部４は、発光素子３１の発光、非発光、発光強度等を制御するための制御回路を含んでいる。電源電圧供給部４は、例えば、基板２の第２面２ｂ上に形成された薄膜回路であってもよい。この場合、薄膜回路を構成する半導体層は、例えば、ＣＶＤ法等の薄膜形成方法によって直接的に形成されたＬＴＰＳ（Low Temperature Poly Silicon）から成る半導体層であってもよい。また、制御回路としてＩＣチップを搭載してもよい。
　表示装置１は、マトリクス状に配列された複数の画素部３の行毎に配置された複数の走査信号線７を有している。また、表示装置１は、マトリクス状に配列された複数の画素部３の列毎に配置された複数の発光制御信号線８を有している。複数の走査信号線７および複数の発光制御信号線８は、電源電圧供給部４によって駆動される。第１面２ａの第１辺２ａａに沿った縁部に位置する第５領域２５には、複数の走査信号線７にそれぞれ電気的に接続される複数の電極パッド７１が配置される。また、第１面２ａの一方の長辺に沿った縁部に位置する第６領域２６には、複数の発光制御信号線８にそれぞれ電気的に接続される複数の電極パッド８１が配置される。
　第１配線導体５は、導電性材料から成り、電源電圧供給部４の第１電源電圧端子と複数の画素部３とを電気的に接続している。第１配線導体５は、複数の第１側面導体５１および複数の第２側面導体５２を含んでいる。
　第１側面導体５１は、基板２の第１領域２１に位置している。第１側面導体５１は、Ａｇ、Ｃｕ、Ａｌ、ステンレススチール等の導電性粒子、未硬化の樹脂成分、アルコール溶媒および水等を含む導電性ペーストを、第１領域２１における所望の部位に塗布した後、加熱法、紫外線等の光照射によって硬化させる光硬化法、光硬化加熱法等の方法によって形成することができる。第１側面導体５１は、メッキ法、蒸着法、ＣＶＤ法等の薄膜形成方法によっても形成することができる。また、第３面２ｃにおける第１側面導体５１を形成する部位に、溝を予め設けておいてもよい。これにより、第１側面導体５１と成る導電性ペーストが、第３面２ｃにおける所望の部位に配置されやすくなる。
　第２側面導体５２は、基板２の第２領域２２に位置している。第２側面導体５２を形成する材料および第２側面導体５２の形成方法は、第１側面導体５１を形成する材料および第１側面導体５１の形成方法とそれぞれ同様であるので、詳細な説明については省略する。
　第２配線導体６は、導電性材料から成り、電源電圧供給部４の第２電源電圧端子と複数の画素部３とを電気的に接続している。第２配線導体６は、複数の第３側面導体６１および複数の第４側面導体６２を含んでいる。
　第３側面導体６１は、基板２の第３領域２３に位置している。第３側面導体６１を形成する材料および第３側面導体６１の形成方法は、第１側面導体５１を形成する材料および第１側面導体５１の形成方法とそれぞれ同様であるので、詳細な説明については省略する。
　第４側面導体６２は、基板２の第４領域２４に位置している。第４側面導体６２を形成する材料および第４側面導体６２の形成方法は、第１側面導体５１を形成する材料および第１側面導体５１の形成方法とそれぞれ同様であるので、詳細な説明については省略する。
　表示装置１は、第１配線導体５が、基板２の第１辺２ａａ側に位置する第１領域２１に配置された複数の第１側面導体５１と、基板２の第２辺２ａｂ側に位置する第２領域２２に配置された複数の第２側面導体５２とを含んでいる。両側に配設することにより、第１面２ａ内における第１電源電圧ＶＤＤの変動を抑制できる。また、表示装置１は、第２配線導体６が、基板２の第１辺２ａａ側に位置する第３領域２３に配置された複数の第３側面導体６１と、基板２の第２辺２ａｂ側に位置する第４領域２４に配置された複数の第４側面導体６２とを含んでいる。両側に配設することにより、第１面２ａ内における第２電源電圧ＶＳＳの変動を抑制することができる。したがって、表示装置１によれば、第１面２ａ内における、第１電源電圧ＶＤＤと第２電源電圧ＶＳＳのとの電位差の変動を低減することができるため、輝度ムラおよび表示ムラを抑制でき、ひいては、表示品位を向上させることができる。
　実施例として、本実施形態の表示装置１における、第１面２ａ内での第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳの電圧分布をコンピュータシミュレーションによって確認した。本シミュレーションでは、基板２として、第１面２ａの対角線の長さが９インチである基板を用いた。第１領域２１に第１側面導体５１を１００個、第２領域２２に第２側面導体５２を１００個、第３領域２３に第３側面導体６１を１００個、第４領域２４に第４側面導体６２を１００個配設した。そして、第１電源電圧ＶＤＤとして１５Ｖ、第２電源電圧ＶＳＳとして３Ｖを印加して、基板における電圧分布を確認した。
　また、比較例として、第２側面導体５２および第４側面導体６２を有していないことを除いては、実施例で用いた表示装置１と同様の表示装置を準備し、該表示装置における、第１面２ａ内での第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳの電圧分布をシミュレーションによって確認した。
　図２Ａは、実施例の表示装置１における第１電源電圧ＶＤＤの電圧分布を示し、図２Ｂは、実施例の表示装置１における第２電源電圧ＶＳＳの電圧分布を示す。図３Ａは、比較例の表示装置における第１電源電圧ＶＤＤの電圧分布を示し、図３Ｂは、比較例の表示装置における第２電源電圧ＶＳＳの電圧分布を示す。図では電圧分布を色の濃淡で示し、色の濃淡レベルは図左に示す電圧レンジで表されている。図２Ａにおいては、電圧値のハイレベルが１５．００Ｖ、ローレベルが１４．６８Ｖであり、分布として０．３２Ｖのバラツキとなった。同様に図２Ｂは、ハイレベルが３．９５９Ｖ、ローレベルが３．００８Ｖであり、０．９５１Ｖのバラツキを示す図である。一方、比較例を示す図３Ａは０．８８Ｖのバラツキ、図３Ｂは２．９２４Ｖのバラツキを示している。
　図２Ａ，３Ａのシミュレーション結果から、実施例の表示装置１では、比較例の表示装置と比較して、第１面２ａ内での第１電源電圧ＶＤＤの変動が抑制されていることがわかる。また、図２Ｂ，３Ｂのシミュレーション結果から、実施例の表示装置１では、比較例の表示装置と比較して、第１面２ａ内での第２電源電圧ＶＳＳの変動が抑制されていることがわかる。したがって、実施例の表示装置１では、比較例の表示装置と比較して、第１面２ａ内での第１電源電圧ＶＤＤと第２電源電圧ＶＳＳとの電位差の変動が低減されていることがわかる。
　次に、表示装置１における第１配線導体５、第２配線導体６および画素部３の構成について説明する。
　図４Ａは、本開示の一実施形態に係る表示装置における第１側面導体５１、第１電極パッド５３および第２電極パッド５４の概略的構成を示す平面図であり、図４Ｂは、図４Ａの切断面線Ａ－Ａで切断した断面図であり、図４Ｃは、本開示の一実施形態に係る表示装置における第１側面導体５１、第１電極パッド５３および第２電極パッド５４の構成を示す断面図である。図５Ａは、本開示の一実施形態に係る表示装置における画素部を示す平面図であり、図５Ｂは、図５Ａの切断面線Ｂ－Ｂで切断した断面図であり、図５Ｃは、本開示の一実施形態に係る表示装置における第１配線パターンを示す平面図であり、図５Ｄは、本開示の一実施形態に係る表示装置における第３配線パターンを示す平面図である。
　第１配線導体５は、第１側面導体５１および第２側面導体５２に加えて、複数の第１電極パッド５３、複数の第２電極パッド５４、複数の第３電極パッド５５、複数の第４電極パッド５６、第１配線パターン５７および第２配線パターン５８を含んでいる。なお、後述するが、第１配線パターン５７は、第１面２ａ側に形成され、第１領域２１、第２領域２２、第３領域２３、第４領域２４、第５領域２５及び第６領域２６以外の画素形成領域に全面的に形成された面状導体部である。また、第２配線パターン５８は、第２面側に形成された線状導体部である。
　複数の第１電極パッド５３は、第１面２ａにおける第１領域２１に位置している。複数の第１電極パッド５３は、例えば図１に示すように、第１辺２ａａに沿って配列されている。複数の第２電極パッド５４は、第２面２ｂにおける第１領域２１に位置しており、平面視で複数の第１電極パッド５３とそれぞれ重なっている。
　例えば図４Ａ，４Ｂに示すように、第１面２ａに配置された第１電極パッド５３と、第２面２ｂに配置され、該第１電極パッド５３と平面視で重なる第２電極パッド５４とは、第１側面導体５１によって電気的に接続されている。第１電極パッド５３は、第１面２ａの内方（図４Ｂ，４Ｃにおける右方向）に引き出され、第１配線パターン５７に接続される。第２電極パッド５４は、第２面２ｂの内方に引き出され、第２配線パターン５８に接続される。また、例えば図４Ｃに示すように、基板２と第１電極パッド５３との間には、ＳｉＯ２、Ｓｉ３Ｎ４等から成る下層絶縁層１０が配置されている。下層絶縁層１０の内部、または基板２と下層絶縁層１０との間には、画素部３を制御するための制御素子、配線導体等が配置されていてもよい。
　第１電極パッド５３および第２電極パッド５４は、導電性材料から成る。第１電極パッド５３および第２電極パッド５４は、単一の金属層であってもよく、複数の金属層が積層されていてもよい。図４Ｃは、第１電極パッド５３が互いに積層された２層の金属層５３ａ，５３ｂから成り、第２電極パッド５４が単一の金属層から成る例を示している。
　第１電極パッド５３および第２電極パッド５４は、例えば、Ａｌ、Ａｌ／Ｔｉ、Ｔｉ／Ａｌ／Ｔｉ、Ｍｏ、Ｍｏ／Ａｌ／Ｍｏ、ＭｏＮｄ／ＡｌＮｄ／ＭｏＮｄ、Ｃｕ、Ｃｒ、Ｎｉ、Ａｇ等から成る。ここで、「Ａｌ／Ｔｉ」は、Ａｌ層上にＴｉ層が積層された積層構造を示す。その他についても同様である。
　第１電極パッド５３および第２電極パッド５４は、複数の金属層の積層体である場合、例えば図４Ｃに示すように、金属層の層間の一部に絶縁層１１が配置されていてもよい。また、第１電極パッド５３における第１面２ａの内方側の端部、および第２電極パッド５４における第１面２ａの内方側の端部には、例えば図４Ｃに示すように、絶縁層１２，１３が配置されていてもよい。これにより、第１電極パッド５３および第２電極パッド５４が、第１面２ａの内方に配置された配線導体と短絡することを抑制できる。絶縁層１１，１２，１３は、ＳｉＯ２、Ｓｉ３Ｎ４、ポリマー材料等から成る。第１電極パッド５３の表面および第２電極パッド５４の表面は、インジウム錫酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）等から成る透明導電層１７によって被覆されていてもよい。
　複数の第３電極パッド５５は、第１面２ａにおける第２領域２２に位置している。複数の第４電極パッド５６は、第２面２ｂにおける第２領域２２に位置しており、平面視で複数の第３電極パッドとそれぞれ重なっている。
　第１面２ａに配置された第３電極パッド５５と、第２面２ｂに配置され、該第３電極パッド５５と平面視で重なる第４電極パッド５６とは、第２側面導体５２によって電気的に接続されている。第２側面導体５２、第３電極パッド５５および第４電極パッド５６の構成は、第１側面導体５１、第１電極パッド５３および第４電極パッド５６の構成とそれぞれ同様であるので、第２側面導体５２、第３電極パッド５５および第４電極パッド５６の構成についての詳細な説明は省略する。
　第１配線パターン５７は、複数の画素部３を、複数の第１電極パッド５３および複数の第３電極パッド５５に電気的に接続している。第１配線パターン５７は、例えば図５Ｃに示すように、特定の箇所の導体部が形成されておらず、かつ第１面２ａ上の略全体に形成された面状導体部からなる配線パターンである。但し、図５Ｃに示すように、後述するパッド３３が形成される領域は開口部が形成されている。発光素子３１は、正電極（アノード電極）が、第１配線パターン５７の一部であるアノードパッドに電気的に接続され、負電極（カソード電極）が、第１配線パターン５７の開口部に形成されたカソードパッドに電気的に接続されている。アノードパッドとカソードパッドとは、電気的に絶縁されている。
　第２配線パターン５８は、電源電圧供給部４を、複数の第２電極パッド５４および複数の第４電極パッド５６に電気的に接続している。第２配線パターン５８は、例えば図１Ｂに示すように、第２面２ｂ上に形成された線状導電部からなる配線パターンである。
　第１配線パターン５７および第２配線パターン５８は、例えば、単層のＡｌ、Ａｇ、複層のＭｏ／Ａｌ／Ｍｏ、ＭｏＮｄ／ＡｌＮｄ／ＭｏＮｄ等から成る。
　上記構成の第１配線導体５によれば、面状導体部からなる配線パターンによって抵抗分布が少なくなると共に、面状導体部に対して両側から電圧を入力できることにより、第１面２ａ内における第１電源電圧ＶＤＤの変動を抑制することができる。これにより、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることが可能になる。
　第２配線導体６は、第３側面導体６１および第４側面導体６２に加えて、複数の第５電極パッド６３、複数の第６電極パッド６４、複数の第７電極パッド６５、複数の第８電極パッド６６、第３配線パターン６７および第４配線パターン６８を含んでいる。第３配線パターン６７は、第１面２ａ側に形成され、第１領域２１、第２領域２２、第３領域２３、第４領域２４、第５領域２５及び第６領域２６以外の画素形成領域に形成された面状導体部である。また、第４配線パターン６８は、第２面側に形成された線状導体部である。但し、第３配線パターン６７は、第１面２ａの第１配線パターンとは異なる層に絶縁膜を介して形成されている。
　複数の第５電極パッド６３は、第１面２ａにおける第３領域２３に位置している。複数の第５電極パッド６３は、例えば図１に示すように、第１辺２ａａに沿って配列されている。複数の第６電極パッド６４は、第２面２ｂにおける第３領域２３に位置しており、平面視で複数の第５電極パッド６３とそれぞれ重なっている。
　第１面２ａに配置された第５電極パッド６３と、第２面２ｂに配置され、該第５電極パッド６３と平面視で重なる第６電極パッド６４とは、第３側面導体６１によって電気的に接続されている。第３側面導体６１、第５電極パッド６３および第６電極パッド６４の構成は、第１側面導体５１、第１電極パッド５３および第４電極パッド５６の構成とそれぞれ同様であるので、第３側面導体６１、第５電極パッド６３および第６電極パッド６４の構成についての詳細な説明は省略する。
　複数の第７電極パッド６５は、第１面２ａにおける第４領域２４に位置している。複数の第７電極パッド６５は、例えば図１に示すように、第２辺２ａｂに沿って配列されている。複数の第８電極パッド６６は、第２面２ｂにおける第４領域２４に位置しており、平面視で複数の第７電極パッド６５とそれぞれ重なっている。
　第１面２ａに配置された第７電極パッド６５と、第２面２ｂに配置され、該第７電極パッド６５と平面視で重なる第８電極パッド６６とは、第４側面導体６２によって電気的に接続されている。第４側面導体６２、第７電極パッド６５および第８電極パッド６６の構成は、第１側面導体５１、第１電極パッド５３および第４電極パッド５６の構成とそれぞれ同様であるので、第４側面導体６２、第７電極パッド６５および第８電極パッド６６の構成についての詳細な説明は省略する。
　第３配線パターン６７は、複数の画素部３を、複数の第５電極パッド６３および複数の第７電極パッド６５に電気的に接続している。第３配線パターン６７は、第１面２ａ上の略全体に形成された面状導体部からなる配線パターンである。但し、発光素子３１が搭載される領域は開口部が形成されている。また、第３配線パターン６７は、第１配線パターン５７よりも下層の第１面２ａ側に位置している。第１配線パターン５７と第３配線パターン６７とは、絶縁層１４，１５によって互いに絶縁されている。絶縁層１４，１５は、ＳｉＯ２、Ｓｉ３Ｎ４、ポリマー材料等から成る。
　第４配線パターン６８は、電源電圧供給部４を、複数の第６電極パッド６４および複数の第８電極パッド６６に電気的に接続している。第２配線パターン５８は、例えば図１Ｂに示すように、第２面２ｂ上に形成された線状導体部からなる配線パターンである。
　第３配線パターン６７および第４配線パターン６８は、例えば、単層のＡｌ、Ａｇ、複層のＭｏ／Ａｌ／Ｍｏ、ＭｏＮｄ／ＡｌＮｄ／ＭｏＮｄ等から成る。
　上記構成の第２配線導体６によれば、面状導体部からなる配線パターンによって抵抗分布が少なくなると共に、面状導体部に対して両側から電圧を入力できることにより、第１面２ａ内における第２電源電圧ＶＳＳの変動を抑制することができる。これにより、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることが可能になる。
　複数の画素部３は、各々が、例えば図５Ａに示すように、赤色光を発光する発光素子３１Ｒ、緑色光を発光する発光素子３１Ｇおよび青色光を発光する発光素子３１Ｂを有している。これにより、各画素部３は、カラーの階調表示が可能となっている。
　発光素子３１Ｒ，３１Ｇ，３１Ｂは、例えば図５Ａに示すように、平面視したときに、Ｌ字状に配列されていてもよい。これにより、画素部３の平面視における面積が小さくなり、また画素部３の平面視における形状をコンパクトな正方形状等とすることができる。ひいては、表示装置１の画素密度を向上させることができ、高画質な画像表示が可能となる。
　発光素子３１の正電極（アノード電極）３１ａは、第１配線パターン５７の一部であるアノードパッド３２に電気的に接続されている。発光素子３１の負電極（カソード電極）３１ｂは、第１配線パターン５７と同一層にあるカソードパッド３３に電気的に接続されている。アノードパッド３２とカソードパッド３３とは、カソードパッド３３の周囲に形成された第１配線パターン５７の開口部（切り欠き）によって、互いに絶縁されている。カソードパッド３３は、コンタクトホールを介して、引き回し配線導体３４の一端部３４ａに電気的に接続されている。引き回し配線導体３４は、第３配線パターン６７と同一層にある。第３配線パターン６７と引き回し配線導体３４とは、引き回し配線導体３４の周囲に形成された切り欠きによって、互いに同層では絶縁されている。引き回し配線導体３４の他端部３４ｂは、後述するように、発光素子３１を電流駆動するＴＦＴのソース電極に電気的に接続される。第３配線パターン６７は、図示していないが、絶縁膜１０に形成されたコンタクトホールを介してＴＦＴのソース電極に電気的に接続されており、電源電圧ＶＳＳを各画素部３に印加することとなる。
　アノードパッド３２およびカソードパッド３３の表面は、ＩＴＯ、ＩＺＯ等から成る透明導電層１７によって被覆されていてもよい。また、例えば図５Ｂに示すように、アノードパッド３２およびカソードパッド３３の周囲には、ＳｉＯ２、Ｓｉ３Ｎ４、ポリマー材料等から成る絶縁層１６が配置されていてもよい。
　表示装置１は、基板２の第１面２ａ上に、ＳｉＯ２、Ｓｉ３Ｎ４等の絶縁材料から成る下層絶縁層１０を有している。下層絶縁層１０は、単一の絶縁層から成っていてもよく、複数の絶縁層が積層されて成っていてもよい。基板２と下層絶縁層１０との間には、例えば図５Ｂに示すように、ＴＦＴ３５が配置されている。
　ＴＦＴ３５は、例えば、ｎチャネル型ＴＦＴであり、発光素子を電流駆動する駆動素子として用いられる。ＴＦＴ３５は、ゲート端であるゲート電極３５ａ、ソース端であるソース電極３５ｂおよびドレイン端であるドレイン電極３５ｃを有する３端子素子である。ＴＦＴ３５は、例えば図５Ｂに示すように、ソース電極３５ｂが、スルーホール等の導電接続部材３６を介して、カソードパッド３３に電気的に接続されている。また、ゲート電極３５ａは、画素ノードに電気的に接続され、ドレイン電極３５ｃは、スルーホール等の導電接続部材を介して、引き回し配線導体３４の他端部３４ｂに電気的に接続されている。
　次に、本開示の一実施形態に係る表示装置における第１乃至第４領域の構成の幾つかの例について説明する。
　表示装置１は、例えば図１Ａに示すように、第１領域２１が第３領域２３と離隔し、第２領域２２が第４領域２４と離隔している構成を有する。これにより、第１配線導体５と第２配線導体６とが短絡することを抑制できるため、信頼性が向上した表示装置を提供することが可能になる。
　また、表示装置１は、例えば図１Ａに示すように、第３面２ｃに直交する方向に見たときに、第１領域２１と第４領域２４とが互いに離隔し、第３領域２３と第２領域２２とが互いに離隔している構成を有する。これにより、複数の表示装置１を同一面上においてタイリング配置して、複合型かつ大型の表示装置（以下、マルチディスプレイともいう）を構成する場合に、一の表示装置１の第３面２ｃと他の表示装置１の第４面２ｄを結合することによって、第１側面導体５１と第４側面導体６２との間の短絡および第３側面導体６１と第２側面導体５２との間の短絡を抑制することができる。ひいては、信頼性が向上したマルチディスプレイを提供することが可能になる。
　表示装置１は、例えば図１Ａに示すように、第３面２ｃに直交する方向に見たときに、第１領域２１が第２領域２２に重なり、第３領域２３が第４領域２４に重なる構成であってもよい。このような構成によれば、基板２の第２面２ｂ上における第２配線パターン５８および第４配線パターン６８の引き回しが容易になる。
　表示装置１は、例えば図１Ａに示すように、基板２が、第１面２ａにおける第１辺２ａａに沿った縁部に位置し、かつ第１辺２ａａに沿った方向において第１領域２１および第３領域２３を挟む一対の第５領域２５を有し、一対の第５領域２５には、複数の走査信号線７にそれぞれ電気的に接続される複数の電極パッド７１が配置されている構成であってもよい。
　第１配線導体５および第２配線導体６は、画素部３に第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳをそれぞれ印加するものである。そのため、第１配線導体５の第１電極パッド５３、および第２配線導体６の第５電極パッド６３は、第１電極パッド５３および第５電極パッド６３における発熱、ならびに該発熱に起因する断線等の接続不良の発生を抑制するために、走査信号線７に電気的に接続される電極パッド７１の表面積よりも大きい表面積を有していてもよい。この場合、第１電極パッド５３が配置される第１領域２１および第５電極パッド６３が配置される第３領域２３と、電極パッド７１が配置される第５領域２５とを分けることで、第１電極パッド５３、第５電極パッド６３および電極パッド７１を効率的に配置することが可能になる。
　次に、本開示の他の実施形態に係る表示装置について説明する。
　図６は、本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。本実施形態の表示装置１Ａは、上記実施形態の表示装置１に対して、第１乃至第４領域の構成が異なっており、その他については、同様の構成であるので、同様の構成については、図示および詳細な説明は省略する。
　表示装置１Ａは、表示装置１と同様に、第１領域２１と第３領域２３とが互いに離隔し、第２領域２２と第４領域２４とが互いに離隔している。また、表示装置１Ａは、表示装置１と同様に、第３面２ｃに直交する方向に見たときに、第１領域２１は、第２領域２２と重なり、第４領域２４と離隔している。さらに、表示装置１Ａは、表示装置１と同様に、第３面２ｃに直交する方向に見たときに、第３領域２３は、第４領域２４と重なり、第２領域２２と離隔している。
　表示装置１Ａは、例えば図６に示すように、第２領域２２の第２辺２ａｂに沿った長さが、第１領域２１の第１辺２ａａに沿った長さよりも長い構成を有する。このような構成によれば、第３電極パッドの数を第１電極パッドの数よりも大きくする、または、隣り合う第３電極パッド同士の間隔を隣り合う第１電極パッド同士の間隔よりも広くすることができるため、第１面２ａ内における第１電源電圧ＶＤＤの変動を効果的に抑制することができる。さらに、電極パッド自体のサイズを大きくすることが可能となる。これにより、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることが可能になる。
　また、表示装置１は、例えば図６に示すように、第４領域２４の第２辺２ａｂに沿った長さが、第３領域２３の第１辺２ａａに沿った長さよりも長い構成を有する。このような構成によれば、第７電極パッドの数を第５電極パッドの数よりも大きくする、または、隣り合う第７電極パッド同士の間隔を隣り合う第５電極パッド同士の間隔よりも広くすることができるため、第１面２ａ内における第２電源電圧ＶＳＳの変動を効果的に抑制することができる。さらに、電極パッド自体のサイズを大きくすることが可能となる。これにより、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることが可能になる。
　図７は、本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。本実施形態の表示装置１Ｂは、上記実施形態の表示装置１に対して、第１乃至第４領域の構成が異なっており、その他については、同様の構成であるので、同様の構成については、図示および詳細な説明は省略する。
　表示装置１Ｂは、表示装置１と同様に、第１領域２１と第３領域２３とが互いに離隔し、第２領域２２と第４領域２４とが互いに離隔している。また、表示装置１Ｂは、表示装置１と同様に、第３面２ｃに直交する方向に見たときに、第１領域２１は、第２領域２２と重なり、第４領域２４と離隔している。さらに、表示装置１Ｂは、表示装置１と同様に、第３面２ｃに直交する方向に見たときに、第３領域２３は、第４領域２４と重なり、第２領域２２と離隔している。
　表示装置１Ｂは、例えば図７に示すように、第１領域２１が、複数の第１部分領域２１ａ，２１ｂから成り、第３領域２３が、複数の第３部分領域２３ａ，２３ｂから成る構成であってもよい。このような構成によれば、第１電極パッド５３および第５電極パッド６３を、第１辺２ａａに沿った方向において分散して配置することができるため、第１面２ａ内における第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳの変動を効果的に抑制することができる。ひいては、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることができる。第１部分領域２１ａ，２１ｂおよび第３部分領域２３ａ，２３ｂは、例えば図７に示すように、第１辺２ａａに沿った方向において交互に配置されていてもよい。
　また、表示装置１Ｂは、例えば図７に示すように、第２領域２２は、複数の第２部分領域２２ａ，２２ｂから成り、第４領域２４は、複数の第４部分領域２４ａ，２４ｂから成る構成を有する。このような構成によれば、第３電極パッド５５および第７電極パッド６５を、第２辺２ａｂに沿った方向において分散して配置することができるため、第１面２ａ内における第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳの変動を効果的に抑制することができる。これにより、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることができる。第２部分領域２２ａ，２２ｂおよび第４部分領域２４ａ，２４ｂは、例えば図７に示すように、第２辺２ａｂに沿った方向において交互に配置されていてもよい。
　図８は、本開示の他の実施形態に係る表示装置の概略的構成を示す平面図である。本実施形態の表示装置１Ｃは、上記実施形態の表示装置１に対して、第１乃至第４領域の構成が異なっており、その他については、同様の構成であるので、同様の構成については、図示および詳細な説明は省略する。
　表示装置１Ｃは、表示装置１と同様に、第１領域２１と第３領域２３とが互いに離隔し、第２領域２２と第４領域２４とが互いに離隔している。また、表示装置１Ｃは、表示装置１と同様に、第３面２ｃに直交する方向に見たときに、第１領域２１は、第４領域２４と離隔し、第３領域２３は、第２領域２２と離隔している。
　表示装置１Ｃは、例えば図８に示すように、第３面２ｃに直交する方向に見たときに、第１領域２１と第２領域２２とが互いに離隔しており、第３領域２３と第４領域２４とが互いに離隔している構成を有する。このような構成によれば、第１電極パッド５３および第５電極パッド６３を、第１辺２ａａに沿った方向において分散して配置し、第３電極パッドおよび第７電極パッドを、第２辺２ａｂに沿った方向において分散して配置することができる。これにより、第１面２ａ内における第１電源電圧ＶＤＤおよび第２電源電圧ＶＳＳの変動を効果的に抑制することができるため、第１電源電圧ＶＤＤと第２電源電圧ＶＳＳのとの電位差の変動を低減することができる。ひいては、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることができる。
　次に、本開示の一実施形態に係るマルチディスプレイについて説明する。
　図９は、本開示の一実施形態に係るマルチディスプレイの概略的構成を示す平面図である。
　本実施形態のマルチディスプレイ１００は、複数の表示装置１を備えている。複数の表示装置１は、第１面２ａが同一方向を向くように、同一面上において縦横に配置され、隣り合う表示装置１は、接着剤等によって、側面同士が結合されている。また、複数の表示装置１は、第１の表示装置１および第２の表示装置１を含み、第１の表示装置１の第３面１ｃと、第２の表示装置１の第４面１ｄとが結合されている。
　マルチディスプレイ１００によれば、複数の表示装置１を備えることで、輝度ムラおよび表示ムラが抑制され、表示品位が向上された大型のマルチディスプレイを実現することができる。また、マルチディスプレイ１００によれば、第１の表示装置１の第１側面導体５１または第２側面導体５２と、第２の表示装置１の第３側面導体６１または第４側面導体６２とが短絡することを抑制できるため、信頼性に優れたマルチディスプレイを提供することができる。
　なお、上記では、マルチディスプレイ１００が複数の表示装置１を備える例について説明したが、マルチディスプレイ１００は、複数の表示装置１Ａを備えていてもよく、複数の表示装置１Ｂを備えていてもよく、または複数の表示装置１Ｃを備えていてもよい。
　本開示は次の実施の形態が可能である。
　本開示の表示装置は、第１面と前記第１面とは反対側の第２面とを有する板状の基板と、
　前記第１面上に位置する複数の画素部と、
　前記第２面上に位置し、前記複数の画素部に印加される第１電源電圧、および前記第１電源電圧よりも低電位である第２電源電圧を出力する電源電圧供給部と、を備える表示装置であって、
　前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第１電源電圧を前記複数の画素部に印加する第１配線導体と前記第２電源電圧を前記複数の画素部に印加する第２配線導体とを有し、
　前記第１配線導体と前記第２配線導体との少なくとも一方が、前記第１面を覆う面状導体部を含んでおり、
　前記面状導体部は前記基板のうち少なくとも２つの辺において前記電源電圧供給部との接続部を有する。
　本開示の表示装置によれば、表示面内における高電位側電源電圧と低電位側電源電圧との電位差の変動を低減することができるため、輝度ムラおよび表示ムラを抑制し、表示品位を向上させることができる。
　以上、本開示の実施形態について詳細に説明したが、本開示は上述の実施の形態に限定されるものではなく、本開示の要旨を逸脱しない範囲内において、種々の変更、改良等が可能である。上記各実施形態をそれぞれ構成する全部または一部を、適宜、矛盾しない範囲で組み合わせ可能であることは、言うまでもない。また、本開示の表示装置は、各種の電子機器に適用できる。その電子機器としては、例えば、複合型かつ大型の表示装置（マルチディスプレイ）、自動車経路誘導システム（カーナビゲーションシステム）、船舶経路誘導システム、航空機経路誘導システム、スマートフォン端末、携帯電話、タブレット端末、パーソナルデジタルアシスタント（ＰＤＡ）、ビデオカメラ、デジタルスチルカメラ、電子手帳、電子辞書、パーソナルコンピュータ、複写機、ゲーム機器の端末装置、テレビジョン、商品表示タグ、価格表示タグ、商業用のプリグラマブル表示装置、カーオーディオ、デジタルオーディオプレイヤー、ファクシミリ、プリンター、現金自動預け入れ払い機（ＡＴＭ）、自動販売機、デジタル表示式腕時計、スマートウォッチなどがある。
　１　　　表示装置
　２　　　基板
　２ａ　　第１面
　２ａａ　第１辺
　２ａｂ　第２辺
　２ｂ　　第２面
　２ｃ　　第３面
　２ｄ　　第４面
　２１　　第１領域
　２１ａ，２１ｂ　第１部分領域
　２２　　第２領域
　２２ａ，２２ｂ　第２部分領域
　２３　　第３領域
　２３ａ，２３ｂ　第３部分領域
　２４　　第４領域
　２４ａ，２４ｂ　第４部分領域
　２５　　第５領域
　２６　　第６領域
　３　　　画素部
　３１，３１Ｒ，３１Ｇ，３１Ｂ　発光素子
　３１ａ　正電極
　３１ｂ　負電極
　３２　　アノードパッド
　３３　　カソードパッド
　３４　　引き回し配線導体
　３４ａ　一端部
　３４ｂ　他端部
　３５　　ＴＦＴ
　３５ａ　ゲート電極
　３５ｂ　ソース電極
　３５ｃ　ドレイン電極
　３６　　導電接続部材
　４　　　電源電圧供給部
　５　　　第１配線導体
　５１　　第１側面導体
　５２　　第２側面導体
　５３　　第１電極パッド
　５３ａ，５３ｂ　金属層
　５４　　第２電極パッド
　５５　　第３電極パッド
　５６　　第４電極パッド
　５７　　第１配線パターン
　５８　　第２配線パターン
　６　　　第２配線導体
　６１　　第３側面導体
　６２　　第４側面導体
　６３　　第５電極パッド
　６４　　第６電極パッド
　６５　　第７電極パッド
　６６　　第８電極パッド
　６７　　第３配線パターン
　６８　　第４配線パターン
　７　　　走査信号線
　７１　　電極パッド
　８　　　発光制御信号線
　８１　　電極パッド
　１０　　下層絶縁層
　１１，１２，１３，１４，１５，１６　絶縁層
　１７　　透明導電層
　１００　マルチディスプレイ

Claims (12)

  1. 　第１面と前記第１面とは反対側の第２面とを有する基板と、
    　前記第１面上に位置する複数の画素部と、
    　前記第２面上に位置し、前記複数の画素部に印加される第１電源電圧、および前記第１電源電圧よりも低電位である第２電源電圧を出力する電源電圧供給部と、を備え、
    　前記電源電圧供給部と前記複数の画素部とを電気的に接続し、前記第１電源電圧を前記複数の画素部に印加する第１配線導体と前記第２電源電圧を前記複数の画素部に印加する第２配線導体とを有し、
    　前記第１配線導体と前記第２配線導体との少なくとも一方が、前記第１面を覆う面状導体部を含んでおり、
    　前記面状導体部は前記基板のうち少なくとも２つの辺において前記電源電圧供給部との接続部を有する表示装置。
  2. 　前記基板は、前記第１面の第１辺において前記第１面と前記第２面とを接続する第３面、および前記第３面とは反対側の第４面を有し、
    　前記第１配線導体は、
    　　前記第１面における前記第１辺に沿った縁部から前記第３面および前記第２面にかけての第１領域に位置する複数の第１側面導体と、
    　　前記第１面における、前記第１辺に対向する第２辺に沿った縁部から前記第４面および前記第２面にかけての第２領域に位置する複数の第２側面導体とを有し、
    　前記第２配線導体は、
    　　前記第１面における前記第１辺に沿った縁部から前記第３面および前記第２面にかけての第３領域に位置する複数の第３側面導体と、
    　　前記第１面における前記第２辺に沿った縁部から前記第４面および前記第２面にかけての第４領域に位置する複数の第４側面導体を含む第２配線導体とを有する、請求項１に記載の表示装置。
  3. 　前記第１配線導体は、
    　　前記第１面における前記第１領域に位置する複数の第１電極パッドと、
    　　前記第２面における前記第１領域に位置し、平面視で前記複数の第１電極パッドとそれぞれ重なる複数の第２電極パッドと、
    　　前記第１面における前記第２領域に位置する複数の第３電極パッドと、
    　　前記第２面における前記第２領域に位置し、平面視で前記複数の第３電極パッドとそれぞれ重なる複数の第４電極パッドと、
    　　前記第１面上に位置し、前記複数の画素部を前記複数の第１電極パッドおよび前記複数の第３電極パッドに電気的に接続する第１配線パターンと、
    　　前記第２面上に位置し、前記電源電圧供給部を前記複数の第２電極パッドおよび前記複数の第４電極パッドに電気的に接続する第２配線パターンとをさらに含み、
    　前記複数の第１側面導体は、前記複数の第１電極パッドと前記複数の第２電極パッドとをそれぞれ接続し、
    　前記複数の第２側面導体は、前記複数の第３電極パッドと前記複数の第４電極パッドとをそれぞれ接続している、請求項２に記載の表示装置。
  4. 　前記第２配線導体は、
    　　前記第１面における前記第３領域に位置する複数の第５電極パッドと、
    　　前記第２面における前記第３領域に位置し、平面視で前記複数の第５電極パッドにそれぞれ重なる複数の第６電極パッドと、
    　　前記第１面における前記第４領域に位置する複数の第７電極パッドと、
    　　前記第２面における前記第４領域に位置し、平面視で前記複数の第７電極パッドとそれぞれ重なる複数の第８電極パッドと、
    　　前記第１面上に位置し、前記複数の画素部を前記複数の第５電極パッドおよび前記複数の第７電極パッドに電気的に接続する第３配線パターンと、
    　　前記第２面上に位置し、前記電源電圧供給部を前記複数の第６電極パッドおよび前記複数の第８電極パッドに電気的に接続する第４配線パターンとをさらに含み、
    　前記複数の第３側面導体は、前記複数の第５電極パッドと前記複数の第６電極パッドとをそれぞれ接続し、
    　前記複数の第４側面導体は、前記複数の第７電極パッドと前記複数の第８電極パッドとをそれぞれ接続している、請求項２に記載の表示装置。
  5. 　前記第１領域と前記第３領域とは互いに離隔しており、前記第２領域と前記第４領域とは互いに離隔している、請求項３または４に記載の表示装置。
  6. 　前記第３面に直交する方向に見たときに、前記第１領域と前記第４領域とは互いに離隔しており、前記第３領域と前記第２領域とは互いに離隔している、請求項５に記載の表示装置。
  7. 　前記第３面に直交する方向に見たときに、前記第１領域は前記第２領域に重なっており、前記第３領域は前記第４領域に重なっている、請求項６に記載の表示装置。
  8. 　前記第３面に直交する方向に見たときに、前記第１領域と前記第２領域は互いに離隔しており、前記第３領域と前記第４領域とは互いに離隔している、請求項６に記載の表示装置。
  9. 　前記第１面上に位置する複数の走査信号線をさらに備え、
    　前記基板は、前記第１面における前記第１辺に沿った縁部に位置する一対の第５領域であって、前記第１辺に沿った方向において前記第１領域および前記第３領域を挟む一対の第５領域を有し、
    　前記一対の第５領域には、前記複数の走査信号線にそれぞれ電気的に接続される複数の電極パッドが配置されている、請求項１～８のいずれかに記載の表示装置。
  10. 　前記板状の基板は矩形であり、前記第１面は長方形状であり、前記第１辺および前記第２辺は短辺である、請求項１～９のいずれかに記載の表示装置。
  11. 　前記複数の画素部の各々は、少なくとも１つのマイクロＬＥＤ素子を含む、請求項１～１０のいずれかに記載の表示装置。
  12. 　前記面状導体部は、画素部において、前記マイクロＬＥＤ素子の少なくとも一方の電極部位に開口が形成されている請求項１１に記載の表示装置。
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