WO2015000273A1 - 一种阵列基板、显示面板和显示装置 - Google Patents

一种阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2015000273A1
WO2015000273A1 PCT/CN2013/089660 CN2013089660W WO2015000273A1 WO 2015000273 A1 WO2015000273 A1 WO 2015000273A1 CN 2013089660 W CN2013089660 W CN 2013089660W WO 2015000273 A1 WO2015000273 A1 WO 2015000273A1
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Prior art keywords
tft
gate
array substrate
turned
sub
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PCT/CN2013/089660
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English (en)
French (fr)
Inventor
王洁琼
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/422,410 priority Critical patent/US9613574B2/en
Publication of WO2015000273A1 publication Critical patent/WO2015000273A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and more particularly to an array substrate, a display panel, and a display device.
  • the liquid crystal based display device is a flat display which is widely used at present, and has advantages of low power consumption, light weight, no radiation, and the like compared with other display modes.
  • a liquid crystal based display device generally includes an array substrate, a color filter substrate, and a liquid crystal layer. As shown in FIG. 1, the display area on the array substrate includes a plurality of sub-display areas, and each of the sub-display areas is generally formed by two gate lines 101 (scanning lines) and two data lines 102.
  • a thin film transistor 103 and a pixel electrode 104 are disposed inside the sub display region.
  • the voltage applied to the common electrode and/or the pixel electrode 104 on the color filter substrate is controlled to control the electric field intensity applied between the color filter substrate and the array substrate, thereby controlling the deflection direction of the liquid crystal molecules.
  • the TFT Thin FET
  • the data voltage of the corresponding row is driven by the source to the corresponding pixel electrode 104, and the color film substrate and the array substrate are changed.
  • the electric field strength which in turn affects the deflection of the liquid crystal.
  • the gate electrode 1031 of the thin film transistor 103 is opposed to a partial region of the drain electrode 1032, so that when the voltage between the gate electrode 1031 and the drain electrode 1032 changes, a parasitic capacitance C gd is generated.
  • Its equivalent circuit is shown in Figure i.
  • Opening the gate voltage is changed from V gh ⁇ to the moment of turn-off voltage, due to a sudden change in the gate voltage, so that the charge will move inside of the parasitic capacitance C gd, once the charge transfer will cause a voltage across C gd occur
  • the change, and the voltage change is conducted from the drain to the pixel electrode 104, causing the electric field strength between the color filter substrate and the array substrate to change, and the electric field intensity between the color filter substrate and the array substrate changes to cause liquid crystal
  • the deflection angle of the molecules changes, which affects the transmittance, resulting in inaccurate grayscale display of the image.
  • An object of the embodiments of the present invention is to provide an array substrate, a display panel, and a display device.
  • an embodiment of the present invention provides an array substrate, including: dividing a display area into a plurality of sub-display areas of a plurality of data lines and a plurality of gate lines;
  • the source is electrically connected to the data line, and the drain and the pixel electrode are electrically connected.
  • a parasitic capacitance is formed between the gate and the drain of the TFT, and the array substrate further includes: a switch circuit, configured to turn on when the gate driving signal of the TFT changes from a high level to a low level Passing through the two ends of the parasitic capacitance.
  • the switch circuit comprises:
  • a first switching unit disposed in the at least one sub-display area, the first switching unit being connected in parallel with a parasitic capacitance formed on the TFT in the corresponding sub-display area;
  • One end of the parallel circuit formed by the parasitic capacitance and the first switching unit is electrically connected to the drain of the TFT, and the other end is electrically connected to the gate of the TFT;
  • the first switching unit When the gate driving signal of the TFT in the corresponding sub-display area transitions from a high level to a low level, the first switching unit is turned on, and the first switching unit is turned off at other times.
  • the first switching unit is controlled to be turned on when the gate driving signal transitions from a high level to a low level by an external controller, and is turned off at other times.
  • each of the row gate lines is correspondingly provided with one of the external controllers, and the signal output by the external controller is synchronized with the gate driving signal of the corresponding gate line.
  • the first switching unit is a TFT element having a gate connected to the external controller, a source connected to a gate of the TFT, and a drain connected to a drain of the TFT.
  • the switch circuit comprises:
  • a first switching unit disposed in the at least one sub-display area, the first switching unit being connected in parallel with a parasitic capacitance formed on the TFT in the corresponding sub-display area;
  • One end of the parallel circuit formed by the parasitic capacitance and the first switching unit is electrically connected to the drain of the TFT, and the other end is electrically connected to the gate of the TFT through the second switching unit;
  • the first switching unit When the gate driving signal of the TFT in the corresponding sub-display area changes from a high level to a low level 0 inch, the first switching unit is turned on, and the second switching unit is turned off.
  • the first switching unit is a first TFT that is turned off when the gate is in a high level control
  • the second switching unit is a second TFT that is turned on when the gate is in a high level control.
  • the gates of the first TFT and the second TFT are electrically connected to the gate line.
  • each row of gate lines is correspondingly provided with an external controller
  • the signal output by the external controller is synchronized with the gate driving signal of the corresponding gate line
  • the first switching unit is the gate is high a first TFT that is turned off during the flat control
  • the second switching unit is a second TFT whose gate is in a high level control day
  • the gates of the first TFT and the second TFT are connected to the external controller .
  • an embodiment of the present invention further provides a display panel including any of the above array substrates.
  • an embodiment of the present invention further provides a display device including the above display panel.
  • both ends of the parasitic capacitance are turned on when the gate driving signal of the TFT transitions from a high level to a low level.
  • the potentials across the parasitic capacitance are the same. In the case where the potential across the parasitic capacitance is the same, the parasitic capacitance is neither discharged nor charged, that is, the charge does not move inside the parasitic capacitance.
  • the voltage on the drain electrode and the pixel electrode electrically connected to the drain is not affected, that is, the pixel electrode
  • the voltage can maintain the voltage after charging, so the parasitic capacitance between the gate and the drain is reduced to the pixel electrode.
  • 1 is an equivalent circuit diagram of a conventional array substrate
  • FIG. 3 is an equivalent circuit diagram of another array substrate according to an embodiment of the present invention.
  • a switching circuit is disposed to turn on both ends of the parasitic capacitance when the gate driving signal of the TFT transitions from a high level to a low level, so that parasitic The phenomenon that the charge does not move inside the capacitor, the effect of the parasitic capacitance between the gate and the drain on the voltage of the pixel electrode is lowered, and the display effect is improved.
  • the source is electrically connected to the data line
  • the drain is electrically connected to the pixel electrode
  • the gate is electrically connected to the gate line
  • a parasitic capacitance is formed between the gate and the drain of the TFT, and the array substrate further includes: a switch circuit, configured to turn on when the gate driving signal of the TFT changes from a high level to a low level Passing through the two ends of the parasitic capacitance.
  • both ends of the parasitic capacitance are turned on when the gate driving signal of the TFT transitions from a high level to a low level.
  • the potentials across the parasitic capacitance are the same. In the case where the potential across the parasitic capacitance is the same, the parasitic capacitance will neither discharge nor be charged, that is, the charge integration will not occur inside the parasitic capacitance.
  • the gate drive signal of the TFT is from a high level.
  • the transition to low level does not affect the parasitic capacitance, and therefore, it does not affect the voltage on the drain and the pixel electrode electrically connected to the drain, that is, the voltage of the pixel electrode can maintain the voltage after charging. Therefore, the influence of the parasitic capacitance between the gate and the drain on the voltage of the pixel electrode is reduced, and the display effect is improved.
  • the above-mentioned switching circuit can be implemented in various ways, and several of them are described in detail below.
  • the switching circuit is implemented by only one switching unit.
  • the switch circuit of the first implementation manner includes:
  • a first switching unit 201 disposed in at least one sub-display area, wherein both ends of the first switching unit 201 are respectively connected to both ends of the parasitic capacitance C gd formed on the TFTs in the corresponding sub-display area, and are not shown
  • An external controller controls the conduction and disconnection of the first switching unit 201;
  • the parasitic capacitance C gd and the first switching unit 201 form a parallel circuit 200, one end of which is electrically connected to the drain 1032 of the TFT 103, and the other end of the parallel circuit 200 and the gate of the TFT 103! 03 ! Electrical connection;
  • the first switching unit 201 is controlled to be turned on by the external controller, and the first switching unit 201 is controlled to be turned off in other periods.
  • an external controller may be disposed corresponding to each row of gate lines, and the signal output by the external controller is synchronized with the gate driving signal of the corresponding gate line.
  • the first switching unit 201 may be a TFT element whose gate is connected to the external controller, whose source is connected to the gate 1031 of the TFT 103, and whose drain is connected to the drain 1032 of the TFT 103 or Other switching elements.
  • the first switching unit when the gate driving signal transitions from the high level to the low level, the first switching unit is turned on. Therefore, the two ends of the parasitic capacitance c gd are respectively turned on, and the potential across the parasitic capacitance is The same, so that the parasitic capacitance will neither discharge nor charge. Therefore, the level change of the gate driving signal is not conducted to the pixel electrode by the parasitic capacitance c gd , and the voltage of the pixel electrode after charging is not changed, so that the electric field between the pixel electrode and the common electrode can be maintained.
  • the gray scale display of the display sub-area is correct, and the display effect is improved.
  • the first switching unit 201 it is necessary to control the first switching unit 201 to be in a transit state only during a period in which the gate driving signal changes from a high level to a low level and is stabilized to a low level. It is necessary to keep the disconnection state in other time periods. This is briefly explained as follows.
  • the gate driving signal when the gate driving signal is at a high level, if the first switching unit 201 is turned on, the gate driving signal is applied to the pixel electrode, resulting in charging error of the pixel electrode:
  • the gate driving signal is at a low level, if the first switching unit 201 is turned on, a gate driving signal at a low level is applied to the pixel electrode, causing the pixel electrode to discharge.
  • the first switching unit 201 can only be in a conducting state during a period in which the gate driving signal changes from a high level to a low level and is stabilized to a low level, and is required in other periods of time. Is in the disconnected state. It can be found that the control precision of the pair of first switching units is higher, that is, the control precision of the external controller is higher, otherwise the voltage of the pixel electrode may be improperly changed.
  • the switch circuit of the second implementation manner includes:
  • a first switching unit 201 disposed in at least one sub-display area, wherein two ends of the first switching unit 201 are respectively connected to two ends of a parasitic capacitance C gd formed on the TFTs in the corresponding sub-display area, how to control the first switch
  • the conduction and disconnection of unit 201 will be described in detail later;
  • the parasitic capacitance C gd and the first switching unit 201 form a parallel circuit 200, one end of which is electrically connected to the drain 1032 of the TFT 103, and the other end of the parallel circuit 200 passes through the second switching unit 202 and the TFT
  • the gate 1031 is electrically connected;
  • one end of the second switching unit 202 is electrically connected to one end of the parallel circuit 200, and the other end of the second switching unit 202 is electrically connected to the gate 1031 of the TFT, and how to control the conduction and disconnection of the second switching unit 202 will be Detailed description will be given later;
  • the second switching unit 202 When the gate driving signal of the TFT in the corresponding sub-display area is at a high level, that is, in a period in which the gate driving signal is at a high level, the second switching unit 202 is controlled to be turned on, the first The switching unit 201 is turned off.
  • the gate driving signal transitions from the high level to the low level, the first switching unit 201 is turned on, and the second switching unit 202 is turned off.
  • the gate driving signal is not Passing to the pixel electrode, affecting the pixel electrode;
  • the first switching unit 201 is turned on, and the two ends of the parasitic capacitance C gd are respectively turned on, and the potentials at both ends of the parasitic capacitance are the same, so that the parasitic capacitance is neither discharged nor Will charge.
  • the level change of the gate driving signal is not conducted to the pixel electrode by the parasitic capacitance C gd , and thus the voltage of the charged pixel electrode is not changed, so that the electric field between the pixel electrode and the common electrode can be maintained.
  • the gray scale display of the display sub-area is correct, and the display effect is improved.
  • the gate driving signal of the TFT in the corresponding sub-display area is at a high level, controlling the The second switching unit 202 is turned on, and the first switching unit 201 is turned off.
  • the actual equivalent circuit corresponds to the equivalent circuit shown in FIG. 1, and thus the entire array substrate operates normally.
  • the switching circuit illustrated in FIG. 3 can be controlled in two ways.
  • an external controller can be separately provided for each row of gate lines, and the signal output by the external controller and the gate drive of the corresponding gate line are driven.
  • Signal synchronization as shown in FIG. 3, the corresponding first switching unit is the first TFT that is turned off when the gate is in the high level control, and the second switching unit is the second TFT that is turned on when the gate is in the high level control
  • the gates of the first TFT and the second TFT are connected to an external controller, and the signal output by the external controller is synchronized with the gate driving signal.
  • the control signal is synchronized with the gate drive signal, that is, the control signal is the same as the gate drive signal, therefore, when the gate drive signal is at the high level ⁇ , the control signal is also at the high level, therefore,
  • the first TFT ie, the first switching unit 201
  • the second TFT ie, the second switching unit 202
  • the control signal When the gate driving signal jumps from a high level, the control signal also jumps. Therefore, the first TFT (ie, the first switching unit 201) is turned on, and the second TFT (ie, the second switching unit 202) is turned off. Therefore, the two ends of the parasitic capacitance are guided away, and the electric charge movement inside the parasitic capacitance is prevented, so that the electric field between the pixel electrode and the common electrode can be maintained.
  • the control signal is also at a low level, so that the first TFT (ie, the first switching unit 201) is turned on, and the second TFT (ie, the second switching unit 202) is turned off.
  • the gate drive signal of the low level does not pass through the output of the second switch unit to the pixel electrode, so the pixel electrode voltage does not change during the sustain phase, and the array substrate operates normally.
  • the control of the switching circuit illustrated in FIG. 3 can also be directly controlled by the gate driving signal, which is the most compact.
  • the first switching unit is in the gate. a first TFT that is turned off when the high level is controlled, and a second TFT that is turned on when the gate is at the high level control, and the gates of the first and second TFTs are electrically connected to the gate line connection.
  • the embodiment of the invention further discloses a display panel comprising any of the array substrates described above.
  • an embodiment of the present invention further discloses a display device including the above display panel.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any display product or component.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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  • Liquid Crystal (AREA)

Abstract

提供了一种阵列基板、显示面板和显示装置。阵列基板包括：将显示区域划分为多个子显示区域的多根数据线（102）和多根栅线（101）；设置于每一个子显示区域中的像素电极（104）；和设置于每一个子显示区域中，源极与数据线（102）电连接，漏极（1032）与像素电极（104）电连接，栅极（1031）与栅线（101）电连接的TFT（103）；TFT（103）的栅极（1031）与漏极（1032）之间形成有寄生电容（Cgd），阵列基板还包括：一开关电路，用于在TFT（103）的栅极驱动信号从高电平向低电平转变时，导通寄生电容（Cgd）的两端，因此降低了栅极（1031）和漏极（1032）之间的寄生电容（Cgd）对像素电极（104）的电压的影响，提高了显示效果。

Description

本发明涉及显示技术领域， 特别是一种阵列基板、显示面板和显示装置。
基于液晶的显示装置是目前被广泛使用的一种平面显示器， 与其他显示 方式相比， 其具有低功耗、 重量轻、 无辐射等优点。
基于液晶的显示装置一般包括阵列基板、 彩膜基板及液晶层。 如图 1所 示， 阵列基板上的显示区域包含多个子显示区域， 每个子显示区域一般为两 条栅线 101 (扫描线） 与两条数据线 102交叉包围形成。
如图 i所示， 子显示区域内部设置有薄膜晶体管 103和像素电极 104。 遥过控制施加在彩膜基板上的公共电极和 /或像素电极 104上的电压， 来控制 施加于彩膜基板和阵列基板之间的电场强度，进而控制液晶分子的偏转方向。
工作时， 在栅极驱动信号的控制下， TFT (薄膜场效应晶体管)导遥， 对应 行的数据电压由源极驱动送至对应的像素电极 104上， 改变彩膜基板和阵列 基板之间的电场强度， 进而影响液晶的偏转。
然而， 在阵列基板的结构中， 薄膜晶体管 103的栅极 1031 与漏极 1032 的部分区域相对， 这样在栅极 1031与漏极 1032之间的电压出现变化时， 就 会产生寄生电容 Cgd， 其等效电路如图 i所示。
在栅极从打开电压 Vgh变化到关断电压 的 ^刻， 由于栅极上电压的突 然改变， 会使得寄生电容 Cgd内部的电荷移动， 而一旦电荷移动就会导致 Cgd 两端的电压发生变化， 而这种电压变化会由漏极传导到像素电极 104， 导致 彩膜基板和阵列基板之间的电场强度发生变化， 而彩膜基板和阵列基板之间 的电场强度发生变化又会导致液晶分子的偏转角度发生变动， 从而影响透过 率， 导致图像的灰度显示不准确。
本发明实施例的目的在于提供一种阵列基板、 显示面板和显示装置， 降 为了实现上述目的， 本发明实施例提供了一种阵列基板， 包括： 将显示区域划分为多个子显示区域的多根数据线和多根栅线；
设置于每一个子显示区域中的像素电极； 和
一个子显示区域中， 源极与数据线电连接、 漏极与像素电极电
Figure imgf000004_0001
所述 TFT的栅极与漏极之间形成有寄生电容， 所述阵列基板还包括： 一开关电路，用于在所述 TFT的栅极驱动信号从高电平向低电平转变时, 导通所述寄生电容的两端。
上述的阵列基板， 其中， 所述开关电路包括：
设置于至少一个子显示区域中的第一开关单元， 该第一开关单元与对应 子显示区域中的所述 TFT上形成的寄生电容并联；
所述寄生电容与第一开关单元形成的并联电路的一端与所述 TFT的漏极 电连接， 另一端与所述 TFT的栅极电连接；
当对应子显示区域中的所述 TFT的栅极驱动信号从高电平向低电平转变 时， 所述第一开关单元导通， 在除此以外的时间所述第一开关单元断开。
上述的阵列基板， 其中， 通过外部控制器来控制所述第一开关单元在所 述栅极驱动信号从高电平向低电平转变时导通、 在除此以外的时间断开。
上述的阵列基板， 其中， 每一行栅线对应设置有一个所述外部控制器， 所述外部控制器输出的信号与对应栅线的栅极驱动信号同步。
上述的阵列基板， 其中， 所述第一开关单元为栅极与所述外部控制器连 接、 源极与所述 TFT的栅极连接、 漏极与所述 TFT的漏极连接的 TFT元件。
上述的阵列基板， 其中， 所述开关电路包括：
设置于至少一个子显示区域中的第一开关单元， 该第一开关单元与对应 子显示区域中的所述 TFT上形成的寄生电容并联；
与第一开关单元对应设置的第二开关单元；
所述寄生电容和第一开关单元形成的并联电路的一端与所述 TFT的漏极 电连接， 另一端通过所述第二开关单元与所述 TFT的栅极电连接；
当对应子显示区域中的所述 TFT的栅极驱动信号从高电平向低电平转变 0寸， 所述第一开关单元导通， 所述第二开关单元断开。
上述的阵列基板， 其中， 所述第一开关单元为栅极处于高电平控制时断 开的第一 TFT， 第二开关单元为栅极处于高电平控制时导通的第二 TFT， 所 述第一 TFT和第二 TFT的栅极与所述栅线电连接。
上述的阵列基板， 其中， 每一行栅线对应设置有一个外部控制器， 所述 外部控制器输出的信号与对应栅线的栅极驱动信号同步， 所述第一开关单元 为栅极处于高电平控制时断开的第一 TFT， 第二开关单元为栅极处于高电平 控制日寸导通的第二 TFT，所述第一 TFT和第二 TFT的栅极与所述外部控制器 连接。
为了更好地实现上述目的， 本发明实施例还提供了一种显示面板， 包括 上述任意的阵列基板。
为了更好地实现上述目的， 本发明实施例还提供了一种显示装置， 包括 上述的显示面板。
本发明实施例至少具有如下的有益效果：
由于开关电路的存在， 其在 TFT的栅极驱动信号从高电平向低电平转变 时， 导通寄生电容的两端。 而寄生电容的两端一旦导通， 则寄生电容两端的 电位相同。 在寄生电容两端电位相同的情况下， 寄生电容既不会放电， 也不 会充电， 也就是说， 寄生电容内部不会发生电荷的移动。 由于 TFT的栅极驱 动信号从高电平向低电平的转变不会影响寄生电容， 因此， 也就不会对漏极 以及与漏极电连接的像素电极上的电压产生影响， 即像素电极的电压能够维 持充电后的电压不变， 因此， 降低了栅极和漏极之间的寄生电容对像素电极
Figure imgf000005_0001
图 1表示现有的阵列基板的等效电路图；
图 2表示本发明实施例的一种阵列基板的等效电路图；
图 3表示本发明实施例的另一种阵列基板的等效电路图 本发明实施例的阵列基板、 显示面板和显示装置中， 设置一开关电路， 在 TFT的栅极驱动信号从高电平向低电平转变时，导通所述寄生电容的两端， 使得寄生电容内部不会发生电荷移动的现象， 因此， 降低了栅极和漏极之间 的寄生电容对像素电极的电压的影响， 提高了显示效果。
本发明实施例的阵列基板， 包括：
将显示区域划分为多个子显示区域的多根数据线和多根栅线；
设置于每一个子显示区域中的像素电极； 和
设置于每一个子显示区域中， 源极与数据线电连接、 漏极与像素电极电 连接、 栅极与栅线电连接的 TFT;
所述 TFT的栅极与漏极之间形成有寄生电容， 所述阵列基板还包括： 一开关电路，用于在所述 TFT的栅极驱动信号从高电平向低电平转变时， 导通所述寄生电容的两端。
在本发明的具体实施例中， 由于开关电路的存在， 其在 TFT的栅极驱动 信号从高电平向低电平转变时， 导通寄生电容的两端。 而寄生电容的两端一 旦导通， 则寄生电容两端的电位相同。 在寄生电容两端电位相同的情况下， 寄生电容既不会放电， 也不会充电， 也就是说， 寄生电容内部不会发生电荷 综合以上描述可以发现， TFT的栅极驱动信号从高电平向低电平的转变 不会影响寄生电容， 因此， 也就不会对漏极以及与漏极电连接的像素电极上 的电压产生影响， 即像素电极的电压能够维持充电后的电压不变， 因此， 降 低了栅极和漏极之间的寄生电容对像素电极的电压的影响，提高了显示效果。
在本发明的具体实施例中， 上述的开关电路可以通过多种方式实现， 在 此对其中的几种方式详细说明如下。
<开关电路实现方式一 >
在实现方式一中， 仅通过一个开关单元来实现开关电路。
如图 2所示， 实现方式一的开关电路包括：
设置于至少一个子显示区域中的第一开关单元 201， 第一开关单元 201 的两端分别与对应子显示区域中的 TFT上形成的寄生电容 Cgd的两端连接， 并且通过未图示的外部控制器来控制第一开关单元 201的导通与断开； 所述寄生电容 Cgd和第一开关单元 201形成并联电路 200， 并联电路 200 的一端与 TFT 103的漏极 1032电连接，并联电路 200的另一端与 TFT 103的 栅极！03 !电连接；
当对应子显示区域中的 TFT的栅极驱动信号认高电平向低电平转变时， 即，在栅极驱动信号从高电平向低电平变化且稳定为低电平为止的时间段内， 通过所述外部控制器控制所述第一开关单元 201导通， 在除此以外的时间段 内控制所述第一开关单元 201断开。
此外， 可以每一行栅线对应设置有一个外部控制器， 外部控制器输出的 信号与对应栅线的栅极驱动信号同步。
此外， 如图 2所示， 第一开关单元 201可以是栅极与所述外部控制器连 接、 源极与 TFT 103的栅极 1031连接、 漏极与 TFT 103的漏极 1032连接的 TFT元件或其它开关元件。
在上述的实现方式一中， 当栅极驱动信号从高电平向低电平转变时， 第 一开关单元导通， 因此， 寄生电容 cgd的两端相应导通， 则寄生电容两端的 电位相同， 使得寄生电容既不会放电， 也不会充电。 因此， 栅极驱动信号的 电平变化不会由寄生电容 cgd传导到像素电极， 也就不会改变充电后的像素 电极的电压， 使得像素电极与公共电极之间的电场能够维持不变， 实现显示 子区域的灰度显示正确， 提高了显示效果。
<开关电路实现方式二 >
在上述的实现方式一中， 需要控制第一开关单元 201仅在栅极驱动信号 从高电平向低电平变化且稳定为低电平为止的时间段内处于导遥状态， 而在 除此以外的时间段内都需要保持断开状态， 对此简要说明如下。
以图 2所示的结构为例， 当栅极驱动信号处于高电平时， 第一开关单元 201 如果导通， 则会导致栅极驱动信号施加到像素电极， 导致像素电极的充 电错误:， 而栅极驱动信号处于低电平时， 第一开关单元 201如果导通， 则会 导致处于低电平的栅极驱动信号施加到像素电极， 导致像素电极放电。
因此， 第一开关单元 201只能在栅极驱动信号从高电平向低电平变化且 稳定为低电平为止的时间段内处于导通状态， 而在除此以外的时间段内都需 要处于断开状态。 可以发现， 实现方式一对第一开关单元的控制精度要求较高， 即对外部 控制器的控制精度要求较高， 否则可能导致像素电极的电压产生不恰当的改 变。
为了降低控制精度， 在本发明的具体实施例中， 如图 3所示， 实现方式 二的开关电路包括：
设置于至少一个子显示区域中的第一开关单元 201， 第一开关单元 201 的两端分别与对应子显示区域中的 TFT上形成的寄生电容 Cgd的两端连接， 关于如何控制第一开关单元 201的导通与断开将在后文进行详细说明；
所述寄生电容 Cgd和第一开关单元 201形成并联电路 200， 并联电路 200 的一端与 TFT 103的漏极 1032电连接，并联电路 200的另一端通过所述第二 开关单元 202与所述 TFT的栅极 1031电连接；
即， 第二开关单元 202的一端与并联电路 200的一端电连接， 第二开关 单元 202的另一端与 TFT的栅极 1031 电连接， 关于如何控制第二开关单元 202的导通与断开将在后文进行详细说明；
当对应子显示区域中的 TFT的栅极驱动信号从高电平向低电平转变时， 即，在栅极驱动信号从高电平向低电平变化—且.稳定为低电平为止的时间段内， 控制所述第一开关单元 201导通、 所述第二开关单元 202断开；
当对应子显示区域中的 TFT的栅极驱动信号处于高电平^, 即， 在栅极 驱动信号为高电平的时间段内， 控制所述第二开关单元 202导通、 所述第一 开关单元 201断开。
在上述的实现方式二中， 当栅极驱动信号从高电平向低电平转变时， 第 一开关单元 201导通， 所述第二开关单元 202断开， 首先， 栅极驱动信号不 会传递到像素电极， 对像素电极产生影响； 其次， 第一开关单元 201导通， 寄生电容 Cgd的两端相应导通， 则寄生电容两端的电位相同， 使得寄生电容 既不会放电， 也不会充电。 因此， 栅极驱动信号的电平变化不会由寄生电容 Cgd传导到像素电极， 也就不会改变充电后的像素电极的电压， 使得像素电极 与公共电极之间的电场能够维持不变， 实现显示子区域的灰度显示正确， 提 高了显示效果。
而当对应子显示区域中的 TFT的栅极驱动信号处于高电平时， 控制所述 第二开关单元 202导通、 所述第一开关单元 201断开， 此时实际的等效电路 相当于图 1所示的等效电路， 因此整个阵列基板正常工作。
上述方式与图 2所示的电路结果相比， 其控制方式更加灵活和简单。 图 3所示意的开关电路可以通过两种方式实现控制， 一种方式下， 可以 为每一行栅线单独设置有一个外部控制器， 所述外部控制器输出的信号与对 应栅线的栅极驱动信号同步， 如图 3所示， 对应的第一开关单元为栅极处于 高电平控制时断开的第一 TFT， 第二开关单元为栅极处于高电平控制时导通 的第二 TFT, 所述第一 TFT和第二 TFT的栅极与外部控制器连接， 所述外部 控制器输出的信号与栅极驱动信号同步。
这种方式下， 由于控制信号与栅极驱动信号同步， 也就是说控制信号与 栅极驱动信号相同， 因此， 当栅极驱动信号处于高电平^, 控制信号也处于 高电平， 因此， 第一 TFT (即第一开关单元 201 ) 断开， 而第二 TFT (即第 二开关单元 202 ) 导通， 此时相当于图 i所示的电路结构， 阵列基板正常工 作。
而当栅极驱动信号从高电平跳变时，控制信号也会跳变，因此，第一 TFT (即第一开关单元 201 ) 导通， 而第二 TFT (即第二开关单元 202) 断开， 因 此， 使得寄生电容的两端导遥， 阻止了寄生电容内部的电荷运动， 也就使得 像素电极与公共电极之间的电场能够维持不变。
而当栅极驱动信号处于低电平^, 控制信号也处于低电平， 因此， 第一 TFT (即第一开关单元 201 )导通， 而第二 TFT (即第二开关单元 202)断开， 此时低电平的栅极驱动信号的不会遥过第二开关单元输出到像素电极， 因此 在维持阶段， 像素电极电压也不会发生变化， 阵列基板正常工作。
作为另一种控制方式， 图 3所示意的开关电路的控制也可以直接通过栅 极驱动信号来控制， 这种方式实现最为筒单， 这种方式下， 所述第一开关单 元为栅极处于高电平控制时断开的第一 TFT, 第二开关单元为栅极处于高电 平控制时导通的第二 TFT,所述第一 TFT和第二 TFT的栅极与所述栅线电连 接。
这种控制方式与第一种控制方式的区别仅在于控制信号的区别， 其工作 方式完全相同， 在此不再重复描述。 本发明实施例还公开了一种显示面板， 包括上述任意的阵列基板。
同时， 本发明实施例还公开了一种显示装置， 包括上述的显示面板。 所 述显示装置可以为： 液晶面板、 电子纸、 OLED 面板、 手机、 平板电脑、 电 视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品 或部件。
以上所述仅是本发明的实施方式， 应当指出， 对于本技术领域的普通技 术人员来说， 在不脱离本发明原理的前提下， 还可以作出若干改进和润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1. 一种阵列基板， 包括：
将显示区域划分为多个子显示区域的多根数据线和多根栅线；
设置于每一个子显示区域中的像素电极； 和
设置于每一个子显示区域中， 源极与数据线电连接、 漏极与像素电极电 连接、 栅极与栅线电连接的薄膜场效应晶体管 TFT;
所述 TFT的栅极与漏极之间形成有寄生电容，
其特征在于， 所述阵列基板还包括：
一开关电路，用于在所述 TFT的栅极驱动信号从高电平向低电平转变时, 导通所述寄生电容的两端。
2, 根据权利要求 1所述的阵列基板， 其特征在于， 所述开关电路包括： 设置于至少一个子显示区域中的第一开关单元， 该第一开关单元与对应 子显示区域中的所述 TFT上形成的寄生电容并联；
所述寄生电容与第一开关单元形成的并联电路的一端与所述 TFT的漏极 电连接， 另一端与所述 TFT的栅极电连接；
当对应子显示区域中的所述 TFT的栅极驱动信号从高电平向低电平转变 时， 所述第一开关单元导通， 在除此以外的时间所述第一开关单元断开。
3. 根据权利要求 2所述的阵列基板， 其特征在于，
通过外部控制器来控制所述第一开关单元在所述栅极驱动信号从高电平 向低电平转变时导通、 在除此以外的时间断开。
4, 根据权利要求 3所述的阵列基板， 其特征在于，
每一行栅线对应设置有一个所述外部控制器， 所述外部控制器输出的信 号与对应栅线的栅极驱动信号同步。
5. 根据权利要求 4所述的阵列基板， 其特征在于，
所述第一开关单元为栅极与所述外部控制器连接、 源极与所述 TFT的栅 极连接、 漏极与所述 TFT的漏极连接的 TFT元件。
6, 根据权利要求 1所述的阵列基板， 其特征在于， 所述开关电路包括： 设置于至少一个子显示区域中的第一开关单元， 该第一开关单元与对应 子显示区域中的所述 TFT上形成的寄生电容并联；
与第一开关单元对应设置的第二开关单元；
所述寄生电容和第一开关单元形成的并联电路的一端与所述 TFT的漏极 电连接， 另一端通过所述第二开关单元与所述 TFT的栅极电连接；
当对应子显示区域中的所述 TFT的栅极驱动信号从高电平向低电平转变 时， 所述第一开关单元导通， 所述第二开关单元断开。
7. 根据权利要求 6所述的阵列基板， 其特征在于， 所述第一开关单元为 栅极处于高电平控制日寸断开的第一 TFT, 第二开关单元为栅极处于高电平控 制时导通的第二 TFT, 所述第一 TFT和第二 TFT的栅极与所述栅线电连接。
8. 根据权利要求 6所述的阵列基板， 其特征在于， 每一行栅线对应设置 有一个外部控制器， 所述外部控制器输出的信号与对应栅线的栅极驱动信号 同步， 所述第一开关单元为栅极处于高电平控制时断开的第一 TFT, 第二开 关单元为栅极处于高电平控制时导通的第二 TFT， 所述第一 TFT和第二 TFT 的栅极与所述外部控制器连接。
9. 一种显示面板， 包括权利要求 1-8中任意一项所述的阵列基板。
10. 一种显示装置， 包括权利要求 9所述的显示面板。
PCT/CN2013/089660 2013-07-01 2013-12-17 一种阵列基板、显示面板和显示装置 WO2015000273A1 (zh)

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