WO2016078230A1 - 提升不良检出率的像素结构及检测方法 - Google Patents

提升不良检出率的像素结构及检测方法 Download PDF

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Publication number
WO2016078230A1
WO2016078230A1 PCT/CN2015/072367 CN2015072367W WO2016078230A1 WO 2016078230 A1 WO2016078230 A1 WO 2016078230A1 CN 2015072367 W CN2015072367 W CN 2015072367W WO 2016078230 A1 WO2016078230 A1 WO 2016078230A1
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pixel
electrically connected
charge sharing
electrode plate
thin film
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PCT/CN2015/072367
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English (en)
French (fr)
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王醉
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深圳市华星光电技术有限公司
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Priority to US14/423,431 priority Critical patent/US9523899B2/en
Publication of WO2016078230A1 publication Critical patent/WO2016078230A1/zh

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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136259—Repairing; Defects
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel structure and a detection method for improving a poor detection rate.
  • LCD Liquid Crystal Display
  • LCD TVs mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens, etc.
  • PDAs personal digital assistants
  • liquid crystal displays which include a casing, a liquid crystal display panel disposed in the casing, and a backlight module disposed in the casing.
  • the liquid crystal display panel is the main component of the liquid crystal display, but the liquid crystal display panel itself does not emit light, and the light source provided by the backlight module needs to be used to display the image normally.
  • a liquid crystal display panel is formed by laminating two glass substrates, and liquid crystal is poured between two glass substrates, and pixel electrodes and a common electrode are respectively disposed on opposite sides of the two glass substrates, and liquid crystal molecules are controlled by energization or not. Change the direction and refract the light from the backlight module to produce a picture.
  • the prior art adopts a charge sharing pixel design, that is, the pixel is divided into a main pixel (Main Pixel) 100 and a sub-pixel.
  • the main pixel 100 has a first thin film transistor T1 electrically connected to each other, a first storage capacitor C ST1 , and a first liquid crystal capacitor C LC1
  • the second pixel 200 has a second thin film transistor T2
  • the second storage capacitor C ST2 , the second liquid crystal capacitor C LC2 , the charge sharing thin film transistor T3 , and the charge sharing capacitor C ST3 , the gates of the first thin film transistor T1 and the second thin film transistor T2 are electrically connected to the charging
  • the scan line Gate1(m) and the source are electrically connected to the data signal line Date(n), m and n are positive integers, Gate1(m) represents the mth charging scan line Gate1, and Date(n) represents the nth.
  • first storage capacitor C ST1 , the second storage capacitor C ST2 , and the charge sharing capacitor C ST3 are electrically connected to the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2, respectively.
  • Pole and charge sharing thin film transistor T3 The drain is electrically connected to the common voltage signal line Com(m); the gate of the charge sharing thin film transistor T3 is electrically connected to the charge sharing scan line Gate2(m), and the drain is electrically connected to the charge Shared capacitor C ST3 .
  • the charge scan line Gate1(m) is turned on while the charge share scan line Gate2(m) is turned off, and the main pixel 100 and the sub-pixel 200 are charged to the same potential; then the charge scan line Gate1(m) is turned off while charge sharing scanning line Gate2 (m) to open due to the effect of the charge sharing capacitance C ST3 so that a potential lower than the potential of the sub-pixels 200 of the main pixel 100.
  • the different potentials cause the liquid crystal molecules in the two display regions to have different steering distributions, thereby having the effect of improving the bias of the large-view character. As shown in FIG. 2 and FIG.
  • the charge sharing capacitor C ST3 in the pixel using the charge sharing technology is composed of an indium tin oxide (ITO) layer upper electrode plate 420 and a metal layer lower electrode plate 20 . And an insulating layer 30 sandwiched between two layers, wherein the ITO layer upper electrode plate 420 and the ITO pixel electrode 410 are in the same layer, and the ITO layer upper electrode plate 420 passes through the via (VIA) 305 and the charge sharing transistor T3 The pole layer is connected, and the metal layer lower electrode plate 20 is connected as a pixel common electrode to the common voltage signal line Com(m).
  • ITO indium tin oxide
  • an ITO residual problem may occur in actual production, causing the ITO layer upper electrode plate 420 of the charge sharing capacitor C ST3 to be short-circuited with the ITO pixel electrode 410, resulting in failure of the charge sharing function.
  • the sub-pixels of the pixels with the short-circuit problem in the gray scale are brighter than the sub-pixels of the other pixels, and the micro-brightness phenomenon appears on the liquid crystal display panel.
  • the commonly used detection method is to open all the charging scan lines at the same time or to open the parity, and charge all the pixels or all the corresponding parity rows, so that the main pixel and the sub-pixel are at the same potential, in this detection mode. Even if the short circuit between the above ITOs occurs, it cannot be effectively detected, resulting in a decrease in yield and an increase in product cost.
  • An object of the present invention is to provide a pixel structure for improving a poor detection rate, which can improve a detection rate of a short circuit between an electrode plate on an ITO layer and an ITO pixel electrode of a charge sharing capacitor, improve a micro-brightness problem of a product, and improve a yield. cut costs.
  • Another object of the present invention is to provide a detection method for improving the detection rate of defects, which can improve the detection rate of short circuit between the electrode plate on the ITO layer and the ITO pixel electrode of the charge sharing capacitor, improve the problem of product micro-brightness, and improve the yield. ,cut costs.
  • the present invention provides a pixel structure for improving a poor detection rate, comprising two regions of a main pixel and a sub-pixel, wherein the sub-pixel has a charge sharing thin film transistor and a charge sharing capacitor; and the charge sharing film
  • the gate of the transistor is electrically connected to the charge sharing scan line;
  • the charge sharing capacitor is composed of an upper electrode plate of the ITO layer, a lower electrode plate of the metal layer, and a sandwich between the upper electrode plate of the ITO layer and the lower electrode plate of the metal layer.
  • An insulating layer is formed; the upper electrode plate of the ITO layer is in the same layer as the ITO pixel electrode, and the upper electrode plate of the ITO layer is connected as a pixel common electrode to a common voltage signal line, and the lower electrode plate of the metal layer is connected to the charge sharing transistor of Drain.
  • the upper electrode plate of the ITO layer is connected as a pixel common electrode to a common voltage signal line through a via.
  • the second sub-pixel further has a second thin film transistor electrically connected to each other, a second storage capacitor, and a second liquid crystal capacitor; the gate of the second thin film transistor is electrically connected to the charging scan line, and the source is electrically connected a drain is electrically connected to a source of the charge sharing thin film transistor; a second end of the second storage capacitor is electrically connected to a drain of the second thin film transistor, and the other end is electrically connected to the common voltage signal. line.
  • the main pixel has a first thin film transistor electrically connected to each other, a first storage capacitor, and a first liquid crystal capacitor; a gate of the first thin film transistor is electrically connected to the charging scan line, and the source is electrically connected to the source a data signal line; one end of the first storage capacitor is electrically connected to the drain of the first thin film transistor, and the other end is electrically connected to the common voltage signal line.
  • the ITO pixel electrode When the ITO pixel electrode is short-circuited with the upper electrode plate of the ITO layer of the charge sharing capacitor, the corresponding sub-pixel is displayed as a dark spot.
  • the invention also provides a detection method for improving the bad detection rate, comprising the following steps:
  • Step 1 providing a liquid crystal display panel to be detected, the liquid crystal display panel comprising a plurality of charging scan lines, a plurality of common voltage signal lines, a plurality of charge sharing scanning lines, a plurality of data signal lines, and a plurality of arrays arranged in an array a pixel; each pixel includes two regions of a main pixel and a sub-pixel, wherein the sub-pixel has a charge sharing thin film transistor and a charge sharing capacitor; a gate of the charge sharing thin film transistor is electrically connected to the charge sharing scan line;
  • the charge sharing capacitor is composed of an ITO layer upper electrode plate, a metal layer lower electrode plate, and an insulating layer sandwiched between the upper ITO layer electrode plate and the metal layer lower electrode plate; the ITO layer upper electrode plate and ITO The pixel electrodes are on the same layer;
  • Step 2 connecting the upper ITO layer electrode plate of the charge sharing capacitor as a pixel common electrode to a common voltage signal line, and connecting the metal layer lower electrode plate to a drain of the charge sharing transistor;
  • Step 3 Turn all charging scan lines on at the same time or open parity, and charge all pixels or all corresponding parity rows, so that the main pixels and the sub-pixels are at the same potential;
  • Step 4 detecting a dark spot on the liquid crystal display panel, and detecting that the ITO pixel electrode in the sub-pixel corresponding to the dark spot and the electrode plate on the ITO layer of the charge sharing capacitor are short-circuited.
  • the upper electrode plate of the ITO layer is connected as a pixel common electrode to a common voltage signal line through a via.
  • the second sub-pixel further has a second thin film transistor electrically connected to each other, a second storage capacitor, and a second liquid crystal capacitor; the gate of the second thin film transistor is electrically connected to the charging scan line, and the source is electrically connected In the data signal line, the drain is electrically connected to the charge sharing thin film transistor
  • the first storage capacitor has one end electrically connected to the drain of the second thin film transistor and the other end electrically connected to the common voltage signal line.
  • the main pixel has a first thin film transistor electrically connected to each other, a first storage capacitor, and a first liquid crystal capacitor; a gate of the first thin film transistor is electrically connected to the charging scan line, and the source is electrically connected to the source a data signal line; one end of the first storage capacitor is electrically connected to the drain of the first thin film transistor, and the other end is electrically connected to the common voltage signal line.
  • the present invention provides a pixel structure and a detection method for improving a poor detection rate, and an upper electrode plate of an ITO layer of a charge sharing capacitor is connected as a pixel common electrode to a common voltage signal line, and a charge sharing capacitor is used.
  • the lower electrode plate of the metal layer is connected to the charge sharing transistor, so that when the ITO pixel electrode is short-circuited with the electrode plate on the ITO layer of the charge sharing capacitor, the corresponding sub-pixel is displayed as a dark point, and the dark spot is more easily detected, which can improve the charge sharing capacitance.
  • the detection rate of short circuit between the electrode plate on the ITO layer and the ITO pixel electrode improves the micro-brightness problem of the product, improves the yield, and reduces the cost.
  • 1 is an equivalent circuit diagram of a conventional charge sharing pixel structure
  • FIG. 2 is a schematic cross-sectional view showing a charge sharing capacitor in a conventional charge sharing pixel structure
  • FIG. 3 is a top plan view corresponding to FIG. 2;
  • FIG. 4 is an equivalent circuit diagram of a pixel structure for improving a poor detection rate according to the present invention.
  • FIG. 5 is a schematic cross-sectional view showing a charge sharing capacitor in a pixel structure for improving a poor detection rate according to the present invention
  • Figure 6 is a top plan view corresponding to Figure 5;
  • FIG. 7 is a flow chart of a method for detecting a poor detection rate according to the present invention.
  • the present invention provides a pixel structure for improving a poor detection rate, including two regions of a main pixel 10 and a sub-pixel 20.
  • the main pixel 10 has a first thin film transistor T1 electrically connected to each other, a first storage capacitor C ST1 , and a first liquid crystal capacitor C LC1 ; the sub-pixel 20 has a second thin film transistor T2 and a second storage capacitor C ST2 . a second liquid crystal capacitor C LC2 , a charge sharing thin film transistor T3 , and a charge sharing capacitor C ST3 .
  • the gates of the first thin film transistor T1 and the second thin film transistor T2 are electrically connected to the charging scan line Gate1(m), and the source is electrically connected to the data signal line Date(n). Both m and n are positive. Integer, Gate1(m) represents the mth charging scan line Gate1, and Date(n) represents the nth data signal line Date; the first storage capacitor CST1 , the second storage capacitor CST2 , and the charge sharing capacitor CST3 One end is electrically connected to the drain of the first thin film transistor T1, the drain of the second thin film transistor T2, and the drain of the charge sharing thin film transistor T3, and the other end is electrically connected to the common voltage signal line Com(m).
  • Com(m) represents the mth common voltage signal line Com; the gate of the charge sharing thin film transistor T3 is electrically connected to the charge sharing scan line Gate2(m), and the source is electrically connected to the drain of the second thin film transistor T2
  • the pole, Gate2(m) represents the mth charge-sharing scan line Gate2.
  • the charge sharing capacitor C ST3 is composed of an ITO layer upper electrode plate 42, a metal layer lower electrode plate 2, and an insulating layer 3 sandwiched between the ITO layer upper electrode plate 42 and the metal layer lower electrode plate 2.
  • the metal layer lower electrode plate 2 and the insulating layer 3 are both formed on a glass substrate 1.
  • the ITO layer upper electrode plate 42 and the ITO pixel electrode 41 are located in the same layer, and the ITO layer upper electrode plate 42 is connected as a pixel common electrode to a common voltage signal line Com(m) through a via 35, the metal layer
  • the lower electrode plate 2 is connected to the drain of the charge sharing transistor T3. This structure is opposite to the prior art in which the upper ITO layer electrode plate of the charge sharing capacitor is connected to the drain of the charge sharing transistor, and the metal layer lower electrode plate of the charge sharing capacitor is connected to the common voltage signal line.
  • the charge scan line Gate1(m) is turned on while the charge share scan line Gate2(m) is turned off, the main pixel 10 and the sub-pixel 20 are charged to the same potential; then the charge scan line Gate1(m) ) is closed, while the charge-sharing scanning line Gate2 (m) is opened, since the charge sharing effect so that the potential of the capacitor C ST3 sub-pixel 20 is lower than the potential of the pixel 10 is main.
  • the different potentials cause the liquid crystal molecules in the two display regions to have different steering distributions, thereby having the effect of improving the bias of the large-view character.
  • the ITO pixel electrode 41 is electrically connected to the ITO layer upper electrode plate 42 as the pixel common electrode, and simultaneously with the common voltage.
  • the signal line Com(m) is turned on, so that the corresponding sub-pixel 20 which is short-circuited under the same gray level appears as a dark point on the liquid crystal display panel, and the dark point is more easily detected than the micro-bright point, which is convenient for timely repairing.
  • the detection rate of short-circuit between the electrode plate 42 and the ITO pixel electrode 41 on the ITO layer of the charge-sharing capacitor C ST3 can be improved, the problem of product micro-brightness can be improved, the yield can be improved, and the cost can be reduced.
  • the present invention further provides a method for detecting a poor detection rate, including the following steps:
  • Step 1 Provide a liquid crystal display panel to be detected.
  • the liquid crystal display panel includes a plurality of charging scan lines Gate1(m), a plurality of common voltage signal lines Com(m), a plurality of charge sharing scanning lines Gate2(m), a plurality of data signal lines Date(n), and a plurality of Arranged pixels in an array.
  • Each pixel includes two regions of a main pixel 10 and a sub-pixel 20.
  • the main pixel 10 has a first thin film transistor T1 electrically connected to the first, a first storage capacitor C ST1 , and a first liquid crystal capacitor C LC1 .
  • the sub-pixel 20 has a second thin film transistor T2 and a second storage capacitor C ST2 .
  • a second liquid crystal capacitor C LC2 a charge sharing thin film transistor T3 , and a charge sharing capacitor C ST3 .
  • the charge sharing capacitor C ST3 is composed of an ITO layer upper electrode plate 42, a metal layer lower electrode plate 2, and an insulating layer 3 sandwiched between the ITO layer upper electrode plate 42 and the metal layer lower electrode plate 2.
  • the ITO layer upper electrode plate 42 and the ITO pixel electrode 41 are located in the same layer.
  • the gates of the first thin film transistor T1 and the second thin film transistor T2 are electrically connected to the charging scan line Gate1(m), and the source is electrically connected to the data signal line Date(n); the first storage capacitor C ST1 and one end of the second storage capacitor C ST2 are electrically connected to the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2, respectively, and the other end is electrically connected to the common voltage signal line Com(m).
  • the gate of the charge sharing thin film transistor T3 is electrically connected to the charge sharing scan line Gate2(m), and the source is electrically connected to the drain of the second thin film transistor T2.
  • Step 2 the ITO layer upper electrode plate 42 of the charge sharing capacitor C ST3 is connected as a pixel common electrode to the common voltage signal line Com(m) through a via 35, and the metal layer lower electrode plate 2 is connected to the charge.
  • the drain of transistor T3 is shared.
  • Step 3 Turn on all the charging scan lines Gate1(m) at the same time or divide them into parity, and charge all the pixels or all the corresponding parity rows, so that the main pixels 10 and the sub-pixels 20 are at the same potential.
  • Step 4 detecting a dark spot on the liquid crystal display panel, and detecting that the ITO pixel electrode 41 in the sub-pixel 20 corresponding to the dark spot and the ITO layer upper electrode plate 42 of the charge sharing capacitor C ST3 are short-circuited.
  • the ITO pixel electrode 41 is electrically connected to the ITO layer upper electrode plate 42 as a pixel common electrode, and simultaneously with the common voltage signal line Com ( m) conducting, causing the corresponding sub-pixel 20 which is short-circuited under the same gray level to appear as a dark point on the liquid crystal display panel, and the dark point is more easily detected than the micro-bright point, and the charge sharing capacitor C ST3 can be improved.
  • the detection rate of the short circuit between the electrode plate 42 and the ITO pixel electrode 41 on the ITO layer improves the micro-brightness problem of the product, improves the yield, and reduces the cost.
  • the pixel structure and the detection method for improving the poor detection rate of the present invention connect the upper electrode plate of the ITO layer of the charge sharing capacitor as a common electrode of the pixel to the common voltage signal. a line connecting the lower electrode plate of the metal layer of the charge sharing capacitor to the charge sharing transistor, so that when the ITO pixel electrode is short-circuited with the electrode plate of the ITO layer of the charge sharing capacitor, the corresponding sub-pixel is displayed as a dark point, and the dark spot is more easily detected.
  • the detection rate of short circuit between the electrode plate on the ITO layer and the ITO pixel electrode of the charge sharing capacitor can be improved, the problem of product micro-brightness is improved, the yield is improved, and the cost is reduced.

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Abstract

一种提升不良检出率的像素结构及检测方法，该提升不良检出率的像素结构包括主像素（10）和次像素（20）两个区域，次像素（20）内具有电荷共享薄膜晶体管（T3）与电荷共享电容（C ST3）；电荷共享薄膜晶体管（T3）的栅极电性连接于电荷共享扫描线（Gate2（m））；电荷共享电容（C ST3）由ITO层上电极板（42）、金属层下电极板（2）、以及夹于ITO层上电极板（42）与金属层下电极板（2）之间的绝缘层（3）构成；ITO层上电极板（42）与ITO像素电极（41）位于同一层，且所述ITO层上电极板（42）作为像素公共电极连接至公共电压信号线（Com（m）），所述金属层下电极板（2）连接至电荷共享晶体管（T3）的漏极。

Description

提升不良检出率的像素结构及检测方法 技术领域
本发明涉及显示技术领域，尤其涉及一种提升不良检出率的像素结构及检测方法。
背景技术
液晶显示器(LCD，Liquid Crystal Display)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括壳体、设于壳体内的液晶显示面板及设于壳体内的背光模组。液晶显示面板是液晶显示器的主要组件，但液晶显示面板本身不发光，需要借由背光模组提供的光源来正常显示影像。
通常液晶显示面板由两片玻璃基板贴合而成，且在两片玻璃基板之间灌入液晶，分别在两片玻璃基板的相对内侧设置像素电极、公共电极，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
现有的LCD中，大视角下会发生严重的色偏现象，尤其在垂直配向(Vertical Alignment，VA)型的LCD中更为明显。如图1所示，为了改善VA型液晶显示器在大视角出现的色偏现象，现有技术会采用电荷共享(Charge Sharing)的像素设计，即将像素分为主像素(Main Pixel)100和次像素(Sub Pixel)200两个区域，主像素100内具有相互电性连接的第一薄膜晶体管T1、第一存储电容CST1、及第一液晶电容CLC1，次像素200内具有第二薄膜晶体管T2、第二存储电容CST2、第二液晶电容CLC2、电荷共享薄膜晶体管T3、及电荷共享电容CST3，所述第一薄膜晶体管T1与第二薄膜晶体管T2的栅极均电性连接于充电扫描线Gate1(m)、源极均电性连接于数据信号线Date(n)，m与n均为正整数，Gate1(m)代表第m条充电扫描线Gate1，Date(n)代表第n条数据信号线Date；所述第一存储电容CST1、第二存储电容CST2、及电荷共享电容CST3的一端分别电性连接第一薄膜晶体管T1的漏极、第二薄膜晶体管T2的漏极及电荷共享薄膜晶体管T3的漏极，另一端均电性连接于公共电压信号线Com(m)；所述电荷共享薄膜晶体 管T3的栅极电性连接于电荷共享扫描线Gate2(m)，漏极电性连接于电荷共享电容CST3。在正常显示时，充电扫描线Gate1(m)打开，同时电荷共享扫描线Gate2(m)关闭，主像素100和次像素200充电到相同电位；随后充电扫描线Gate1(m)关闭，同时电荷共享扫描线Gate2(m)打开，由于电荷共享电容CST3的作用使得次像素200的电位低于主像素100的电位。不同的电位使得两个显示区域的液晶分子转向分布不同，从而具备改善大视角色偏的作用。如图2、图3所示所示，现有的采用电荷共享技术的像素中的电荷共享电容CST3由氧化铟锡(Indium Tin Oxide，ITO)层上电极板420、金属层下电极板20以及夹于两层之间的绝缘层30构成，其中ITO层上电极板420与ITO像素电极410位于同一层，且ITO层上电极板420通过过孔(VIA)305与电荷共享晶体管T3的漏极相连接，金属层下电极板20作为像素公共电极连接至公共电压信号线Com(m)。
然而，实际生产中可能会出现ITO残留问题，使得电荷共享电容CST3的ITO层上电极板420与ITO像素电极410短路，导致电荷共享功能失效。同样灰阶下存在短路问题的像素的次像素会比其他像素的次像素更亮，在液晶显示面板上呈现微亮点现象。目前通常采用的检测方式是将所有的充电扫描线同时打开或分奇偶打开，并给所有像素或所有对应的奇偶行像素充电，使得主像素和次像素都处于同样电位，在这种检测方式下即使出现上述ITO间短路的现象也无法有效检出，导致良率下降，产品成本增加。
发明内容
本发明的目的在于提供一种提升不良检出率的像素结构，能够提高电荷共享电容的ITO层上电极板与ITO像素电极间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
本发明的目的还在于提供一种提升不良检出率的检测方法，能够提高电荷共享电容的ITO层上电极板与ITO像素电极间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
为实现上述目的，本发明提供一种提升不良检出率的像素结构，包括主像素和次像素两个区域，所述次像素内具有电荷共享薄膜晶体管、与电荷共享电容；所述电荷共享薄膜晶体管的栅极电性连接于电荷共享扫描线；所述电荷共享电容由ITO层上电极板、金属层下电极板、以及夹于所述ITO层上电极板与金属层下电极板之间的绝缘层构成；所述ITO层上电极板与ITO像素电极位于同一层，且所述ITO层上电极板作为像素公共电极连接至公共电压信号线，所述金属层下电极板连接至电荷共享晶体管的 漏极。
所述ITO层上电极板作为像素公共电极通过过孔连接至公共电压信号线。
所述次像素内还具有相互电性连接的第二薄膜晶体管、第二存储电容、与第二液晶电容；所述第二薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线，漏极电性连接于所述电荷共享薄膜晶体管的源极；所述第二存储电容的一端电性连接于第二薄膜晶体管的漏极、另一端电性连接于公共电压信号线。
所述主像素内具有相互电性连接的第一薄膜晶体管、第一存储电容、及第一液晶电容；所述第一薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线；所述第一存储电容的一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于公共电压信号线。
所述ITO像素电极与所述电荷共享电容的ITO层上电极板短路时，相应的次像素显示为暗点。
本发明还提供一种提升不良检出率的检测方法，包括如下步骤：
步骤1、提供需检测的液晶显示面板，该液晶显示面板包括多条充电扫描线、多条公共电压信号线、多条电荷共享扫描线、多条数据信号线、及多个呈阵列式排布的像素；每一像素包括主像素和次像素两个区域，所述次像素内具有电荷共享薄膜晶体管、与电荷共享电容；所述电荷共享薄膜晶体管的栅极电性连接于电荷共享扫描线；所述电荷共享电容由ITO层上电极板、金属层下电极板、以及夹于所述ITO层上电极板与金属层下电极板之间的绝缘层构成；所述ITO层上电极板与ITO像素电极位于同一层；
步骤2、将所述电荷共享电容的ITO层上电极板作为像素公共电极连接至公共电压信号线，将所述金属层下电极板连接至电荷共享晶体管的漏极；
步骤3、将所有的充电扫描线同时打开或分奇偶打开，并给所有像素或所有对应的奇偶行像素充电，使得主像素和次像素都处于同样电位；
步骤4、检测该液晶显示面板上的暗点，检出与所述暗点相应的次像素内的ITO像素电极与电荷共享电容的ITO层上电极板发生短路。
所述步骤2中，所述ITO层上电极板作为像素公共电极通过过孔连接至公共电压信号线。
所述次像素内还具有相互电性连接的第二薄膜晶体管、第二存储电容、与第二液晶电容；所述第二薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线，漏极电性连接于所述电荷共享薄膜晶体管的 源极；所述第二存储电容的一端电性连接于第二薄膜晶体管的漏极、另一端电性连接于公共电压信号线。
所述主像素内具有相互电性连接的第一薄膜晶体管、第一存储电容、及第一液晶电容；所述第一薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线；所述第一存储电容的一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于公共电压信号线。
本发明的有益效果：本发明提供的一种提升不良检出率的像素结构及检测方法，将电荷共享电容的ITO层上电极板作为像素公共电极连接至公共电压信号线，将电荷共享电容的金属层下电极板连接至电荷共享晶体管，使得ITO像素电极与电荷共享电容的ITO层上电极板短路时，相应的次像素显示为暗点，暗点更容易检出，能够提高电荷共享电容的ITO层上电极板与ITO像素电极间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有电荷共享的像素结构的等效电路图；
图2为现有电荷共享的像素结构中显示电荷共享电容的剖面示意图；
图3为对应图2的平面俯视示意图；
图4为本发明提升不良检出率的像素结构的等效电路图；
图5为本发明提升不良检出率的像素结构中显示电荷共享电容的剖面示意图；
图6为对应图5的平面俯视示意图；
图7为本发明提升不良检出率的检测方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图4至图6，本发明提供一种提升不良检出率的像素结构，包括主像素10和次像素20两个区域。
所述主像素10内具有相互电性连接的第一薄膜晶体管T1、第一存储电容CST1、及第一液晶电容CLC1；次像素20内具有第二薄膜晶体管T2、第 二存储电容CST2、第二液晶电容CLC2、电荷共享薄膜晶体管T3、及电荷共享电容CST3。
所述第一薄膜晶体管T1与第二薄膜晶体管T2的栅极均电性连接于充电扫描线Gate1(m)、源极均电性连接于数据信号线Date(n)，m与n均为正整数，Gate1(m)代表第m条充电扫描线Gate1，Date(n)代表第n条数据信号线Date；所述第一存储电容CST1、第二存储电容CST2、及电荷共享电容CST3的一端分别电性连接于第一薄膜晶体管T1的漏极、第二薄膜晶体管T2的漏极及电荷共享薄膜晶体管T3的漏极，另一端均电性连接于公共电压信号线Com(m)，Com(m)代表第m条公共电压信号线Com；所述电荷共享薄膜晶体管T3的栅极电性连接于电荷共享扫描线Gate2(m)，源极电性连接于第二薄膜晶体管T2的漏极，Gate2(m)代表第m条电荷共享扫描线Gate2。
进一步的，所述电荷共享电容CST3由ITO层上电极板42、金属层下电极板2、以及夹于所述ITO层上电极板42与金属层下电极板2之间的绝缘层3构成，所述金属层下电极板2与绝缘层3均形成于一玻璃基板1上。所述ITO层上电极板42与ITO像素电极41位于同一层，且所述ITO层上电极板42作为像素公共电极通过一过孔35连接至公共电压信号线Com(m)，所述金属层下电极板2连接至电荷共享晶体管T3的漏极。这种结构与现有技术中将电荷共享电容的ITO层上电极板连接至电荷共享晶体管的漏极、将电荷共享电容的金属层下电极板连接至公共电压信号线相反。
在正常显示时，所述充电扫描线Gate1(m)打开，同时电荷共享扫描线Gate2(m)关闭，所述主像素10和次像素20充电到相同电位；随后所述充电扫描线Gate1(m)关闭，同时电荷共享扫描线Gate2(m)打开，由于所述电荷共享电容CST3的作用使得次像素20的电位低于主像素10的电位。不同的电位使得两个显示区域的液晶分子转向分布不同，从而具备改善大视角色偏的作用。
当由于ITO残留问题使得电荷共享电容CST3的ITO层上电极板42与ITO像素电极41短路时，ITO像素电极41即与作为像素公共电极的ITO层上电极板42导通，同时与公共电压信号线Com(m)导通，导致同样灰阶下发生短路的相应的次像素20在液晶显示面板上呈现为暗点，相比于微亮点，暗点更容易被有效检出，便于及时修补，能够提高电荷共享电容CST3的ITO层上电极板42与ITO像素电极41间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
请参阅图7，同时参阅图4至图6，本发明还提供一种提升不良检出率的检测方法，包括如下步骤：
步骤1、提供需检测的液晶显示面板。
该液晶显示面板包括多条充电扫描线Gate1(m)、多条公共电压信号线Com(m)、多条电荷共享扫描线Gate2(m)、多条数据信号线Date(n)、及多个呈阵列式排布的像素。每一像素包括主像素10和次像素20两个区域。
所述主像素10内具有相互电性连接的第一薄膜晶体管T1、第一存储电容CST1、及第一液晶电容CLC1；次像素20内具有第二薄膜晶体管T2、第二存储电容CST2、第二液晶电容CLC2、电荷共享薄膜晶体管T3、及电荷共享电容CST3。
所述电荷共享电容CST3由ITO层上电极板42、金属层下电极板2、以及夹于所述ITO层上电极板42与金属层下电极板2之间的绝缘层3构成。所述ITO层上电极板42与ITO像素电极41位于同一层。
所述第一薄膜晶体管T1与第二薄膜晶体管T2的栅极均电性连接于充电扫描线Gate1(m)、源极均电性连接于数据信号线Date(n)；所述第一存储电容CST1、与第二存储电容CST2的一端分别电性连接第一薄膜晶体管T1的漏极与第二薄膜晶体管T2的漏极，另一端均电性连接于公共电压信号线Com(m)。所述电荷共享薄膜晶体管T3的栅极电性连接于电荷共享扫描线Gate2(m)，源极电性连接于第二薄膜晶体管T2的漏极。
步骤2、将所述电荷共享电容CST3的ITO层上电极板42作为像素公共电极通过一过孔35连接至公共电压信号线Com(m)，将所述金属层下电极板2连接至电荷共享晶体管T3的漏极。
步骤3、将所有的充电扫描线Gate1(m)同时打开或分奇偶打开，并给所有像素或所有对应的奇偶行像素充电，使得主像素10和次像素20都处于同样电位。
步骤4、检测该液晶显示面板上的暗点，检出与所述暗点相应的次像素20内的ITO像素电极41与电荷共享电容CST3的ITO层上电极板42发生短路。
由于电荷共享电容CST3的ITO层上电极板42与ITO像素电极41发生短路时，ITO像素电极41即与作为像素公共电极的ITO层上电极板42导通，同时与公共电压信号线Com(m)导通，导致同样灰阶下发生短路的相应的次像素20在液晶显示面板上呈现为暗点，相比于微亮点，暗点更容易被有效检出，能够提高电荷共享电容CST3的ITO层上电极板42与ITO像素电极41间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
综上所述，本发明的一种提升不良检出率的像素结构及检测方法，将电荷共享电容的ITO层上电极板作为像素公共电极连接至公共电压信号 线，将电荷共享电容的金属层下电极板连接至电荷共享晶体管，使得ITO像素电极与电荷共享电容的ITO层上电极板短路时，相应的次像素显示为暗点，暗点更容易检出，能够提高电荷共享电容的ITO层上电极板与ITO像素电极间发生短路的检出率，改善产品微亮点问题，提高良率，降低成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种提升不良检出率的像素结构，包括主像素和次像素两个区域，所述次像素内具有电荷共享薄膜晶体管、与电荷共享电容；所述电荷共享薄膜晶体管的栅极电性连接于电荷共享扫描线；所述电荷共享电容由ITO层上电极板、金属层下电极板、以及夹于所述ITO层上电极板与金属层下电极板之间的绝缘层构成；所述ITO层上电极板与ITO像素电极位于同一层，且所述ITO层上电极板作为像素公共电极连接至公共电压信号线，所述金属层下电极板连接至电荷共享晶体管的漏极。
  2. 如权利要求1所述的提升不良检出率的像素结构，其中，所述ITO层上电极板作为像素公共电极通过过孔连接至公共电压信号线。
  3. 如权利要求1所述的提升不良检出率的像素结构，其中，所述次像素内还具有相互电性连接的第二薄膜晶体管、第二存储电容、与第二液晶电容；所述第二薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线，漏极电性连接于所述电荷共享薄膜晶体管的源极；所述第二存储电容的一端电性连接于第二薄膜晶体管的漏极、另一端电性连接于公共电压信号线。
  4. 如权利要求1所述的提升不良检出率的像素结构，其中，所述主像素内具有相互电性连接的第一薄膜晶体管、第一存储电容、及第一液晶电容；所述第一薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线；所述第一存储电容的一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于公共电压信号线。
  5. 如权利要求1所述的提升不良检出率的像素结构，其中，所述ITO像素电极与所述电荷共享电容的ITO层上电极板短路时，相应的次像素显示为暗点。
  6. 一种提升不良检出率的检测方法，包括如下步骤：
    步骤1、提供需检测的液晶显示面板，该液晶显示面板包括多条充电扫描线、多条公共电压信号线、多条电荷共享扫描线、多条数据信号线、及多个呈阵列式排布的像素；每一像素包括主像素和次像素两个区域，所述次像素内具有电荷共享薄膜晶体管、与电荷共享电容；所述电荷共享薄膜晶体管的栅极电性连接于电荷共享扫描线；所述电荷共享电容由ITO层上电极板、金属层下电极板、以及夹于所述ITO层上电极板与金属层下电极板之间的绝缘层构成；所述ITO层上电极板与ITO像素电极位于同一层；
    步骤2、将所述电荷共享电容的ITO层上电极板作为像素公共电极连接至公共电压信号线，将所述金属层下电极板连接至电荷共享晶体管的漏极；
    步骤3、将所有的充电扫描线同时打开或分奇偶打开，并给所有像素或所有对应奇偶行像素充电，使得主像素和次像素都处于同样电位；
    步骤4、检测该液晶显示面板上的暗点，检出与所述暗点相应的次像素内的ITO像素电极与电荷共享电容的ITO层上电极板发生短路。
  7. 如权利要求6所述的提升不良检出率的检测方法，其中，所述步骤2中，所述ITO层上电极板作为像素公共电极通过过孔连接至公共电压信号线。
  8. 如权利要求6所述的提升不良检出率的检测方法，其中，所述次像素内还具有相互电性连接的第二薄膜晶体管、第二存储电容、与第二液晶电容；所述第二薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线，漏极电性连接于所述电荷共享薄膜晶体管的源极；所述第二存储电容的一端电性连接于第二薄膜晶体管的漏极、另一端电性连接于公共电压信号线。
  9. 如权利要求6所述的提升不良检出率的检测方法，其中，所述主像素内具有相互电性连接的第一薄膜晶体管、第一存储电容、及第一液晶电容；所述第一薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线；所述第一存储电容的一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于公共电压信号线。
  10. 一种提升不良检出率的检测方法，包括如下步骤：
    步骤1、提供需检测的液晶显示面板，该液晶显示面板包括多条充电扫描线、多条公共电压信号线、多条电荷共享扫描线、多条数据信号线、及多个呈阵列式排布的像素；每一像素包括主像素和次像素两个区域，所述次像素内具有电荷共享薄膜晶体管、与电荷共享电容；所述电荷共享薄膜晶体管的栅极电性连接于电荷共享扫描线；所述电荷共享电容由ITO层上电极板、金属层下电极板、以及夹于所述ITO层上电极板与金属层下电极板之间的绝缘层构成；所述ITO层上电极板与ITO像素电极位于同一层；
    步骤2、将所述电荷共享电容的ITO层上电极板作为像素公共电极连接至公共电压信号线，将所述金属层下电极板连接至电荷共享晶体管的漏极；
    步骤3、将所有的充电扫描线同时打开或分奇偶打开，并给所有像素或所有对应奇偶行像素充电，使得主像素和次像素都处于同样电位；
    步骤4、检测该液晶显示面板上的暗点，检出与所述暗点相应的次像素内的ITO像素电极与电荷共享电容的ITO层上电极板发生短路；
    其中，所述步骤2中，所述ITO层上电极板作为像素公共电极通过过孔连接至公共电压信号线；
    其中，所述次像素内还具有相互电性连接的第二薄膜晶体管、第二存储电容、与第二液晶电容；所述第二薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线，漏极电性连接于所述电荷共享薄膜晶体管的源极；所述第二存储电容的一端电性连接于第二薄膜晶体管的漏极、另一端电性连接于公共电压信号线；
    其中，所述主像素内具有相互电性连接的第一薄膜晶体管、第一存储电容、及第一液晶电容；所述第一薄膜晶体管的栅极电性连接于充电扫描线，源极电性连接于数据信号线；所述第一存储电容的一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于公共电压信号线。
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