WO2021244133A9 - 显示基板及其驱动方法、维修方法、显示面板、显示装置 - Google Patents
显示基板及其驱动方法、维修方法、显示面板、显示装置 Download PDFInfo
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Definitions
- the present disclosure relates to the field of display technology, and in particular, to a display substrate, a driving method, a maintenance method, a display panel, and a display device thereof.
- LCD liquid crystal display
- An LCD panel generally includes: a base substrate, and a plurality of pixel units located on the base substrate, and each pixel unit includes a thin film transistor and a pixel electrode connected to each other.
- the present disclosure provides a display substrate, a driving method, a maintenance method, a display panel, and a display device thereof, and the technical solutions are as follows:
- a display substrate comprising:
- each of the pixel units includes: a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected to one of the gate lines, and the first electrode is connected to One of the data lines is connected, and the second pole is connected to the pixel electrode;
- the orthographic projection of the gates of the thin film transistors included in the pixel unit in the nth row and the connected gate lines on the base substrate is the same as that in the nth row.
- the orthographic projection of the first electrode and the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is the same as the pixel electrode included in the pixel unit in the n+1th row.
- the orthographic projections on the base substrate overlap.
- the orthographic projection of the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is also on the base substrate with the pixel electrode included in the pixel unit in the nth row.
- the orthographic projections overlap.
- the spacing of the pixel electrodes included in any two adjacent pixel units in the extending direction of the grid lines is within a first spacing range
- the spacing in the extending direction of the data line is within the second spacing range
- the vertical distance between the pixel electrode and the data line connected to the thin film transistor is within a third spacing range.
- the first pitch range and the second pitch range are both 3 microns to 7 microns; the third pitch range is 3 microns to 5 microns.
- the material of the pixel electrode included in each of the pixel units is a metal material, and the reflectivity of the metal material is greater than a reflectivity threshold;
- the display substrate further includes: a reflective material layer on the side of the pixel electrode away from the base substrate, and the area of the orthographic projection of the reflective material layer on the base substrate is the same as the pixel electrode The area of the orthographic projection on the base substrate is positively correlated.
- the thin film transistors and pixel electrodes included in each of the pixel units are stacked in sequence along a direction away from the base substrate;
- the display substrate further includes: a dielectric layer between the thin film transistor and the pixel electrode;
- the orthographic projection of the gate electrode of the thin film transistor on the base substrate and the orthographic projection of the pixel electrode on the base substrate have an overlapping area
- the dielectric layer on the base substrate has an overlapping area.
- the orthographic projection overlaps the overlapping area.
- the dielectric constant of the dielectric layer is less than a dielectric constant threshold, and the thickness of the dielectric layer is greater than the thickness threshold.
- the material of the dielectric layer is an organic resin material.
- the orthographic projection of the dielectric layer on the base substrate covers the orthographic projection of the gate electrode of the thin film transistor on the base substrate.
- the material of the dielectric layer is a metal material.
- the thin film transistor further includes: an active layer; the orthographic projection of the dielectric layer on the base substrate does not overlap with the orthographic projection of the active layer on the base substrate.
- a method for driving a display substrate wherein the display substrate is the display substrate according to the above aspect, and the method includes:
- the thin film transistor in the nth row pixel unit charges the pixel electrode in the nth row pixel unit in response to the gate driving signal and the data signal to the first potential; and when the gate driving signal is provided to the nth gate line, the gates of the thin film transistors in the nth row of pixel units and the nth gate line are connected to the nth gate line with the n+th gate line. Under the coupling effect of the parasitic capacitance formed by the pixel electrodes in the pixel units in the 1 row, the pixel electrodes in the pixel units in the n+1 row are pulled to a second potential; the second potential is smaller than the first potential.
- a method for repairing a display substrate wherein the display substrate is the display substrate according to the above aspect, and the method includes:
- the first target pixel unit is located in one of the nth row and the n+1th row
- the second target pixel unit is located in the nth row and the n+1th row.
- n is greater than or an integer equal to 1.
- a display panel comprising: a cell assembling substrate, and the display substrate according to the above aspect.
- the display panel further includes: a driving circuit
- the driving circuit is respectively connected to a plurality of gate lines and a plurality of data lines in the display substrate, and the driving circuit is used for providing gate driving signals to the plurality of gate lines and to the plurality of data lines provide data signals.
- the display panel is a total reflection type liquid crystal display panel, or a transflective liquid crystal display panel.
- a display device comprising: the display panel according to the above aspect.
- FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure
- FIG. 3 is a timing chart of charging of pixel electrodes included in an LCD panel in the related art
- FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
- FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure.
- FIG. 8 is a charging timing diagram of a pixel electrode provided by an embodiment of the present disclosure.
- FIG. 9 is a flowchart of a maintenance method for a display substrate provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
- FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
- Vcom 12 is a schematic diagram of an actual measured value of Vcom provided by an embodiment of the present disclosure.
- FIG. 13 is a schematic diagram of an actual measured value of a flicker degree provided by an embodiment of the present disclosure.
- LCD panels generally include: transmissive LCD panels and reflective liquid crystal display (reflection type liquid crystal display, RLCD) panels. And, the RLCD panel may further include a total reflection type LCD panel and a transflective type LCD panel.
- a transmissive LCD panel refers to a panel that uses light emitted by a backlight to achieve display
- an RLCD panel refers to a panel that uses ambient light for reflection to achieve display.
- the LCD panel described in the embodiment of the present disclosure can be any kind of LCD panel, and the following embodiments take the R LCD panel as an example to describe the application content.
- the pixel electrode in each pixel unit of a transmissive LCD panel, the pixel electrode generally does not cover the entire thin film transistor, and may only cover one electrode (eg, source electrode) of the source and drain electrodes of the thin film transistor connected to the pixel electrode.
- the gate electrode of the thin film transistor does not form parasitic capacitance with the pixel electrode.
- the inventor found that for an R CD panel with multiplexed pixel electrodes as the light reflective layer, in order to improve the reflectivity, a larger area of pixel electrodes may generally be set to increase the reflective area, resulting in that in each pixel unit, The pixel electrode and the gate of the thin film transistor overlap in the direction perpendicular to the display panel. At this time, a parasitic capacitance is formed between the pixel electrode and the gate of the thin film transistor, which leads to flickering phenomenon when the R LCD panel displays the picture.
- Embodiments of the present disclosure provide a display substrate, and in a display panel using the display substrate, the problem of screen flicker caused by parasitic capacitance formed between a pixel electrode in a pixel unit and a gate of a thin film transistor of the pixel unit can be effectively alleviated , and further, the reflectivity of the R LCD panel using the display substrate can be effectively improved.
- FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
- the display substrate may include: a base substrate 01 , a plurality of gate lines G1 and a plurality of data lines D1 located on the base substrate 01 , and a plurality of pixel unit 02.
- each gate line G1 may extend along the first direction
- each data line D1 may extend along the second direction
- the first direction and the second direction may intersect each other, for example, may be perpendicular to each other.
- FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure.
- each pixel unit 02 may include: a thin film transistor (thin film transistor) T1 and a pixel electrode P1.
- the gate G0 of the thin film transistor T1 may be connected to a gate line G1, such as G1(n+1) shown in FIG. 2 .
- the first electrode D0 of the thin film transistor T1 may be connected to a data line D1, and the second electrode S0 of the thin film transistor T1 may be connected to the pixel electrode P1.
- the first electrode of the thin film transistor T1 may be one electrode of the source electrode and the drain electrode, and the second electrode may be the other electrode of the source electrode and the drain electrode. Referring to FIG. 1 , the embodiment of the present disclosure is described by taking the first electrode drain D0 of the thin film transistor T1 and the source electrode S0 of the second electrode of the thin film transistor T1 as an example.
- each pixel unit 02 may further include a common electrode Vcom, which may be disposed on the display substrate, or may also be disposed on an opposite substrate opposite to the display substrate.
- a common electrode Vcom is arranged on the cell-to-cell substrate (for example, a twisted nematic liquid crystal display panel, Twisted Nematic, TN)
- liquid crystal molecules may be included between the common electrode Vcom and the pixel electrode P1
- the common electrode Vcom and the pixel electrode may include liquid crystal molecules.
- P1 can be equivalent to a liquid crystal capacitor (capacitance of liquid crystal) Clc, at the same time, a common electrode Vc om2 can also be set on the display substrate, and a storage capacitor can also be formed between the common electrode Vcom2 and the pixel electrode P1. of storage) Cst.
- the thin film transistor T1 can output the data signal from the connected data line D1 to the pixel electrode P1 to which it is connected in response to the gate driving signal provided by the gate line G1 to which it is connected, so as to charge the pixel electrode P1, thereby making the pixel electrode P1 A potential difference is formed between P1 and the common electrode Vcom.
- the liquid crystal molecules can be deflected under the action of the potential difference, so that the pixel unit 02 emits light.
- the pixel electrode in each pixel unit may cover the gate of the thin film transistor.
- the gate of the thin film transistor included in the pixel unit and the gate line connected to the gate will form a pixel electrode included in the pixel unit.
- the parasitic capacitance refer to the dotted line in Figure 2 to mark Cgs1.
- each pixel unit in each pixel unit, another parasitic capacitance Cgs2 is formed between the gate electrode of the thin film transistor and one electrode of the pixel electrode connected to the thin film transistor, that is, the source electrode.
- the parasitic capacitance Cgs2 is caused by the defects of the structure of the thin film transistor device itself, and cannot be avoided.
- the parasitic capacitance Cgs1 is caused by the large area of the pixel electrode and the overlapping area with the gate of the thin film transistor.
- the pixel electrode is multiplexed as a light reflection layer, and in order to improve the reflectivity, a display substrate included in an RLCD panel with a larger area of pixel electrodes is provided.
- a display substrate included in an RLCD panel with a larger area of pixel electrodes is provided.
- it may also be a transmissive LCD panel in which a larger area of pixel electrodes is provided in order to increase the capacitance.
- FIG. 3 shows a schematic diagram of the bit timing sequence of charging to the pixel unit 02 of the nth row and the pixel unit 02 of the n+1th row in the related art.
- n is an integer greater than or equal to 1.
- the potential difference ⁇ Vp between the actual potential and the set potential can satisfy:
- C1 refers to the sum of the capacitance values of the parasitic capacitors Cgs1 and Cgs2
- C2 refers to the capacitance value of the liquid crystal capacitor Clc
- C3 refers to the capacitance value of the storage capacitor Cst
- Vgh refers to the effective potential of the gate drive signal
- Vgl refers to The inactive potential of the gate drive signal
- C1, C3, Vgh and Vgl are generally constant values.
- the effective potential may be greater than the ineffective potential, or the effective potential may be smaller than the ineffective potential. It can be seen from the above formula (1) that the larger the capacitance of the parasitic capacitance Cgs1 is, the larger the C1 is, and the greater the difference between the ⁇ Vp of different grayscales, the more serious the screen flickering.
- the gate G0 of the thin film transistor T1 in the n-th row of pixel units 02 and the connected gate line G1 on the base substrate 01 The orthographic projection is separated from the orthographic projection of the pixel electrode P1 in the pixel unit 02 in the nth row on the base substrate 01, and is different from the normal projection of the pixel electrode P1 in the pixel unit 02 in the n+1th row on the base substrate 01. Projections overlap.
- the orthographic projection of the gate G0 of the thin film transistor T1 and the connected gate line G1 on the base substrate 01 in the pixel unit 02 in the nth row is only the same as that in the pixel unit 02 in the n+1th row.
- the orthographic projection of the pixel electrode P1 on the base substrate 01 overlaps, but does not overlap with the orthographic projection of the pixel electrode P1 in the n-th row of pixel units 02 on the base substrate 01 .
- the gate G0 of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line G1 will not form a parasitic capacitance with the pixel electrode P1 in the pixel unit 02 in the nth row (as shown in FIG. 2 shows Cgs1).
- the parasitic capacitance Cgs1 is The pixel units in the n rows and the pixel units in the n+1 row are charged sequentially, that is, after the scanning of the n th gate line G1(n) is completed, the n+1 th gate line G1(n+1) starts to scan.
- the potential of the n-th gate line G1(n) has already become stable when charging to the pixel unit 02 in the n+1-th row starts, and the gate G0 of the thin-film transistor T1 in the pixel unit 02 in the n-th row and the The parasitic capacitance Cgs1 formed between the gate line G1 and the pixel electrode P1 in the pixel unit 02 in the n+1th row does not affect the potential of the pixel unit 02 in the n+1th row which is being charged or has been charged.
- the embodiments of the present disclosure provide a display substrate. Due to the scanning direction of the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the substrate is the same as that of the pixel electrode in the pixel unit in the n+1th row on the substrate.
- the orthographic projections on the pixel units in the nth row overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate, that is, they do not overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate.
- the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode in the pixel unit of the n+1th row, and will not be connected with the pixel electrode of the pixel unit of the nth row. form parasitic capacitance.
- the driving circuit sequentially charges the pixel units in the nth row and the n+1th row
- the gates and nth gate lines of the thin film transistors in the nth row of pixel units are the same as the pixels in the n+1th row of pixel units.
- the parasitic capacitance formed by the electrodes will not affect the pixel unit in the n+1th row being charged.
- the display panel using the display substrate has better display effect.
- the display substrate may further include: a reflective material layer on the side of the pixel electrode away from the base substrate.
- the area of the orthographic projection of the provided reflective material layer on the base substrate may be positively correlated with the area of the orthographic projection of the pixel electrode on the base substrate. That is, the larger the area of the pixel electrode, the larger the area of the reflective material layer; the smaller the area of the pixel electrode, the smaller the area of the reflective material layer.
- the material of the pixel electrode P1 included in each pixel unit 02 may be a metal material, and the reflectivity of the metal material may be greater than the reflectivity threshold. That is, the pixel electrode P1 can be multiplexed to achieve conduction and at the same time reflect light.
- the reflection area of the RLCD is positively correlated with the area of the pixel electrode P1. Therefore, with reference to FIG. 1, in the embodiment of the present disclosure, by setting each pixel unit 02, the orthographic projection of the pixel electrode P1 on the base substrate overlaps with the orthographic projection of the source electrode S0 of the thin film transistor T1 on the base substrate . It can ensure that the area of the pixel electrode P1 is larger and the reflectivity is improved.
- the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 can be smaller than the distance threshold.
- the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 in the extending direction of the gate line G1 may be within the first distance range.
- the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 in the extending direction of the data line D1 may be within the second distance range.
- the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be within a third spacing range.
- the above-mentioned distance range can be flexibly set according to the manufacturing process when manufacturing the display substrate.
- the first pitch range and the second pitch range may be generally both 3 micrometers ( ⁇ m) to 7 ⁇ m.
- the third pitch may generally range from 3 ⁇ m to 5 ⁇ m. That is, for the pixel electrodes P1 included in any two adjacent pixel units 02, the spacing in the extending direction of the gate line G1 and the spacing in the extending direction of the data line D1 may be greater than or equal to 3 ⁇ m and less than or equal to 7 ⁇ m, For example, it can be 5 ⁇ m. In each pixel unit 02, the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be greater than or equal to 3 ⁇ m and less than or equal to 5 ⁇ m, for example, may be 4 ⁇ m.
- FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- the orthographic projections of the first electrode D0 and the second electrode S0 of the thin film transistor T1 included in the pixel unit 02 in the nth row on the base substrate 01 may also be the same as those included in the pixel unit 02 in the n+1th row.
- the orthographic projections of the pixel electrode P1 on the base substrate 01 overlap. That is, the main body of the thin film transistor T1 in the pixel unit 02 in the nth row can be placed under the pixel electrode P1 in the pixel unit 02 in the n+1th row. That is, referring to FIG.
- the pixel electrode P1 in the pixel unit 02 in the n+1th row may cover the main body of the thin film transistor T1 in the pixel unit 02 in the nth row.
- the main body of the thin film transistor T1 includes: the entire gate electrode, most of the first electrode (ie, drain electrode) D0 and most of the second electrode (ie, source electrode S0 ) of the thin film transistor T1 .
- the gate G0 and the connected gate line G1 of the pixel unit 02 in the nth row are located under the pixel electrode P1 in the pixel unit in the n+1th row, that is, the pixels in the nth row are further avoided.
- the gate G0 and the connected gate line G1 of the thin film transistor T1 in the unit 02 form a parasitic capacitance Cgs1 with the pixel electrode P1, thereby effectively improving the display effect.
- the area of the pixel electrode P1 is further increased, and the reflectivity of the RLCD panel in which the pixel electrode P1 is multiplexed as a light reflection layer is improved.
- the second pole S0 of the thin film transistor T1 needs to be connected to the pixel electrode P1, in order to ensure a reliable connection between the two, in conjunction with FIG. 1 and FIG.
- the orthographic projection of the pole S0 on the base substrate 01 may also overlap with the orthographic projection of the pixel electrode P1 included in the nth row of pixel units 02 on the base substrate 01 .
- FIG. 5 shows a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure
- FIG. 6 is a schematic structural schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
- the thin film transistor T1 and the pixel electrode P1 included in each pixel unit 02 may be stacked in sequence along the direction away from the base substrate 01 .
- the display substrate may further include: a dielectric layer 03 located between the thin film transistor T1 and the pixel electrode P1 in the overlapping area.
- the dielectric layer 03 is located between the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1th row. Moreover, the orthographic projection of the dielectric layer 03 on the base substrate 01 may overlap with the overlapping area.
- the dielectric layer 03 can be used to reduce the capacitance value of the parasitic capacitance formed by the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, and the pixel electrode P1 in the pixel unit 02 in the n+1th row.
- the parasitic capacitance formed by the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line and the pixel electrode P1 in the pixel unit 02 in the n+1th row is directly shielded, thereby further improving the display effect.
- the material of the dielectric layer 03 shown in FIG. 5 may be a non-metallic material. And if the material of the dielectric layer 03 is a non-metallic material, in order to effectively reduce the gate electrode of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, it is formed with the pixel electrode P1 in the pixel unit 02 in the n+1th row.
- the capacitance value of the parasitic capacitance, the dielectric constant of the dielectric layer 03 may be less than the dielectric constant threshold, and the thickness of the dielectric layer 03 may be greater than the thickness threshold. Referring to FIG.
- the orthographic projection of the dielectric layer 03 on the base substrate 01 can cover the orthographic projection of the gate G0 of the thin film transistor T1 on the base substrate 01 .
- the material of the dielectric layer 03 may be an organic resin material.
- the orthographic projection of the dielectric layer 03 on the substrate 01 refers to: the orthographic projection of the dielectric layer 03 on the base substrate 01 covers the gate of the thin film transistor T1 in the pixel unit 02 in the nth row G0.
- the material of the dielectric layer 03 shown in FIG. 6 may be a metal material.
- the dielectric layer 03 made of this metal material can realize the parasitic formation between the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, and the pixel electrode P1 in the pixel unit 02 in the n+1th row. Direct shielding of capacitors.
- the thin film transistor T1 may include an active layer (active) A0 in addition to the gate electrode G0 and the source and drain electrodes (S0 and D0).
- the active layer A0 may be located between the source and drain electrodes (S0 and D0) and the gate electrode G0, and the source electrode S0 and the drain electrode D0 may partially cover the active layer A0.
- the dielectric layer 03 is made of a metal material
- the dielectric layer 03 made of a metal material is The orthographic projection on the base substrate 01 and the orthographic projection of the active layer A0 on the base substrate 01 may not overlap.
- the dielectric layer 03 is located between the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1th row, then there is no overlap here.
- the orthographic projections of the active layer A0 of the thin film transistor T1 in the n-row pixel unit on the base substrate 01 do not overlap.
- the dielectric layer 03 also needs to be connected to the active thin film transistor T1 in the pixel unit 02 in other rows (eg, the n+1th row).
- the orthographic projections of the layer A0 on the base substrate 01 do not overlap.
- the parasitic capacitance formed with the pixel electrode P1 in the pixel unit 02 in the n+1th row will cause the display effect to be affected.
- the influence of the multi-layer dielectric layer 03 can be set.
- a dielectric layer 03 made of an organic resin material may be provided, and a dielectric layer 03 made of a metal material may be provided.
- the display substrate may further include an insulating layer (for example, reference numerals 04, 05 and 06) disposed between each adjacent two-layer structures.
- FIG. 6 also shows the formed parasitic capacitances Cgs1 and Cgs2. Assuming that the dielectric layer 03 shown in FIGS.
- Cgs1 here refers to the th
- Cgs2 refers to the thin film in the pixel unit 02 in the nth row.
- the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the base substrate is the same as that of the pixel electrode in the pixel unit in the nth row on the base substrate.
- the medium described above can be directly arranged between the thin film transistor in the pixel unit in the nth row and the pixel electrode in the pixel unit in the nth row where the overlapping area exists Layer 03.
- the display substrate may include a display area (active area, AA) and a non-display area, and the pixel units 02 described in the above embodiments may be disposed in the AA area.
- the non-display area can be used to provide driving circuits that provide signals for gate lines and data lines.
- the thin film transistor T1 described in the embodiments of the present disclosure may be made of a-silicon (a-Si) material, or may be made of low temperature polysilicon (LTPS) material, or may be made of Made of oxide material.
- the embodiments of the present disclosure provide a display substrate. Due to the scanning direction of the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the substrate is the same as that of the pixel electrode in the pixel unit in the n+1th row on the substrate.
- the orthographic projections on the pixel units in the nth row overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate, that is, they do not overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate.
- the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode in the pixel unit of the n+1th row, and will not be connected with the pixel electrode of the pixel unit of the nth row. form parasitic capacitance.
- the driving circuit sequentially charges the pixel units in the nth row and the n+1th row
- the gates and nth gate lines of the thin film transistors in the nth row of pixel units are the same as the pixels in the n+1th row of pixel units.
- the parasitic capacitance formed by the electrodes will not affect the pixel unit in the n+1th row being charged.
- the display panel using the display substrate has better display effect.
- FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure, and the display substrate may be the display substrate shown in any of FIG. 1 , FIG. 4 to FIG. 6 . As shown in Figure 7, the method may include:
- Step 701 along the scanning direction of the plurality of gate lines in the display substrate, sequentially provide gate driving signals to each of the gate lines, and provide data signals to the plurality of data lines in the display substrate.
- the gate driving signal is provided to the nth gate line G1(n)
- the thin film transistor T1 in the pixel unit 02 of the nth row can respond to the gate driving signal and the data signal, and the nth row
- the pixel electrode P1(n) in the pixel unit 02 is charged to the first potential V1.
- the parasitic capacitance Cgs1 formed by the gate of the thin film transistor T1 and the nth gate line of the pixel unit 02 in the nth row and the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row Under the action of coupling, the pixel electrode P1(n+1) in the pixel unit 02 of the n+1th row is pulled to the second potential V2. And the second potential V2 may be smaller than the first potential V1.
- the charging process for the pixel unit of the nth row and the pixel unit of the n+1th row can be divided into three stages: Referring to FIG. 8 , in the first stage t1, the nth gate line G1(n) is first supplied with The gate driving signal, at this time, only the thin film transistors T1 in the pixel unit 02 in the nth row are turned on, and a plurality of data lines D1 pass through the turned-on thin film transistors T1 to the pixel electrode P1(n) in the pixel unit 02 in the nth row. Write the first potential.
- the nth gate line G1(n) pulls the potential of the pixel electrode P1(n+1) in the n+1th row pixel unit 02 to a certain extent.
- the potential of the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row is pulled to the second potential, which is deviated from the initial potential.
- the supply of the gate driving signal to the nth gate line G1(n) is stopped, and the supply of the gate driving signal to the n+1th gate line G1(n+1) is started.
- the thin film transistors T1 in the pixel unit 02 in the n+1th row are turned on, and the plurality of data lines D1 pass through the turned-on thin film transistors T1 to the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row ) to write the first potential.
- the gate G0 and the nth gate line G1(n) of the thin film transistor T1 of the pixel unit 02 in the nth row are connected with the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row.
- the parasitic capacitance Cgs1 formed by ) does not have any influence on the potential of the pixel electrode P1 (n+1).
- the charging of the pixel unit 02 in the n+1 th row is completed and reaches the set potential.
- the potential of the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row is only affected by the parasitic capacitance Cgs2, and the variation range is small, and further, the flickering phenomenon of the display screen is significantly improved.
- supplying the gate driving signal to the gate line is a gate driving signal for supplying an effective potential to the gate line
- stopping supplying the gate driving signal to the gate line is a gate driving signal for supplying an inactive potential to the gate line.
- the effective potential may be a high potential, and correspondingly, the inactive potential may be a low potential; or, the effective potential may be a low potential, and correspondingly, the inactive potential may be a high potential.
- the level of the effective potential and the ineffective potential depends on the type of the thin film transistor T1.
- the effective potential may be high and the inactive potential may be low; if the thin film transistor T1 is a P-type transistor, the effective potential may be low and the inactive potential may be high.
- the embodiments of the present disclosure provide a method for driving a display substrate. Because when the gate driving signal is supplied to the nth gate line, the thin film transistor in the pixel unit in the nth row can charge the pixel electrode in the pixel unit in the nth row to the first potential in response to the gate driving signal and the data signal ; And under the coupling action of the parasitic capacitance formed by the gate electrode and the nth gate line of the thin film transistor of the pixel unit in the nth row, and the pixel electrode in the pixel unit in the n+1th row, in the pixel unit in the n+1th row The pixel electrode of is pulled to a second potential that is less than the first potential.
- the gate and the nth gate line of the thin film transistor in the nth row of pixel units are the same as the pixel electrodes in the n+1th row of pixel units.
- the resulting parasitic capacitance does not affect the pixel cell being charged.
- the display effect of the display panel using the display substrate provided by the embodiment of the present disclosure is better.
- FIG. 9 is a flowchart of a maintenance method for a display substrate provided by an embodiment of the present disclosure, and the display substrate may be the display substrate shown in any of FIG. 1 , FIG. 4 to FIG. 6 .
- the method may include:
- Step 901 determining the first target pixel unit with a dead pixel.
- the first target pixel unit with a dead pixel may be determined through various testing methods (eg, array testing).
- the display substrate is a twisted nematic (TN) type display substrate, and the display panel made of the TN type display substrate is normally displayed in a normally white state as an example, the dead pixel determined in step 901 may be a bright point.
- TN twisted nematic
- Step 902 Connect the pixel electrode included in the first target pixel unit to the gate line connected to the second target pixel unit.
- the pixel electrode included in the first target pixel unit may be connected to the grid line connected to the second target pixel unit by means of laser welding.
- the first target pixel unit may be located in one of the nth row and the n+1th row
- the second target pixel unit may be located in another row of the nth row and the n+1th row, where n is Integer greater than or equal to 1. That is, if the first target pixel unit is a certain pixel unit in the nth row of pixel units, the second target pixel unit is a certain pixel unit in the n+1th row of pixel units. If the first target pixel unit is a certain pixel unit in the n+1th row of pixel units, the second target pixel unit is a certain pixel unit in the nth row of pixel units.
- the gate of the thin film transistor included in the pixel unit in the nth row and the orthographic projection of the connected gate line on the substrate are the same as the pixel electrode included in the pixel unit in the n+1th row on the substrate.
- the first target pixel unit is a pixel unit in the pixel unit in the n+1th row
- the second target pixel unit is a pixel unit in the pixel unit in the nth row
- the dead pixel is If it is a bright spot, when a bright spot is detected in the first target pixel unit, the pixel electrode included in the pixel unit lit in the n+1th row of pixel units can be connected to the gate line G1 connected to the nth row of pixel units. After being connected, a large voltage difference can be formed between the pixel electrode and the common electrode of the lit first target pixel unit, thereby making the lit first target pixel unit darker to achieve the effect of repairing the bright spot.
- the embodiments of the present disclosure provide a maintenance method for a display substrate. Due to the unique arrangement positions of the thin film transistors in the pixel units in the nth row and the pixel electrodes in the pixel units in the n+1th row in the display substrate, when the first target pixel unit with a dead pixel is determined, the The pixel electrode included in a target pixel unit is connected to the gate line connected to the second target pixel unit to achieve the purpose of repairing the dead pixels, and the repair method is relatively simple.
- FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
- the display panel may include: a cell assembling substrate 100 , and a display substrate 200 as shown in any one of FIGS. 1 , 4 to 6 .
- the cell assembling substrate 100 may be a color filter substrate, and the display substrate 200 may be an array substrate.
- the display panel may further include: a liquid crystal liquid crystal disposed between the cell assembling substrate 100 and the display substrate 200 Layer 300, the liquid crystal layer 300 includes a plurality of liquid crystal molecules. That is, the display panel may be an LCD panel.
- FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
- the display panel may further include: a driving circuit 400 .
- the driving circuit 400 can be connected to a plurality of gate lines G1 and a plurality of data lines D1 in the display substrate 200, respectively, and the driving circuit 400 can be used for providing gate driving signals to the plurality of gate lines G1, and providing a plurality of data lines to the plurality of data lines.
- Line D1 provides the data signal.
- the driving circuit 400 may include a gate driving circuit 4001 and a source driving circuit 4002, and the gate driving circuit 4001 may be connected to a plurality of gate lines G1 for providing gate driving signals to the plurality of gate lines G1 ;
- the source drive circuit 4002 can be connected to a plurality of data lines D1 for providing data signals to the plurality of data lines D1.
- the RLCD panel may be a total reflection type RLCD panel, or may be a transflective type RLCD panel.
- FIG. 12 and FIG. 13 respectively show 10 randomly selected samples (ie, pixels). unit), each sample is affected by the parasitic capacitance, at the moment when the thin film transistor T1 is turned off, the measured value of the potential of the common electrode Vcom, and the measured value of the degree of ficker.
- the parasitic capacitance includes Cgs2 and Cdp (that is, the parasitic capacitance formed between the data line D1 and the pixel electrode P1); for a conventional RLCD, the parasitic capacitance includes Cgs1, Cgs2 and Cdp ;
- the parasitic capacitance includes Cgs1, Cgs2 and Cdp. Referring to FIG. 12 , it can be seen that the measured value of Vcom of the RLCD of the present disclosure drops from about 0.55 to about 0.2 compared with the conventional RLCD. Since the ideal potential of Vcom is 0 in the positive and negative driving switching stages, the smaller the measured value of Vcom, the better the display effect.
- the display effect of the RLCD provided by the embodiment of the present disclosure is better.
- the flicker degree of the RLCD of the present disclosure is reduced from about 6% to about 4% compared with the conventional RLCD, and the flicker degree is significantly reduced.
- an embodiment of the present disclosure further provides a display device, and the display device may include the display panel shown in FIG. 10 or FIG. 11 .
- the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, and navigator.
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Abstract
Description
Claims (20)
- 一种显示基板,其中,所述显示基板包括:衬底基板;位于所述衬底基板上的多条栅线和多条数据线;位于所述衬底基板上且阵列排布的多个像素单元,每个所述像素单元包括:薄膜晶体管和像素电极,所述薄膜晶体管的栅极与一条所述栅线连接,第一极与一条所述数据线连接,第二极与所述像素电极连接;其中,沿所述多条栅线的扫描方向,第n行所述像素单元包括的薄膜晶体管的栅极和所连接的栅线在所述衬底基板上的正投影,与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影存在间隔,且与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠,n为大于或等于1的整数。
- 根据权利要求1所述的显示基板,其中,第n行所述像素单元包括的薄膜晶体管的第一极和第二极在所述衬底基板上的正投影,与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
- 根据权利要求1所述的显示基板,其中,第n行所述像素单元包括的薄膜晶体管的第二极在所述衬底基板上的正投影,还与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
- 根据权利要求1至3任一所述的显示基板,其中,任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内。
- 根据权利要求4所述的显示基板,其中,所述第一间距范围和所述第二间 距范围均为3微米至7微米;所述第三间距范围为3微米至5微米。
- 根据权利要求1至5任一所述的显示基板,其中,每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 根据权利要求1至6任一所述的显示基板,其中,每个所述像素单元包括的薄膜晶体管和像素电极沿远离所述衬底基板的方向依次层叠;所述显示基板还包括:位于所述薄膜晶体管和所述像素电极之间的介质层;其中,所述薄膜晶体管的栅极在所述衬底基板上的正投影和所述像素电极在所述衬底基板上的正投影存在重叠区域,所述介质层在所述衬底基板上的正投影与所述重叠区域重叠。
- 根据权利要求7所述的显示基板,其中,所述介质层的介电常数小于介电常数阈值,且所述介质层的厚度大于厚度阈值。
- 根据权利要求8所述的显示基板,其中,所述介质层的材料为有机树脂材料。
- 根据权利要求8所述的显示基板,其中,所述介质层在所述衬底基板上的正投影,覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影。
- 根据权利要求7所述的显示基板,其中,所述介质层的材料为金属材料。
- 根据权利要求11所述的显示基板,其中,所述薄膜晶体管还包括:有源层;所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠。
- 根据权利要求8所述的显示基板,其中,所述介质层在所述衬底基板上的正投影,覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影;任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内;所述第一间距范围和所述第二间距范围均为3微米至7微米;所述第三间距范围为3微米至5微米;每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 根据权利要求11所述的显示基板,其中,所述薄膜晶体管还包括:有源层;所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠;任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内;所述第一间距范围和所述第二间距范围均为3微米至7微米;所述第三间距范围为3微米至5微米;每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 一种显示基板的驱动方法,其中,所述显示基板为如权利要求1至14任一所述的显示基板,所述方法包括:沿所述显示基板中多条栅线的扫描方向,依次向每条所述栅线提供栅极驱动信号;向所述显示基板中的多条数据线提供数据信号;其中,在向第n条栅线提供栅极驱动信号时,第n行像素单元中的薄膜晶体管响应于所述栅极驱动信号和所述数据信号,将第n行像素单元中的像素电极充电至第一电位;且在向第n条栅线提供栅极驱动信号时,在所述第n行像素单元中的薄膜晶体管的栅极和所述第n条栅线,与所述第n+1行像素单元中的像素电极形成的寄生电容的耦合作用下,第n+1行像素单元中的像素电极被拉动至第二电位;所述第二电位小于所述第一电位。
- 一种显示基板的维修方法,其中,所述显示基板为如权利要求1至14任一所述的显示基板,所述方法包括:确定出现坏点的第一目标像素单元;将所述第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接;其中,所述第一目标像素单元位于第n行和第n+1行中的一行,第二目标像素单元位于所述第n行和所述第n+1行中的另一行,n为大于或等于1的整数。
- 一种显示面板,其中,所述显示面板包括:对盒基板,以及如权利要求1至14任一所述的显示基板。
- 根据权利要求17所述的显示面板,其中,所述显示面板还包括:驱动电路;所述驱动电路分别与所述显示基板中的多条栅线和多条数据线连接,所述驱动电路用于向所述多条栅线提供栅极驱动信号,以及向所述多条数据线提供数据信号。
- 根据权利要求17所述的显示面板,其中,所述显示面板为全反射型液晶显示面板,或,半透半反射型液晶显示面板。
- 一种显示装置,其中,所述显示装置包括:如权利要求17至19任一所 述的显示面板。
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JP3062090B2 (ja) * | 1996-07-19 | 2000-07-10 | 日本電気株式会社 | 液晶表示装置 |
US6300987B1 (en) * | 1998-12-04 | 2001-10-09 | Samsung Electronics Co., Ltd. | Thin film transistor array panels for liquid crystal displays |
JP4016977B2 (ja) * | 2004-09-03 | 2007-12-05 | セイコーエプソン株式会社 | 液晶表示装置、電子機器 |
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US20110298785A1 (en) * | 2010-06-02 | 2011-12-08 | Apple Inc. | Gate shielding for liquid crystal displays |
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