WO2021244133A9 - 显示基板及其驱动方法、维修方法、显示面板、显示装置 - Google Patents

显示基板及其驱动方法、维修方法、显示面板、显示装置 Download PDF

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WO2021244133A9
WO2021244133A9 PCT/CN2021/085935 CN2021085935W WO2021244133A9 WO 2021244133 A9 WO2021244133 A9 WO 2021244133A9 CN 2021085935 W CN2021085935 W CN 2021085935W WO 2021244133 A9 WO2021244133 A9 WO 2021244133A9
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Prior art keywords
pixel
base substrate
thin film
row
display
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PCT/CN2021/085935
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English (en)
French (fr)
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WO2021244133A1 (zh
Inventor
廖力勍
王栋
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US17/609,969 priority Critical patent/US20220308413A1/en
Publication of WO2021244133A1 publication Critical patent/WO2021244133A1/zh
Publication of WO2021244133A9 publication Critical patent/WO2021244133A9/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a driving method, a maintenance method, a display panel, and a display device thereof.
  • LCD liquid crystal display
  • An LCD panel generally includes: a base substrate, and a plurality of pixel units located on the base substrate, and each pixel unit includes a thin film transistor and a pixel electrode connected to each other.
  • the present disclosure provides a display substrate, a driving method, a maintenance method, a display panel, and a display device thereof, and the technical solutions are as follows:
  • a display substrate comprising:
  • each of the pixel units includes: a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected to one of the gate lines, and the first electrode is connected to One of the data lines is connected, and the second pole is connected to the pixel electrode;
  • the orthographic projection of the gates of the thin film transistors included in the pixel unit in the nth row and the connected gate lines on the base substrate is the same as that in the nth row.
  • the orthographic projection of the first electrode and the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is the same as the pixel electrode included in the pixel unit in the n+1th row.
  • the orthographic projections on the base substrate overlap.
  • the orthographic projection of the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is also on the base substrate with the pixel electrode included in the pixel unit in the nth row.
  • the orthographic projections overlap.
  • the spacing of the pixel electrodes included in any two adjacent pixel units in the extending direction of the grid lines is within a first spacing range
  • the spacing in the extending direction of the data line is within the second spacing range
  • the vertical distance between the pixel electrode and the data line connected to the thin film transistor is within a third spacing range.
  • the first pitch range and the second pitch range are both 3 microns to 7 microns; the third pitch range is 3 microns to 5 microns.
  • the material of the pixel electrode included in each of the pixel units is a metal material, and the reflectivity of the metal material is greater than a reflectivity threshold;
  • the display substrate further includes: a reflective material layer on the side of the pixel electrode away from the base substrate, and the area of the orthographic projection of the reflective material layer on the base substrate is the same as the pixel electrode The area of the orthographic projection on the base substrate is positively correlated.
  • the thin film transistors and pixel electrodes included in each of the pixel units are stacked in sequence along a direction away from the base substrate;
  • the display substrate further includes: a dielectric layer between the thin film transistor and the pixel electrode;
  • the orthographic projection of the gate electrode of the thin film transistor on the base substrate and the orthographic projection of the pixel electrode on the base substrate have an overlapping area
  • the dielectric layer on the base substrate has an overlapping area.
  • the orthographic projection overlaps the overlapping area.
  • the dielectric constant of the dielectric layer is less than a dielectric constant threshold, and the thickness of the dielectric layer is greater than the thickness threshold.
  • the material of the dielectric layer is an organic resin material.
  • the orthographic projection of the dielectric layer on the base substrate covers the orthographic projection of the gate electrode of the thin film transistor on the base substrate.
  • the material of the dielectric layer is a metal material.
  • the thin film transistor further includes: an active layer; the orthographic projection of the dielectric layer on the base substrate does not overlap with the orthographic projection of the active layer on the base substrate.
  • a method for driving a display substrate wherein the display substrate is the display substrate according to the above aspect, and the method includes:
  • the thin film transistor in the nth row pixel unit charges the pixel electrode in the nth row pixel unit in response to the gate driving signal and the data signal to the first potential; and when the gate driving signal is provided to the nth gate line, the gates of the thin film transistors in the nth row of pixel units and the nth gate line are connected to the nth gate line with the n+th gate line. Under the coupling effect of the parasitic capacitance formed by the pixel electrodes in the pixel units in the 1 row, the pixel electrodes in the pixel units in the n+1 row are pulled to a second potential; the second potential is smaller than the first potential.
  • a method for repairing a display substrate wherein the display substrate is the display substrate according to the above aspect, and the method includes:
  • the first target pixel unit is located in one of the nth row and the n+1th row
  • the second target pixel unit is located in the nth row and the n+1th row.
  • n is greater than or an integer equal to 1.
  • a display panel comprising: a cell assembling substrate, and the display substrate according to the above aspect.
  • the display panel further includes: a driving circuit
  • the driving circuit is respectively connected to a plurality of gate lines and a plurality of data lines in the display substrate, and the driving circuit is used for providing gate driving signals to the plurality of gate lines and to the plurality of data lines provide data signals.
  • the display panel is a total reflection type liquid crystal display panel, or a transflective liquid crystal display panel.
  • a display device comprising: the display panel according to the above aspect.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure
  • FIG. 3 is a timing chart of charging of pixel electrodes included in an LCD panel in the related art
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a charging timing diagram of a pixel electrode provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a maintenance method for a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • Vcom 12 is a schematic diagram of an actual measured value of Vcom provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of an actual measured value of a flicker degree provided by an embodiment of the present disclosure.
  • LCD panels generally include: transmissive LCD panels and reflective liquid crystal display (reflection type liquid crystal display, RLCD) panels. And, the RLCD panel may further include a total reflection type LCD panel and a transflective type LCD panel.
  • a transmissive LCD panel refers to a panel that uses light emitted by a backlight to achieve display
  • an RLCD panel refers to a panel that uses ambient light for reflection to achieve display.
  • the LCD panel described in the embodiment of the present disclosure can be any kind of LCD panel, and the following embodiments take the R LCD panel as an example to describe the application content.
  • the pixel electrode in each pixel unit of a transmissive LCD panel, the pixel electrode generally does not cover the entire thin film transistor, and may only cover one electrode (eg, source electrode) of the source and drain electrodes of the thin film transistor connected to the pixel electrode.
  • the gate electrode of the thin film transistor does not form parasitic capacitance with the pixel electrode.
  • the inventor found that for an R CD panel with multiplexed pixel electrodes as the light reflective layer, in order to improve the reflectivity, a larger area of pixel electrodes may generally be set to increase the reflective area, resulting in that in each pixel unit, The pixel electrode and the gate of the thin film transistor overlap in the direction perpendicular to the display panel. At this time, a parasitic capacitance is formed between the pixel electrode and the gate of the thin film transistor, which leads to flickering phenomenon when the R LCD panel displays the picture.
  • Embodiments of the present disclosure provide a display substrate, and in a display panel using the display substrate, the problem of screen flicker caused by parasitic capacitance formed between a pixel electrode in a pixel unit and a gate of a thin film transistor of the pixel unit can be effectively alleviated , and further, the reflectivity of the R LCD panel using the display substrate can be effectively improved.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate may include: a base substrate 01 , a plurality of gate lines G1 and a plurality of data lines D1 located on the base substrate 01 , and a plurality of pixel unit 02.
  • each gate line G1 may extend along the first direction
  • each data line D1 may extend along the second direction
  • the first direction and the second direction may intersect each other, for example, may be perpendicular to each other.
  • FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure.
  • each pixel unit 02 may include: a thin film transistor (thin film transistor) T1 and a pixel electrode P1.
  • the gate G0 of the thin film transistor T1 may be connected to a gate line G1, such as G1(n+1) shown in FIG. 2 .
  • the first electrode D0 of the thin film transistor T1 may be connected to a data line D1, and the second electrode S0 of the thin film transistor T1 may be connected to the pixel electrode P1.
  • the first electrode of the thin film transistor T1 may be one electrode of the source electrode and the drain electrode, and the second electrode may be the other electrode of the source electrode and the drain electrode. Referring to FIG. 1 , the embodiment of the present disclosure is described by taking the first electrode drain D0 of the thin film transistor T1 and the source electrode S0 of the second electrode of the thin film transistor T1 as an example.
  • each pixel unit 02 may further include a common electrode Vcom, which may be disposed on the display substrate, or may also be disposed on an opposite substrate opposite to the display substrate.
  • a common electrode Vcom is arranged on the cell-to-cell substrate (for example, a twisted nematic liquid crystal display panel, Twisted Nematic, TN)
  • liquid crystal molecules may be included between the common electrode Vcom and the pixel electrode P1
  • the common electrode Vcom and the pixel electrode may include liquid crystal molecules.
  • P1 can be equivalent to a liquid crystal capacitor (capacitance of liquid crystal) Clc, at the same time, a common electrode Vc om2 can also be set on the display substrate, and a storage capacitor can also be formed between the common electrode Vcom2 and the pixel electrode P1. of storage) Cst.
  • the thin film transistor T1 can output the data signal from the connected data line D1 to the pixel electrode P1 to which it is connected in response to the gate driving signal provided by the gate line G1 to which it is connected, so as to charge the pixel electrode P1, thereby making the pixel electrode P1 A potential difference is formed between P1 and the common electrode Vcom.
  • the liquid crystal molecules can be deflected under the action of the potential difference, so that the pixel unit 02 emits light.
  • the pixel electrode in each pixel unit may cover the gate of the thin film transistor.
  • the gate of the thin film transistor included in the pixel unit and the gate line connected to the gate will form a pixel electrode included in the pixel unit.
  • the parasitic capacitance refer to the dotted line in Figure 2 to mark Cgs1.
  • each pixel unit in each pixel unit, another parasitic capacitance Cgs2 is formed between the gate electrode of the thin film transistor and one electrode of the pixel electrode connected to the thin film transistor, that is, the source electrode.
  • the parasitic capacitance Cgs2 is caused by the defects of the structure of the thin film transistor device itself, and cannot be avoided.
  • the parasitic capacitance Cgs1 is caused by the large area of the pixel electrode and the overlapping area with the gate of the thin film transistor.
  • the pixel electrode is multiplexed as a light reflection layer, and in order to improve the reflectivity, a display substrate included in an RLCD panel with a larger area of pixel electrodes is provided.
  • a display substrate included in an RLCD panel with a larger area of pixel electrodes is provided.
  • it may also be a transmissive LCD panel in which a larger area of pixel electrodes is provided in order to increase the capacitance.
  • FIG. 3 shows a schematic diagram of the bit timing sequence of charging to the pixel unit 02 of the nth row and the pixel unit 02 of the n+1th row in the related art.
  • n is an integer greater than or equal to 1.
  • the potential difference ⁇ Vp between the actual potential and the set potential can satisfy:
  • C1 refers to the sum of the capacitance values of the parasitic capacitors Cgs1 and Cgs2
  • C2 refers to the capacitance value of the liquid crystal capacitor Clc
  • C3 refers to the capacitance value of the storage capacitor Cst
  • Vgh refers to the effective potential of the gate drive signal
  • Vgl refers to The inactive potential of the gate drive signal
  • C1, C3, Vgh and Vgl are generally constant values.
  • the effective potential may be greater than the ineffective potential, or the effective potential may be smaller than the ineffective potential. It can be seen from the above formula (1) that the larger the capacitance of the parasitic capacitance Cgs1 is, the larger the C1 is, and the greater the difference between the ⁇ Vp of different grayscales, the more serious the screen flickering.
  • the gate G0 of the thin film transistor T1 in the n-th row of pixel units 02 and the connected gate line G1 on the base substrate 01 The orthographic projection is separated from the orthographic projection of the pixel electrode P1 in the pixel unit 02 in the nth row on the base substrate 01, and is different from the normal projection of the pixel electrode P1 in the pixel unit 02 in the n+1th row on the base substrate 01. Projections overlap.
  • the orthographic projection of the gate G0 of the thin film transistor T1 and the connected gate line G1 on the base substrate 01 in the pixel unit 02 in the nth row is only the same as that in the pixel unit 02 in the n+1th row.
  • the orthographic projection of the pixel electrode P1 on the base substrate 01 overlaps, but does not overlap with the orthographic projection of the pixel electrode P1 in the n-th row of pixel units 02 on the base substrate 01 .
  • the gate G0 of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line G1 will not form a parasitic capacitance with the pixel electrode P1 in the pixel unit 02 in the nth row (as shown in FIG. 2 shows Cgs1).
  • the parasitic capacitance Cgs1 is The pixel units in the n rows and the pixel units in the n+1 row are charged sequentially, that is, after the scanning of the n th gate line G1(n) is completed, the n+1 th gate line G1(n+1) starts to scan.
  • the potential of the n-th gate line G1(n) has already become stable when charging to the pixel unit 02 in the n+1-th row starts, and the gate G0 of the thin-film transistor T1 in the pixel unit 02 in the n-th row and the The parasitic capacitance Cgs1 formed between the gate line G1 and the pixel electrode P1 in the pixel unit 02 in the n+1th row does not affect the potential of the pixel unit 02 in the n+1th row which is being charged or has been charged.
  • the embodiments of the present disclosure provide a display substrate. Due to the scanning direction of the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the substrate is the same as that of the pixel electrode in the pixel unit in the n+1th row on the substrate.
  • the orthographic projections on the pixel units in the nth row overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate, that is, they do not overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate.
  • the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode in the pixel unit of the n+1th row, and will not be connected with the pixel electrode of the pixel unit of the nth row. form parasitic capacitance.
  • the driving circuit sequentially charges the pixel units in the nth row and the n+1th row
  • the gates and nth gate lines of the thin film transistors in the nth row of pixel units are the same as the pixels in the n+1th row of pixel units.
  • the parasitic capacitance formed by the electrodes will not affect the pixel unit in the n+1th row being charged.
  • the display panel using the display substrate has better display effect.
  • the display substrate may further include: a reflective material layer on the side of the pixel electrode away from the base substrate.
  • the area of the orthographic projection of the provided reflective material layer on the base substrate may be positively correlated with the area of the orthographic projection of the pixel electrode on the base substrate. That is, the larger the area of the pixel electrode, the larger the area of the reflective material layer; the smaller the area of the pixel electrode, the smaller the area of the reflective material layer.
  • the material of the pixel electrode P1 included in each pixel unit 02 may be a metal material, and the reflectivity of the metal material may be greater than the reflectivity threshold. That is, the pixel electrode P1 can be multiplexed to achieve conduction and at the same time reflect light.
  • the reflection area of the RLCD is positively correlated with the area of the pixel electrode P1. Therefore, with reference to FIG. 1, in the embodiment of the present disclosure, by setting each pixel unit 02, the orthographic projection of the pixel electrode P1 on the base substrate overlaps with the orthographic projection of the source electrode S0 of the thin film transistor T1 on the base substrate . It can ensure that the area of the pixel electrode P1 is larger and the reflectivity is improved.
  • the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 can be smaller than the distance threshold.
  • the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 in the extending direction of the gate line G1 may be within the first distance range.
  • the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 in the extending direction of the data line D1 may be within the second distance range.
  • the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be within a third spacing range.
  • the above-mentioned distance range can be flexibly set according to the manufacturing process when manufacturing the display substrate.
  • the first pitch range and the second pitch range may be generally both 3 micrometers ( ⁇ m) to 7 ⁇ m.
  • the third pitch may generally range from 3 ⁇ m to 5 ⁇ m. That is, for the pixel electrodes P1 included in any two adjacent pixel units 02, the spacing in the extending direction of the gate line G1 and the spacing in the extending direction of the data line D1 may be greater than or equal to 3 ⁇ m and less than or equal to 7 ⁇ m, For example, it can be 5 ⁇ m. In each pixel unit 02, the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be greater than or equal to 3 ⁇ m and less than or equal to 5 ⁇ m, for example, may be 4 ⁇ m.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the orthographic projections of the first electrode D0 and the second electrode S0 of the thin film transistor T1 included in the pixel unit 02 in the nth row on the base substrate 01 may also be the same as those included in the pixel unit 02 in the n+1th row.
  • the orthographic projections of the pixel electrode P1 on the base substrate 01 overlap. That is, the main body of the thin film transistor T1 in the pixel unit 02 in the nth row can be placed under the pixel electrode P1 in the pixel unit 02 in the n+1th row. That is, referring to FIG.
  • the pixel electrode P1 in the pixel unit 02 in the n+1th row may cover the main body of the thin film transistor T1 in the pixel unit 02 in the nth row.
  • the main body of the thin film transistor T1 includes: the entire gate electrode, most of the first electrode (ie, drain electrode) D0 and most of the second electrode (ie, source electrode S0 ) of the thin film transistor T1 .
  • the gate G0 and the connected gate line G1 of the pixel unit 02 in the nth row are located under the pixel electrode P1 in the pixel unit in the n+1th row, that is, the pixels in the nth row are further avoided.
  • the gate G0 and the connected gate line G1 of the thin film transistor T1 in the unit 02 form a parasitic capacitance Cgs1 with the pixel electrode P1, thereby effectively improving the display effect.
  • the area of the pixel electrode P1 is further increased, and the reflectivity of the RLCD panel in which the pixel electrode P1 is multiplexed as a light reflection layer is improved.
  • the second pole S0 of the thin film transistor T1 needs to be connected to the pixel electrode P1, in order to ensure a reliable connection between the two, in conjunction with FIG. 1 and FIG.
  • the orthographic projection of the pole S0 on the base substrate 01 may also overlap with the orthographic projection of the pixel electrode P1 included in the nth row of pixel units 02 on the base substrate 01 .
  • FIG. 5 shows a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the thin film transistor T1 and the pixel electrode P1 included in each pixel unit 02 may be stacked in sequence along the direction away from the base substrate 01 .
  • the display substrate may further include: a dielectric layer 03 located between the thin film transistor T1 and the pixel electrode P1 in the overlapping area.
  • the dielectric layer 03 is located between the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1th row. Moreover, the orthographic projection of the dielectric layer 03 on the base substrate 01 may overlap with the overlapping area.
  • the dielectric layer 03 can be used to reduce the capacitance value of the parasitic capacitance formed by the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, and the pixel electrode P1 in the pixel unit 02 in the n+1th row.
  • the parasitic capacitance formed by the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line and the pixel electrode P1 in the pixel unit 02 in the n+1th row is directly shielded, thereby further improving the display effect.
  • the material of the dielectric layer 03 shown in FIG. 5 may be a non-metallic material. And if the material of the dielectric layer 03 is a non-metallic material, in order to effectively reduce the gate electrode of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, it is formed with the pixel electrode P1 in the pixel unit 02 in the n+1th row.
  • the capacitance value of the parasitic capacitance, the dielectric constant of the dielectric layer 03 may be less than the dielectric constant threshold, and the thickness of the dielectric layer 03 may be greater than the thickness threshold. Referring to FIG.
  • the orthographic projection of the dielectric layer 03 on the base substrate 01 can cover the orthographic projection of the gate G0 of the thin film transistor T1 on the base substrate 01 .
  • the material of the dielectric layer 03 may be an organic resin material.
  • the orthographic projection of the dielectric layer 03 on the substrate 01 refers to: the orthographic projection of the dielectric layer 03 on the base substrate 01 covers the gate of the thin film transistor T1 in the pixel unit 02 in the nth row G0.
  • the material of the dielectric layer 03 shown in FIG. 6 may be a metal material.
  • the dielectric layer 03 made of this metal material can realize the parasitic formation between the gate of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line, and the pixel electrode P1 in the pixel unit 02 in the n+1th row. Direct shielding of capacitors.
  • the thin film transistor T1 may include an active layer (active) A0 in addition to the gate electrode G0 and the source and drain electrodes (S0 and D0).
  • the active layer A0 may be located between the source and drain electrodes (S0 and D0) and the gate electrode G0, and the source electrode S0 and the drain electrode D0 may partially cover the active layer A0.
  • the dielectric layer 03 is made of a metal material
  • the dielectric layer 03 made of a metal material is The orthographic projection on the base substrate 01 and the orthographic projection of the active layer A0 on the base substrate 01 may not overlap.
  • the dielectric layer 03 is located between the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1th row, then there is no overlap here.
  • the orthographic projections of the active layer A0 of the thin film transistor T1 in the n-row pixel unit on the base substrate 01 do not overlap.
  • the dielectric layer 03 also needs to be connected to the active thin film transistor T1 in the pixel unit 02 in other rows (eg, the n+1th row).
  • the orthographic projections of the layer A0 on the base substrate 01 do not overlap.
  • the parasitic capacitance formed with the pixel electrode P1 in the pixel unit 02 in the n+1th row will cause the display effect to be affected.
  • the influence of the multi-layer dielectric layer 03 can be set.
  • a dielectric layer 03 made of an organic resin material may be provided, and a dielectric layer 03 made of a metal material may be provided.
  • the display substrate may further include an insulating layer (for example, reference numerals 04, 05 and 06) disposed between each adjacent two-layer structures.
  • FIG. 6 also shows the formed parasitic capacitances Cgs1 and Cgs2. Assuming that the dielectric layer 03 shown in FIGS.
  • Cgs1 here refers to the th
  • Cgs2 refers to the thin film in the pixel unit 02 in the nth row.
  • the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the base substrate is the same as that of the pixel electrode in the pixel unit in the nth row on the base substrate.
  • the medium described above can be directly arranged between the thin film transistor in the pixel unit in the nth row and the pixel electrode in the pixel unit in the nth row where the overlapping area exists Layer 03.
  • the display substrate may include a display area (active area, AA) and a non-display area, and the pixel units 02 described in the above embodiments may be disposed in the AA area.
  • the non-display area can be used to provide driving circuits that provide signals for gate lines and data lines.
  • the thin film transistor T1 described in the embodiments of the present disclosure may be made of a-silicon (a-Si) material, or may be made of low temperature polysilicon (LTPS) material, or may be made of Made of oxide material.
  • the embodiments of the present disclosure provide a display substrate. Due to the scanning direction of the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit in the nth row and the connected gate line on the substrate is the same as that of the pixel electrode in the pixel unit in the n+1th row on the substrate.
  • the orthographic projections on the pixel units in the nth row overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate, that is, they do not overlap with the orthographic projections of the pixel electrodes in the nth row of pixel units on the base substrate.
  • the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode in the pixel unit of the n+1th row, and will not be connected with the pixel electrode of the pixel unit of the nth row. form parasitic capacitance.
  • the driving circuit sequentially charges the pixel units in the nth row and the n+1th row
  • the gates and nth gate lines of the thin film transistors in the nth row of pixel units are the same as the pixels in the n+1th row of pixel units.
  • the parasitic capacitance formed by the electrodes will not affect the pixel unit in the n+1th row being charged.
  • the display panel using the display substrate has better display effect.
  • FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure, and the display substrate may be the display substrate shown in any of FIG. 1 , FIG. 4 to FIG. 6 . As shown in Figure 7, the method may include:
  • Step 701 along the scanning direction of the plurality of gate lines in the display substrate, sequentially provide gate driving signals to each of the gate lines, and provide data signals to the plurality of data lines in the display substrate.
  • the gate driving signal is provided to the nth gate line G1(n)
  • the thin film transistor T1 in the pixel unit 02 of the nth row can respond to the gate driving signal and the data signal, and the nth row
  • the pixel electrode P1(n) in the pixel unit 02 is charged to the first potential V1.
  • the parasitic capacitance Cgs1 formed by the gate of the thin film transistor T1 and the nth gate line of the pixel unit 02 in the nth row and the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row Under the action of coupling, the pixel electrode P1(n+1) in the pixel unit 02 of the n+1th row is pulled to the second potential V2. And the second potential V2 may be smaller than the first potential V1.
  • the charging process for the pixel unit of the nth row and the pixel unit of the n+1th row can be divided into three stages: Referring to FIG. 8 , in the first stage t1, the nth gate line G1(n) is first supplied with The gate driving signal, at this time, only the thin film transistors T1 in the pixel unit 02 in the nth row are turned on, and a plurality of data lines D1 pass through the turned-on thin film transistors T1 to the pixel electrode P1(n) in the pixel unit 02 in the nth row. Write the first potential.
  • the nth gate line G1(n) pulls the potential of the pixel electrode P1(n+1) in the n+1th row pixel unit 02 to a certain extent.
  • the potential of the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row is pulled to the second potential, which is deviated from the initial potential.
  • the supply of the gate driving signal to the nth gate line G1(n) is stopped, and the supply of the gate driving signal to the n+1th gate line G1(n+1) is started.
  • the thin film transistors T1 in the pixel unit 02 in the n+1th row are turned on, and the plurality of data lines D1 pass through the turned-on thin film transistors T1 to the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1th row ) to write the first potential.
  • the gate G0 and the nth gate line G1(n) of the thin film transistor T1 of the pixel unit 02 in the nth row are connected with the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row.
  • the parasitic capacitance Cgs1 formed by ) does not have any influence on the potential of the pixel electrode P1 (n+1).
  • the charging of the pixel unit 02 in the n+1 th row is completed and reaches the set potential.
  • the potential of the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row is only affected by the parasitic capacitance Cgs2, and the variation range is small, and further, the flickering phenomenon of the display screen is significantly improved.
  • supplying the gate driving signal to the gate line is a gate driving signal for supplying an effective potential to the gate line
  • stopping supplying the gate driving signal to the gate line is a gate driving signal for supplying an inactive potential to the gate line.
  • the effective potential may be a high potential, and correspondingly, the inactive potential may be a low potential; or, the effective potential may be a low potential, and correspondingly, the inactive potential may be a high potential.
  • the level of the effective potential and the ineffective potential depends on the type of the thin film transistor T1.
  • the effective potential may be high and the inactive potential may be low; if the thin film transistor T1 is a P-type transistor, the effective potential may be low and the inactive potential may be high.
  • the embodiments of the present disclosure provide a method for driving a display substrate. Because when the gate driving signal is supplied to the nth gate line, the thin film transistor in the pixel unit in the nth row can charge the pixel electrode in the pixel unit in the nth row to the first potential in response to the gate driving signal and the data signal ; And under the coupling action of the parasitic capacitance formed by the gate electrode and the nth gate line of the thin film transistor of the pixel unit in the nth row, and the pixel electrode in the pixel unit in the n+1th row, in the pixel unit in the n+1th row The pixel electrode of is pulled to a second potential that is less than the first potential.
  • the gate and the nth gate line of the thin film transistor in the nth row of pixel units are the same as the pixel electrodes in the n+1th row of pixel units.
  • the resulting parasitic capacitance does not affect the pixel cell being charged.
  • the display effect of the display panel using the display substrate provided by the embodiment of the present disclosure is better.
  • FIG. 9 is a flowchart of a maintenance method for a display substrate provided by an embodiment of the present disclosure, and the display substrate may be the display substrate shown in any of FIG. 1 , FIG. 4 to FIG. 6 .
  • the method may include:
  • Step 901 determining the first target pixel unit with a dead pixel.
  • the first target pixel unit with a dead pixel may be determined through various testing methods (eg, array testing).
  • the display substrate is a twisted nematic (TN) type display substrate, and the display panel made of the TN type display substrate is normally displayed in a normally white state as an example, the dead pixel determined in step 901 may be a bright point.
  • TN twisted nematic
  • Step 902 Connect the pixel electrode included in the first target pixel unit to the gate line connected to the second target pixel unit.
  • the pixel electrode included in the first target pixel unit may be connected to the grid line connected to the second target pixel unit by means of laser welding.
  • the first target pixel unit may be located in one of the nth row and the n+1th row
  • the second target pixel unit may be located in another row of the nth row and the n+1th row, where n is Integer greater than or equal to 1. That is, if the first target pixel unit is a certain pixel unit in the nth row of pixel units, the second target pixel unit is a certain pixel unit in the n+1th row of pixel units. If the first target pixel unit is a certain pixel unit in the n+1th row of pixel units, the second target pixel unit is a certain pixel unit in the nth row of pixel units.
  • the gate of the thin film transistor included in the pixel unit in the nth row and the orthographic projection of the connected gate line on the substrate are the same as the pixel electrode included in the pixel unit in the n+1th row on the substrate.
  • the first target pixel unit is a pixel unit in the pixel unit in the n+1th row
  • the second target pixel unit is a pixel unit in the pixel unit in the nth row
  • the dead pixel is If it is a bright spot, when a bright spot is detected in the first target pixel unit, the pixel electrode included in the pixel unit lit in the n+1th row of pixel units can be connected to the gate line G1 connected to the nth row of pixel units. After being connected, a large voltage difference can be formed between the pixel electrode and the common electrode of the lit first target pixel unit, thereby making the lit first target pixel unit darker to achieve the effect of repairing the bright spot.
  • the embodiments of the present disclosure provide a maintenance method for a display substrate. Due to the unique arrangement positions of the thin film transistors in the pixel units in the nth row and the pixel electrodes in the pixel units in the n+1th row in the display substrate, when the first target pixel unit with a dead pixel is determined, the The pixel electrode included in a target pixel unit is connected to the gate line connected to the second target pixel unit to achieve the purpose of repairing the dead pixels, and the repair method is relatively simple.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include: a cell assembling substrate 100 , and a display substrate 200 as shown in any one of FIGS. 1 , 4 to 6 .
  • the cell assembling substrate 100 may be a color filter substrate, and the display substrate 200 may be an array substrate.
  • the display panel may further include: a liquid crystal liquid crystal disposed between the cell assembling substrate 100 and the display substrate 200 Layer 300, the liquid crystal layer 300 includes a plurality of liquid crystal molecules. That is, the display panel may be an LCD panel.
  • FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the display panel may further include: a driving circuit 400 .
  • the driving circuit 400 can be connected to a plurality of gate lines G1 and a plurality of data lines D1 in the display substrate 200, respectively, and the driving circuit 400 can be used for providing gate driving signals to the plurality of gate lines G1, and providing a plurality of data lines to the plurality of data lines.
  • Line D1 provides the data signal.
  • the driving circuit 400 may include a gate driving circuit 4001 and a source driving circuit 4002, and the gate driving circuit 4001 may be connected to a plurality of gate lines G1 for providing gate driving signals to the plurality of gate lines G1 ;
  • the source drive circuit 4002 can be connected to a plurality of data lines D1 for providing data signals to the plurality of data lines D1.
  • the RLCD panel may be a total reflection type RLCD panel, or may be a transflective type RLCD panel.
  • FIG. 12 and FIG. 13 respectively show 10 randomly selected samples (ie, pixels). unit), each sample is affected by the parasitic capacitance, at the moment when the thin film transistor T1 is turned off, the measured value of the potential of the common electrode Vcom, and the measured value of the degree of ficker.
  • the parasitic capacitance includes Cgs2 and Cdp (that is, the parasitic capacitance formed between the data line D1 and the pixel electrode P1); for a conventional RLCD, the parasitic capacitance includes Cgs1, Cgs2 and Cdp ;
  • the parasitic capacitance includes Cgs1, Cgs2 and Cdp. Referring to FIG. 12 , it can be seen that the measured value of Vcom of the RLCD of the present disclosure drops from about 0.55 to about 0.2 compared with the conventional RLCD. Since the ideal potential of Vcom is 0 in the positive and negative driving switching stages, the smaller the measured value of Vcom, the better the display effect.
  • the display effect of the RLCD provided by the embodiment of the present disclosure is better.
  • the flicker degree of the RLCD of the present disclosure is reduced from about 6% to about 4% compared with the conventional RLCD, and the flicker degree is significantly reduced.
  • an embodiment of the present disclosure further provides a display device, and the display device may include the display panel shown in FIG. 10 or FIG. 11 .
  • the display device may be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, and navigator.

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Abstract

本公开提供了一种显示基板及其驱动方法、维修方法、显示面板、显示装置，属于显示技术领域。该显示基板中，沿栅线的扫描方向，第n行像素单元中的薄膜晶体管的栅极和所连接栅线在衬底基板上的正投影，与第n行像素单元中的像素电极在衬底基板上的正投影存在间隔，且与第n+1行像素单元中的像素电极在衬底基板上的正投影重叠。相应的，第n行像素单元中的薄膜晶体管的栅极和所连接栅线是与第n+1行像素单元中的像素电极形成寄生电容，而不会与第n行像素单元中的像素电极形成寄生电容。由于驱动电路是依次向第n行和第n+1行像素单元充电，因此形成的寄生电容不会对正在充电的像素单元造成影响。采用该显示基板的显示面板的显示效果较好。

Description

显示基板及其驱动方法、维修方法、显示面板、显示装置
本公开要求于2020年5月30日提交的申请号为202010480551.8、发明名称为“显示基板及其驱动方法、维修方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其驱动方法、维修方法、显示面板、显示装置。
背景技术
液晶显示(liquid crystal display，LCD)面板因其分辨率高、重量轻、低能耗和低辐射等优点被广泛应用于显示领域中。
LCD面板一般包括：衬底基板，以及位于衬底基板上的多个像素单元，每个像素单元包括相互连接的薄膜晶体管和像素电极。
发明内容
本公开提供了一种显示基板及其驱动方法、维修方法、显示面板、显示装置，所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板；
位于所述衬底基板上的多条栅线和多条数据线；
位于所述衬底基板上且阵列排布的多个像素单元，每个所述像素单元包括：薄膜晶体管和像素电极，所述薄膜晶体管的栅极与一条所述栅线连接，第一极与一条所述数据线连接，第二极与所述像素电极连接；
其中，沿所述多条栅线的扫描方向，第n行所述像素单元包括的薄膜晶体管的栅极和所连接的栅线在所述衬底基板上的正投影，与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影存在间隔，且与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠，n为大于或等于1的整数。
可选的，第n行所述像素单元包括的薄膜晶体管的第一极和第二极在所述衬底基板上的正投影，与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
可选的，第n行所述像素单元包括的薄膜晶体管的第二极在所述衬底基板上的正投影，还与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
可选的，任意相邻两个所述像素单元包括的像素电极，在所述栅线的延伸方向上的间距位于第一间距范围内；
任意相邻两个所述像素单元包括的像素电极，在所述数据线的延伸方向上的间距位于第二间距范围内；
每个所述像素单元中，所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内。
可选的，所述第一间距范围和所述第二间距范围均为3微米至7微米；所述第三间距范围为3微米至5微米。
可选的，每个所述像素单元包括的像素电极的材料均为金属材料，且所述金属材料的反射率大于反射率阈值；
或，所述显示基板还包括：位于所述像素电极远离所述衬底基板一侧的反光材料层，且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
可选的，每个所述像素单元包括的薄膜晶体管和像素电极沿远离所述衬底基板的方向依次层叠；
所述显示基板还包括：位于所述薄膜晶体管和所述像素电极之间的介质层；
其中，所述薄膜晶体管的栅极在所述衬底基板上的正投影和所述像素电极在所述衬底基板上的正投影存在重叠区域，所述介质层在所述衬底基板上的正投影与所述重叠区域重叠。
可选的，所述介质层的介电常数小于介电常数阈值，且所述介质层的厚度大于厚度阈值。
可选的，所述介质层的材料为有机树脂材料。
可选的，所述介质层在所述衬底基板上的正投影，覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影。
可选的，所述介质层的材料为金属材料。
可选的，所述薄膜晶体管还包括：有源层；所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠。
另一方面，提供了一种显示基板的驱动方法，所述显示基板为如上述方面所述的显示基板，所述方法包括：
沿所述显示基板中多条栅线的扫描方向，依次向每条所述栅线提供栅极驱动信号；向所述显示基板中的多条数据线提供数据信号；
其中，在向第n条栅线提供栅极驱动信号时，第n行像素单元中的薄膜晶体管响应于所述栅极驱动信号和所述数据信号，将第n行像素单元中的像素电极充电至第一电位；且在向第n条栅线提供栅极驱动信号时，在所述第n行像素单元中的薄膜晶体管的栅极和所述第n条栅线，与所述第n+1行像素单元中的像素电极形成的寄生电容的耦合作用下，第n+1行像素单元中的像素电极被拉动至第二电位；所述第二电位小于所述第一电位。
又一方面，提供了一种显示基板的维修方法，所述显示基板为如上述方面所述的显示基板，所述方法包括：
确定出现坏点的第一目标像素单元；
将所述第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接；
其中，所述第一目标像素单元位于第n行和第n+1行中的一行，第二目标像素单元位于所述第n行和所述第n+1行中的另一行，n为大于或等于1的整数。
再一方面，提供了一种显示面板，所述显示面板包括：对盒基板，以及如上述方面所述的显示基板。
可选的，所述显示面板还包括：驱动电路；
所述驱动电路分别与所述显示基板中的多条栅线和多条数据线连接，所述驱动电路用于向所述多条栅线提供栅极驱动信号，以及向所述多条数据线提供数据信号。
可选的，所述显示面板为全反射型液晶显示面板，或，半透半反射型液晶显示面板。
再一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的显示面板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的结构示意图；
图2是本公开实施例提供的一种像素单元的结构示意图；
图3是相关技术中LCD面板包括的像素电极充电的时序图；
图4是本公开实施例提供的另一种显示基板的结构示意图；
图5是本公开实施例提供的又一种显示基板的结构示意图；
图6是本公开实施例提供的再一种显示基板的结构示意图；
图7是本公开实施例提供的一种显示基板的驱动方法流程图；
图8是本公开实施例提供的一种像素电极充电时序图；
图9是本公开实施例提供的一种显示基板的维修方法流程图；
图10是本公开实施例提供的一种显示面板的结构示意图；
图11是本公开实施例提供的另一种显示面板的结构示意图；
图12是本公开实施例提供的一种Vcom实测值示意图；
图13是本公开实施例提供的一种闪烁程度实测值示意图。
具体实施方式
为使本公开实施例的发明构思的目的、技术方案和优点更加清楚，下面将结合附图和一些实施例对本公开实施例保护的发明构思做详细描述。
LCD面板一般包括：透射型LCD面板、反射型液晶显示(reflection type l iquid crystal display，RLCD)面板。且，RLCD面板又可以包括全反射型LCD面板和半透半反射型LCD面板。透射型LCD面板是指采用背光源所发光线实现显示的一种面板，RLCD面板是指利用环境光进行反射实现显示的一种面板。本公开实施例记载的LCD面板可以为任意一种LCD面板，且下述实施例以RL CD面板为例对申请内容进行说明。
相关技术中，透射型LCD面板的每个像素单元中，像素电极一般不会覆盖整个薄膜晶体管，可能仅覆盖薄膜晶体管的源漏极中连接像素电极的一极(如， 源极)。相应的，每个像素单元中，薄膜晶体管的栅极不会与像素电极形成寄生电容。而发明人在研究过程中发现，对于复用像素电极作为光线反射层的RL CD面板，为了提高反射率，一般可能会设置较大面积的像素电极以增加反射面积，导致每个像素单元中，像素电极与薄膜晶体管的栅极沿垂直于显示面板的方向出现重叠，此时像素电极与薄膜晶体管的栅极之间形成寄生电容，导致RL CD面板显示画面时易出现闪烁现象。
本公开实施例提供了一种显示基板，采用该显示基板的显示面板中，可以有效缓解因像素单元中的像素电极与该像素单元的薄膜晶体管的栅极之间形成寄生电容造成的画面闪烁问题，且进一步的，可以有效提高采用该显示基板的R LCD面板的反射率。
图1是本公开实施例提供的一种显示基板的结构示意图。如图1所示，该显示基板可以包括：衬底基板01，位于该衬底基板01上的多条栅线G1和多条数据线D1，以及位于衬底基板01上且阵列排布的多个像素单元02。其中，每条栅线G1可以均沿第一方向延伸，每条数据线D1可以均沿第二方向延伸，且第一方向和第二方向可以相互交叉，如可以相互垂直。
图2是本公开实施例提供的一种像素单元的结构示意图。结合图1和图2，每个像素单元02可以包括：薄膜晶体管(thin film transistor)T1和像素电极P1。其中，薄膜晶体管T1的栅极(gate)G0可以与一条栅线G1连接，如图2所示的G1(n+1)。薄膜晶体管T1的第一极D0可以与一条数据线D1连接，薄膜晶体管T1的第二极S0可以与像素电极P1连接。可选的，薄膜晶体管T1的第一极可以为源极和漏极中的一极，第二极可以为源极和漏极中的另一极。参考图1，本公开实施例以薄膜晶体管T1的第一极为漏极(drain)D0，薄膜晶体管T1的第二极为源极(source)S0为例进行说明。
且参考图2，每个像素单元02还可以包括公共电极Vcom，该公共电极Vc om可以设置于该显示基板上，或者，也可以设置于与该显示基板相对设置的对置基板上。对于公共电极Vcom设置于对盒基板上的场景(例如扭曲向列型液晶显示面板，Twisted Nematic，TN)，该公共电极Vcom和像素电极P1之间可以包括液晶分子，该公共电极Vcom和像素电极P1可以等效为一个液晶电容(c apacitance of liquid crystal)Clc，与此同时还可在显示基板上另设公共电极Vc  om2，该公共电极Vcom2和像素电极P1之间还可以形成存储电容(capacitance of storage)Cst。薄膜晶体管T1可以响应于其所连接的栅线G1提供的栅极驱动信号，向其所连接的像素电极P1输出来自所连接的数据线D1的数据信号，以为像素电极P1充电，进而使得像素电极P1和公共电极Vcom之间形成电位差。液晶分子在该电位差的作用下可以发生偏转，进而像素单元02发光。
相关技术中，因每个像素单元中的薄膜晶体管在衬底基板上的正投影与像素电极在衬底基板上的正投影重叠，即每个像素单元中的像素电极可能覆盖薄膜晶体管的栅极，甚至覆盖与栅极连接的栅线，故对于每个像素单元，该像素单元包括的薄膜晶体管的栅极和该栅极所连接栅线，与该像素单元包括的像素电极之间会形成一寄生电容，参考图2虚线标注Cgs1。在栅线G1上的电位发生变化时，因Cgs1的耦合作用，拉动与该栅线G1连接的像素电极P1的电位，使其偏离设定电位。因像素电极P1的电位发生变化，而公共电极Vcom的电位一般为定值，故像素电极和公共电极之间的电位差会发生变化，最终导致液晶分子偏转异常，显示效果较差。另外，除寄生电容Cgs1外，每个像素单元中，薄膜晶体管的栅极还会与薄膜晶体管所连接像素电极的一极，即源极之间形成另一寄生电容Cgs2。该寄生电容Cgs2属于薄膜晶体管器件本身结构的缺陷导致，无法避免。而寄生电容Cgs1则是因像素电极面积较大，与薄膜晶体管的栅极存在重叠区域导致。尤其是复用像素电极作为光线反射层，且为了提高反射率，设置较大面积的像素电极的RLCD面板包括的显示基板。当然，也可能是为了提高容值设置较大面积的像素电极的透射型LCD面板。
例如，图3示出了相关技术中向第n行像素单元02和第n+1行像素单元02所充电位时序示意图。参考图3可以看出，在第n条栅线G1(n)提供栅极驱动信号，且第n条数据线D1(n)提供数据信号时，充入至第n行像素单元02的像素电极P1(n)的电位在充电初期和充电末期均发生了一定程度的跳变。且，最终充入至像素电极P1(n)的实际电位偏离设定电位。第n+1行像素单元02同理。其中，n为大于或等于1的整数。
可选的，实际电位与设定电位之间的电位差△Vp可以满足：
Figure PCTCN2021085935-appb-000001
其中，C1是指寄生电容Cgs1和Cgs2的电容值之和，C2是指液晶电容Clc的电容值，C3是指存储电容Cst的电容值，Vgh是指栅极驱动信号的有效电位， Vgl是指栅极驱动信号的无效电位，且C1、C3、Vgh和Vgl一般为定值。可选的，有效电位可以大于无效电位，或者，有效电位可以小于无效电位。从上述公式(1)可以看出，寄生电容Cgs1的容值越大，C1即越大，进而不同灰阶的△Vp差异越大，画面闪烁越严重。
而参考图1，在本公开实施例中，沿多条栅线G1的扫描方向，第n行像素单元02中薄膜晶体管T1的栅极G0和所连接的栅线G1在衬底基板01上的正投影，与第n行像素单元02中的像素电极P1在衬底基板01上的正投影存在间隔，且与第n+1行像素单元02中的像素电极P1在衬底基板01上的正投影重叠。即，在本公开实施例中，第n行像素单元02中薄膜晶体管T1的栅极G0和所连接的栅线G1在衬底基板01上的正投影仅与第n+1行像素单元02中的像素电极P1在衬底基板01上的正投影重叠，而与第n行像素单元02中的像素电极P1在衬底基板01上的正投影不重叠。
通过该设置方式，可以使得第n行像素单元02中的薄膜晶体管T1的栅极G0和所连接的栅线G1，不会与第n行像素单元02中的像素电极P1形成寄生电容(如图2示出的Cgs1)。虽然会使得第n行像素单元02中的薄膜晶体管T1的栅极G0和所连接的栅线G1，与第n+1行像素单元02中的像素电极P1形成寄生电容Cgs1，但因是向第n行像素单元和第n+1行像素单元依次充电，即第n条栅线G1(n)扫描完成后，第n+1条栅线G1(n+1)才开始扫描。故，在向第n+1行像素单元02开始充电时第n条栅线G1(n)的电位已经已经趋于稳定，第n行像素单元02中的薄膜晶体管T1的栅极G0和第n条栅线G1，与第n+1行像素单元02中的像素电极P1之间形成的寄生电容Cgs1也不会对正在充电或已充电完成的第n+1行像素单元02的电位造成影响。
综上所述，本公开实施例提供了一种显示基板。由于沿栅线的扫描方向，第n行像素单元中的薄膜晶体管的栅极和所连接栅线在衬底基板上的正投影，与第n+1行像素单元中的像素电极在衬底基板上的正投影重叠，且与第n行像素单元中的像素电极在衬底基板上的正投影存在间隔，即与第n行像素单元中的像素电极在衬底基板上的正投影不重叠。相应的，第n行像素单元中的薄膜晶体管的栅极和所连接栅线是与第n+1行像素单元中的像素电极形成寄生电容，而不会与第n行像素单元中的像素电极形成寄生电容。由于驱动电路是依次向第n行和第n+1行像素单元充电，因此第n行像素单元中的薄膜晶体管的栅极 和第n条栅线，与第n+1行像素单元中的像素电极形成的寄生电容不会对正在充电的第n+1行像素单元造成影响。采用该显示基板的显示面板显示效果较好。
可选的，本公开下述实施例均以采用显示基板的显示面板为RLCD面板为例进行说明。相应的，为了实现对光线的反射，显示基板还可以包括：位于像素电极远离衬底基板一侧的反光材料层。且为了提高反射率，设置的反光材料层在衬底基板上的正投影的面积与像素电极在衬底基板上的正投影的面积可以正相关。即，像素电极的面积越大，反光材料层的面积也越大；像素电极的面积越小，反光材料层的面积也越小。或者，每个像素单元02包括的像素电极P1的材料可以均为金属材料，且该金属材料的反射率可以大于反射率阈值。即，可以复用像素电极P1实现导电的同时，实现对光线的反射。
并且，在像素电极P1作为光线反射层时，RLCD的反射面积与像素电极P1的面积正相关。故，结合图1，在本公开实施例中，通过设置每个像素单元02中，像素电极P1在衬底基板上的正投影与薄膜晶体管T1的源极S0在衬底基板上的正投影重叠。即可保证像素电极P1的面积较大，提高反射率。
可选的，为了进一步保证像素电极P1的面积较大，还可以设置任意相邻两个像素单元02包括的像素电极P1之间的间距可以小于间距阈值。如，结合图1，任意相邻两个像素单元02包括的像素电极P1，在栅线G1的延伸方向上的间距可以位于第一间距范围内。任意相邻两个像素单元02包括的像素电极P1，在数据线D1的延伸方向上的间距可以位于第二间距范围内。且，每个像素单元02中，像素电极P1与薄膜晶体管T1所连接的数据线D1之间的垂直距离可以位于第三间距范围内。
可选的，上述间距范围可以根据制造显示基板时的制造工艺灵活设置。例如，该第一间距范围和第二间距范围一般可以均为3微米(μm)至7μm。该第三间距范围一般可以为3μm至5μm。也即是，任意相邻两个像素单元02包括的像素电极P1，在栅线G1的延伸方向上的间距和在数据线D1的延伸方向上的间距均可以大于等于3μm，且小于等于7μm，如可以为5μm。每个像素单元02中，像素电极P1与薄膜晶体管T1所连接的数据线D1之间的垂直距离可以大于等于3μm，且小于等于5μm，如可以为4μm。
图4是本公开实施例提供的另一种显示基板的结构示意图。如图4所示， 第n行像素单元02包括的薄膜晶体管T1的第一极D0和第二极S0在衬底基板01上的正投影，也可以与第n+1行像素单元02包括的像素电极P1在衬底基板01上的正投影重叠。即可以将第n行像素单元02中的薄膜晶体管T1的主体置于第n+1行像素单元02中的像素电极P1下方。即，参考图4，第n+1行像素单元02中的像素电极P1可以覆盖第n行像素单元02中的薄膜晶体管T1的主体。另，结合图4，薄膜晶体管T1的主体包括：薄膜晶体管T1的整个栅极、大部分第一极(即漏极)D0和大部分第二极(即源极S0)。
结合图4，通过该设置方式，可以进一步确保第n行像素单元02的栅极G0和所连接栅线G1位于第n+1行像素单元中的像素电极P1下，即进一步避免第n行像素单元02中薄膜晶体管T1的栅极G0和所连接栅线G1，与像素电极P1形成寄生电容Cgs1，进而有效改善了显示效果。且，进一步增加了像素电极P1的面积，提高了复用像素电极P1作为光线反射层的RLCD面板的反射率。
可选的，由于薄膜晶体管T1的第二极S0需要与像素电极P1连接，因此为了确保两者的可靠连接，结合图1和图4，第n行像素单元02包括的薄膜晶体管T1的第二极S0在衬底基板01上的正投影，还可以与第n行像素单元02包括的像素电极P1在衬底基板01上的正投影重叠。
可选的，图5示出了本公开实施例提供的又一种显示基板的结构示意图，图6示出了本公开实施例提供的再一种显示基板的结构示意图。结合图5和图6可以看出，在本公开实施例中，每个像素单元02包括的薄膜晶体管T1和像素电极P1可以沿远离衬底基板01的方向依次层叠。且，结合图4、图5和图6，该显示基板还可以包括：位于存在重叠区域的薄膜晶体管T1和像素电极P1之间的介质层03。如，位于第n行像素单元02中的薄膜晶体管T1和第n+1行像素单元02中的像素电极P1之间的介质层03。且，介质层03在衬底基板01上的正投影可以与该重叠区域重叠。该介质层03可以用于降低第n行像素单元02中的薄膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容的电容值，或者，直接屏蔽第n行像素单元02中的薄膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容，从而进一步改善显示效果。
作为一种可选的实现方式：图5示出的介质层03的材料可以为非金属材料。且若介质层03的材料为非金属材料，为了有效降低第n行像素单元02中的薄 膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容的电容值，介质层03的介电常数可以小于介电常数阈值，且介质层03的厚度可以大于厚度阈值。同时参考图5，该介质层03在衬底基板01上的正投影，可以覆盖薄膜晶体管T1的栅极G0在衬底基板01上的正投影。例如，该介质层03的材料可以为有机树脂材料。其中，假设介质层03位于第n行像素单元02中的薄膜晶体管T1和第n+1行像素单元02中的像素电极P1之间，则此处介质层03在衬底基板01上的正投影，可以覆盖薄膜晶体管T1的栅极G0在衬底基板01上的正投影是指：介质层03在衬底基板01上的正投影，覆盖第n行像素单元02中的薄膜晶体管T1的栅极G0。
作为另一种可选的实现方式：图6示出的介质层03的材料可以为金属材料。由该金属材料制成的介质层03可以实现对第n行像素单元02中的薄膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容的直接屏蔽。
结合图5和图6，该薄膜晶体管T1除栅极G0、源漏极(S0和D0)外还可以包括：有源层(active)A0。该有源层A0可以位于源漏极(S0和D0)和栅极G0之间，且源极S0和漏极D0可以部分覆盖该有源层A0。
需要说明的是，在介质层03由金属材料制成时，为了避免该金属材料对源漏极沟道之间载流子移动的影响，参考图6，由金属材料制成的介质层03在衬底基板01上的正投影与有源层A0在衬底基板01上的正投影可以不重叠。其中，假设介质层03位于第n行像素单元02中的薄膜晶体管T1和第n+1行像素单元02中的像素电极P1之间，则此处不存在重叠是指位于介质层03，与第n行像素单元中的薄膜晶体管T1的有源层A0在衬底基板01上的正投影不重叠。当然，为了进一步避免金属材料对源漏极沟道之间载流子移动的影响，该介质层03也需要与其他行(如第n+1行)像素单元02中的薄膜晶体管T1的有源层A0在衬底基板01上的正投影不重叠。
可选的，为了进一步有效避免第n行像素单元02中的薄膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容对显示效果造成的影响，可以设置多层介质层03。如，可以设置一层由有机树脂材料制成的介质层03，并设置一层由金属材料制成的介质层03。
可选的，结合图5和图6，该显示基板还可以包括设置于每相邻两层结构之 间的绝缘层(如，附图标示的04、05和06)。且，图6还示出了形成的寄生电容Cgs1和Cgs2。假设图5和图6示出的介质层03是位于第n行像素单元02中的薄膜晶体管T1和第n+1行像素单元02中的像素电极P1之间，则此处的Cgs1是指第n行像素单元02中的薄膜晶体管T1的栅极和所连接栅线，与第n+1行像素单元02中的像素电极P1形成的寄生电容，Cgs2是指第n行像素单元02中的薄膜晶体管T1的第二极S0与栅极G0形成的寄生电容。
可选的，若同相关技术，第n行像素单元中的薄膜晶体管的栅极和所连接栅线在衬底基板上的正投影，与第n行像素单元中的像素电极在衬底基板上的正投影重叠，则作为一种上述实施例的可替代方案，可以直接在存在重叠区域的第n行像素单元中的薄膜晶体管和第n行像素单元中的像素电极之间设置上述记载的介质层03。即通过新增介质层03来降低第n行像素单元中的薄膜晶体管的栅极和所连接栅线，与第n行像素单元中的像素电极形成的寄生电容Cgs1的电容值，或，直接屏蔽该寄生电容Cgs1。介质层03的可选设置位置和可选材料可以参考上述图5和图6实施例的记载，在此不再赘述。
可选的，显示基板可以包括显示区域(active area，AA)和非显示区域，上述实施例记载的像素单元02可以设置于AA区域中。非显示区域可以用于设置为栅线和数据线提供信号的驱动电路。且，本公开实施例记载的薄膜晶体管T1可以采用a硅(a-silicon，a-Si)材料制成，或，可以采用低温多晶硅(low temperature poly silicon，LTPS)材料制成，或，可以采用氧化物(oxide)材料制成。
综上所述，本公开实施例提供了一种显示基板。由于沿栅线的扫描方向，第n行像素单元中的薄膜晶体管的栅极和所连接栅线在衬底基板上的正投影，与第n+1行像素单元中的像素电极在衬底基板上的正投影重叠，且与第n行像素单元中的像素电极在衬底基板上的正投影存在间隔，即与第n行像素单元中的像素电极在衬底基板上的正投影不重叠。相应的，第n行像素单元中的薄膜晶体管的栅极和所连接栅线是与第n+1行像素单元中的像素电极形成寄生电容，而不会与第n行像素单元中的像素电极形成寄生电容。由于驱动电路是依次向第n行和第n+1行像素单元充电，因此第n行像素单元中的薄膜晶体管的栅极和第n条栅线，与第n+1行像素单元中的像素电极形成的寄生电容不会对正在充电的第n+1行像素单元造成影响。采用该显示基板的显示面板显示效果较好。
图7是本公开实施例提供的一种显示基板的驱动方法流程图，该显示基板可以为如图1、图4至图6任一所示的显示基板。如图7所示，该方法可以包括：
步骤701、沿显示基板中多条栅线的扫描方向，依次向每条栅线提供栅极驱动信号，并向显示基板中的多条数据线提供数据信号。
因第n行像素单元中的薄膜晶体管的栅极和所连接栅线在衬底基板上的正投影，与第n+1行像素单元中的像素电极在衬底基板上的正投影重叠。故，结合图8，在向第n条栅线G1(n)提供栅极驱动信号时，第n行像素单元02中的薄膜晶体管T1可以响应于栅极驱动信号和数据信号，将第n行像素单元02中的像素电极P1(n)充电至第一电位V1。在同一阶段，在第n行像素单元02的薄膜晶体管T1的栅极和第n条栅线，与第n+1行像素单元02中的像素电极P1(n+1)形成的寄生电容Cgs1的耦合作用下，第n+1行像素单元02中的像素电极P1(n+1)被拉动至第二电位V2。且该第二电位V2可以小于第一电位V1。
即，对比图3和图8，在本公开实施例中，由于将寄生电容Cgs1对相应行的像素单元02中像素电极P1电位带来的影响，调整至未对该行像素单元02充电之前。即参考图8，将寄生电容Cgs1造成的像素电极P1电位跳变时刻进行前置，因此有效避免了对正在充电的像素单元02的正常充电造成影响，改善了显示效果。
结合图8，对第n行像素单元和第n+1行像素单元的充电过程可以分为三个阶段：参考图8，在第一阶段t1，先向第n条栅线G1(n)提供栅极驱动信号，此时，仅第n行像素单元02中的薄膜晶体管T1均开启，多条数据线D1通过开启的薄膜晶体管T1向第n行像素单元中02中的像素电极P1(n)写入第一电位。且，在第一阶段t1，由于第n行像素单元02的薄膜晶体管T1的栅极G0和所连接栅线G1(n)在衬底基板01上的正投影，与第n+1行像素单元02中的像素电极P1在衬底基板01上的正投影存在交叠，因此形成一寄生电容Cgs1。在该寄生电容Cgs1的耦合作用下，使得第n条栅线G1(n)对第n+1行像素单元02中的像素电极P1(n+1)的电位产生一定拉动，此时，参考图8，第n+1行像素单元02中的像素电极P1(n+1)的电位被拉至第二电位，偏离初始电位。
在第二阶段t2，停止向第n条栅线G1(n)提供栅极驱动信号，开始向第n+1条栅线G1(n+1)提供栅极驱动信号。此时，仅第n+1行像素单元02中的薄膜晶体管T1均开启，多条数据线D1通过开启的薄膜晶体管T1向第n+1行 像素单元中02中的像素电极P1(n+1)写入第一电位。且在该第二阶段t2，第n行像素单元02的薄膜晶体管T1的栅极G0和第n条栅线G1(n)，与第n+1行像素单元02的像素电极P1(n+1)形成的寄生电容Cgs1不会对该像素电极P1(n+1)的电位产生任何影响。
在第三阶段t3，第n+1行像素单元02充电完成达到设定电位。此时，第n+1行像素单元02的像素电极P1(n+1)的电位仅受寄生电容Cgs2的影响，变化幅度较小，进而，显示画面闪烁现象得到明显改善。
需要说明的是，向栅线提供栅极驱动信号是指向栅线提供有效电位的栅极驱动信号，停止向栅线提供栅极驱动信号是指向栅线提供无效电位的栅极驱动信号。该有效电位可以为高电位，相应的，该无效电位可以为低电位；或者，该有效电位可以为低电位，相应的，该无效电位可以为高电位。有效电位和无效电位的高低取决于薄膜晶体管T1的类型。如，假设薄膜晶体管T1为N型晶体管，则有效电位可以为高电位，无效电位可以为低电位；假设薄膜晶体管T1为P型晶体管，则有效电位可以为低电位，无效电位可以为高电位。
综上所述，本公开实施例提供了一种显示基板的驱动方法。由于在向第n条栅线提供栅极驱动信号时，第n行像素单元中的薄膜晶体管可以响应于栅极驱动信号和数据信号，将第n行像素单元中的像素电极充电至第一电位；且在第n行像素单元的薄膜晶体管的栅极和第n条栅线，与第n+1行像素单元中的像素电极形成的寄生电容的耦合作用下，第n+1行像素单元中的像素电极被拉动至小于第一电位的第二电位。又由于是依次向第n行和第n+1行像素单元充电，因此第n行像素单元中的薄膜晶体管的栅极和第n条栅线，与第n+1行像素单元中的像素电极形成的寄生电容不会对正在充电的像素单元造成影响。采用本公开实施例提供的显示基板的显示面板的显示效果较好。
可选的，图9本公开实施例提供的一种显示基板的维修方法的流程图，该显示基板可以为如图1、图4至图6任一所示的显示基板。如图9所示，该方法可以包括：
步骤901、确定出现坏点的第一目标像素单元。
可选的，可能有多种不同原因造成像素单元出现坏点，如，像素单元连接的数据线发生短路(open)。在本公开实施例中，可以通过各类测试方法(如， 阵列测试)确定出现坏点的第一目标像素单元。且，以显示基板为扭曲向列(twisted nematic，TN)型显示基板，且TN型显示基板制成的显示面板在正常显示为常白状态为例，步骤901确定的坏点可以为亮点。
步骤902、将第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接。
可选的，可以通过激光焊接的方式将第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接。其中，结合图1，该第一目标像素单元可以位于第n行和第n+1行中的一行，第二目标像素单元可以位于第n行和第n+1行中的另一行，n为大于或等于1的整数。即，若第一目标像素单元为第n行像素单元中的某个像素单元，则第二目标像素单元即为第n+1行像素单元中的某个像素单元。若第一目标像素单元为第n+1行像素单元中的某个像素单元，则第二目标像素单元即为第n行像素单元中的某个像素单元。
由于在本公开实施例中，第n行像素单元包括的薄膜晶体管的栅极和所连接的栅线在衬底基板上的正投影，与第n+1行像素单元包括的像素电极在衬底基板上的正投影重叠，因此假设第一目标像素单元为第n+1行像素单元中的某个像素单元，第二目标像素单元为第n行像素单元中的某个像素单元，且坏点为亮点，则可以在检测到第一目标像素单元出现亮点时，将第n+1行像素单元中被点亮的像素单元包括的像素电极与第n行像素单元所连接栅线G1相接。相接后，即可以使得被点亮的第一目标像素单元的像素电极与公共电极形成一较大压差，进而使得被点亮的第一目标像素单元变暗，达到修复亮点的效果。
综上所述，本公开实施例提供了一种显示基板的维修方法。由于该显示基板中第n行像素单元中薄膜晶体管和第n+1行像素单元中像素电极独特的设置位置，因此使得可以在确定出出现坏点的第一目标像素单元时，通过直接将第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接以达到修复坏点的目的，维修方法较为简单。
可选的，图10是本公开实施例提供的一种显示面板的结构示意图。如图10所示，该显示面板可以包括：对盒基板100，以及如图1、图4至图6任一所示的显示基板200。
可选的，该对盒基板100可以为彩膜基板，显示基板200可以为阵列基板， 相应的，参考图10，该显示面板还可以包括：位于对盒基板100和显示基板200之间的液晶层300，该液晶层300中包括多个液晶分子。即该显示面板可以为LCD面板。
可选的，图11是本公开实施例提供的另一种显示面板的结构示意图。如图11所示，该显示面板还可以包括：驱动电路400。
其中，该驱动电路400可以与显示基板200中的多条栅线G1和多条数据线D1分别连接，驱动电路400可以用于向多条栅线G1提供栅极驱动信号，以及向多条数据线D1提供数据信号。
例如，参考图11，驱动电路400可以包括栅极驱动电路4001和源极驱动电路4002，栅极驱动电路4001可以与多条栅线G1连接，用于向多条栅线G1提供栅极驱动信号；源极驱动电路4002可以与多条数据线D1连接，用于向多条数据线D1提供数据信号。
可选的，该RLCD面板可以为全反射型RLCD面板，或者，可以为半透半反射型RLCD面板。
以显示灰阶为127的画面为例，对比常规LCD、相关技术中的常规RLCD和本公开实施例提供的本公开RLCD，图12和图13分别示出了随机抽取的10个样品(即像素单元)中，每个样品因寄生电容影响，在关断薄膜晶体管T1的瞬间，公共电极Vcom的电位实测值，以及闪烁(ficker)程度实测值。
可选的，对于常规LCD而言，该寄生电容包括Cgs2和Cdp(即，数据线D1和像素电极P1之间形成的寄生电容)；对于常规RLCD而言，该寄生电容包括Cgs1、Cgs2和Cdp；对于本公开RLCD而言，该寄生电容包括Cgs1、Cgs2和Cdp。参考图12可以看出，本公开RLCD相对于常规RLCD，Vcom实测值由0.55左右下降至0.2左右。由于在正极性和负极性驱动切换阶段，Vcom的理想电位为0，因此Vcom实测值越小，显示效果越好。故，本公开实施例提供的RLCD的显示效果较好。且，结合图13也可以看出，本公开RLCD相对于常规RLCD闪烁程度由6％左右降低至4％左右，闪烁程度明显下降。
可选的，本公开实施例还提供了一种显示装置，该显示装置可以包括图10或图11所示的显示面板。可选的，该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的 精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板；
    位于所述衬底基板上的多条栅线和多条数据线；
    位于所述衬底基板上且阵列排布的多个像素单元，每个所述像素单元包括：薄膜晶体管和像素电极，所述薄膜晶体管的栅极与一条所述栅线连接，第一极与一条所述数据线连接，第二极与所述像素电极连接；
    其中，沿所述多条栅线的扫描方向，第n行所述像素单元包括的薄膜晶体管的栅极和所连接的栅线在所述衬底基板上的正投影，与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影存在间隔，且与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠，n为大于或等于1的整数。
  2. 根据权利要求1所述的显示基板，其中，第n行所述像素单元包括的薄膜晶体管的第一极和第二极在所述衬底基板上的正投影，与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
  3. 根据权利要求1所述的显示基板，其中，第n行所述像素单元包括的薄膜晶体管的第二极在所述衬底基板上的正投影，还与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
  4. 根据权利要求1至3任一所述的显示基板，其中，
    任意相邻两个所述像素单元包括的像素电极，在所述栅线的延伸方向上的间距位于第一间距范围内；
    任意相邻两个所述像素单元包括的像素电极，在所述数据线的延伸方向上的间距位于第二间距范围内；
    每个所述像素单元中，所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内。
  5. 根据权利要求4所述的显示基板，其中，所述第一间距范围和所述第二间 距范围均为3微米至7微米；所述第三间距范围为3微米至5微米。
  6. 根据权利要求1至5任一所述的显示基板，其中，
    每个所述像素单元包括的像素电极的材料均为金属材料，且所述金属材料的反射率大于反射率阈值；
    或，所述显示基板还包括：位于所述像素电极远离所述衬底基板一侧的反光材料层，且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
  7. 根据权利要求1至6任一所述的显示基板，其中，每个所述像素单元包括的薄膜晶体管和像素电极沿远离所述衬底基板的方向依次层叠；
    所述显示基板还包括：位于所述薄膜晶体管和所述像素电极之间的介质层；
    其中，所述薄膜晶体管的栅极在所述衬底基板上的正投影和所述像素电极在所述衬底基板上的正投影存在重叠区域，所述介质层在所述衬底基板上的正投影与所述重叠区域重叠。
  8. 根据权利要求7所述的显示基板，其中，所述介质层的介电常数小于介电常数阈值，且所述介质层的厚度大于厚度阈值。
  9. 根据权利要求8所述的显示基板，其中，所述介质层的材料为有机树脂材料。
  10. 根据权利要求8所述的显示基板，其中，所述介质层在所述衬底基板上的正投影，覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影。
  11. 根据权利要求7所述的显示基板，其中，所述介质层的材料为金属材料。
  12. 根据权利要求11所述的显示基板，其中，所述薄膜晶体管还包括：有源层；所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠。
  13. 根据权利要求8所述的显示基板，其中，所述介质层在所述衬底基板上的正投影，覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影；
    任意相邻两个所述像素单元包括的像素电极，在所述栅线的延伸方向上的间距位于第一间距范围内；任意相邻两个所述像素单元包括的像素电极，在所述数据线的延伸方向上的间距位于第二间距范围内；每个所述像素单元中，所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内；所述第一间距范围和所述第二间距范围均为3微米至7微米；所述第三间距范围为3微米至5微米；
    每个所述像素单元包括的像素电极的材料均为金属材料，且所述金属材料的反射率大于反射率阈值；或，所述显示基板还包括：位于所述像素电极远离所述衬底基板一侧的反光材料层，且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
  14. 根据权利要求11所述的显示基板，其中，所述薄膜晶体管还包括：有源层；所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠；
    任意相邻两个所述像素单元包括的像素电极，在所述栅线的延伸方向上的间距位于第一间距范围内；任意相邻两个所述像素单元包括的像素电极，在所述数据线的延伸方向上的间距位于第二间距范围内；每个所述像素单元中，所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内；所述第一间距范围和所述第二间距范围均为3微米至7微米；所述第三间距范围为3微米至5微米；
    每个所述像素单元包括的像素电极的材料均为金属材料，且所述金属材料的反射率大于反射率阈值；或，所述显示基板还包括：位于所述像素电极远离所述衬底基板一侧的反光材料层，且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
  15. 一种显示基板的驱动方法，其中，所述显示基板为如权利要求1至14任一所述的显示基板，所述方法包括：
    沿所述显示基板中多条栅线的扫描方向，依次向每条所述栅线提供栅极驱动信号；向所述显示基板中的多条数据线提供数据信号；
    其中，在向第n条栅线提供栅极驱动信号时，第n行像素单元中的薄膜晶体管响应于所述栅极驱动信号和所述数据信号，将第n行像素单元中的像素电极充电至第一电位；且在向第n条栅线提供栅极驱动信号时，在所述第n行像素单元中的薄膜晶体管的栅极和所述第n条栅线，与所述第n+1行像素单元中的像素电极形成的寄生电容的耦合作用下，第n+1行像素单元中的像素电极被拉动至第二电位；所述第二电位小于所述第一电位。
  16. 一种显示基板的维修方法，其中，所述显示基板为如权利要求1至14任一所述的显示基板，所述方法包括：
    确定出现坏点的第一目标像素单元；
    将所述第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接；
    其中，所述第一目标像素单元位于第n行和第n+1行中的一行，第二目标像素单元位于所述第n行和所述第n+1行中的另一行，n为大于或等于1的整数。
  17. 一种显示面板，其中，所述显示面板包括：对盒基板，以及如权利要求1至14任一所述的显示基板。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板还包括：驱动电路；
    所述驱动电路分别与所述显示基板中的多条栅线和多条数据线连接，所述驱动电路用于向所述多条栅线提供栅极驱动信号，以及向所述多条数据线提供数据信号。
  19. 根据权利要求17所述的显示面板，其中，所述显示面板为全反射型液晶显示面板，或，半透半反射型液晶显示面板。
  20. 一种显示装置，其中，所述显示装置包括：如权利要求17至19任一所 述的显示面板。
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