WO2020220596A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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WO2020220596A1
WO2020220596A1 PCT/CN2019/111382 CN2019111382W WO2020220596A1 WO 2020220596 A1 WO2020220596 A1 WO 2020220596A1 CN 2019111382 W CN2019111382 W CN 2019111382W WO 2020220596 A1 WO2020220596 A1 WO 2020220596A1
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Prior art keywords
array substrate
electrode
thin film
film transistor
common electrode
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PCT/CN2019/111382
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English (en)
French (fr)
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肖偏
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020220596A1 publication Critical patent/WO2020220596A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the electric field that controls the liquid crystal molecules is determined by the voltage difference between the pixel electrode and the common electrode (called the pixel voltage), but due to the existence of parasitic capacitance, the gate When the signal is turned off, the voltage of the pixel electrode will have a Vfth (called feed-through voltage) deviation before and after the jump (feed-through effect).
  • the feedthrough voltage (vfth) is related to the change of gate voltage and various coupling capacitances, namely
  • Vfth is the feedthrough voltage
  • Cgd is the coupling capacitance between the gate and the drain
  • Clc is the liquid crystal capacitance
  • Cst is the storage capacitance
  • Vgh is the gate line high voltage (also called the turn-on voltage)
  • Vgl is the gate Line low voltage (also called shutdown voltage).
  • the feedthrough voltage ⁇ Vp will cause an imbalance when the pixel voltage polarity is reversed, causing the gray-scale voltage reference of each pixel to have several errors, so that the human eye can observe the phenomenon of flickering in the display screen, and reduce the display of the liquid crystal display panel. quality.
  • the prior art has the problems of flickering, low display effect, and uneven display images.
  • the present application provides an array substrate and a display panel to improve the phenomenon of display flicker, display effect, and uneven image.
  • An array substrate comprising a base substrate, a plurality of common electrodes arranged on the base substrate, and a plurality of transparent electrodes arranged on the plurality of common electrodes, the plurality of common electrodes and The transparent electrodes are arranged in one-to-one correspondence, and the transparent electrodes partially overlap the corresponding common electrodes.
  • a storage capacitor is formed in a partially overlapping area of the transparent electrode and the corresponding common electrode, and the storage capacitor is used to adjust the voltage of the common electrode.
  • the size of the overlapping area of the transparent electrode and the common electrode is increasing or decreasing.
  • the overlap area of the transparent electrode and the common electrode has a trend of increasing or decreasing.
  • the overlapping area of the transparent electrode and the corresponding common electrode ranges from 1 square micrometer to 4 square micrometers.
  • the array substrate further includes a plurality of scan lines arranged in a horizontal direction and a plurality of data lines arranged in a vertical direction, and a pixel unit is arranged above the intersection area of the scan line and the data line .
  • the pixel unit includes: a thin film transistor, a gate of the thin film transistor is connected to one of the scan lines, and a source of the thin film transistor is connected to one of the data lines;
  • a pixel electrode connected to the drain of the thin film transistor
  • the transparent electrode and the gate electrode of the thin film transistor, the drain electrode of the thin film transistor or the pixel electrode are arranged in the same layer.
  • the common electrode is provided between the gate of the thin film transistor and the base substrate, and the transparent electrode and the drain of the thin film transistor are provided in the same layer.
  • the transparent electrode and the common electrode are made of the same material, and the material includes indium tin oxide.
  • the present application also provides an array substrate, which includes a base substrate, a plurality of common electrodes arranged on the base substrate, and a plurality of transparent electrodes arranged on the plurality of common electrodes.
  • a common electrode and a plurality of the transparent electrodes are arranged in a one-to-one correspondence, and the transparent electrode and the corresponding common electrode partially overlap;
  • the transparent electrode and a part of the overlapping area corresponding to the common electrode form a storage capacitor, and the storage capacitor is used to adjust the voltage of the common electrode;
  • the overlapping area of the transparent electrode and the common electrode is increasing or decreasing.
  • the overlapping area of the transparent electrode and the common electrode is increasing or decreasing.
  • the size of the overlapping area of the transparent electrode and the corresponding common electrode ranges from 1 square micrometer to 4 square micrometers.
  • the array substrate further includes a plurality of scan lines arranged in a horizontal direction and a plurality of data lines arranged in a vertical direction, and a pixel unit is arranged above the intersection area of the scan line and the data line .
  • the pixel unit includes: a thin film transistor, a gate of the thin film transistor is connected to one of the scan lines, and a source of the thin film transistor is connected to one of the data lines;
  • a pixel electrode connected to the drain of the thin film transistor
  • the transparent electrode and the gate electrode of the thin film transistor, the drain electrode of the thin film transistor or the pixel electrode are arranged in the same layer.
  • the common electrode is provided between the gate of the thin film transistor and the base substrate, and the transparent electrode and the drain of the thin film transistor are provided in the same layer.
  • the transparent electrode and the common electrode are made of the same material, and the material includes indium tin oxide.
  • the present application also provides a display panel, including an array substrate, the array substrate including a base substrate, a plurality of common electrodes arranged on the base substrate, and a plurality of transparent electrodes arranged on the plurality of common electrodes, A plurality of the common electrodes and a plurality of the transparent electrodes are arranged in a one-to-one correspondence, and the transparent electrodes and the corresponding common electrodes partially overlap.
  • the array substrate and the display panel provided by the present application can change the size of the storage capacitor by changing the area where the transparent electrode layer in different pixel units in the array substrate overlap the projection of the common electrode layer, thereby improving display flicker, display effect, and image failure. Homogeneous phenomenon.
  • FIG. 1 is an equivalent circuit diagram of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 2 is a graph of voltage changes across the liquid crystal in the pixel unit of the liquid crystal display panel provided in an embodiment of the application during the charging phase and the holding phase.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • FIG. 4 is a detailed structure diagram of a storage capacitor provided by an embodiment of the application.
  • FIG. 5 is a layout diagram of storage capacitors provided by an embodiment of the application.
  • FIG. 6 is another arrangement diagram of storage capacitors provided by an embodiment of the application.
  • Figure 7 is a process flow diagram provided by an embodiment of the application.
  • the embodiments of the present invention provide an array substrate, a liquid crystal display panel, and a display device, which are used to improve or eliminate the influence of feedthrough voltage, thereby improving the flicker problem of the display screen and improving the display quality of the liquid crystal display panel.
  • the array substrate provided by the embodiment of the present application includes: a base substrate 11, a plurality of scan lines 12 and a plurality of data lines 13 intersectingly arranged on the base substrate 11. At least one scan line 12 is connected for adjustment The storage capacitor 14 for the common electrode voltage Vcom, one end of the storage capacitor 14 is connected to a scan line 12, and the other end is connected to the common electrode voltage Vcom.
  • the storage capacitor 14 of the array substrate includes a common electrode and a transparent electrode (not shown in the figure), the common electrode corresponds to the transparent electrode one-to-one, and the storage capacitor 14 is arranged in an array in the array substrate. That is, the common electrode corresponding to the storage capacitor and the transparent electrode appear in pairs and are arranged in an array, and the transparent electrode and the corresponding common electrode partially overlap.
  • the storage capacitor 14 is disposed on the edge area of the array substrate.
  • the storage capacitor 14 is disposed on the left edge area or the right edge area of the array substrate.
  • each scan line 12 is connected to a storage capacitor 14 (denoted as Cst, as shown by the dashed frame in FIG. 1), so that any pixel on the display liquid crystal display panel At this time, the voltage difference between the pixel electrode and the common electrode will remain basically unchanged. Therefore, the influence of the feedthrough voltage can be eliminated as much as possible, thereby improving the flicker problem of the display screen and improving the display quality of the liquid crystal display panel.
  • one end of the storage capacitor Cst is connected to the common electrode voltage Vcom, but the embodiment of the present application is not limited to this. For example, one end of the storage capacitor Cst may also be connected to the next scan line.
  • FIG. 2 shows that when the thin film transistor is turned on to off, the feed-through effect makes the pixel electrode voltage rise and fall with the rise and fall of the gate voltage.
  • the capacitor used to adjust the common electrode voltage makes the common electrode voltage follow the scan line connected to the capacitor.
  • the feedthrough voltage is mainly caused by the changes of other voltages on the panel, via parasitic capacitance or storage capacitance, which affects the correctness of the display electrode voltage.
  • the most influential factors are the gate drive voltage change (via Cgd or Cs), and the common voltage change (via Clc or Cs+Clc), and the common voltage is fixed, causing the feedthrough voltage
  • the main reason is only the voltage change of the gate drive.
  • Thin film transistors are designed with a stacked structure. Due to the margin of exposure engineering, the source and drain, and the gate and drain will inevitably overlap. When the electrodes overlap, capacitance 14 is likely to be generated, which has a greater impact on the thin film transistor liquid crystal display (TFT-LCD).
  • TFT-LCD thin film transistor liquid crystal display
  • the arrangement of the transparent electrode 141 and the common electrode 142 in the above-mentioned storage capacitor 14 can be implemented in a variety of ways, which are described below with reference to the accompanying drawings.
  • the transparent electrode 141 and the pixel electrode 16 are provided in the same layer, and the common electrode 142 and the gate 152 of the thin film transistor 15 are provided in the same layer.
  • the transparent electrode 141 can be connected to the scan line 12 through a via hole, for example, the common electrode 142 of each storage capacitor 14 can be connected to a line first, and then the common electrode voltage Vcom is connected by the line, and the line is in line with the data line 13
  • the projections on the base substrate 11 may be parallel.
  • the common electrode 142 of each storage capacitor 14 may also be connected to the common electrode voltage Vcom, which is not limited in the embodiment of the present invention.
  • FIG. 4 is a detailed structural diagram of the storage capacitor 14 provided by an embodiment of the application.
  • a storage capacitor 14 is formed by the transparent electrode 141 and the corresponding common electrode 142 in a partially overlapping area, and the storage capacitor is used to adjust the voltage (Vcom) of the common electrode.
  • the length of the overlapping area of the transparent electrode and the corresponding common electrode provided by the embodiment of the present application ranges from 1 micron to 2 microns, and correspondingly, the wide range of the overlapping area It is also 1 micrometer to 2 micrometers; further, in the array substrate provided by the embodiment of the present application, the overlapping area is rectangular, that is, the size of the overlapping area ranges from 1 square micrometer to 4 square micrometers.
  • the overlapping area of the transparent electrode 141 and the common electrode 142 is increasing or decreasing.
  • the formula of area size and capacitance value ⁇ is the dielectric capacitance value of the storage capacitor value
  • S is the facing area of the storage capacitor
  • S is the size of the overlap area
  • k is the electrostatic force constant of the storage capacitor
  • d Is the distance between the two plates of the storage capacitor.
  • the size of the storage capacitor C is proportional to the size of the overlap area; in the embodiment of the present application, the size of the overlap area is reduced , Thereby reducing the size of the storage capacitor.
  • the embodiment of the present application only proposes that in one row of the array substrate, the overlapping area of the transparent electrode 141 and the common electrode 142 is increasing or decreasing.
  • the present application is not limited to the increasing or decreasing trend of the overlapping area of the transparent electrode 141 and the common electrode 142 in a row.
  • along the extending direction of the data line The overlapping area of the transparent electrode 141 and the common electrode 142 in the first row may have an increasing trend, and the overlapping area of the transparent electrode 141 and the common electrode 142 in the second row may have a decreasing trend or an increasing trend, and so on. .
  • the overlapping area of the transparent electrode and the common electrode is increasing or decreasing.
  • the embodiment of the present application only proposes that in one column of the array substrate, the overlapping area of the transparent electrode 141 and the common electrode 142 is increasing or decreasing.
  • the present application is not limited to the increasing or decreasing trend of the overlapping area of the transparent electrode 141 and the common electrode 142.
  • along the extending direction of the data line The overlapping area of the transparent electrode 141 in the first column and the common electrode 142 may have an increasing trend, the overlapping area of the transparent electrode 141 in the second row and the common electrode 142 may have a decreasing trend or an increasing trend, and so on .
  • the embodiment of the present application may prioritize testing the average grayscale value of the array substrate before adjusting the liquid crystal display panel, and according to the feedthrough voltage (vfth) and gate voltage changes Among them, Vfth is the feedthrough voltage, Cgd is the coupling capacitance between the gate and the drain, Clc is the liquid crystal capacitance, Cst is the storage capacitance, Vgh is the gate line high voltage (also called the turn-on voltage), and Vgl is the gate Line low voltage (also called shutdown voltage).
  • Vfth is the feedthrough voltage
  • Cgd is the coupling capacitance between the gate and the drain
  • Clc the liquid crystal capacitance
  • Cst the storage capacitance
  • Vgh is the gate line high voltage (also called the turn-on voltage)
  • Vgl is the gate Line low voltage (also called shutdown voltage).
  • the transparent electrode and the common electrode are made of the same material, and the material includes Indium Tin Oxide (ITO for short).
  • ITO Indium Tin Oxide
  • the common electrode line is connected to the common electrode, the gate of the thin film transistor is not in contact with the common electrode, and the materials of the gate, the scan line and the common electrode line can be Mo/Al/Mo, for example.
  • the source electrode and the data line are connected, and the material of the source electrode, the drain electrode and the data line may be Mo/Al/Mo, for example.
  • the transparent electrode and the common electrode are made of the same material, and the material includes indium tin oxide.
  • the transparent electrode is connected to the drain of the thin film transistor, the transparent electrode 141 is connected to the scan line, and the transparent electrode 141 and the common electrode 142 overlap the projections on the base substrate to form a storage capacitor 14 for adjusting the common electrode voltage.
  • the feed-through effect causes the voltage of the pixel electrode to rise and fall with the rise and fall of the gate voltage, which is used to adjust the capacitance of the common electrode voltage.
  • the common electrode voltage rises and falls with the rise and fall of the gate voltage on the scan line connected to the capacitor.
  • an embodiment of the invention also provides a display panel, including the array substrate provided by any embodiment of the invention.
  • an embodiment of the present invention provides a display device, including: the liquid crystal display panel provided by any embodiment of the present invention.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the beneficial effect is: changing the size of the storage capacitor by changing the area where the transparent electrode layer in different pixel units in the array substrate overlaps the projection of the common electrode layer, thereby improving the phenomenon of display flicker, display effect, and uneven image.

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Abstract

一种阵列基板，包括衬底基板（11）、设置于衬底基板（11）上的多个公共电极（142）、以及设置于多个公共电极（142）上的多个透明电极（141），多个公共电极（142）和多个透明电极（141）一一对应设置，透明电极（141）和对应公共电极（142）部分重叠。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
背景技术
在液晶显示面板(Liquid Crystal Display，简称LCD)中，控制液晶分子的电场是由像素电极和公共电极之间的电压差(称为像素电压)来决定的，但是由于寄生电容的存在，栅极信号在关闭时会导致像素电极的电压在发生跳变前后存在Vfth(称为馈通电压)的偏差(feed-through效应)。
馈通电压(vfth)与栅极(gate)电压的变化和各种耦合电容相关，即
Figure PCTCN2019111382-appb-000001
其中，Vfth为馈通电压，Cgd为栅极和漏极之间的耦合电容、Clc为液晶电容，Cst为存储电容，Vgh为栅极线高电压(也称为开启电压)，Vgl为栅极线低电压(也称为关闭电压)。该馈通电压ΔVp将造成像素电压极性反转时的不平衡，使得各像素的灰阶电压基准有若干误差，因而使人眼观察到显示画面产生闪烁的现象，降低了液晶显示面板的显示品质。
综上所述，现有技术的显示画面闪烁、显示效果低、显示画面不均匀的问题。
技术问题
本申请提供了一种阵列基板及显示面板，以改善显示画面闪烁、显示效果、画面不均匀的现象。
技术解决方案
本申请提供的技术方案如下：
一种阵列基板，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠。
在本申请所提供的阵列基板中，所述透明电极和对应所述公共电极部分重叠区域形成有存储电容，所述存储电容用于调节所述公共电极的电压。
在本申请所提供的阵列基板中，沿着所述扫描线的延伸方向，所述透明电极和所述公共电极的重叠面积大小呈递增或递减趋势。
在本申请所提供的阵列基板中，沿着所述数据线的延伸方向，所述透明电极和所述公共电极的重叠面积大小呈递增或递减趋势。
在本申请所提供的阵列基板中，所述透明电极和对应所述公用电极的重叠面积的范围为1平方微米至4平方微米。
在本申请所提供的阵列基板中，所述阵列基板还包括多条横向排列的扫描线以及多条竖向排列的数据线，所述扫描线与所述数据线的交叉区域上方设置有像素单元。
在本申请所提供的阵列基板中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极连接一条所述扫描线，所述薄膜晶体管的源极连接一条所述数据线；
像素电极，连接所述薄膜晶体管的漏极；
所述透明电极与所述薄膜晶体管的栅极、所述薄膜晶体管的漏极或所述像素电极同层设置。
在本申请所提供的阵列基板中，所述公共电极设置于所述薄膜晶体管的栅极与所述衬底基板之间，所述透明电极与所述薄膜晶体管的漏极同层设置。
在本申请所提供的阵列基板中，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物。
本申请还提供一种阵列基板，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠；
其中，所述透明电极和对应所述公共电极部分重叠区域形成存储电容，所述存储电容用于调节所述公共电极的电压；
沿着所述扫描线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
在本申请所提供的阵列基板中，沿着所述数据线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
在本申请所提供的阵列基板中，所述透明电极和对应所述公用电极的重叠面积大小的范围为1平方微米至4平方微米。
在本申请所提供的阵列基板中，所述阵列基板还包括多条横向排列的扫描线以及多条竖向排列的数据线，所述扫描线与所述数据线的交叉区域上方设置有像素单元。
在本申请所提供的阵列基板中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极连接一条所述扫描线，所述薄膜晶体管的源极连接一条所述数据线；
像素电极，连接所述薄膜晶体管的漏极；
所述透明电极与所述薄膜晶体管的栅极、所述薄膜晶体管的漏极或所述像素电极同层设置。
在本申请所提供的阵列基板中，所述公共电极设置于所述薄膜晶体管的栅极与所述衬底基板之间，所述透明电极与所述薄膜晶体管的漏极同层设置。
在本申请所提供的阵列基板中，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物。
本申请还提供一种显示面板，包括阵列基板，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠。
有益效果
本申请提供的阵列基板及显示面板，通过改变阵列基板中不同像素单元中透明电极层在公用电极层的投影重叠处的面积，改变存储电容的大小，进而改善显示画面闪烁、显示效果、画面不均匀的现象。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实 施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的液晶显示面板的等效线路图。
图2为本申请实施例提供的液晶显示面板中像素单元在充电阶段和保持阶段液晶两端的电压变化图。
图3为本申请实施例提供的阵列基板的结构示意图。
图4为本申请实施例所提供的存储电容的细节结构图。
图5为本申请实施例所提供的存储电容的一种排布图。
图6为本申请实施例所提供的存储电容的另一种排布图。
图7为本申请实施例所提供的工艺流程图。
具体实施方式
本发明实施例提供了一种阵列基板、液晶显示面板及显示装置，用以改善或消除馈通电压的影响，从而改善显示画面闪烁问题，提升液晶显示面板的显示品质。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
需要说明的是，本发明附图中各层的厚度和形状不反映真实 比例，目的只是示意说明本申请实施例内容。
参见图1，本申请实施例提供的阵列基板，包括：衬底基板11，在衬底基板11上交叉布置的多条扫描线12和多条数据线13，至少一条扫描线12连接有用于调节公共电极电压Vcom的存储电容14，该存储电容14的一端连接一条扫描线12，另一端连接至公共电极电压Vcom。
具体的，所述阵列基板的存储电容14包括公共电极与透明电极(图中未示出)，公共电极与所述透明电极一一对应，所述存储电容14在阵列基板中呈阵列排布，即与所述存储电容相对应的公共电极与所述透明电极成对出现，并呈阵列排布，且所述透明电极和对应所述公共电极部分重叠。
在一较佳实施方式中，存储电容14设置在阵列基板的边沿区域，例如，存储电容14设置在阵列基板的左侧边沿区域或右侧边沿区域。
在一较佳实施方式中，如图1所示，每一条扫描线12均连接有存储电容14(记为Cst，如图1中虚线框所示)，这样在显示液晶显示面板上的任意像素时，像素电极和公共电极之间的电压差将基本维持不变，因此，可以尽量消除馈通电压的影响，从而改善显示画面闪烁问题，提升液晶显示面板的显示品质。图1中存储电容Cst一端连接公共电极电压Vcom，但本申请实施例并不限于此，存储电容Cst一端例如还可以连接下一根扫描线。
阵列基板上设置有存储电容14后，包含该阵列基板的液晶显示面板中像素在充电阶段和保持阶段液晶两端的电压变化如图2 所示。图2表明在薄膜晶体管开启至关闭时，feed-through效应使得像素电极电压随着栅极电压的升降而升降，用于调节公共电极电压的电容使得公共电极电压随着与该电容连接的扫描线上的栅极电压的升降而升降，在显示液晶显示面板上的像素时，该像素的透明电极和公共电极之间的电压差基本维持不变，即ΔV1＝ΔV2＝ΔV3＝ΔV4＝ΔV5，因此，可以改善或消除馈通电压的影响，从而改善显示画面闪烁问题，提升液晶显示面板的显示品质。
馈通电压,它的成因主要是因为面板上其它电压的变化,经由寄生电容或是储存电容，影响到显示电极电压的正确性。在LCD面板上主要的电压变化来源有3个,分别是栅极驱动(gate driver)电压变化，源极驱动(source driver)电压变化,以及公共电极(common)电压变化。而这其中影响最大的就是栅极驱动电压变化(经由Cgd或是Cs),以及公共电压变化(经由Clc或是Cs+Clc)，而在公共电压固定不动的架构下，造成feed through电压的主因就只有栅极驱动的电压变化了。
薄膜晶体管采用叠层结构设计，由于曝光工程余量，源极与漏极、栅极与漏极必然产生重叠。电极发生重叠时，容易产生电容14，并对薄膜晶体管液晶显示器(TFT-LCD)产生较大的影响。
上述存储电容14中透明电极141和公共电极142的设置可以有多种实现方式，下面结合附图对其进行举例说明。
参见图3，本发明实施例提供的阵列基板中，在衬底基板11上，所述透明电极141与像素电极16同层设置，公共电极142 与薄膜晶体管15的栅极152同层设置。透明电极141例如可以通过过孔与扫描线12连接，各个存储电容14的公共电极142可以先连接到一根线上，然后再由该线连接公共电极电压Vcom，该线与数据线13在衬底基板11上的投影可以平行。当然，各个存储电容14的公共电极142也可以各自与公共电极电压Vcom连接，本发明实施例对此并不进行限定。
具体的，请参见图4，图4为本申请实施例所提供的存储电容14的细节结构图。
在本申请实施例所提供的存储电容14由所述透明电极141和对应的所述公共电极142部分重叠区域形成存储电容14，所述存储电容用于调节所述公共电极的电压(Vcom)。
在一较佳实施方式中，本申请实施例所提供的所述透明电极和对应所述公用电极的重叠面积的长的范围为1微米-2微米，与之对应的，重叠面积的宽的范围也为1微米-2微米；进一步的，在本申请实施例所提供的阵列基板中，所述重叠面积为矩形，即重叠面积大小的范围为1平方微米至4平方微米。
在一较佳实施方式中，请参见图5，沿着所述扫描线的延伸方向，所述透明电极141和所述公共电极142的重叠面积大小呈递增或递减趋势，进一步的，根据电容的面积大小与电容值的公式
Figure PCTCN2019111382-appb-000002
ε为所述存储电容值的介电电容值，S为所述存储电容的正对面积，在本申请实施例中，S即重叠面积的大小，k为所述存储电容的静电力常量，d为所述存储电容两极板之间的距 离，根据公式可知，所述存储电容C的大小与所述重叠面积的大小成正比；在本申请实施例中，由于减小了所述重叠面积的大小，进而减小了所述存储电容的大小。
具体的，在该图5中，本申请实施例只提出在阵列基板的一行中，所述透明电极141和所述公共电极142的重叠面积大小呈递增或递减趋势。除此之外，本申请不限于一行所述透明电极141和所述公共电极142的重叠面积大小的递增或递减趋势，例如，在一较佳实施例中，沿着所述数据线的延伸方向，所述第一行透明电极141和所述公共电极142的重叠面积大小成递增趋势，第二行透明电极141和所述公共电极142的重叠面积大小可以成递减趋势或者递增趋势，以此类推。
在一较佳实施方式中，请参见图6，沿着所述数据线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
具体的，在该图5中，本申请实施例只提出在阵列基板的一列中，所述透明电极141和所述公共电极142的重叠面积大小呈递增或递减趋势。除此之外，本申请不限于一列所述透明电极141和所述公共电极142的重叠面积大小的递增或递减趋势，例如，在一较佳实施例中，沿着所述数据线的延伸方向，所述第一列透明电极141和所述公共电极142的重叠面积大小成递增趋势，第二行透明电极141和所述公共电极142的重叠面积大小可以成递减趋势或者递增趋势，以此类推。
在一较佳实施例中，由于液晶显示面板中寄生电容的存在， 使得栅极信号在关闭时会导致像素电极的电压在发生跳变前后存在馈通电压的偏差，进一步的，所述阵列基板中，任意一个所述像素单元中的馈通电压的大小不同，本申请实施例可在调节所述液晶显示面板之前，优先测试所述阵列基板的平均灰阶值，并根据所述馈通电压(vfth)与栅极(gate)电压的变化
Figure PCTCN2019111382-appb-000003
其中，Vfth为馈通电压，Cgd为栅极和漏极之间的耦合电容、Clc为液晶电容，Cst为存储电容，Vgh为栅极线高电压(也称为开启电压)，Vgl为栅极线低电压(也称为关闭电压)。计算出所述阵列基板的平均存储电容值，并根据所述阵列基板中的平均存储电容值，计算出所述阵列基板中的重叠面积的大小，并对所述这阵列基板的重叠面积大小进行调节。
除此之外，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物(Indium Tin Oxide，简称ITO)。
下面以本发明实施例提供的阵列基板为例，结合图7来具体说明本申请实施例提供的阵列基板的制备工艺流程。
S10，在衬底基板上形成公共电极；
S20，在所述公共电极上形成薄膜晶体管的栅极、扫描线和公共电极线；
其中，公共电极线与公共电极连接，薄膜晶体管的栅极与公共电极不接触，栅极、扫描线和公共电极线的材料例如可以采用Mo/Al/Mo。
S30，在栅极、扫描线和公共电极线上形成栅绝缘层，在栅绝缘层上形成有源层、源极、漏极和数据线；
其中，源极和数据线连接，源极、漏极和数据线的材料例如可以采用Mo/Al/Mo。
S40，在源极、漏极和数据线上形成钝化层；
S50，在所述钝化层上形成像素电极和透明电极；
其中，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物。
其中，透明电极与薄膜晶体管的漏极连接，透明电极141与扫描线连接，透明电极141和公共电极142在衬底基板上的投影重叠，构成用于调节公共电极电压的存储电容14。
在本申请实施例提供的阵列基板中，在所述阵列基板的薄膜晶体管开启至关闭时，feed-through效应使得像素电极的电压随栅极电压的升降而升降，用于调节公共电极电压的电容使得公共电极电压随着与该电容连接的扫描线上的栅极电压的升降而升降，这样，在显示扫描线上连接有该电容的像素时，透明电极和公共电极之间的电压差将基本维持不变，因此，可以改变或消除馈通电压的影响，从而改善显示画面闪烁问题，进而提升显示面板的显示品质。
基于同一发明申请构思，本发明实施例还提供了一种显示面板，包括本发明任意实施例提供的阵列基板。
基于同一发明申请构思，本发明实施例提供了一种显示装置，包括：本发明任意实施例提供的液晶显示面板。该显示装置可以 为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有益效果为：通过改变阵列基板中不同像素单元中透明电极层在公用电极层的投影重叠处的面积，改变存储电容的大小，进而改善显示画面闪烁、显示效果、画面不均匀的现象。
除上述实施例外，本申请还可以有其他实施方式。凡采用等同替换或等效替换形成的技术方案，均落在本申请要求的保护范围。
综上所述，虽然本申请已将优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠；
    其中，所述透明电极和对应所述公共电极部分重叠区域形成存储电容，所述存储电容用于调节所述公共电极的电压；
    沿着所述扫描线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
  2. 根据权利要求1所述的阵列面板，其中，沿着所述数据线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
  3. 根据权利要求1所述的阵列基板，其中，所述透明电极和对应所述公用电极的重叠面积大小的范围为1平方微米至4平方微米。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括多条横向排列的扫描线以及多条竖向排列的数据线，所述扫描线与所述数据线的交叉区域上方设置有像素单元。
  5. 根据权利要求4所述的阵列基板，其中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极连接一条所述扫描线，所述薄膜晶体管的源极连接一条所述数据线；
    像素电极，连接所述薄膜晶体管的漏极；
    所述透明电极与所述薄膜晶体管的栅极、所述薄膜晶体管的 漏极或所述像素电极同层设置。
  6. 根据权利要求5所述的阵列基板，其中，所述公共电极设置于所述薄膜晶体管的栅极与所述衬底基板之间，所述透明电极与所述薄膜晶体管的漏极同层设置。
  7. 根据权利要求6所述的阵列基板，其中，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物。
  8. 一种阵列基板，其中，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠。
  9. 根据权利要求8所述的阵列基板，其中，所述透明电极和对应所述公共电极部分重叠区域形成存储电容，所述存储电容用于调节所述公共电极的电压。
  10. 根据权利要求8所述的阵列面板，其中，沿着所述扫描线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
  11. 根据权利要求8所述的阵列面板，其中，沿着所述数据线的延伸方向，所述透明电极和所述公共电极的重叠面积呈递增或递减趋势。
  12. 根据权利要求8所述的阵列基板，其中，所述透明电极和对应所述公用电极的重叠面积大小的范围为1平方微米至4平方微米。
  13. 根据权利要求8所述的阵列基板，其中，所述阵列基板 还包括多条横向排列的扫描线以及多条竖向排列的数据线，所述扫描线与所述数据线的交叉区域上方设置有像素单元。
  14. 根据权利要求13所述的阵列基板，其中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极连接一条所述扫描线，所述薄膜晶体管的源极连接一条所述数据线；
    像素电极，连接所述薄膜晶体管的漏极；
    所述透明电极与所述薄膜晶体管的栅极、所述薄膜晶体管的漏极或所述像素电极同层设置。
  15. 根据权利要求14所述的阵列基板，其中，所述公共电极设置于所述薄膜晶体管的栅极与所述衬底基板之间，所述透明电极与所述薄膜晶体管的漏极同层设置。
  16. 根据权利要求1所述的阵列基板，其中，所述透明电极与所述公共电极的材料相同，所述材料包括铟锡氧化物。
  17. 一种显示面板，其包括阵列基板，所述阵列基板包括衬底基板、设置于衬底基板上的多个公共电极、以及设置于所述多个公共电极上的多个透明电极，多个所述公共电极和多个所述透明电极一一对应设置，所述透明电极和对应所述公共电极部分重叠。
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