WO2021244133A1 - 显示基板及其驱动方法、维修方法、显示面板、显示装置 - Google Patents
显示基板及其驱动方法、维修方法、显示面板、显示装置 Download PDFInfo
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Definitions
- the present disclosure relates to the field of display technology, and in particular to a display substrate, a driving method thereof, a maintenance method, a display panel, and a display device.
- LCD liquid crystal display
- An LCD panel generally includes a base substrate, and a plurality of pixel units on the base substrate, and each pixel unit includes a thin film transistor and a pixel electrode connected to each other.
- the present disclosure provides a display substrate, a driving method thereof, a maintenance method, a display panel, and a display device.
- the technical solutions are as follows:
- a display substrate is provided, and the display substrate includes:
- each of the pixel units includes: a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected to one of the gate lines, and the first electrode is connected to the One of the data lines is connected, and the second electrode is connected to the pixel electrode;
- the orthographic projection of the gates of the thin film transistors included in the pixel unit in the nth row and the connected gate lines on the base substrate is the same as that of the nth row
- the orthographic projection of the pixel electrode included in the pixel unit on the base substrate is spaced apart, and overlaps the orthographic projection of the pixel electrode included in the pixel unit in the n+1th row on the base substrate, and n is greater than or An integer equal to 1.
- the orthographic projection of the first electrode and the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is identical to the pixel electrode included in the pixel unit in the n+1 row.
- the orthographic projections on the base substrate overlap.
- the orthographic projection of the second electrode of the thin film transistor included in the pixel unit in the nth row on the base substrate is also on the base substrate with the pixel electrode in the pixel unit in the nth row
- the orthographic projections overlap.
- the pitch in the extending direction of the gate line is within a first pitch range
- the pitch in the extending direction of the data line is within a second pitch range
- the vertical distance between the pixel electrode and the data line connected to the thin film transistor is within a third pitch range.
- the first pitch range and the second pitch range are both 3 ⁇ m to 7 ⁇ m; the third pitch range is 3 ⁇ m to 5 ⁇ m.
- the material of the pixel electrode included in each pixel unit is a metal material, and the reflectivity of the metal material is greater than a reflectivity threshold;
- the display substrate further includes: a light-reflecting material layer located on a side of the pixel electrode away from the base substrate, and the area of the orthographic projection of the light-reflecting material layer on the base substrate and the pixel electrode The area of the orthographic projection on the base substrate is positively correlated.
- the thin film transistors and pixel electrodes included in each pixel unit are sequentially stacked in a direction away from the base substrate;
- the display substrate further includes: a dielectric layer located between the thin film transistor and the pixel electrode;
- the dielectric constant of the dielectric layer is less than the dielectric constant threshold, and the thickness of the dielectric layer is greater than the thickness threshold.
- the material of the medium layer is an organic resin material.
- the orthographic projection of the dielectric layer on the base substrate covers the orthographic projection of the gate of the thin film transistor on the base substrate.
- the material of the dielectric layer is a metal material.
- the thin film transistor further includes: an active layer; the orthographic projection of the dielectric layer on the base substrate and the orthographic projection of the active layer on the base substrate do not overlap.
- a method for driving a display substrate is provided.
- the display substrate is the display substrate as described in the above aspect, and the method includes:
- the thin film transistor in the pixel unit of the nth row charges the pixel electrode in the pixel unit of the nth row in response to the gate driving signal and the data signal.
- a gate drive signal is provided to the n-th gate line
- the gate of the thin film transistor in the n-th row of pixel units and the n-th gate line are connected to the n-th gate line.
- the pixel electrodes in the pixel unit of the (n+1)th row are pulled to a second potential; the second potential is less than the first potential.
- a method for repairing a display substrate is provided.
- the display substrate is the display substrate as described in the above aspect, and the method includes:
- the first target pixel unit is located in one of the nth row and the n+1th row
- the second target pixel unit is located in the other of the nth row and the n+1th row
- n is greater than Or an integer equal to 1.
- a display panel in yet another aspect, includes: a box substrate, and the display substrate as described in the above-mentioned aspect.
- the display panel further includes: a driving circuit
- the driving circuit is respectively connected to a plurality of gate lines and a plurality of data lines in the display substrate, and the driving circuit is used to provide gate driving signals to the plurality of gate lines, and to provide gate driving signals to the plurality of data lines. Provide data signals.
- the display panel is a total reflection type liquid crystal display panel, or a transflective liquid crystal display panel.
- a display device in yet another aspect, includes the display panel as described in the foregoing aspect.
- FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure
- FIG. 3 is a timing chart of charging pixel electrodes included in an LCD panel in the related art
- FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
- FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure.
- FIG. 8 is a charging timing diagram of a pixel electrode provided by an embodiment of the present disclosure.
- FIG. 9 is a flowchart of a method for repairing a display substrate provided by an embodiment of the present disclosure.
- FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
- FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
- FIG. 12 is a schematic diagram of a measured value of Vcom provided by an embodiment of the present disclosure.
- FIG. 13 is a schematic diagram of an actual measured value of the degree of flicker provided by an embodiment of the present disclosure.
- LCD panels generally include: transmissive LCD panels and reflective liquid crystal display (reflection type iquid crystal display, RLCD) panels.
- the RLCD panel may include a fully reflective LCD panel and a transflective LCD panel.
- a transmissive LCD panel refers to a panel that uses light-emitting lines from a backlight source to achieve display
- an RLCD panel refers to a panel that uses ambient light for reflection to achieve display.
- the LCD panel described in the embodiments of the present disclosure may be any type of LCD panel, and the following embodiments take an RL CD panel as an example to describe the application content.
- the pixel electrode in each pixel unit of a transmissive LCD panel, the pixel electrode generally does not cover the entire thin film transistor, and may only cover one electrode (eg, source) of the source and drain of the thin film transistor connected to the pixel electrode.
- the gate of the thin film transistor does not form a parasitic capacitance with the pixel electrode.
- the inventor discovered that for RL CD panels that multiplex pixel electrodes as the light reflection layer, in order to increase the reflectivity, it is generally possible to set a larger area of the pixel electrode to increase the reflection area, resulting in each pixel unit, The pixel electrode and the gate of the thin film transistor overlap in a direction perpendicular to the display panel. At this time, a parasitic capacitance is formed between the pixel electrode and the gate of the thin film transistor, which causes flicker when the RL CD panel displays a picture.
- the embodiments of the present disclosure provide a display substrate, and a display panel using the display substrate can effectively alleviate the problem of screen flicker caused by the parasitic capacitance formed between the pixel electrode in the pixel unit and the gate of the thin film transistor of the pixel unit And further, the reflectivity of the R LCD panel using the display substrate can be effectively improved.
- FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
- the display substrate may include: a base substrate 01, a plurality of gate lines G1 and a plurality of data lines D1 located on the base substrate 01, and a plurality of arrays arranged on the base substrate 01.
- One pixel unit 02. each gate line G1 may extend in a first direction
- each data line D1 may extend in a second direction
- the first direction and the second direction may cross each other, for example, may be perpendicular to each other.
- FIG. 2 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure.
- each pixel unit 02 may include: a thin film transistor T1 and a pixel electrode P1.
- the gate G0 of the thin film transistor T1 can be connected to a gate line G1, such as G1(n+1) as shown in FIG. 2.
- the first electrode D0 of the thin film transistor T1 may be connected to a data line D1, and the second electrode S0 of the thin film transistor T1 may be connected to the pixel electrode P1.
- the first electrode of the thin film transistor T1 may be one of the source electrode and the drain electrode, and the second electrode may be the other electrode of the source electrode and the drain electrode. Referring to FIG. 1, the embodiment of the present disclosure is described by taking the drain D0 of the first electrode of the thin film transistor T1 and the source S0 of the second electrode of the thin film transistor T1 as an example.
- each pixel unit 02 may further include a common electrode Vcom, and the common electrode Vcom may be disposed on the display substrate, or may also be disposed on an opposite substrate disposed opposite to the display substrate.
- the common electrode Vcom is disposed on the cell substrate (for example, twisted nematic, TN)
- the common electrode Vcom and the pixel electrode P1 may include liquid crystal molecules, and the common electrode Vcom and the pixel electrode P1 can be equivalent to a liquid crystal capacitor (c apacitance of liquid crystal) Clc, and at the same time, a common electrode Vc om2 can be additionally provided on the display substrate.
- a storage capacitor (capacitance) can also be formed between the common electrode Vcom2 and the pixel electrode P1.
- the thin film transistor T1 can respond to the gate drive signal provided by the connected gate line G1, and output the data signal from the connected data line D1 to the connected pixel electrode P1 to charge the pixel electrode P1, thereby making the pixel electrode P1 A potential difference is formed between P1 and the common electrode Vcom.
- the liquid crystal molecules can be deflected under the action of the potential difference, and the pixel unit 02 emits light.
- the orthographic projection of the thin film transistor in each pixel unit on the base substrate overlaps the orthographic projection of the pixel electrode on the base substrate, that is, the pixel electrode in each pixel unit may cover the gate of the thin film transistor.
- the gate of the thin film transistor included in the pixel unit and the gate line connected to the gate will form a gap with the pixel electrode included in the pixel unit.
- Parasitic capacitance refer to Figure 2 dashed line marked Cgs1.
- each pixel unit in each pixel unit, another parasitic capacitance Cgs2 is formed between the gate of the thin film transistor and one electrode of the pixel electrode connected to the thin film transistor, that is, the source.
- the parasitic capacitance Cgs2 is caused by a defect in the structure of the thin film transistor device itself and cannot be avoided.
- the parasitic capacitance Cgs1 is caused by the large area of the pixel electrode and the overlapping area with the gate of the thin film transistor.
- the pixel electrode is multiplexed as a light reflection layer, and in order to improve the reflectivity, a display substrate included in the RLCD panel with a larger area of the pixel electrode is provided.
- a display substrate included in the RLCD panel with a larger area of the pixel electrode is provided.
- it may also be a transmissive LCD panel with a larger area of pixel electrodes to increase the capacitance.
- FIG. 3 shows a schematic diagram of a timing diagram of charging bits to the pixel unit 02 of the nth row and the pixel unit 02 of the n+1th row in the related art.
- n is an integer greater than or equal to 1.
- the potential difference ⁇ Vp between the actual potential and the set potential can satisfy:
- C1 refers to the sum of the capacitance values of the parasitic capacitances Cgs1 and Cgs2
- C2 refers to the capacitance value of the liquid crystal capacitor Clc
- C3 refers to the capacitance value of the storage capacitor Cst
- Vgh refers to the effective potential of the gate drive signal
- Vgl refers to The invalid potential of the gate drive signal
- C1, C3, Vgh, and Vgl are generally fixed values.
- the effective potential may be greater than the ineffective potential, or the effective potential may be less than the ineffective potential. It can be seen from the above formula (1) that the larger the capacitance value of the parasitic capacitance Cgs1, the larger the value of C1, and the larger the ⁇ Vp difference of different gray levels, the more serious the screen flicker.
- the gate G0 of the thin film transistor T1 in the pixel unit 02 of the nth row and the connected gate line G1 are on the base substrate 01
- the orthographic projection is spaced apart from the orthographic projection of the pixel electrode P1 in the pixel unit 02 in the nth row on the base substrate 01, and is aligned with the pixel electrode P1 in the pixel unit 02 in the n+1th row on the base substrate 01. The projections overlap.
- the orthographic projection of the gate G0 of the thin film transistor T1 and the connected gate line G1 on the base substrate 01 in the pixel unit 02 in the nth row is only the same as that in the pixel unit 02 in the n+1 row.
- the orthographic projection of the pixel electrode P1 on the base substrate 01 overlaps, but does not overlap with the orthographic projection of the pixel electrode P1 in the n-th row of pixel units 02 on the base substrate 01.
- the gate G0 and the connected gate line G1 of the thin film transistor T1 in the pixel unit 02 in the nth row will not form a parasitic capacitance with the pixel electrode P1 in the pixel unit 02 in the nth row (as shown in the figure) 2 shows Cgs1).
- the gate G0 of the thin film transistor T1 in the pixel unit 02 in the nth row and the connected gate line G1, and the pixel electrode P1 in the pixel unit 02 in the n+1th row form a parasitic capacitance Cgs1, it is The pixel units of the n rows and the pixel units of the n+1th row are charged sequentially, that is, after the scanning of the nth gate line G1(n) is completed, the n+1th gate line G1(n+1) starts to scan.
- the potential of the nth gate line G1(n) has stabilized, and the gate G0 and the nth gate of the thin film transistor T1 in the pixel unit 02 in the nth row
- the parasitic capacitance Cgs1 formed between the gate line G1 and the pixel electrode P1 in the pixel unit 02 in the n+1th row will not affect the potential of the pixel unit 02 in the n+1th row that is being charged or has been charged.
- the embodiments of the present disclosure provide a display substrate. Due to the scanning direction along the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line on the base substrate is the same as that of the pixel electrode in the pixel unit of the n+1th row on the base substrate.
- the orthographic projection on the pixel unit overlaps, and there is a gap with the orthographic projection of the pixel electrode in the nth row of pixel unit on the base substrate, that is, it does not overlap with the orthographic projection of the pixel electrode in the nth row of pixel unit on the base substrate.
- the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode of the pixel unit of the n+1th row, but not with the pixel electrode of the pixel unit of the nth row.
- Form parasitic capacitance Since the driving circuit sequentially charges the pixel units in the nth row and the n+1th row, the gates of the thin film transistors in the nth row of pixel units and the nth gate line are the same as the pixels in the n+1th row of pixel units.
- the parasitic capacitance formed by the electrode will not affect the pixel unit in the n+1th row that is being charged.
- the display panel adopting the display substrate has a better display effect.
- the display panel adopting the display substrate is an RLCD panel as an example for description.
- the display substrate may further include: a reflective material layer located on the side of the pixel electrode away from the base substrate.
- the area of the orthographic projection of the provided reflective material layer on the base substrate and the area of the orthographic projection of the pixel electrode on the base substrate may be positively correlated. That is, the larger the area of the pixel electrode, the larger the area of the reflective material layer; the smaller the area of the pixel electrode, the smaller the area of the reflective material layer.
- the material of the pixel electrode P1 included in each pixel unit 02 may be a metal material, and the reflectance of the metal material may be greater than the reflectance threshold. That is, the pixel electrode P1 can be multiplexed to realize conduction while realizing reflection of light.
- the reflection area of the RLCD is positively correlated with the area of the pixel electrode P1. Therefore, in conjunction with FIG. 1, in the embodiment of the present disclosure, by setting each pixel unit 02, the orthographic projection of the pixel electrode P1 on the base substrate overlaps with the orthographic projection of the source electrode S0 of the thin film transistor T1 on the base substrate. . That can ensure that the area of the pixel electrode P1 is larger, and the reflectivity is improved.
- the distance between the pixel electrodes P1 included in any two adjacent pixel units 02 may be smaller than the distance threshold.
- the pixel electrodes P1 included in any two adjacent pixel units 02 may have a pitch in the extending direction of the gate line G1 within the first pitch range.
- the pitch of the pixel electrodes P1 included in any two adjacent pixel units 02 in the extending direction of the data line D1 may be within the second pitch range.
- the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be within the third pitch range.
- the above-mentioned pitch range can be flexibly set according to the manufacturing process when manufacturing the display substrate.
- the first pitch range and the second pitch range may generally both be 3 micrometers ( ⁇ m) to 7 ⁇ m.
- the third pitch range can generally be 3 ⁇ m to 5 ⁇ m. That is, for the pixel electrodes P1 included in any two adjacent pixel units 02, the pitch in the extension direction of the gate line G1 and the pitch in the extension direction of the data line D1 may both be greater than or equal to 3 ⁇ m and less than or equal to 7 ⁇ m, For example, it can be 5 ⁇ m.
- the vertical distance between the pixel electrode P1 and the data line D1 connected to the thin film transistor T1 may be greater than or equal to 3 ⁇ m and less than or equal to 5 ⁇ m, for example, it may be 4 ⁇ m.
- FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
- the orthographic projection of the first electrode D0 and the second electrode S0 of the thin film transistor T1 included in the pixel unit 02 in the nth row on the base substrate 01 may also be the same as the orthographic projection of the pixel unit 02 in the n+1 row.
- the orthographic projection of the pixel electrode P1 on the base substrate 01 overlaps. That is, the main body of the thin film transistor T1 in the pixel unit 02 in the nth row can be placed under the pixel electrode P1 in the pixel unit 02 in the n+1th row. That is, referring to FIG.
- the pixel electrode P1 in the pixel unit 02 in the n+1th row may cover the main body of the thin film transistor T1 in the pixel unit 02 in the nth row.
- the main body of the thin film transistor T1 includes: the entire gate of the thin film transistor T1, most of the first electrode (ie, drain) D0, and most of the second electrode (ie, source SO).
- this arrangement can further ensure that the gate G0 of the pixel unit 02 in the nth row and the connected gate line G1 are located under the pixel electrode P1 in the pixel unit of the n+1th row, that is, to further avoid the pixel in the nth row.
- the gate G0 of the thin film transistor T1 and the connected gate line G1 form a parasitic capacitance Cgs1 with the pixel electrode P1, thereby effectively improving the display effect.
- the area of the pixel electrode P1 is further increased, and the reflectivity of the RLCD panel that multiplexes the pixel electrode P1 as a light reflection layer is improved.
- the second electrode S0 of the thin film transistor T1 needs to be connected to the pixel electrode P1, in order to ensure a reliable connection between the two, in conjunction with FIG. 1 and FIG. 4, the second electrode of the thin film transistor T1 included in the pixel unit 02 in the nth row
- the orthographic projection of the pole S0 on the base substrate 01 may also overlap with the orthographic projection of the pixel electrode P1 included in the pixel unit 02 in the nth row on the base substrate 01.
- FIG. 5 shows a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure
- FIG. 6 shows a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
- the thin film transistor T1 and the pixel electrode P1 included in each pixel unit 02 may be sequentially stacked in a direction away from the base substrate 01.
- the display substrate may further include: a dielectric layer 03 located between the thin film transistor T1 and the pixel electrode P1 in the overlapping area.
- the orthographic projection of the dielectric layer 03 on the base substrate 01 may overlap the overlapping area.
- the dielectric layer 03 can be used to reduce the capacitance value of the parasitic capacitance formed by the gate and the connected gate line of the thin film transistor T1 in the pixel unit 02 in the n+1 row and the pixel electrode P1 in the pixel unit 02 in the n+1 row.
- the parasitic capacitance formed by the gate and the connected gate line of the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1 row is directly shielded, thereby further improving the display effect.
- the material of the dielectric layer 03 shown in FIG. 5 may be a non-metallic material. And if the material of the dielectric layer 03 is a non-metallic material, in order to effectively reduce the gate and the connected gate line of the thin film transistor T1 in the pixel unit 02 in the nth row, it is formed with the pixel electrode P1 in the pixel unit 02 in the n+1th row.
- the dielectric constant of the dielectric layer 03 may be less than the dielectric constant threshold, and the thickness of the dielectric layer 03 may be greater than the thickness threshold.
- the orthographic projection of the dielectric layer 03 on the base substrate 01 can cover the orthographic projection of the gate G0 of the thin film transistor T1 on the base substrate 01.
- the material of the dielectric layer 03 may be an organic resin material.
- the orthographic projection of the dielectric layer 03 on the base substrate 01 here , The orthographic projection of the gate G0 on the base substrate 01 that can cover the thin film transistor T1 refers to the orthographic projection of the dielectric layer 03 on the base substrate 01, covering the gate of the thin film transistor T1 in the pixel unit 02 of the nth row G0.
- the material of the dielectric layer 03 shown in FIG. 6 may be a metal material.
- the dielectric layer 03 made of this metal material can realize the parasitic formation between the gate and the connected gate line of the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1 row. Direct shielding of capacitors.
- the thin film transistor T1 may include an active layer (active) A0 in addition to the gate electrode G0 and the source and drain electrodes (S0 and D0).
- the active layer A0 may be located between the source and drain (S0 and D0) and the gate G0, and the source S0 and the drain D0 may partially cover the active layer A0.
- the dielectric layer 03 is made of a metal material
- the dielectric layer 03 made of a metal material is The orthographic projection on the base substrate 01 and the orthographic projection of the active layer A0 on the base substrate 01 may not overlap.
- the dielectric layer 03 is located between the thin film transistor T1 in the pixel unit 02 in the nth row and the pixel electrode P1 in the pixel unit 02 in the n+1 row, there is no overlap here means that it is located in the dielectric layer 03, and the pixel electrode P1 in the pixel unit 02 in the n+1th row.
- the orthographic projection of the active layer A0 of the thin film transistor T1 in the n-row pixel unit on the base substrate 01 does not overlap.
- the dielectric layer 03 also needs to be combined with the active thin film transistor T1 in the pixel unit 02 in other rows (such as the n+1th row).
- the orthographic projection of the layer A0 on the base substrate 01 does not overlap.
- multi-layer dielectric layer 03 can be set.
- a dielectric layer 03 made of organic resin material may be provided, and a dielectric layer 03 made of metal material may be provided.
- the display substrate may further include an insulating layer (e.g., 04, 05, and 06 indicated in the drawings) disposed between every two adjacent structures.
- FIG. 6 also shows the parasitic capacitances Cgs1 and Cgs2 formed.
- the Cgs1 here refers to the pixel electrode P1 in the pixel unit 02 in the n+1th row.
- the gate and the connected gate line of the thin film transistor T1 in the pixel unit 02 in the n row form a parasitic capacitance with the pixel electrode P1 in the pixel unit 02 in the n+1 row.
- Cgs2 refers to the thin film in the pixel unit 02 in the n row.
- the orthographic projection of the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line on the base substrate is the same as that of the pixel electrode of the pixel unit of the nth row on the base substrate.
- the above-mentioned medium can be directly arranged between the thin film transistor in the pixel unit of the nth row and the pixel electrode in the pixel unit of the nth row where the overlapping area exists.
- a dielectric layer 03 to reduce the capacitance value of the parasitic capacitance Cgs1 formed by the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line, and the pixel electrode of the pixel unit of the nth row, or directly shield The parasitic capacitance Cgs1.
- the optional location and optional materials of the dielectric layer 03 can be referred to the record of the embodiment of FIG. 5 and FIG. 6, and details are not described herein again.
- the display substrate may include a display area (AA) and a non-display area, and the pixel unit 02 described in the above embodiment may be disposed in the AA area.
- the non-display area can be used to provide a driving circuit for providing signals to the gate line and the data line.
- the thin film transistor T1 described in the embodiments of the present disclosure may be made of a-silicon (a-silicon, a-Si) material, or may be made of low temperature polysilicon (LTPS) material, or may be made of Made of oxide material.
- the embodiments of the present disclosure provide a display substrate. Due to the scanning direction along the gate line, the orthographic projection of the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line on the base substrate is the same as that of the pixel electrode in the pixel unit of the n+1th row on the base substrate.
- the orthographic projection on the pixel unit overlaps, and there is a gap with the orthographic projection of the pixel electrode in the nth row of pixel unit on the base substrate, that is, it does not overlap with the orthographic projection of the pixel electrode in the nth row of pixel unit on the base substrate.
- the gate of the thin film transistor in the pixel unit of the nth row and the connected gate line form a parasitic capacitance with the pixel electrode of the pixel unit of the n+1th row, but not with the pixel electrode of the pixel unit of the nth row.
- Form parasitic capacitance Since the driving circuit sequentially charges the pixel units in the nth row and the n+1th row, the gates of the thin film transistors in the nth row of pixel units and the nth gate line are the same as the pixels in the n+1th row of pixel units.
- the parasitic capacitance formed by the electrode will not affect the pixel unit in the n+1th row that is being charged.
- the display panel adopting the display substrate has a better display effect.
- FIG. 7 is a flowchart of a method for driving a display substrate provided by an embodiment of the present disclosure.
- the display substrate may be the display substrate shown in any one of FIGS. 1 and 4 to 6. As shown in Figure 7, the method may include:
- Step 701 Along the scanning direction of a plurality of gate lines in the display substrate, a gate driving signal is provided to each gate line in turn, and a data signal is provided to a plurality of data lines in the display substrate.
- the thin film transistor T1 in the pixel unit 02 of the nth row can respond to the gate driving signal and the data signal to transfer the nth row
- the pixel electrode P1(n) in the pixel unit 02 is charged to the first potential V1.
- the gate line and the n-th gate line of the thin film transistor T1 of the pixel unit 02 in the nth row and the pixel electrode P1(n+1) in the pixel unit 02 in the n+1th row form a parasitic capacitance Cgs1.
- the pixel electrode P1(n+1) in the pixel unit 02 in the n+1th row is pulled to the second potential V2.
- the second potential V2 may be less than the first potential V1.
- the charging process for the pixel unit of the nth row and the pixel unit of the n+1th row can be divided into three stages: Referring to FIG. 8, in the first stage t1, the nth gate line G1(n) is provided Gate drive signal. At this time, only the thin film transistors T1 in the pixel unit 02 in the nth row are all turned on, and multiple data lines D1 are directed to the pixel electrode P1(n) in 02 in the pixel unit 02 in the nth row through the turned-on thin film transistors T1. Write the first potential.
- the pixel unit in the n+1th row is The orthographic projection of the pixel electrode P1 in 02 on the base substrate 01 overlaps, so a parasitic capacitance Cgs1 is formed.
- the nth gate line G1(n) causes a certain pull on the potential of the pixel electrode P1(n+1) in the pixel unit 02 in the n+1th row.
- the potential of the pixel electrode P1(n+1) in the pixel unit 02 in the n+1th row is pulled to the second potential, which deviates from the initial potential.
- the gate driving signal to the nth gate line G1(n) is stopped, and the gate driving signal is started to be provided to the n+1th gate line G1(n+1).
- the thin film transistors T1 in the pixel unit 02 in the n+1 row are all turned on, and a plurality of data lines D1 are directed to the pixel electrode P1 (n+1) in the pixel unit 02 in the n+1 row through the turned-on thin film transistor T1. ) Write the first potential.
- the gate G0 of the thin film transistor T1 of the pixel unit 02 in the nth row and the gate line G1(n) of the nth row are connected with the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row.
- the parasitic capacitance Cgs1 formed by) does not have any influence on the potential of the pixel electrode P1(n+1).
- the pixel unit 02 in the n+1th row is fully charged and reaches the set potential.
- the potential of the pixel electrode P1(n+1) of the pixel unit 02 in the n+1th row is only affected by the parasitic capacitance Cgs2, and the variation range is small. Furthermore, the flicker phenomenon of the display screen is significantly improved.
- providing a gate drive signal to the gate line is a gate drive signal that provides an effective potential to the gate line
- stopping providing a gate drive signal to the gate line is a gate drive signal that provides an ineffective potential to the gate line.
- the effective potential may be a high potential, and correspondingly, the ineffective potential may be a low potential; or, the effective potential may be a low potential, and correspondingly, the ineffective potential may be a high potential.
- the effective potential and the ineffective potential depend on the type of thin film transistor T1.
- the effective potential can be a high potential and the ineffective potential can be a low potential; if the thin film transistor T1 is a P-type transistor, the effective potential can be a low potential and the ineffective potential can be a high potential.
- the embodiments of the present disclosure provide a method for driving a display substrate.
- the gate driving signal is provided to the nth gate line
- the thin film transistor in the pixel unit of the nth row can charge the pixel electrode in the pixel unit of the nth row to the first potential in response to the gate driving signal and the data signal.
- the pixel unit of the n+1th row The pixel electrode of is pulled to a second potential that is less than the first potential.
- the gates of the thin film transistors in the nth row of pixel units and the nth gate line are the same as the pixel electrodes in the n+1th row of pixel units.
- the formed parasitic capacitance will not affect the pixel unit being charged.
- the display effect of the display panel using the display substrate provided by the embodiment of the present disclosure is better.
- FIG. 9 is a flowchart of a method for repairing a display substrate provided by an embodiment of the present disclosure.
- the display substrate may be the display substrate shown in any one of FIGS. 1, 4 to 6. As shown in Figure 9, the method may include:
- Step 901 Determine the first target pixel unit where a bad pixel occurs.
- the data line connected to the pixel unit is short-circuited (open).
- various test methods for example, array test
- the dead pixels determined in step 901 may be bright spots.
- Step 902 Connect the pixel electrode included in the first target pixel unit and the gate line connected to the second target pixel unit.
- the pixel electrode included in the first target pixel unit and the gate line connected to the second target pixel unit may be connected by laser welding.
- the first target pixel unit may be located in one of the nth row and the n+1th row
- the second target pixel unit may be located in the other of the nth row and the n+1th row, where n is An integer greater than or equal to 1. That is, if the first target pixel unit is a certain pixel unit in the nth row of pixel units, the second target pixel unit is a certain pixel unit in the n+1th row of pixel units. If the first target pixel unit is a certain pixel unit in the n+1th row of pixel units, the second target pixel unit is a certain pixel unit in the nth row of pixel units.
- the orthographic projection of the gate of the thin film transistor included in the pixel unit of the nth row and the connected gate line on the base substrate is similar to that of the pixel electrode included in the pixel unit of the n+1th row on the substrate.
- the first target pixel unit is a certain pixel unit in the n+1th row of pixel units
- the second target pixel unit is a certain pixel unit in the nth row of pixel units
- the dead pixels If it is a bright spot, when a bright spot is detected in the first target pixel unit, the pixel electrode included in the pixel unit in the n+1th row of pixel units can be connected to the gate line G1 connected to the nth row of pixel units. After being connected, the pixel electrode of the lighted first target pixel unit and the common electrode can form a relatively large voltage difference, thereby making the lighted first target pixel unit darker, achieving the effect of repairing bright spots.
- the embodiments of the present disclosure provide a method for repairing a display substrate. Due to the unique placement of the thin film transistors in the nth row of pixel units and the pixel electrodes in the n+1th row of pixel units in the display substrate, it is possible to determine the first target pixel unit with dead pixels by directly
- the pixel electrode included in one target pixel unit is connected to the gate line connected to the second target pixel unit to achieve the purpose of repairing the dead pixels, and the repair method is relatively simple.
- FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
- the display panel may include: a box substrate 100 and a display substrate 200 as shown in any one of FIGS. 1, 4 to 6.
- the pair of cell substrates 100 may be a color filter substrate, and the display substrate 200 may be an array substrate.
- the display panel may further include: a liquid crystal located between the pair of cell substrates 100 and the display substrate 200.
- the liquid crystal layer 300 includes a plurality of liquid crystal molecules. That is, the display panel may be an LCD panel.
- FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As shown in FIG. 11, the display panel may further include a driving circuit 400.
- the driving circuit 400 may be respectively connected to a plurality of gate lines G1 and a plurality of data lines D1 in the display substrate 200, and the driving circuit 400 may be used to provide gate driving signals to the plurality of gate lines G1 and to a plurality of data lines.
- Line D1 provides a data signal.
- the driving circuit 400 may include a gate driving circuit 4001 and a source driving circuit 4002.
- the gate driving circuit 4001 may be connected to a plurality of gate lines G1 for providing gate driving signals to the plurality of gate lines G1.
- the source driving circuit 4002 can be connected to a plurality of data lines D1 for providing data signals to the plurality of data lines D1.
- the RLCD panel may be a fully reflective RLCD panel, or may be a transflective RLCD panel.
- FIG. 12 and FIG. 13 respectively show 10 randomly selected samples (ie, pixel pixels).
- the measured value of the potential of the common electrode Vcom due to the parasitic capacitance of each sample, at the moment when the thin film transistor T1 is turned off, the measured value of the potential of the common electrode Vcom and the measured value of the degree of flicker (ficker).
- the parasitic capacitance includes Cgs2 and Cdp (that is, the parasitic capacitance formed between the data line D1 and the pixel electrode P1); for a conventional RLCD, the parasitic capacitance includes Cgs1, Cgs2, and Cdp ;
- the parasitic capacitance includes Cgs1, Cgs2, and Cdp.
- the RLCD provided by the embodiments of the present disclosure has a better display effect. Moreover, it can also be seen in conjunction with FIG. 13 that the degree of flicker of the RLCD of the present disclosure is reduced from about 6% to about 4% compared with the conventional RLCD, and the degree of flicker is significantly reduced.
- an embodiment of the present disclosure further provides a display device, and the display device may include the display panel shown in FIG. 10 or FIG. 11.
- the display device may be any product or component with a display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, navigator, etc.
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Abstract
Description
Claims (20)
- 一种显示基板,其中,所述显示基板包括:衬底基板;位于所述衬底基板上的多条栅线和多条数据线;位于所述衬底基板上且阵列排布的多个像素单元,每个所述像素单元包括:薄膜晶体管和像素电极,所述薄膜晶体管的栅极与一条所述栅线连接,第一极与一条所述数据线连接,第二极与所述像素电极连接;其中,沿所述多条栅线的扫描方向,第n行所述像素单元包括的薄膜晶体管的栅极和所连接的栅线在所述衬底基板上的正投影,与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影存在间隔,且与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠,n为大于或等于1的整数。
- 根据权利要求1所述的显示基板,其中,第n行所述像素单元包括的薄膜晶体管的第一极和第二极在所述衬底基板上的正投影,与第n+1行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
- 根据权利要求1所述的显示基板,其中,第n行所述像素单元包括的薄膜晶体管的第二极在所述衬底基板上的正投影,还与第n行所述像素单元包括的像素电极在所述衬底基板上的正投影重叠。
- 根据权利要求1至3任一所述的显示基板,其中,任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内。
- 根据权利要求4所述的显示基板,其中,所述第一间距范围和所述第二间 距范围均为3微米至7微米;所述第三间距范围为3微米至5微米。
- 根据权利要求1至5任一所述的显示基板,其中,每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 根据权利要求1至6任一所述的显示基板,其中,每个所述像素单元包括的薄膜晶体管和像素电极沿远离所述衬底基板的方向依次层叠;所述显示基板还包括:位于所述薄膜晶体管和所述像素电极之间的介质层;其中,所述薄膜晶体管的栅极在所述衬底基板上的正投影和所述像素电极在所述衬底基板上的正投影存在重叠区域,所述介质层在所述衬底基板上的正投影与所述重叠区域重叠。
- 根据权利要求7所述的显示基板,其中,所述介质层的介电常数小于介电常数阈值,且所述介质层的厚度大于厚度阈值。
- 根据权利要求8所述的显示基板,其中,所述介质层的材料为有机树脂材料。
- 根据权利要求8所述的显示基板,其中,所述介质层在所述衬底基板上的正投影,覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影。
- 根据权利要求7所述的显示基板,其中,所述介质层的材料为金属材料。
- 根据权利要求11所述的显示基板,其中,所述薄膜晶体管还包括:有源层;所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠。
- 根据权利要求8所述的显示基板,其中,所述介质层在所述衬底基板上的正投影,覆盖所述薄膜晶体管的栅极在所述衬底基板上的正投影;任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内;所述第一间距范围和所述第二间距范围均为3微米至7微米;所述第三间距范围为3微米至5微米;每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 根据权利要求11所述的显示基板,其中,所述薄膜晶体管还包括:有源层;所述介质层在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重叠;任意相邻两个所述像素单元包括的像素电极,在所述栅线的延伸方向上的间距位于第一间距范围内;任意相邻两个所述像素单元包括的像素电极,在所述数据线的延伸方向上的间距位于第二间距范围内;每个所述像素单元中,所述像素电极与所述薄膜晶体管所连接的数据线之间的垂直距离位于第三间距范围内;所述第一间距范围和所述第二间距范围均为3微米至7微米;所述第三间距范围为3微米至5微米;每个所述像素单元包括的像素电极的材料均为金属材料,且所述金属材料的反射率大于反射率阈值;或,所述显示基板还包括:位于所述像素电极远离所述衬底基板一侧的反光材料层,且所述反光材料层在所述衬底基板上的正投影的面积与所述像素电极在所述衬底基板上的正投影的面积正相关。
- 一种显示基板的驱动方法,其中,所述显示基板为如权利要求1至14任一所述的显示基板,所述方法包括:沿所述显示基板中多条栅线的扫描方向,依次向每条所述栅线提供栅极驱动信号;向所述显示基板中的多条数据线提供数据信号;其中,在向第n条栅线提供栅极驱动信号时,第n行像素单元中的薄膜晶体管响应于所述栅极驱动信号和所述数据信号,将第n行像素单元中的像素电极充电至第一电位;且在向第n条栅线提供栅极驱动信号时,在所述第n行像素单元中的薄膜晶体管的栅极和所述第n条栅线,与所述第n+1行像素单元中的像素电极形成的寄生电容的耦合作用下,第n+1行像素单元中的像素电极被拉动至第二电位;所述第二电位小于所述第一电位。
- 一种显示基板的维修方法,其中,所述显示基板为如权利要求1至14任一所述的显示基板,所述方法包括:确定出现坏点的第一目标像素单元;将所述第一目标像素单元包括的像素电极与第二目标像素单元所连接的栅线连接;其中,所述第一目标像素单元位于第n行和第n+1行中的一行,第二目标像素单元位于所述第n行和所述第n+1行中的另一行,n为大于或等于1的整数。
- 一种显示面板,其中,所述显示面板包括:对盒基板,以及如权利要求1至14任一所述的显示基板。
- 根据权利要求17所述的显示面板,其中,所述显示面板还包括:驱动电路;所述驱动电路分别与所述显示基板中的多条栅线和多条数据线连接,所述驱动电路用于向所述多条栅线提供栅极驱动信号,以及向所述多条数据线提供数据信号。
- 根据权利要求17所述的显示面板,其中,所述显示面板为全反射型液晶显示面板,或,半透半反射型液晶显示面板。
- 一种显示装置,其中,所述显示装置包括:如权利要求17至19任一所 述的显示面板。
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US12019343B2 (en) | 2021-01-29 | 2024-06-25 | Hefb Boe Optoelectronics Technology Co., Ltd. | Array substrate and reflective display panel |
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