WO2018039856A1 - 薄膜晶体管制造方法 - Google Patents

薄膜晶体管制造方法 Download PDF

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WO2018039856A1
WO2018039856A1 PCT/CN2016/097132 CN2016097132W WO2018039856A1 WO 2018039856 A1 WO2018039856 A1 WO 2018039856A1 CN 2016097132 W CN2016097132 W CN 2016097132W WO 2018039856 A1 WO2018039856 A1 WO 2018039856A1
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Prior art keywords
layer
region
metal layer
thin film
film transistor
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English (en)
French (fr)
Inventor
赵继刚
袁泽
余晓军
魏鹏
古普塔⋅阿米特
鲁萍
琼⋅蒂娜
罗浩俊
游⋅埃里克⋅凱翔
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to US16/329,291 priority Critical patent/US20190252414A1/en
Priority to KR1020197005170A priority patent/KR20190031543A/ko
Priority to JP2019505517A priority patent/JP2019523565A/ja
Priority to PCT/CN2016/097132 priority patent/WO2018039856A1/zh
Priority to CN201680015888.3A priority patent/CN107438903B/zh
Publication of WO2018039856A1 publication Critical patent/WO2018039856A1/zh
Anticipated expiration legal-status Critical
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a method of fabricating a thin film transistor.
  • Thin-film transistors (TFT) array substrates are widely used in different types of displays, such as LCD or AMOLED displays. As display screen sizes increase, large currents are required for TFTs to support higher resolutions.
  • an etch barrier layer is disposed on the active layer for protecting the active layer in the process to ensure the stability of the active layer electrical properties. Under the influence of the conventional arrangement of the TFT, the etching stopper layer increases the length of the channel formed between the source drain and the active layer, thereby affecting the resolution of the display.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor, which solves the technical problem that the etching barrier layer is connected to the source and drain to increase the length of the channel, and generates a large parasitic capacitance to affect the resolution.
  • the method for fabricating a thin film transistor of the present invention comprises:
  • the method for fabricating a thin film transistor of the present application uses a metal layer to cover the photoresist layer and then removes a portion of the etch barrier layer by a plasma ashing process to define a metal layer to be removed to form a source and a drain, thereby achieving etching through the barrier layer and the source.
  • the drain is self-aligned, and the source and drain locations can be accurately defined; and the present application directly defines the source and the drain on the active layer, that is, reduces the channel region between the source and the drain to the active layer. The length, which in turn reduces the generation of parasitic capacitance.
  • FIG. 1 is a process diagram of a method of fabricating a thin film transistor according to a first embodiment of the present invention.
  • FIG. 2 to 13 are schematic cross-sectional views showing respective manufacturing flows of the method of manufacturing the thin film transistor shown in Fig. 1.
  • Fig. 14 is a view showing the steps of a method of manufacturing a thin film transistor of a second embodiment of the present invention.
  • 15 to 20 are schematic cross-sectional views showing respective manufacturing flows of the method of manufacturing the thin film transistor shown in Fig. 14.
  • the present invention provides a thin film transistor for use in a liquid crystal display or an organic display.
  • a method for fabricating a thin film transistor according to a first embodiment of the present invention includes the following steps:
  • Step S1 forming a gate electrode, a gate insulating layer, and an active layer on the substrate.
  • step S11 a substrate 10 is provided, and a gate electrode 11 is formed on a surface of the substrate 10.
  • Step S12 forming a gate insulating layer 12 on the surface of the gate 11 and the substrate 10 (as shown in FIG. 3).
  • the substrate 10 is made of a flexible material.
  • the substrate 10 is made of polyimide or polyethylene naphthalate.
  • the substrate 30 includes a flexible substrate and a support layer that supports the flexible substrate, the support layer being made of glass, metal, silicon, or a plastic material.
  • the gate electrode 11 is coated on the surface of the substrate 10 by a metal material, and is formed by removing a redundant portion by a patterning process.
  • the patterning process described in the next step includes a conventional patterning process such as photomasking, development, etching, and the like.
  • step S13 forming an active layer 13 over the gate on the gate insulating layer 12.
  • a semiconductor layer 102 is formed on a surface of the gate insulating layer 12 facing away from the substrate 10; the semiconductor layer 102 is patterned to form the active layer 13, wherein the active layer 13 Located above the gate 11 and projected may cover the gate 11.
  • the material of the semiconductor layer 102 is indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (InZnO) or zinc tin oxide (ZnSnO) or low temperature polycrystalline silicon or amorphous silicon.
  • the gate insulating layer 12 is made of one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiNxOy).
  • step S2 forming a protective layer on the gate insulating layer 12 and the active layer 13;
  • the protective layer may be an organic material, an electrodeless material, or a mixture of organic material and an infinite material.
  • the protective layer 12 is patterned to form an etch stop layer 14 on the active layer 13.
  • the step specifically includes: forming an organic layer (not shown) on the active layer 13 and the gate insulating layer 12, and then patterning the organic layer to form the etching barrier located in the middle of the active layer 13.
  • Layer 14 The etch stop layer 14 is used to protect the active layer 13, and the etch barrier material is an organic material such as a photoresist or other photosensitive organic material. It can easily remove solvents or other chemicals without damaging the active active layer 13. It will be appreciated that in other embodiments, the etch stop layer 14 may remain.
  • step S4 forming a metal layer 15 on the active 13, etch stop layer 14 and the gate insulating layer 12; the metal layer 15 includes an orthographic projection covering the etch stop layer 14 and an active layer A first area 151 of 13 and a second area 152 connecting opposite sides of the first area 151.
  • the first region 151 and the second region 152 are formed, the first region 151 covers the outer surface of the etching stopper layer 14 and the entire outer surface of the active layer 13.
  • the second region 152 is connected.
  • the first regions are located on both sides of the active layer 13.
  • Step S5 The photosensitive layer 16 is coated on the first region 151 of the metal layer 15.
  • the step includes covering a first region of the metal layer 15 with a photoresist or a photosensitive organic material, and then forming a positive projection through the patterned photoresist to cover the active layer 13 and the etch barrier layer 14 .
  • the photosensitive layer 16 covers the first region 151 of the metal layer.
  • Step S6 removing a portion of the photosensitive layer 16 to expose a portion of the first region 151 covering the metal layer 15 on the etch stop layer 14.
  • this step includes S61, removing metal layers other than the first region 151 of the metal layer 15 on both sides of the photosensitive layer 16.
  • the portion of the metal layer other than the first region 151 may be removed by a wet etching process or a dry etching process, and the remaining first region 151 is covered by the photosensitive layer 16.
  • this step further includes S62, removing part of the photosensitive layer 16 to expose part of the first portion. Area 151.
  • the partial photosensitive layer 16 is removed by a plasma ashing process to expose a portion of the first region 151 covering the etch stop layer 14, such that the remaining photosensitive layer covers another portion of the first region of the metal layer, and the remaining The photosensitive layer forms a self-aligned plane 162 on both sides of the exposed portion of the metal layer.
  • the first region 151 includes a portion 153 that is located on the active layer and a region 153 that is orthographically projected on both sides of the active layer.
  • the exposed portion of the photosensitive layer 16 is removed from the first region portion that is projected onto the active layer, and the exposed first region 151 is substantially inverted U-shaped and is higher than the remaining photosensitive layer 16.
  • the remaining photosensitive layer is located on region 153 to form a self-aligned plane 162.
  • the patterning process of the mask mode is omitted, and part of the photosensitive layer 16 is removed by the plasma ashing process, thereby avoiding the introduction of foreign reagents and the like to the active layer 13 or the metal layer 15 in the manufacturing process.
  • step S7 removing the etch stop layer 14 from the exposed portion of the metal layer. A portion of the first region 151 of the exposed metal layer is removed by an etching process and the etch stop layer 14 is exposed, and the surface 154 of the remaining metal layer after etching is aligned with the self-aligned plane 162.
  • step S8 the method further includes removing the remaining photosensitive layer to expose the remaining metal layer to form the source and drain.
  • the remaining first region on the side of the etch stop layer 14 and the region 153 connected thereto constitute the source electrode 17, and the remaining first region on the other side of the etch barrier layer 14 and the region 153 connected thereto constitute a drain Extreme 18.
  • This step is to remove the exposed first region 151 by a patterning process, leaving the remaining first region 151 on both sides of the etch barrier layer 14 connected to the region 153, and the remaining first region 151 and the The region 153 constitutes the drain 18 and the source 17.
  • This step includes:
  • the remaining photoresist layer is protected by using the remaining photoresist layer as a mask, and the exposed first region is etched; the remaining photoresist layer is stripped to form a remaining first region.
  • the method further includes a step S9 of removing the remaining photosensitive layer 16 to expose the source 17 and the drain 18.
  • the remaining photosensitive layer refers to a photosensitive layer covering the remaining first region.
  • the source 17 is spaced apart from the drain 18 and connected to portions on opposite sides of the active layer 13.
  • the method further includes the step S10 (not shown in FIG. 1 ) removing the etch stop layer to form a channel region of the thin film transistor: specifically, the etch stop layer 14 is removed by a patterning process, A gap between the source 17 and the drain 18 is exposed. In this step, both the source and the source are included The portion of the electrode 17 and the drain electrode 18 connected to the etching stopper layer 14 is subjected to planarization processing.
  • step S10 may not be included, the etch stop layer is not removed, thereby remaining on the channel region of the thin film transistor, and the etch stop layer is retained without lithography of the etch stop layer. This saves the number of masks, reduces the process flow, and the etch stop layer is retained to enhance the strength of the final entire thin film transistor.
  • the thin film transistor manufacturing method of the present application uses a metal layer to cover the etch barrier layer, and then removes part of the photosensitive layer 16 by a plasma ashing process to define a metal layer to be removed to form the source electrode 17 and the drain electrode 18, thereby achieving an etch barrier layer.
  • the source 17 and the drain 18 are self-aligned, and the source and drain locations can be accurately defined; and the present application directly compares the source and drain of the etch stop layer formed by the reticle on the etch barrier layer in the prior art.
  • the source and the drain are defined on the active layer 13, that is, the length of the channel region between the source 17 and the drain 18 to the active layer 13 is reduced, thereby reducing the generation of parasitic capacitance, and additionally saving one
  • the reticle patterning process reduces process flow and saves costs.
  • the difference from the first embodiment is that the support layer 45 and the support layer 46 are formed while the etching stopper layer 44 is formed.
  • the support layer is two, and finally a pair of source and drain connection active layers 43 are formed.
  • the specific steps are as follows. The same steps as the above-described first embodiment will not be described again.
  • the thin film transistor manufacturing method includes:
  • Step S20 forming a protective layer on the gate insulating layer and the active layer; the protective layer may be an organic material, an electrodeless material or an organic material mixed with an electrodeless material.
  • the steps of forming the gate, the gate insulating layer and the active layer on the substrate before the step S20 are the same as the method of the step S1 of the first embodiment.
  • the first embodiment can be used for reference to FIG. 1 to FIG. 3 of the first embodiment. .
  • step S21 the protective layer is patterned to form an etch barrier layer 44 and support layers 45, 46 on both sides of the etch barrier layer 44 on the gate insulating layer 12.
  • the formation of the etch stop layer 44 and the support layers 45, 46 is accomplished by the same process, that is, in the present embodiment, when the etch stop layer 44 is formed, the support layers 45, 46 on both sides are formed, thus saving the number of masks. , reduce the process flow.
  • step S22 forming a metal layer 47 on the etching barrier layer 44, the supporting layers 45, 46, and forming a photosensitive layer 48 on the metal layer 47, wherein the photosensitive layer can be planarized.
  • the functional organic layer is replaced.
  • This step and the step S4 form a metal layer on the active layer, the etch barrier layer and the gate insulating layer, and the step S5 applies a photosensitive layer in the first region of the metal layer.
  • the layers are all completed by the same process, that is, the metal layer of step S4 also covers the support layer, and the metal layer on the support layer also has a photosensitive layer or an organic planarization layer, which can save one step process.
  • step S23 a portion of the metal layer 47 on which the photosensitive layer 48 is exposed on the support layer 45, 46 and the etch stop layer 44 is removed by the same process; this step and the step S6 removing a portion of the photosensitive layer to expose a portion of the first region of the metal layer over the etch stop layer is the same process.
  • Another embodiment of this step is to selectively remove the support layer and the organic planarization layer on the etch stop layer by coating the organic photosensitive planarization layer and by incomplete exposure and corresponding development.
  • step S24 the metal layer 47 is removed to expose the support layer 45, 46 to the etching barrier layer 44.
  • This step is completed by the same process, thereby saving the number of masks and reducing the process flow.
  • the step S25 may be included to remove the support layer.
  • Removing the support layer includes the step of first removing the remaining photosensitive layer.
  • the support layer may be retained, and the support layer may be retained without lithography of the support layer, thereby saving the number of masks, reducing the process flow, and retaining the support layer to enhance the final film. The strength of the transistor.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)

Abstract

薄膜晶体管制造方法，包括：在基板（10）的表面上依次形成栅极（11）、覆盖栅极（11）及基板（10）表面形成栅极绝缘层（12）、位于所述栅极（11）上方形成有源层（13）、正投影于有源层（13）中部的蚀刻阻挡层（14）及在有源层（13）、蚀刻阻挡层（14）及栅极绝缘层（12）上形成包括覆盖所述蚀刻阻挡层（14）的第一区域（151）以及连接所述第一区域（151）相对两侧的第二区域（152），所述每一第二区域（152）与所述有源层（13）及蚀刻阻挡层（14）连接的金属层（15）；在金属层（15）上形成光阻层（16）并形成被光阻层（16）覆盖的与第一区域（151）连接的第三区域；去除部分光阻层（16），保留覆盖第三区域的剩余光阻层（16）并以露出部分第一区域（151）；去除露出的第一区域（151），保留位于蚀刻阻挡层（14）相对两侧的与剩余光阻层（16）连接且高度相同的剩余的第一区域（151），同时露出蚀刻阻挡层（14）；去除剩余的光阻层（16）。

Description

薄膜晶体管制造方法 技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种薄膜晶体管制造方法。
背景技术
薄膜晶体管(Thin-film transistors，TFT)阵列基板被广泛应用于不同类型的显示屏中，如LCD或AMOLED显示屏。随着显示屏尺寸的越来越大，对于TFT而言需要有大的电流以支持较高的分辨率。对于底栅型的薄膜晶体管，蚀刻阻挡层设于有源层上，用于在制程中保护有源层，以保证有源层电学性能的稳定。而受到TFT常规设置的影响，蚀刻阻挡层会增大源漏极与有源层之间形成的沟道的长度，从而影响显示器的分辨率。
发明内容
本发明实施例提供一种薄膜晶体管制造方法，用以解决蚀刻阻挡层与源漏极连接增大沟道的长度，产生较大的寄生电容而影响分辨率的技术问题。
本发明所述薄膜晶体管制造方法包括：
在基板的上形成栅极、栅极绝缘层以及有源层；
在所述栅极绝缘层和有源层上形成保护层；
图案化所述保护层以在所述有源层上形成蚀刻阻挡层；
在所述有源层、蚀刻阻挡层及栅极绝缘层上形成金属层；
在所述金属层的第一区域涂覆光敏层；
去除部分所述光敏层显露覆盖所述蚀刻阻挡层上的部分所述金属层；以及去除所述金属层露出部分所述蚀刻阻挡层。
本申请的薄膜晶体管制造方法采用金属层上覆盖光阻层后通过等离子灰化工艺先去除部分蚀刻阻挡层以限定需要去除的金属层来形成源极与漏极，实现通过蚀刻阻挡层与源极、漏极自对准，可以准确定义源漏极位置；而且本申请直接将源极与漏极定义在有源层上，即减小源极与漏极到有源层之间的沟道区域的长度，进而减小寄生电容的产生。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的薄膜晶体管制造方法步骤图。
图2至图13是图1所示的薄膜晶体管制造方法的各个制造流程的截面示意图。
图14是本发明第二实施例的薄膜晶体管制造方法步骤图。
图15至图20是图14所示的薄膜晶体管制造方法的各个制造流程的截面示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
本发明提供了薄膜晶体管用于液晶显示屏或者有机显示屏中。
请参阅图1，本发明第一实施例所述的薄膜晶体管制造方法包括如下步骤：
步骤S1：在基板的上形成栅极、栅极绝缘层以及有源层。
一并参阅图2，具体包括步骤S11：提供一基板10，在所述基板10的表面上形成栅极11。步骤S12：在所述栅极11及所述基板10表面上形成栅极绝缘层12(如图3)。所述基板10为柔性材料制成。所述基板10为聚酰亚胺或者聚萘二甲酸乙二醇酯制成。在其它实施例中，所述基板30包括柔性基层及支撑柔性基层的支撑层，所述支撑层由玻璃、金属、硅或者塑胶材料制成。所述栅极11为金属材料涂于基板10的表面上，再通过图案化工艺去除多余的部分形成。一下步骤中所述的图案化工艺包括光罩、显影、蚀刻等现有构图工艺。
参阅图4与图5，步骤S13：在所述栅极绝缘层12上位于所述栅极上方形成有源层13。具体的，在所述栅极绝缘层12背向所述基板10的表面上形成半导体层102；图案化所述半导体层102形成所述有源层13，其中有源层13 位于所述栅极11正上方并且投影可以覆盖所述栅极11。其中，所述半导体层102的材料为氧化铟镓锌(IGZO)、氧化锌(ZnO)、氧化铟锌(InZnO)或氧化锌锡(ZnSnO)或者为低温多晶硅、非晶硅。所述栅极绝缘层12采用氧化硅(SiOx)、氮化硅(SiNx)与氮氧化硅(SiNxOy)中的一种制成。
参阅图6，步骤S2：在所述栅极绝缘层12和有源层13上形成保护层；所保护层可以是有机材料、无极材料或者有机材料无极材料混合。
步骤S3，图案化所述保护层12以在所述有源层13上形成蚀刻阻挡层14。该步骤具体包括：在所述有源层13及栅极绝缘层12上形成有机物层(图未示)，然后，图案化所述有机物层形成位于所述有源层13中部的所述蚀刻阻挡层14。所述蚀刻阻挡层14用于保护所述有源层13，蚀刻阻挡层材料为有机材料，如光阻抗蚀剂或其他光敏有机材料。它可以很容易地除去溶剂或其他化学物质，而不破坏活动的有源层13。可以理解，在其它实施方式中，所述蚀刻阻挡层14可以保留。
请参阅图7，步骤S4：在所述有源13、蚀刻阻挡层14及栅极绝缘层12上形成金属层15；所述金属层15包括正投影覆盖所述蚀刻阻挡层14及有源层13的第一区域151以及连接所述第一区域151相对两侧的第二区域152。
具体的，在形成第一区域151与第二区域152时，使所述第一区域151覆盖所述蚀刻阻挡层14外表面及所述有源层13整个外表面，所述第二区域152连接所述第一区域位于有源层13的两侧。
步骤S5：在所述金属层15的第一区域151涂覆光敏层16。请参阅图8，本步骤包括在所述金属层15的第一区域上覆盖光刻胶或光敏有机材料，再通过图案化光刻胶形成正投影覆盖所述有源层13及蚀刻阻挡层14的所述光敏层16，所述光敏层16覆盖所述金属层的第一区域151。
步骤S6：去除部分所述光敏层16以显露覆盖所述蚀刻阻挡层14上的部分所述金属层15的第一区域151。
请参阅图9，本步骤包括S61，去除露出所述光敏层16两侧的金属层15的第一区域151以外的金属层。本步可以通过湿蚀刻工艺或者干蚀刻工艺去除所述第一区域151以外的金属层部分，剩余的第一区域151被光敏层16覆盖。
请参阅图10，本步骤还包括S62，去除部分光敏层16露出部分所述第一 区域151。本步骤中中采用等离子灰化工艺去除所述部分光敏层16以显露覆盖所述蚀刻阻挡层14的部分第一区域151，使剩余的光敏层覆盖金属层的另一部分第一区域，并且剩余的光敏层位于露出的部分金属层两侧形成自对准平面162。具体的，所述第一区域151包括位于所述正投影于有源层的部分及正投影位于有源层两侧的区域153。去除部分光敏层16露出部分位于正投影于有源层的第一区域部分，露出的第一区域151大致呈倒置U形并且高出剩余的光敏层16。剩余的光敏层位于区域153上构成自对准平面162。本步骤省去光罩方式的图案化工艺，采用等离子灰化工艺去除部分光敏层16，可以避免制造过程中对有源层13或者金属层15带来外来试剂等污染物。
请参阅图11，步骤S7：去除所述金属层露出部分所述蚀刻阻挡层14。通过蚀刻工艺去除所述露出的金属层的部分第一区域151并露出所述蚀刻阻挡层14，蚀刻后的剩余的金属层的表面154与所述自对准平面162对齐。
请参阅图12，步骤S8，所述方法还包括：去除剩余的光敏层显露剩余的金属层以形成所述源极和漏极。
位于所述蚀刻阻挡层14一侧的剩余的第一区域与其相连接的区域153构成源极17，位于所述蚀刻阻挡层14另一侧的剩余的第一区域与其相连接的区域153构成漏极18。本步骤是通过图案化工艺去除露出的所述第一区域151，留下位于所述蚀刻阻挡层14两侧的与所述区域153连接的剩余第一区域151，剩余第一区域151与所述区域153构成漏极18及源极17。本步骤中包括：
在所述露出的第一区域表面以及剩余光阻层的表面涂布光刻胶层；
图案化所述光刻胶层，移除覆盖所述露出的第一区域的部分光刻胶层；
以剩余的光刻胶层为掩膜保护剩余光阻层，对所述露出的第一区域进行蚀刻；剥离剩余的所述光刻胶层，形成剩余的第一区域。
本方法还包括步骤S9：去除剩余的光敏层16以露出所述源极17与所述漏极18。剩余的光敏层是指覆盖剩余第一区域的光敏层。所述源极17与所述漏极18间隔设置并连接所述有源层13相对两侧的部分。
请参阅图13，本方法中，还可以包括步骤S10(图1未示)去除所述蚀刻阻挡层以形成所述薄膜晶体管的沟道区域：具体为图案化工艺去除所述蚀刻阻挡层14，露出所述源极17与漏极18之间的间隙。此步骤中，同时包括对源 极17、漏极18与所述蚀刻阻挡层14连接的部分进行平整化加工。
在其他实施例中，也可以不包括步骤S10，蚀刻阻挡层没有被去除，从而保留在所述薄膜晶体管的沟道区域上，蚀刻阻挡层被保留可以不需要最后再对蚀刻阻挡层进行光刻，从而节省光罩次数，减少工艺流程，而且蚀刻阻挡层被保留也能增强最后整个薄膜晶体管的强度。
本申请的薄膜晶体管制造方法采用金属层上覆盖蚀刻阻挡层后通过等离子灰化工艺先去除部分光敏层16以限定需要去除的金属层来形成源极17与漏极18，实现通过蚀刻阻挡层与源极17、漏极18自对准，可以准确定义源漏极位置；而且相较于现有技术的在蚀刻阻挡层上通过光罩形成连接部分蚀刻阻挡层的源漏极，本申请直接将源极与漏极定义在有源层13上，即减小源极17与漏极18到有源层13之间的沟道区域的长度，进而减小寄生电容的产生，另外可以节省了一道光罩式图案化工艺，减少工艺流程，节省成本。
请参阅图14，本发明第二实施例中，与第一实施例不同之处在于在形成蚀刻阻挡层44的同时形成支撑层45及支撑层46。本实施例中，支撑层为两个，最后形成一对源漏极连接有源层43。具体的步骤如下，与上述第一实施例相同的步骤再次不再做过多赘述，所述薄膜晶体管制造方法包括：
步骤S20：在所述栅极绝缘层和有源层上形成保护层；所保护层可以是有机材料、无极材料或者有机材料无极材料混合。在此步骤S20之前在基板的上形成栅极、栅极绝缘层以及有源层是与第一实施例的步骤S1的方法相同，本实施例中可以借鉴第一实施例的图1至图3。
请参阅图15，步骤S21，图案化所述保护层以在所述栅极绝缘层12上形成蚀刻阻挡层44及位于所述蚀刻阻挡层44两侧的支撑层45、46。形成蚀刻阻挡层44及支撑层45、46是通过同一道工艺完成，也就是本实施例中，在说形成蚀刻阻挡层44时就形成了两侧的支撑层45、46，如此节省光罩次数，减少工艺流程。
请参阅图16与图17，步骤S22，在所述蚀刻阻挡层44、支撑层45、46上形成金属层47以及在所述金属层47上形成光敏层48，其中光敏层可以用有平坦化功能的有机层代替。此步骤与所述步骤S4在所述有源层、蚀刻阻挡层及栅极绝缘层上形成金属层，及步骤S5在所述金属层的第一区域涂覆光敏 层均是通过同一道工艺完成，也就是说步骤S4的金属层同样覆盖支撑层，支撑层上的金属层同样有光敏层或有机平坦化层，如此可以节省一步工艺。
请参阅图18，步骤S23，通过同一道工艺完成去除部分所述光敏层48显露位于所述支撑层上45、46以及蚀刻阻挡层44上的部分所述金属层47；本步骤与所述步骤S6去除部分所述光敏层显露覆盖所述蚀刻阻挡层上的部分所述金属层的第一区域是同一工艺。本步骤的另一种实施方式是通过涂布有机光敏平坦化层，并通过不完全曝光以及对应的显影，选择性的去除支撑层以及蚀刻阻挡层上的有机平坦化层。
请参阅图19，步骤S24，去除所述金属层47显露部分所述支撑层45、46蚀刻阻挡层44，本步骤是通过同一道工艺完成，如此节省光罩次数，减少工艺流程。
本实施例中可以包括S25步骤，去除所述支撑层。去除所述支撑层包括先去除剩余的光敏层的步骤。在其它实施方式中，可以保留所述支撑层，支撑层被保留可以不需要最后再对支撑层进行光刻，从而节省光罩次数，减少工艺流程，而且支撑层被保留也能增强最后整个薄膜晶体管的强度。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (14)

  1. 一种薄膜晶体管制造方法，其特征在于，所述方法包括：
    在基板的上形成栅极、栅极绝缘层以及有源层；
    在所述栅极绝缘层和有源层上形成保护层；
    图案化所述保护层以在所述有源层上形成蚀刻阻挡层；
    在所述有源层、蚀刻阻挡层及栅极绝缘层上形成金属层；
    在所述金属层的第一区域涂覆光敏层；
    去除部分所述光敏层显露覆盖所述蚀刻阻挡层上的部分所述金属层的第一区域；以及
    去除所述金属层露出部分所述蚀刻阻挡层。
  2. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所述方法还包括：去除剩余的光敏层显露剩余的金属层以形成所述源极和漏极。
  3. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述方法还包括：去除所述蚀刻阻挡层以形成所述薄膜晶体管的沟道区域。
  4. 如权利要求2或3所述的薄膜晶体管制造方法，其特征在于，所述步骤去除部分所述光敏层显露覆盖所述蚀刻阻挡层上的部分所述金属层及去除所述金属层显露部分所述蚀刻阻挡层包括：
    等离子灰化工艺去除部分所述光敏层以显露覆盖所述蚀刻阻挡层的部分第一区域，使剩余的光敏层覆盖金属层的另一部分第一区域，并且剩余的光敏层位于露出的部分金属层两侧形成自对准平面；
    蚀刻工艺去除所述露出部分第一区域并露出所述蚀刻阻挡层，蚀刻后的剩余的金属层的表面与所述自对准平面对齐。
  5. 如权利要求2所述的薄膜晶体管制造方法，其特征在于，所述步骤在所述金属层的第一区域涂覆光敏层；包括：在所述金属层的第一区域形成有光刻胶层，图案化光刻胶层形成正投影覆盖所述有源层及蚀刻阻挡层的光阻敏层。
  6. 如权利要求5所述薄膜晶体管制造方法，其特征在于，所述方法还包括去除露出所述光敏层两侧的金属层第一区域以外的金属层的步骤。
  7. 如权利要求6所述薄膜晶体管制造方法，其特征在于，去除露出所述 光阻层两侧的部分金属层中采用湿蚀刻工艺或者干蚀刻工艺。
  8. 如权利要求1所述的薄膜晶体管制造方法，其特征在于，所保护层可以是有机材料、无极材料或者有机材料无极材料混合。
  9. 如权利要求1-4任一项所述的薄膜晶体管制造方法，其特征在于，所述方法还包括：
    图案化所述保护层以在所述栅极绝缘层上形成位于所述蚀刻阻挡层两侧的支撑层；
    在所述支撑层上形成金属层以及在所述金属层上形成光敏层；
    去除部分所述光敏层显露位于所述支撑层上的部分所述金属层；
    去除所述金属层显露部分所述支持层；以及
    去除所述支撑层。
  10. 如权利要求9所述的薄膜晶体管制造方法，其特征在于，所述步骤图案化所述保护层以在所述栅极绝缘层上形成蚀刻阻挡层及位于所述蚀刻阻挡层两侧的支撑层通过同一道工艺完成。
  11. 如权利要求9所述的薄膜晶体管制造方法，其特征在于，所述步骤在所述支撑层上形成金属层以及在所述金属层上形成光敏层与所述步骤在所述有源层、蚀刻阻挡层及栅极绝缘层上形成金属层，在所述金属层的第一区域涂覆光敏层均是通过同一道工艺完成。
  12. 如权利要求9所述的薄膜晶体管制造方法，其特征在于，步骤在去除部分所述光敏层显露位于所述支撑层上的部分所述金属层与所述步骤去除部分所述光敏层显露覆盖所述蚀刻阻挡层上的部分所述金属层是通过同一道工艺完成。
  13. 如权利要求9所述的薄膜晶体管制造方法，其特征在于，所述步骤去除所述金属层显露部分所述支持层与所述步骤去除所述金属层露出部分所述蚀刻阻挡层是通过同一道工艺完成。
  14. 如权利要求9所述的薄膜晶体管制造方法，其特征在于，所述步骤去除所述支撑层包括先去除剩余的光敏层的步骤。
PCT/CN2016/097132 2016-08-29 2016-08-29 薄膜晶体管制造方法 Ceased WO2018039856A1 (zh)

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JP2019505517A JP2019523565A (ja) 2016-08-29 2016-08-29 薄膜トランジスタの製造方法
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