WO2017199728A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2017199728A1 WO2017199728A1 PCT/JP2017/016834 JP2017016834W WO2017199728A1 WO 2017199728 A1 WO2017199728 A1 WO 2017199728A1 JP 2017016834 W JP2017016834 W JP 2017016834W WO 2017199728 A1 WO2017199728 A1 WO 2017199728A1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
- G03F9/7046—Strategy, e.g. mark, sensor or wavelength selection
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Definitions
- the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a large-area semiconductor device that requires divided exposure and a manufacturing method thereof.
- photolithography is used for manufacturing a semiconductor device.
- This is a technique in which a resist is applied to a semiconductor substrate, exposed through a mask including a pattern using an exposure machine, and then the resist is developed to obtain a desired pattern.
- the element pattern necessary for the semiconductor device having a large size as described above may be larger than the size that can be exposed by the exposure machine.
- the imaging unit alone has a size of 36 mm ⁇ 24 mm, and the size of the peripheral circuit unit is added to this, so that the entire semiconductor device is further enlarged.
- the size that can be exposed by a general exposure machine is, for example, about 33 mm ⁇ 26 mm, and a pattern cannot be formed by a single exposure.
- joint exposure is used in which the semiconductor device is divided into a plurality of regions having a size that can be exposed, and each region is separately exposed and joined.
- FIG. 17 shows a solid-state imaging device 11 that includes an imaging unit 12 and a peripheral circuit unit 13 and is divided by a scribe region 14. Since the pattern of the solid-state imaging device 11 is larger than the size that can be exposed at one time, the pattern is divided into two division patterns 16a and 16b at the division position (joint portion 15), and these are individually exposed to form a desired pattern. Get.
- splicing accuracy for accurately splicing the divided patterns 16a and 16b is important.
- the joining accuracy is insufficient, a defect such as a circuit disconnection occurs in the joint 15.
- the elements are regularly arranged at a narrow interval, assuming that the elements are arranged at a joint portion, the characteristics of the element fluctuate due to a pattern shift, resulting in the joint portion in the acquired image. May become apparent.
- FIG. 18 an example of an image acquired by an imaging device in which the imaging unit 12 is divided into two left and right regions and a connecting unit is located at the center is illustrated in FIG. 18.
- FIG. 18 When there is a manifested connection portion 25 as in the acquired image 21 in FIG. 18, a discontinuous image is formed in a conspicuous portion in the center, and visual discomfort is large. Therefore, it should be avoided that a connecting portion exists near the center of the imaging unit 12.
- an object of the technology of the present disclosure is to connect adjacent patterns with high accuracy and to be able to flexibly set a position of a connection portion in a semiconductor device using connection exposure and a manufacturing method thereof.
- a semiconductor device includes a first inspection mark region and a second inspection mark region having the same pattern including a plurality of overlay inspection marks, and a first inspection mark region. And a first element region having a portion overlapping with the second inspection mark region, and a second element region having a portion overlapping with the second inspection mark region.
- the first element region and the second element region are adjacent to each other and have different areas.
- the first element region has a first pattern aligned with a plurality of first overlay inspection marks that are part of the plurality of overlay inspection marks.
- the second element region has a second pattern aligned with a plurality of second overlay inspection marks that are part of the plurality of overlay inspection marks.
- the manufacturing method of the semiconductor device includes exposing a test mark mask to a first test mark region having the same pattern including a plurality of overlay test marks. And a step of forming a second inspection mark region, and a first element region having a portion overlapping with the first inspection mark region is formed by exposing the first mask to form a first pattern. And a step of forming a second element region having a portion overlapping with the second inspection mark region by exposing the second mask to form a second pattern. The first element region and the second element region are adjacent to each other and have different areas.
- the first mask is aligned using a plurality of first overlay inspection marks that are part of the plurality of overlay inspection marks.
- the second mask is aligned using a plurality of second overlay inspection marks that are part of the plurality of overlay inspection marks.
- the first element region and the second element region having two patterns having different areas are positioned with respect to the first inspection mark region and the second inspection mark region having the same pattern. Since they are aligned, the position of the connecting portion between the first element region and the second element region is not fixed and can be set freely. Therefore, restrictions on the layout of elements can be relaxed, and the time and labor required for designing can be reduced and / or the semiconductor device can be downsized.
- the technology of the present disclosure is applied to an image sensor, it is possible to avoid the presence of a connection portion near the center of the image pickup unit, and therefore, the connection portion is prevented from becoming apparent at a prominent position near the center of the acquired image. Can do.
- FIG. 1 is a schematic diagram for explaining splicing exposure according to the present disclosure.
- FIG. 2 is a schematic diagram for explaining conventional splice exposure.
- FIG. 3 is a plan view schematically illustrating an exemplary semiconductor device of the present disclosure.
- FIG. 4 is a schematic plan view of a mask used for pattern formation of the element isolation layer in the first embodiment of the present disclosure.
- FIG. 5 is a schematic plan view of a mask used for forming an overlay inspection mark before forming an element isolation layer in the first embodiment of the present disclosure.
- FIG. 6 is a perspective view schematically showing the position of the pattern of the element isolation layer with respect to the overlay inspection mark in the first embodiment of the present disclosure.
- FIG. 1 is a schematic diagram for explaining splicing exposure according to the present disclosure.
- FIG. 2 is a schematic diagram for explaining conventional splice exposure.
- FIG. 3 is a plan view schematically illustrating an exemplary semiconductor device of the present disclosure.
- FIG. 4 is a schematic plan view of
- FIG. 7 is a diagram schematically illustrating a pattern arrangement when the layer pattern including the overlay inspection mark and the semiconductor element is repeatedly exposed in the first embodiment of the present disclosure.
- FIG. 8 is a schematic plan view of a mask used for forming a pattern of the gate electrode layer in the first embodiment of the present disclosure.
- FIG. 9 is a perspective view schematically showing the position of the pattern of the gate electrode layer with respect to the pattern of the element isolation layer in the first embodiment of the present disclosure.
- FIG. 10 is a schematic plan view of a mask used for pattern formation of the element isolation layer in the second embodiment of the present disclosure.
- FIG. 11 is a schematic plan view of a mask used for forming an overlay inspection mark before forming an element isolation layer in the second embodiment of the present disclosure.
- FIG. 12 is a perspective view schematically showing the position of the pattern of the element isolation layer with respect to the overlay inspection mark in the second embodiment of the present disclosure.
- FIG. 13 is a diagram schematically illustrating a pattern arrangement when a layer pattern including overlay inspection marks and semiconductor elements is repeatedly exposed in the second embodiment of the present disclosure.
- FIG. 14 is a schematic plan view of a mask used for forming a pattern of the gate electrode layer in the second embodiment of the present disclosure.
- FIG. 15 is a perspective view schematically showing the position of the pattern of the gate electrode layer with respect to the pattern of the element isolation layer in the second embodiment of the present disclosure.
- FIG. 16 is a diagram illustrating an image acquired by the semiconductor device of the present disclosure.
- FIG. 17 is a plan view schematically showing a conventional semiconductor device.
- FIG. 18 is a diagram showing an image acquired by the semiconductor device of FIG.
- FIG. 1 and FIG. 2 are diagrams for explaining splicing exposure according to the present disclosure and conventional splicing exposure, and are diagrams schematically showing mainly the overlapping and positional relationship between regions.
- first inspection mark area mask In the conventional splice exposure shown in FIG. 2, exposure using the same mask (inspection mark area mask) is performed to form the adjacent first inspection mark area 31a and second inspection mark area 31b. These inspection mark areas 31a and 31b have overlay inspection marks 41 at the four corners, respectively.
- a first element region 32 that overlaps with the first inspection mark region 31a and has the same area is formed using a first mask having a pattern for forming a semiconductor element.
- the positions of the mask and the semiconductor substrate are adjusted so that the positions of the inspection mark 41 in the first inspection mark area 31a and the inspection mark 42 in the first element area 32 are aligned.
- a second element region 33 that overlaps with the second inspection mark region 31b and has the same area is formed using a second mask.
- the positions of the mask and the semiconductor substrate are adjusted so that the inspection marks 41 in the second inspection mark region 31b and the inspection marks 42 in the second element region 33 are aligned.
- the first mask and the second mask have the same exposure area, but the patterns may be different.
- a semiconductor element having a size combining the first element region 32 and the second element region 33 can be formed.
- the inspection mark areas 31a and 31b are formed by exposure of the same mask, so that the joining accuracy is improved.
- the connecting portion 35 of both regions is fixed at the center of the entire semiconductor device and is free. Cannot be set. As a result, the deterioration of the performance of the semiconductor device when the misalignment occurs in the connecting portion is significant, or the layout of the semiconductor element is limited to avoid this, and the size of the semiconductor device is increased. happenss.
- first inspection mark areas 51 a and second inspection marks are obtained.
- Region 51b is formed.
- these inspection mark areas 51a and 51b have at least two overlay inspection marks at each of the four corners. More specifically, the first overlay inspection mark 61a is disposed near the corners of the four corners, and the second overlay inspection mark 61b is disposed at a position closer to the corner than these.
- the first and second overlay inspection marks 61a and 61b are arranged in the direction in which the first and second inspection mark regions 51a and 51b are arranged.
- the first element region 52 and the second element region 53 having different areas can be formed with high accuracy by joint exposure. .
- a first mask having a pattern for forming a semiconductor element is used to form a first element region 52 having a portion overlapping with the first inspection mark region 51a but having a smaller area.
- the position of the mask and the semiconductor substrate is adjusted so that the first overlay inspection mark 61a in the first inspection mark region 51a and the inspection mark 62a in the first element region 52 are aligned.
- a second element region 53 having a portion overlapping with the second inspection mark region 51b and having a larger area is formed.
- the position of the mask and the semiconductor substrate is adjusted so that the second overlay inspection mark 61b in the second inspection mark region 51b and the inspection mark 62b in the second element region 53 are aligned.
- a semiconductor element having a size in which the first element region 52 and the second element region 53 are combined can be formed in the same manner as the conventional joining.
- the inspection mark regions 51a and 51b are formed by exposure of the same mask, so that the joining accuracy is improved.
- the position of the connecting portion 55 is not limited to the center of the entire semiconductor device, and can be set as necessary. it can. Therefore, for example, in the case of an imaging apparatus, it is possible to reduce the sense of discomfort even if a discontinuity occurs in the acquired image by avoiding the connecting portion being located at the center of the imaging region.
- the inspection mark areas 51a and 51b are adjacent (arranged without leaving a gap), but this is not essential.
- FIG. 3 shows a schematic plan view of an exemplary semiconductor device 101 of the present disclosure.
- the semiconductor device 101 is a solid-state imaging device, and includes an imaging unit 102 in the center and an imaging unit 103 that includes the imaging unit 102.
- a peripheral circuit 104 is provided around the periphery, and a scribe region 105 is located around the periphery circuit 104.
- the elements in the inner imaging unit 102 are used, and when capturing a still image, the elements in the imaging unit 103 (the elements in the inner imaging unit 102 and the outer elements thereof). Both with partial elements).
- the pattern of the semiconductor device 101 is divided into a plurality (here, three) of patterns 107a, 107b, and 107c by the connecting portions 106a and 106b.
- the semiconductor device 101 is manufactured by connecting these by connecting exposure.
- the semiconductor device 101 is assumed to be composed of a semiconductor element formed by an element isolation layer and a gate electrode layer, but it is not limited to this.
- FIG. 4 shows a first element formation mask 108 and a second element formation mask 109 used for splice exposure for forming an element isolation layer of the semiconductor device 101.
- the pattern of the semiconductor device 101 is divided so that the patterns 107 a and 107 c in FIG. 3 are included in the mask 108 and the pattern 107 b is included in the mask 109.
- most of the imaging unit 103 and the entire imaging unit 102 are included in the mask 109.
- a pattern of the entire semiconductor device in which the pattern 107b is sandwiched between the pattern 107a and the pattern 107c is formed.
- the exposure region 110 of the element forming mask 108 is a rectangle having a height h and a width a, and the size thereof is a ⁇ h.
- the exposure region 111 of the element forming mask 109 is a rectangle having a height h and a width b, and the size is b ⁇ h.
- one feature of the plurality of divided masks is that the height of the exposure region is the same but the width is different, resulting in different areas.
- the masks 108 and 109 include overlay inspection marks 112a to 112h and 113a to 113h in addition to the pattern of the semiconductor element. Although not shown, alignment marks, dimension inspection patterns, and the like are also provided.
- FIG. 5 shows an inspection mark mask for forming such an overlay inspection mark.
- the inspection mark mask 114 includes only a pattern formed in a scribe region such as an overlay inspection mark and an alignment mark (not shown), and does not include a pattern for forming a semiconductor element.
- the exposure area 115 of the inspection mark mask 114 has a height of h, a width of c, and a size of c ⁇ h.
- the width c is the sum of the width a of the exposure region 110 of the element forming mask 108 and the width b of the exposure region 111 of the element forming mask 109 divided by 2, that is, (a + b) / 2. equal.
- the total exposure area of the element formation masks 108 and 109 is equal to twice the exposure area of the inspection mark mask 114.
- At least two overlay inspection marks are arranged near the four corners of the inspection mark mask 114.
- inspection marks 116a, 116d, 116e, and 116h are arranged at the four corners of the inspection mark mask 114, and along the side of the width c, they are closer to the inside in the inspection mark region.
- Inspection marks 116b, 116c, 116f, and 116g are arranged at the positions.
- FIG. 6 shows one of the processes for manufacturing the semiconductor device 101.
- the exposure apparatus is set so that the areas to be exposed are adjacent to each other, the inspection mark areas 117a, 117b, and 117c are exposed, further developed, and an overlay inspection mark. Formed.
- an area where one exposure area overlaps an adjacent exposure area may be set in the inspection mark mask 114, and an overlay inspection mark between areas adjacent to the area may be arranged.
- the semiconductor substrate is etched using the pattern obtained by such exposure to form an overlay inspection mark, an alignment mark, etc. on the semiconductor substrate, and then the resist film is removed.
- an element isolation layer pattern is formed using the element formation masks 108 and 109.
- an oxide film and a nitride film are formed, and a resist is applied.
- alignment is performed using the overlay inspection marks 116a to 116g previously formed, and exposure is performed. More specifically, the overlay inspection marks 112b, 112c, 112f, and 112g of the element forming mask 108 and the overlay inspection marks 116b, 116c, 116f, and 116g in the inspection mark region 117a overlap with the mask 108, respectively. Exposure is performed by adjusting the position with the semiconductor substrate. Thereby, a pattern of the element isolation layer is formed in the element region 118a.
- the inspection mark regions (117a, 117b) and the element regions 118a and 118b formed by being aligned with them have to be all the same size.
- the degree of freedom in the size of the element regions 118a and 118b is increased, and the position of the joint portion can be set to a desired location. It is possible.
- the overlay inspection marks 112b, 112c, 112f, and 112g of the element forming mask 108 are aligned with the overlay inspection marks 116b, 116c, 116f, and 116g, and exposure is performed on the inspection mark region 117c. As a result, a pattern of the element isolation layer is formed in the element region 118c.
- the pattern 107b of the element region 118b formed by the mask 109 and the pattern of the element region 118a formed by the mask 108 on one side (left side in FIG. 6).
- a pattern corresponding to the entire semiconductor device 101 is formed which includes the pattern 107c of the element region 118c formed by the mask 108 on the other side (right side in FIG. 6) 107a.
- pattern formation using the element formation masks 108 and 109 is alternately and repeatedly performed in this manner.
- the inspection mark regions (117a to 117g) repeatedly formed using the inspection mark mask 114 and the overlay inspection marks formed thereon are aligned with the element formation masks 108 and 109 alternately.
- the positional relationship of element regions (118a to 118g) formed repeatedly is shown.
- a portion corresponding to one of the semiconductor devices 101 is indicated as a region 101a.
- the overlay inspection is performed using the overlay inspection mark included in the obtained pattern. If the overlay accuracy is within a predetermined standard, the nitride film is etched to expose the oxide film, and then the resist is removed. If the overlay accuracy is out of specification, the resist is removed and exposure is performed again. That is, after the resist is removed, the resist is applied again, the measurement value of the overlay inspection is fed back, the stage position of the exposure machine is adjusted, and the exposure is performed.
- the oxide film and the semiconductor substrate are etched to form a trench.
- an unnecessary insulating material is removed by CMP (Chemical Mechanical Polish) to form element isolation.
- a gate oxide film is formed, and a polysilicon layer serving as a material for the gate electrode is formed thereon.
- FIG. 8 shows a mask used for forming the gate electrode.
- the exposure region 121 of the gate electrode formation mask 119 is a rectangle having a height h and a width a, and the size is a ⁇ h, which is the same as the exposure region 110 of the first element formation mask 108.
- the exposure region 122 of the gate electrode formation mask 120 is a rectangle having a height h and a width b, and the size is b ⁇ h, which is the same as the exposure region 111 of the second element formation mask 109.
- the gate electrode forming masks 119 and 120 also include overlay inspection marks 123a to 123d and 124a to 124d in addition to the semiconductor element pattern. Although not shown, an alignment mark, a dimension inspection pattern, and the like are also provided.
- a resist is applied to the semiconductor substrate on which the polysilicon layer is formed, and then exposure using the gate electrode formation masks 119 and 120 is performed. This is shown in FIG.
- the overlay inspection marks 123a, 123b, 123c of the gate electrode formation mask 119 are added to the overlay inspection marks 112a, 112d, 112e and 112h of the element region 118a formed by the first element formation mask 108 in the previous step. Exposure is performed by adjusting the positions of the mask and the semiconductor substrate so that 123d overlap each other. Thus, a gate electrode pattern is formed in the element region 118a.
- the overlay inspection marks 124a, 124b, 124c, and 124d of the gate electrode formation mask 120 are added to the overlay inspection marks 113a, 113d, 113e, and 113h of the element region 118b formed by the second element formation mask 109.
- the exposure is performed by adjusting the positions of the mask and the semiconductor substrate so that the two overlap each other.
- a gate electrode pattern is formed in the element region 118b.
- the overlay inspection is performed using the overlay inspection mark included in the obtained pattern.
- pattern distortion tends to occur near the edge of the area.
- the masks 119 and 120 so that the overlay inspection mark is arranged at the end of the element region 118b, the distortion of the pattern at the time of exposure can be fed back more accurately.
- the element isolation pattern and the gate electrode pattern can be superimposed with higher accuracy.
- Etching the polysilicon layer using the obtained pattern and removing the resist to form a gate electrode is manufactured.
- the description is limited to the two layers here.
- the above method can be applied to all layers that perform joint exposure, such as wiring, hole patterns, and patterns used for ion implantation.
- a pattern can be formed using the overlay inspection mark and alignment mark formed by the inspection mark mask 114, and processing such as ion implantation and etching can be performed.
- a pattern can be formed using the overlay inspection mark or alignment mark formed by the inspection mark mask 114, and processing such as ion implantation and etching can be performed.
- FIG. 1 An example of an image captured by the manufactured semiconductor device 101 is shown in FIG. 1
- the still image 301 is acquired by the imaging unit 103 (including the imaging unit 102) illustrated in FIG. Since the connecting portions 106 a and 106 b exist near both ends of the imaging unit 103, even when the connecting portions become apparent due to a slight shift in the pattern, the connecting portions 303 a and 303 b that appear near both ends of the still image 301 are located. .
- This is an image that is less uncomfortable than the conventional acquired image 21 shown in FIG. That is, in the conventional acquired image 21, since the connecting portion 25 that has been manifested is located in a conspicuous portion near the center, there is a great sense of discomfort.
- the manifested connecting portions 303a and 303b are close to the edge of the image, and most of the image is not affected. Yes.
- the distance d (see FIG. 5) between the centers of the inspection marks (for example, the inspection mark 116a and the inspection mark 116b) arranged at the same corner of the inspection mark mask 114 is the exposure area 110 of the element forming mask 108.
- the distance d is half of the difference between the width b of the exposure region 111 of the element formation mask 109 and the width c of the exposure region 115 of the inspection mark mask 114, that is, (bc) / 2. It is almost equal. Thereby, each inspection mark can be arranged in a desired region.
- a plurality of inspection marks used in exposure be arranged at positions apart from each other in one mask.
- the inspection mark region (117b) is used for alignment of the element formation mask 109 for exposing the element region 118b (the larger one of the two large and small element regions).
- the inspection marks 116a, 116d, 116e and 116h are arranged as close as possible to the outer corners of the four corners), and are used.
- an inspection mark closer to the inside in the inspection mark region (117a or 117c) is used.
- 116b, 116c, 116f, and 116g are arranged and used.
- the inspection marks 116b, 116c, 116f, and 116g should be positioned as close to the inspection mark region (116a or 116c) as possible.
- the corresponding position in the element region 118a or 118c is out of the range of the element region 118a or 118c and enters the element region 118b, and cannot be used for alignment.
- the inner inspection mark 116b is separated from the boundary between the inspection mark areas by a distance i or more. Need to be placed. Further, as described above, if the distance is more than the distance i, it is better to arrange the element regions close to each other (that is, closer to the outside of the element regions).
- the distance i is half the difference between the width a or the width b and the width c, that is, (ca) / 2 or (bc) / 2. It is. Accordingly, the distance between the central tube between the outer inspection mark (for example, 116a) and the inner inspection mark (for example, 116b) at the same corner of the inspection mark region is set to (ca) / 2 or (bc). It is good to set it to about / 2.
- each inspection mark can be used for alignment and arranged as far as possible, and both of the two types of element regions (118a and 118b, etc.) can be aligned better.
- the inspection marks 112b, 112c, 112f and 112g used for alignment of the element regions 118a and 118b are used for the inspection used for alignment of the gate electrode layer later in the process of FIG. It is formed inside the marks 112a, 112d, 112e and 112h.
- the inspection marks 116b, 116c, 116f, and 116g in the inspection mark region 117a are also formed on the inner side by the corresponding dimensions. As described above, the specific position of the inspection mark may be determined in consideration of various factors.
- FIG. 10 shows a first element formation mask 201 and a second element formation mask 202 which are used for splice exposure for forming an element isolation layer of the semiconductor device 101 in this embodiment.
- the first element forming mask 201 is a rectangle whose exposure area 203 has a height h and a width a, and has overlay inspection marks 205a to 205h.
- the second element formation mask 202 is a rectangle whose exposure region 204 has a height h and a width b, and has overlay inspection marks 206a to 206h.
- first and second element formation masks 201 and 202 have substantially the same configuration as the first and second element formation masks 108 and 109 in the first embodiment, and the patterns 107a and 107 in FIG. The pattern corresponding to 107c is included.
- the inspection marks (206b, 206c, 206f, and 206g) from the inside are the case of the second element formation mask 109 of the first embodiment (113b, 113c, 113f). And 113g).
- an overlay inspection mark, an alignment mark, and the like are formed by exposure of one mask prior to pattern formation of the element isolation layer.
- An inspection mark mask 207 for this purpose is shown in FIG.
- the inspection mark mask 207 includes only a pattern formed in a scribe region such as an overlay inspection mark and an alignment mark (not shown), and does not include a pattern for forming a semiconductor element.
- the exposure area 208 of the inspection mark mask 207 has a height of h, a width of e, and a size of e ⁇ h.
- the width e of the exposure region is larger than the width a of the exposure region of the first element formation mask 201 and the width of the exposure regions of the first and second element formation masks 201 and 202. Is less than the sum a + b.
- the same inspection mark mask 207 is used, and the overlay inspection mark is formed so that the areas to be exposed are not adjacent to each other and are spaced apart from each other. This is shown in FIG.
- the step f (distance f) of moving the stage of the exposure machine to expose the next inspection mark area 210b includes first and second element formation masks 201 and 202.
- the total of the widths of the exposure areas 203 and 204 is equal to a + b.
- the semiconductor substrate After exposure and development, the semiconductor substrate is etched to form overlay inspection marks and alignment marks on the semiconductor substrate, and the resist is removed.
- an element isolation layer pattern is formed using the element formation masks 201 and 202.
- an oxide film and a nitride film are formed, and a resist is applied.
- the element formation is performed such that the overlay inspection marks 205b, 205c, 205f, and 205g of the element formation mask 201 overlap the overlay inspection marks 209b, 209c, 209f, and 209g of the region 210a.
- Exposure is performed by adjusting the positions of the mask 201 and the semiconductor substrate. Thereby, a pattern of the element isolation layer is formed in the element region 211a.
- a pattern is formed in the element region 211b by using a plurality of inspection marks arranged in the two regions 210a and 210b. More specifically, the overlay inspection marks 206b and 206f of the element forming mask 202 overlap with the overlay inspection marks 209d and 209h in the area 210a, respectively, and the overlay inspection marks 209a and 209e in another area 210b overlap with the element. Exposure is performed by adjusting the positions of the mask and the semiconductor substrate so that the overlay inspection marks 206c and 206g of the formation mask 202 overlap each other.
- the connection portion The position can be set at a desired location.
- the overlay inspection marks 205b, 205c, 205f, and 205g of the element forming mask 201 are aligned with the overlay inspection marks 209b, 209c, 209f, and 209g of the region 210b, and exposure is performed on the element region 211c.
- the overlay inspection marks 205b, 205c, 205f, and 205g of the element forming mask 201 are aligned with the overlay inspection marks 209b, 209c, 209f, and 209g of the region 210b, and exposure is performed on the element region 211c.
- pattern formation using the element formation masks 201 and 202 is alternately and repeatedly performed in this manner. This is further illustrated in FIG. That is, the element formation masks 201 and 202 are alternately repeated in alignment with the inspection mark regions (210a to 210d) repeatedly formed using the inspection mark mask 207 and the overlay inspection marks formed there. The positional relationship of the element regions (211a to 211g) formed by using them is shown. A portion corresponding to one of the semiconductor devices 101 is indicated as a region 101b.
- overlay inspection is performed as in the first embodiment.
- an element isolation layer is formed in the same manner as in the first embodiment. Further, after forming a gate insulating film and a polysilicon layer, they are patterned to form a gate electrode layer.
- FIG. 14 shows a mask used for forming the gate electrode.
- These element formation masks 212 and 213 have the same configuration as the gate electrode formation masks (119 and 120 in FIG. 8) in the first embodiment. That is, the exposure regions 214 and 215 of the element formation masks 212 and 213 have sizes of a ⁇ h and b ⁇ h in order, and the exposure of the element formation masks 201 and 202 for forming the element isolation layer shown in FIG. It is equal to the size of the areas 203 and 204.
- the element formation masks 212 and 213 also include overlay inspection marks 216a to 216d and 217a to 217d in addition to the pattern of the semiconductor element. Although not shown, an alignment mark, a dimension inspection pattern, and the like are also provided.
- a resist is applied to the semiconductor substrate on which the polysilicon layer is formed, and then exposure using the element formation masks 212 and 213 is performed. This is shown in FIG.
- the overlay inspection marks 216a, 216b, 216c, and 216d of the element formation mask 212 overlap with the overlay inspection marks 205a, 205d, 205e, and 205h of the element region 211a formed by the element formation mask 201 in the previous step.
- exposure is performed by adjusting the positions of the mask and the semiconductor substrate. Thereby, the pattern of the element region 211a is formed.
- overlay inspection marks 217a, 217b, 217c, and 217d of the element formation mask 213 overlap with overlay inspection marks 206a, 206d, 206e, and 206h of the element region 211b formed by the element formation mask 202, respectively.
- exposure is performed by adjusting the positions of the mask and the semiconductor substrate. Thereby, a pattern of the element region 211b is formed.
- the overlay inspection is performed using the overlay inspection mark included in the obtained pattern.
- Etching the polysilicon layer using the obtained pattern and removing the resist to form a gate electrode Thereby, the semiconductor device 101 including the element isolation layer and the gate electrode layer is manufactured. Note that applications such as being applicable to other layers are the same as in the first embodiment.
- the same effect as described in the first embodiment can be obtained. Further, the number of inspection mark regions to be formed can be reduced as compared with the first embodiment.
- one semiconductor device may be divided into two large and small patterns, and one semiconductor device may be formed by the two patterns.
- the degree of freedom of the position of the joint portion is increased while maintaining high accuracy in joint exposure, and thus it is useful as a semiconductor device and a manufacturing method thereof.
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Abstract
Description
図3に、本開示の例示的半導体装置101の模式的な平面図を示す。半導体装置101は固体撮像装置であり、中央に撮像部102と、当該撮像部102を内包する撮像部103とを有する。その周囲には周辺回路104が設けられ、更に周囲にはスクライブ領域105が位置する。ここで、動画を撮像する際には内側の撮像部102内の素子を使用し、静止画を撮像する際には撮像部103内の素子(内側の撮像部102内の素子と、その外側の部分の素子との両方)を使用する。
第2の実施形態について説明する。本実施形態についても、図3の例示的半導体装置101を例として説明する。
12 撮像部
13 周辺回路部
14 スクライブ領域
15 繋ぎ部
16a、16b 分割パターン
21 取得画像
25 顕在化した繋ぎ部
31a 第1の検査マーク領域
31b 第2の検査マーク領域
32 第1の素子領域
33 第2の素子領域
35 繋ぎ部
41、42 検査マーク
51a 第1の検査マーク領域
51b 第2の検査マーク領域
52 第1の素子領域
53 第2の素子領域
55 繋ぎ部
61a、61b 検査マーク
62a、62b 検査マーク
101 半導体装置
102 撮像部(動画用)
103 撮像部(静止画用)
104 周辺回路
105 スクライブ領域
106a、106b 繋ぎ部
107a~107c パターン
108 第1の素子形成用マスク
109 第2の素子形成用マスク
110、111 露光領域
112a、112d、112e、112h 検査マーク
112b、112c、112f、112g 検査マーク
113a、113d、113e、113h 検査マーク
113b、113c、113f、113g 検査マーク
114 検査マーク用マスク
115 露光領域
116a、116d、116e、116h 検査マーク
116b、116c、116f、116g 検査マーク
117a~117g 検査マーク領域
118a~118g 素子領域
119、120 ゲート電極形成用マスク
121、122 露光領域
123a~123d 検査マーク
124a~124d 検査マーク
201 第1の素子形成用マスク
202 第2の素子形成用マスク
203、204 露光領域
205a、205d、205e、205h 検査マーク
205b、205c、205f、205g 検査マーク
206a、206d、206e、206h 検査マーク
206b、206c、206f、206g 検査マーク
207 検査マーク用マスク
208 露光領域
209a、209d、209e、209h 検査マーク
209b、209c、209f、209g 検査マーク
210a、210b、210c、210d 検査マーク領域
211a~211g 素子領域
212、213 素子形成用マスク
214、215 露光領域
216a~216d 検査マーク
217a~217d 検査マーク
301 静止画
302 動画
303a、303b 繋ぎ部
Claims (18)
- 複数の重ね合わせ検査マークを含む同一のパターンを有する第1の検査マーク領域及び第2の検査マーク領域と、
前記第1の検査マーク領域と重複する部分を有する第1の素子領域と、
前記第2の検査マーク領域と重複する部分を有する第2の素子領域とを備え、
前記第1の素子領域及び前記第2の素子領域は、互いに隣接し且つ異なる面積を有しており、
前記第1の素子領域は、前記複数の重ね合わせ検査マークの一部である複数の第1の重ね合わせ検査マークに位置合わせされた第1のパターンを有し、
前記第2の素子領域は、前記複数の重ね合わせ検査マークの一部である複数の第2の重ね合わせ検査マークに位置合わせされた第2のパターンを有することを特徴とする半導体装置。 - 請求項1の半導体装置において、
前記第1の検査マーク領域及び前記第2の検査マーク領域は隣接しており、
前記第1の重ね合わせ検査マークは、いずれも前記第1の検査マーク領域に配置され、
前記第2の重ね合わせ検査マークは、いずれも前記第2の検査マーク領域に配置されていることを特徴とする半導体装置。 - 請求項2の半導体装置において、
前記第1の検査マーク領域及び前記第2の検査マーク領域の面積の合計は、前記第1の素子領域及び前記第2の素子領域の面積の合計と等しいことを特徴とする半導体装置。 - 請求項2又は3の半導体装置において、
前記第1の検査マーク領域及び前記第2の検査マーク領域の四隅それぞれに、前記第1の検査マーク領域と前記第2の検査マーク領域とが隣接する隣接方向に並ぶ少なくとも2つの前記重ね合わせ検査マークが設けられ、当該2つの重ね合わせ検査マークの中心同士の間の距離は、前記隣接方向における、前記第1の素子領域又は前記第2の素子領域の寸法と、前記第1の検査マーク領域の寸法との差の二分の一程度であることを特徴とする半導体装置。 - 請求項2~4のいずれか1つの半導体装置において、
前記第1の検査マーク領域と同一のパターンを有し、且つ、前記第2の検査マーク領域に対して前記第1の検査マーク領域と反対側に隣接する第3の検査マーク領域と、
第3の検査マーク領域と重複する部分を有し、且つ、前記第2の素子領域に対して前記第1の素子領域と反対側に隣接する第3の素子領域とを更に備え、
前記第3の素子領域は、前記第3の検査マーク領域に配置された前記重ね合わせ検査マークに位置合わせされた第3のパターンを有することを特徴とする半導体装置。 - 請求項1の半導体装置において、
前記第1の検査マーク領域と、前記第2の検査マーク領域とは間隔を置いて設けられており、
前記第1の重ね合わせ検査マークは、いずれも前記第1の検査マーク領域に配置され、
前記第2の重ね合わせ検査マークは、前記第1の検査マーク領域及び前記第2の検査マーク領域に亘って配置されていることを特徴とする半導体装置。 - 請求項6の半導体装置において、
前記第1の検査マーク領域及び前記第2の検査マーク領域の四隅それぞれに、前記第1の検査マーク領域と前記第2の検査マーク領域とが並ぶ方向に並ぶように、少なくとも2つの前記重ね合わせ検査マークが設けられていることを特徴とする半導体装置。 - 請求項6又は7の半導体装置において、
前記第2の検査マーク領域と重複する部分を有し、且つ、前記第2の素子領域に対して前記第1の素子領域と反対側に隣接する第4の素子領域を更に備え、
前記第4の素子領域は、少なくとも前記第2の検査マーク領域に配置された前記重ね合わせ検査マークに位置合わせされた第4のパターンを有することを特徴とする半導体装置。 - 請求項1~8のいずれか1つの半導体装置において、
前記第1の素子領域は、第3の重ね合わせ検査マークを備え、
前記第2の素子領域は、第4の重ね合わせ検査マークを備え、
前記第3の重ね合わせ検査マークに位置合わせされた第5のパターンを有し、且つ、前記第1の素子領域と重複する部分を有する、第5の素子領域と、
前記第4の重ね合わせ検査マークに位置合わせされた第6のパターンを有し、且つ、前記第2の素子領域と重複する部分を有する、第6の素子領域とを更に備えることを特徴とする半導体装置。 - 検査マーク用マスクを露光することにより、複数の重ね合わせ検査マークを含む同一のパターンを有する第1の検査マーク領域及び第2の検査マーク領域を形成する工程と、
第1のマスクを露光して第1のパターンを形成することにより、第1の検査マーク領域と重複する部分を有する第1の素子領域を形成する工程と、
第2のマスクを露光して第2のパターンを形成することにより、第2の検査マーク領域と重複する部分を有する第2の素子領域を形成する工程とを備え、
前記第1の素子領域及び前記第2の素子領域は、互いに隣接し且つ異なる面積を有しており、
前記第1の素子領域を形成する工程において、前記複数の重ね合わせ検査マークの一部である複数の第1の重ね合わせ検査マークを利用して前記第1のマスクの位置合わせを行い、
前記第2の素子領域を形成する工程において、前記複数の重ね合わせ検査マークの一部である複数の第2の重ね合わせ検査マークを利用して前記第2のマスクの位置合わせを行うことを特徴とする半導体装置の製造方法。 - 請求項10の半導体装置の製造方法において、
前記第1の検査マーク領域及び前記第2の検査マーク領域は隣接しており、
前記第1の重ね合わせ検査マークは、前記第1の検査マーク領域に配置され、
前記第2の重ね合わせ検査マークは、前記第2の検査マーク領域に配置されていることを特徴とする半導体装置の製造方法。 - 請求項11の半導体装置の製造方法において
前記第2の検査マーク領域及び前記第2の検査マーク領域の面積の合計は、前記第1の素子領域及び前記第2の素子領域の面積の合計と等しいことを特徴とする半導体装置の製造方法。 - 請求項11又は12の半導体装置の製造方法において、
前記第1の検査マーク領域及び前記第2の検査マーク領域の四隅それぞれに、前記第1の検査マーク領域と前記第2の検査マーク領域とが隣接する隣接方向に並ぶ少なくとも2つの前記重ね合わせ検査マークが設けられ、当該2つの重ね合わせ検査マークの中心同士の間の距離は、前記隣接方向における、前記第1の素子領域又は前記第2の素子領域の寸法と、前記第1の検査マーク領域の寸法との差の二分の一程度であることを特徴とする半導体装置の製造方法。 - 請求項11~13のいずれか1つの半導体装置の製造方法において、
前記検査マーク用マスクを露光することにより、前記第2の検査マーク領域に対して前記第1の検査マーク領域と反対側に隣接する第3の検査マーク領域を形成する工程と、
第3のマスクを露光して第3のパターンを形成することにより、第3の検査マーク領域と重複する部分を有する第3の素子領域を形成する工程とを更に備え、
前記第3の素子領域を形成する工程において、前記第3の検査マーク領域に配置された前記重ね合わせ検査マークを利用して前記第3のマスクの位置合わせを行うことを特徴とする半導体装置の製造方法。 - 請求項10の半導体装置の製造方法において、
前記第1の検査マーク領域と、前記第2の検査マーク領域とは間隔を置いて設けられており、
前記第1の重ね合わせ検査マークは、前記第1の検査マーク領域に配置され、
前記第2の重ね合わせ検査マークは、前記第1の検査マーク領域及び前記第2の検査マーク領域に亘って配置されていることを特徴とする半導体装置の製造方法。 - 請求項15の半導体装置の製造方法において、
前記第1の検査マーク領域及び前記第2の検査マーク領域の四隅それぞれに、前記第1の検査マーク領域と前記第2の検査マーク領域とが並ぶ方向に並ぶように少なくとも2つの前記重ね合わせ検査マークが設けられていることを特徴とする半導体装置の製造方法。 - 請求項15又は16の半導体装置の製造方法において、
第4のマスクを露光して第4のパターンを形成することにより、前記第2の検査マーク領域と重複する部分を有し、且つ、前記第2の素子領域に対して前記第1の素子領域と反対側に隣接する第4の素子領域を形成する工程を更に備え、
前記第4の素子領域を形成する工程において、前記第2の検査マーク領域に配置された前記重ね合わせ検査マークを利用して前記第4のマスクの位置合わせを行うことを特徴とする半導体装置の製造方法。 - 請求項10~17のいずれか1つの半導体装置の製造方法において、
前記第1の素子領域に形成する前記第1のパターンは、第3の重ね合わせ検査マークを含み、
前記第2の素子領域に形成する前記第2のパターンは、第4の重ね合わせ検査マークを含み、
前記第3の重ね合わせ検査マークに位置合わせして第5のマスクを露光し、第5のパターンを形成することにより、前記第1の素子領域と重複する部分を有する第5の素子領域を形成する工程と、
前記第4の重ね合わせ検査マークに位置合わせして第6のマスクを露光し、第6のパターンを形成することにより、前記第1の素子領域と重複する部分を有する第5の素子領域を形成する工程とを更に備えることを特徴とする半導体装置の製造方法。
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CN201780028680.XA CN109074006B (zh) | 2016-05-18 | 2017-04-27 | 半导体装置及其制造方法 |
KR1020187035081A KR20190009313A (ko) | 2016-05-18 | 2017-04-27 | 반도체 장치 및 그 제조 방법 |
JP2018518196A JP6847936B2 (ja) | 2016-05-18 | 2017-04-27 | 半導体装置の製造方法 |
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EP (1) | EP3451062B1 (ja) |
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CN109375478A (zh) * | 2018-10-02 | 2019-02-22 | 友达光电股份有限公司 | 曝光装置及其对位曝光方法 |
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EP3602624A1 (de) * | 2017-03-20 | 2020-02-05 | EV Group E. Thallner GmbH | Verfahren zur ausrichtung zweier substrate |
US11158600B2 (en) * | 2018-09-28 | 2021-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Lithography process for semiconductor packaging and structures resulting therefrom |
CN110471259B (zh) * | 2019-06-19 | 2021-12-14 | 上海华力微电子有限公司 | 芯片拼接方法 |
JP7114537B2 (ja) * | 2019-09-13 | 2022-08-08 | 株式会社東芝 | 半導体検査装置及び半導体装置の検査方法 |
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JPWO2017199728A1 (ja) | 2019-03-14 |
EP3451062A1 (en) | 2019-03-06 |
CN109074006A (zh) | 2018-12-21 |
JP2021064001A (ja) | 2021-04-22 |
US20190088602A1 (en) | 2019-03-21 |
EP3451062A4 (en) | 2019-06-05 |
CN109074006B (zh) | 2021-03-23 |
KR20190009313A (ko) | 2019-01-28 |
JP6847936B2 (ja) | 2021-03-24 |
US10679948B2 (en) | 2020-06-09 |
EP3451062B1 (en) | 2020-08-19 |
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