WO2017187785A1 - 過電流保護回路 - Google Patents
過電流保護回路 Download PDFInfo
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- WO2017187785A1 WO2017187785A1 PCT/JP2017/008536 JP2017008536W WO2017187785A1 WO 2017187785 A1 WO2017187785 A1 WO 2017187785A1 JP 2017008536 W JP2017008536 W JP 2017008536W WO 2017187785 A1 WO2017187785 A1 WO 2017187785A1
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- signal
- threshold
- value
- voltage
- overcurrent protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/006—Calibration or setting of parameters
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
- B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
- B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
- B60R16/03—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/087—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current for dc applications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
Definitions
- the present invention relates to an overcurrent protection circuit.
- an overcurrent protection circuit as one of their abnormality protection circuits.
- an in-vehicle IPD intelligent power device
- an overcurrent limit that limits the output current flowing to the power transistor to less than the overcurrent setting value so that the device will not be destroyed even if the load connected to the power transistor is short-circuited.
- a current protection circuit is provided.
- an overcurrent protection circuit that can arbitrarily adjust an overcurrent set value using an external resistor has been proposed.
- Patent Document 1 and Patent Document 2 can be cited as examples of conventional techniques related to the above.
- in-vehicle ICs are required to comply with ISO 26262 (international standard for functional safety related to automobile electrical / electronics), and higher reliability design is important for in-vehicle IPDs. It has become.
- the invention disclosed in the present specification is an overcurrent protection capable of both ensuring an instantaneous current and overcurrent protection according to a load.
- An object is to provide a circuit.
- the overcurrent protection circuit disclosed in the present specification switches whether the overcurrent detection threshold is set to the first set value or the second set value lower than the first set value according to the threshold control signal.
- a threshold generation unit an overcurrent detection unit that generates an overcurrent protection signal by comparing the sense signal corresponding to the monitoring target current and the overcurrent detection threshold, and generates a reference value corresponding to the second set value
- a reference value generation unit a comparison unit that compares the sense signal with the reference value to generate a comparison signal
- a threshold control unit that monitors the comparison signal and generates the threshold control signal.
- the threshold control unit masks the sense signal while exceeding the reference value when the overcurrent detection threshold is the first set value.
- a configuration (second configuration) may be employed in which the threshold control signal is generated so that the overcurrent detection threshold is switched to the second set value when the period has elapsed.
- the threshold control unit is configured to detect when the sense signal falls below the reference value when the overcurrent detection threshold is the second set value.
- the threshold control signal may be generated (third configuration) so that the overcurrent detection threshold is switched to the first set value.
- the mask period may be a variable value (fourth configuration).
- the first set value is a fixed value and the second set value is a variable value (fifth configuration). Good.
- a semiconductor integrated circuit device disclosed in the present specification includes a power transistor that conducts / cuts off a current path through which an output current flows, an output current monitoring unit that generates a sense signal corresponding to the output current, and a control A gate control unit that generates a drive signal for the power transistor in response to the signal, and an overcurrent protection circuit having any one of the first to fifth configurations that monitors the sense signal and generates an overcurrent protection signal.
- the gate controller is configured to be integrated (sixth configuration) having a function of forcibly turning off the power transistor in accordance with the overcurrent protection signal.
- the semiconductor integrated circuit device having the sixth configuration further comprises a signal output unit that selectively outputs one of the output current detection result and the abnormality flag as a status notification signal to the outside of the device (seventh configuration). Configuration).
- an electronic device disclosed in this specification includes a semiconductor integrated circuit device having the sixth or seventh configuration and a load connected to the semiconductor integrated circuit device (eighth). Composition).
- the load may be a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (9th configuration).
- the vehicle disclosed in the present specification has a configuration (tenth configuration) including an electronic device having the eighth or ninth configuration.
- the overcurrent protection circuit disclosed in the present specification sets the first overcurrent detection threshold to the first set value or lower than the first set value according to the first threshold control signal.
- a first threshold value generation unit that switches whether to set a value, and whether the second overcurrent detection threshold value is set to a third set value or a fourth set value that is lower than the third set value according to a second threshold control signal
- a second threshold generation unit that switches between, a first overcurrent detection unit that generates a first overcurrent protection signal by comparing a first sense signal corresponding to a first monitored current and the first overcurrent detection threshold;
- a second overcurrent detection unit that generates a second overcurrent protection signal by comparing a second sense signal corresponding to a second monitored current and the second overcurrent detection threshold; and according to the second set value
- a first reference value generator for generating a first reference value, and a second reference value corresponding to the fourth set value
- a second reference value generation unit a first comparison unit that generates a first comparison signal by comparing the first sense signal and the first
- the threshold control unit compares the external terminal for externally attaching the capacitor with the charging voltage appearing at the external terminal and a predetermined reference voltage.
- a comparator that generates a signal; a first flip-flop that generates the first threshold control signal according to the internal signal and the first comparison signal; and the second threshold according to the internal signal and the second comparison signal.
- a second flip-flop for generating a control signal; a discharge control unit for controlling discharge of the capacitor in accordance with the internal signal; and a charge control for the capacitor in accordance with both the first comparison signal and the second comparison signal.
- a charge control unit that performs (a twelfth configuration).
- the discharge control unit includes not only the internal signal but also the first comparison signal, the second comparison signal, the first threshold control signal, and the The input of the second threshold control signal is received, and after the logic level change occurs in one of the first comparison signal and the second comparison signal and the capacitor charging operation is started, the charging voltage is changed to the reference voltage.
- the capacitor is temporarily discharged (a thirteenth configuration).
- the threshold control unit includes a first delay unit that delays the first comparison signal to generate a first delay signal, and a second comparison signal. And a second delay unit that generates a second delay signal by providing a delay, and the first flip-flop and the second flip-flop are replaced with the first comparison signal and the second comparison signal, respectively.
- the first delay signal and the second delay signal may be input (fourteenth configuration).
- the first set value and the third set value are both fixed values, and the second set value and the fourth set value are set.
- the semiconductor integrated circuit device disclosed in this specification conducts the first power transistor that conducts / cuts off the first current path through which the first output current flows and the second current path through which the second output current flows. / A second power transistor to be cut off; a first output current monitoring unit that generates a first sense signal according to the first output current; and a second output that generates a second sense signal according to the second output current.
- a second gate control unit to be generated; and any one of the eleventh to fifteenth configurations for monitoring the first sense signal and the second sense signal to generate the first overcurrent protection signal and the second overcurrent protection signal.
- the second power transistor is configured to have a function of forcibly turning off (a sixteenth configuration).
- the semiconductor integrated circuit device having the sixteenth configuration includes a first signal output unit that generates one of the detection result of the first output current and the abnormality flag as a first state notification signal, and the second output current.
- a second signal output unit that generates one of the detection result and the abnormality flag as a second state notification signal; and a multiplexer that selectively outputs one of the first state notification signal and the second state notification signal to the outside of the apparatus.
- An integrated configuration (17th configuration) is preferable.
- An electronic device disclosed in the present specification is connected to the semiconductor integrated circuit device having the sixteenth or seventeenth configuration, the first load connected to the first power transistor, and the second power transistor. And a second load to be configured (eighteenth configuration).
- the first load and the second load may be configured as a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (a nineteenth configuration). .
- the vehicle disclosed in the present specification has a configuration (twentieth configuration) having an electronic device having the eighteenth or nineteenth configuration.
- an overcurrent protection circuit capable of both ensuring an instantaneous current and overcurrent protection according to a load.
- FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device Block diagram showing one configuration example of signal output unit Block diagram showing one configuration example of the gate control unit Block diagram showing one configuration example of overcurrent protection circuit Circuit diagram showing one configuration example of the first current generator Circuit diagram showing one configuration example of the second current generator
- the circuit diagram which shows one structural example of a threshold voltage generation part and an overcurrent detection part Schematic diagram showing an example of overcurrent set value Circuit diagram showing a configuration example of the reference voltage generation unit and the comparison unit Circuit diagram showing one configuration example of threshold control unit Timing chart showing an example of overcurrent protection operation Flow chart showing an example of threshold switching operation Schematic diagram showing a first usage example of an overcurrent protection circuit Schematic diagram showing a second usage example of the overcurrent protection circuit Block diagram showing a second embodiment of a semiconductor integrated circuit device Block diagram showing an example of the configuration of a two-channel overcurrent protection circuit Block diagram showing a first embodiment of the threshold control unit Timing chart showing threshold value switching operation of the first embodiment Timing chart showing problems of the first embodiment Block diagram showing
- FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device.
- ECU electronic control unit
- IPD IPD
- the semiconductor integrated circuit device 1 includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device.
- the external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (for example, 12V) from a battery (not shown).
- the external terminal T2 is a load connection terminal (OUT pin) for externally connecting the load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, or the like).
- the external terminal T3 is a signal input terminal (IN pin) for receiving an external input of the external control signal Si from the ECU 2.
- the external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU 2.
- An external sense resistor 4 is externally connected between the external terminal T4 and the ground terminal.
- the semiconductor integrated circuit device 1 includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output.
- the current detector 80 and the signal output unit 90 are integrated.
- the NMOSFET 10 is a high breakdown voltage (for example, 42V breakdown voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2.
- the NMOSFET 10 connected in this way functions as a switch element (high side switch) for conducting / cutting off a current path from the application end of the power supply voltage VBB to the ground end via the load 3.
- the NMOSFET 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.
- the NMOSFET 10 may be designed so that the on-resistance value is several tens of m ⁇ .
- the lower the on-resistance value of the NMOSFET 10, the more easily an overcurrent flows when the external terminal T 2 is grounded ( a short-circuit to the ground terminal or a low-potential terminal corresponding thereto), and abnormal heat generation is likely to occur. Therefore, as the on-resistance value of the NMOSFET 10 is lowered, the importance of an overcurrent protection circuit 71 and a temperature protection circuit 73 described later becomes higher.
- the NMOSFETs 21 and 21 ′ are mirror transistors connected in parallel to the NMOSFET 10, and generate sense currents Is and Is ′ corresponding to the output current Io.
- the size ratio between the NMOSFET 10 and the NMOSFETs 21 and 21 ' is m: 1 (where m> 1). Therefore, the sense currents Is and Is ′ have a magnitude obtained by reducing the output current Io to 1 / m.
- the NMOSFETs 21 and 21 ' are turned on when the gate drive signal G1 is at a high level and turned off when the gate voltage G2 is at a low level, as in the NMOSFET 10.
- This is a current / voltage conversion element that generates an output voltage that appears.
- the gate control unit 30 performs on / off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 with an increased current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively.
- the gate control unit 30 has a function of forcibly turning off the NMOSFETs 10 and 21 without depending on the gate control signal S1 when the overcurrent protection signal S71 is at the logic level at the time of abnormality detection.
- control logic unit 40 monitors various abnormality protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and reduced voltage protection signal S74).
- the control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the abnormality protection signals described above. Yes.
- the signal input unit 50 is a Schmitt trigger that receives an external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60.
- the external control signal Si is, for example, at a high level when the NMOSFET 10 is turned on and at a low level when the NMOSFET 10 is turned off.
- the internal power supply unit 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each part of the semiconductor integrated circuit device 1. Note that whether or not the internal power supply unit 60 is operable is controlled according to the external control signal Si. More specifically, the internal power supply unit 60 is in an operating state when the external control signal Si is at a high level, and is in a non-operating state when the external control signal Si is at a low level.
- the abnormality protection unit 70 is a circuit block that detects various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a voltage drop protection circuit 74. .
- the overcurrent protection signal S71 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.
- the open protection signal S72 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.
- a protection signal S73 is generated.
- the temperature protection signal S73 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.
- the reduced voltage protection signal S74 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.
- the output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases.
- the fixed voltage V90 is selected and output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So.
- FIG. 2 is a block diagram illustrating a configuration example of the signal output unit 90.
- the signal output unit 90 of this configuration example includes a selector 91.
- the selector 91 selectively outputs the sense current Is ′ to the external terminal T4 when the output selection signal S2 is at the logic level when no abnormality is detected (for example, low level), and the output selection signal S2 is at the logic level when the abnormality is detected.
- the fixed voltage V90 is selectively output to the external terminal T4.
- the fixed voltage V90 is set to a voltage value higher than the upper limit value of the output detection voltage V80 described above.
- both the detection result of the output current Io and the abnormality flag can be transmitted to the ECU 2 using a single state notification signal So, which contributes to the reduction of the number of external terminals. It becomes possible.
- the state notification signal So may be A / D [analog-to-digital] converted.
- the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.
- FIG. 3 is a block diagram illustrating a configuration example of the gate control unit 30.
- the gate control unit 30 in this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, and an NMOSFET 35.
- An increased gate drive signal G1 is generated.
- the oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33. Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40.
- the charge pump 33 generates a boosted voltage VG higher than the power supply voltage VBB by driving the flying capacitor using the clock signal CLK. Whether or not the charge pump 33 can operate is controlled according to the enable signal Sb from the control logic unit 40.
- the output voltage Vo becomes a negative voltage ( ⁇ GND) due to the back electromotive force of the load 3. Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.
- the drain of the NMOSFET 35 is connected to the gate of the NMOSFET 10.
- the source of the NMOSFET 35 is connected to the external terminal T2.
- the gate of the NMOSFET 35 is connected to the application terminal of the overcurrent protection signal S71.
- FIG. 4 is a block diagram illustrating a configuration example of the overcurrent protection circuit 71.
- the overcurrent protection circuit 71 of this configuration example includes a first current generation unit 110, a second current generation unit 120, a threshold voltage generation unit 130, an overcurrent detection unit 140, a reference voltage generation unit 150, and a comparison unit. 160 and a threshold control unit 170.
- the first current generator 110 generates the first current Iref and outputs it to the threshold voltage generator 130.
- the current value of the first current Iref is fixed inside the semiconductor integrated circuit device 1.
- the second current generator 120 generates the second current Iset and outputs it to the threshold voltage generator 130.
- the current value of the second current Iset can be arbitrarily adjusted from the outside of the semiconductor integrated circuit device 1.
- the internal set value VthH is a fixed value (corresponding to the first set value) set in accordance with the first current Iref.
- the external set value VthL is a variable value (corresponding to the second set value) set according to the second current Iset.
- the overcurrent detection unit 140 compares the sense voltage Vs and the threshold voltage Vth to generate an overcurrent protection signal S71.
- the comparison unit 160 compares the sense voltage Vs with the reference voltage VIset to generate a comparison signal VCMP.
- the threshold control unit 170 monitors the comparison signal VCMP and generates a threshold control signal S170.
- the threshold control signal S170 is, for example, a low level when the internal set value VthH is to be selected as the threshold voltage Vth, and a high level when the external set value VthL is to be selected as the threshold voltage Vth.
- FIG. 5 is a circuit diagram illustrating a configuration example of the first current generation unit 110.
- the first current generation unit 110 of this configuration example includes an operational amplifier 111, an NMOSFET 112, and a resistor 113 (resistance value: R113).
- the power supply terminal of the operational amplifier 111 is connected to the application terminal of the internal power supply voltage Vreg.
- the reference potential terminal of the operational amplifier 111 is connected to the ground terminal GND.
- the non-inverting input terminal (+) of the operational amplifier 111 is connected to an application terminal for a reference voltage Vref (for example, a bandgap reference voltage that is not easily affected by power supply fluctuations, temperature fluctuations, etc.).
- the inverting input terminal ( ⁇ ) of the operational amplifier 111 and the source of the NMOSFET 112 are connected to the first terminal of the resistor 113.
- a second end of the resistor 113 is connected to the ground end GND.
- the output terminal of the operational amplifier 111 is connected to the gate of the NMOSFET 112.
- the drain of the NMOSFET 112 is connected to the output terminal of the first current Iref.
- FIG. 6 is a circuit diagram illustrating a configuration example of the second current generator 120.
- the second current generation unit 120 of this configuration example includes an operational amplifier 121, an NMOSFET 122, a resistor 123 (resistance value: R123), and an external terminal SET.
- the power supply terminal of the operational amplifier 121 is connected to the application terminal of the internal power supply voltage Vreg.
- the reference potential terminal of the operational amplifier 121 is connected to the ground terminal GND.
- the non-inverting input terminal (+) of the operational amplifier 121 is connected to the application terminal for the reference voltage Vref.
- the inverting input terminal ( ⁇ ) of the operational amplifier 121 and the source of the NMOSFET 122 are connected to the external terminal SET.
- the output terminal of the operational amplifier 121 is connected to the gate of the NMOSFET 122.
- the drain of the NMOSFET 122 is connected to the output terminal of the second current Iset.
- the resistor 123 is connected between the external terminal SET and the ground terminal GND outside the semiconductor integrated circuit device 1.
- the operational amplifier 121 connected as described above controls the gate of the transistor 122 so that the non-inverting input terminal (+) and the inverting input terminal ( ⁇ ) are imaginarily short-circuited.
- FIG. 7 is a circuit diagram illustrating a configuration example of the threshold voltage generation unit 130 and the overcurrent detection unit 140.
- the threshold voltage generation unit 130 includes a current source 131, a resistor 132, and a current mirror 133.
- the overcurrent detection unit 140 includes a comparator 141.
- the current source 131 is connected between the current input terminal of the current mirror unit 133 and the application terminal of the constant voltage VBBM5, and selectively outputs one of the first current Iref and the second current Iset according to the threshold control signal S170. To do. More specifically, the current source 131 selectively outputs the first current Iref when the threshold control signal S170 is at a low level, and selectively outputs the second current Iset when the threshold control signal S170 is at a high level. To do.
- the current mirror unit 133 also functions as a level shifter that transfers the first current Iref or the second current Iset from the first power supply system (VBB_REF-VBBM5 system) to the second power supply system (VG-Vo system).
- VBB_REF and the constant voltage VBBM5 are both reference voltages generated inside the semiconductor integrated circuit device 1.
- VBB_REF ⁇ VBB and VBBM5 ⁇ VBB-5V.
- the power supply terminal of the comparator 141 is connected to the application terminal of the boost voltage VG.
- the reference potential terminal of the comparator 141 is connected to the application terminal (external terminal T2) of the output voltage Vo.
- the non-inverting input terminal (+) of the comparator 141 is connected to the application terminal for the sense voltage Vs.
- the inverting input terminal ( ⁇ ) of the comparator 141 is connected to the application terminal for the threshold voltage Vth.
- the comparator 141 connected in this way compares the sense voltage Vs with the threshold voltage Vth and generates an overcurrent protection signal S71.
- FIG. 8 is a schematic diagram showing an example of the overcurrent set value.
- the threshold voltage Vth compared with the sense voltage Vs is switched to one of the internal set value VthH and the external set value VthL according to the threshold control signal S170. This is equivalent to switching the overcurrent set value Iocp to be compared with the output current Io to one of the internal set value IocpH and the external set value IocpL.
- the internal set value IocpH is a fixed value (for example, about 15 A) corresponding to the on-resistance value and the element breakdown voltage of the NMOSFET 10 so that the semiconductor integrated circuit device 1 is not destroyed even when a short circuit abnormality of the load 3 occurs. Is desirable.
- the internal set value IocpH is only for the purpose of protecting the semiconductor integrated circuit device 1 itself, and often deviates greatly from the steady value of the output current Io.
- the external set value IocL is desirably a variable value (for example, 1A to 10A) corresponding to the load 3.
- the output current Io when the bulb lamp is driven is generally larger than the output current Io when the solenoid is driven.
- the external set value IocL may be set higher than when the solenoid is driven.
- the output current Io when driving the light emitting diode is generally smaller than the output current Io when driving the solenoid.
- the external set value IocL may be set lower than when the solenoid is driven.
- some loads 3 to be driven by the semiconductor integrated circuit device 1 need to flow a large output current Io instantaneously as a normal operation thereof. For example, when the bulb lamp is started, a larger inrush current flows instantaneously than during steady operation. Depending on the load 3, a difference of several tens of times may occur between the output current Io at the time of startup and the output current Io at the time of steady operation.
- the overcurrent set value Iocp compared with the output current Io (and thus the threshold voltage Vth compared with the sense voltage Vs). ) Must be switched at an appropriate time.
- FIG. 9 is a circuit diagram illustrating a configuration example of the reference voltage generation unit 150 and the comparison unit 160.
- the reference voltage generation unit 150 includes a current source 151 and a resistor 152 (resistance value: R152).
- the comparison unit 160 includes a comparator 161.
- the current source 151 is connected between the application terminal of the boosted voltage VG and the resistor 152, and the second current Iset generated by the second current generator 120 (more precisely, equivalent to the second current Iset). Variable current).
- the power supply terminal of the comparator 161 is connected to the application terminal of the boost voltage VG.
- the reference potential terminal of the comparator 161 is connected to the application terminal (external terminal T2) of the output voltage Vo.
- the non-inverting input terminal (+) of the comparator 161 is connected to the application terminal for the sense voltage Vs.
- the inverting input terminal ( ⁇ ) of the comparator 161 is connected to the application terminal of the reference voltage VIset.
- the comparator 161 connected in this way compares the sense voltage Vs with the reference voltage VIset and generates a comparison signal VCMP.
- the comparison signal VCMP becomes a low level when the sense voltage Vs is lower than the reference voltage VIset, and becomes a high level when the sense voltage Vs is higher than the reference voltage VIset.
- the resistance value R152 of the resistor 152 is switched to one of the first resistance value Rdet1 and the second resistance value Rdet2 (where Rdet1> Rdet2) according to the comparison signal VCMP. More specifically, the resistance value R152 of the resistor 152 becomes the first resistance value Rdet1 when the comparison signal VCMP is at a low level, and becomes the second resistance value Rdet2 when the comparison signal VCMP is at a high level. Hysteresis characteristics can be imparted to the comparison unit 160 by such switching control of the resistance value R152.
- FIG. 10 is a circuit diagram illustrating a configuration example of the threshold control unit 170.
- Threshold control unit 170 includes a comparator 171, a current source 172, a level shifter 173, an RS flip-flop 174, a discharge control unit 175, an NMOSFET 176, a capacitor 177, and an external terminal DLY.
- the power supply terminal of the comparator 171 is connected to the application terminal of the internal power supply voltage Vreg.
- the reference potential terminal of the comparator 171 is connected to the ground terminal GND.
- the non-inverting input terminal (+) of the comparator 171 is connected to the external terminal DLY (application terminal for the charging voltage Vd).
- the inverting input terminal ( ⁇ ) of the comparator 171 is connected to the application terminal of the mask period expiration voltage Vdref.
- the comparator 171 connected in this way compares the charging voltage Vd with the mask period expiration voltage Vdref and generates an internal signal Sx.
- the internal signal Sx becomes high level when the charging voltage Vd is higher than the mask period expiration voltage Vdref, and becomes low level when the charging voltage Vd is lower than the mask period expiration voltage Vdref.
- the RS flip-flop 174 outputs a threshold control signal S170 from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal Sy input to the reset terminal (R). More specifically, the RS flip-flop 174 sets the threshold control signal S170 to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170 to a low level at the falling timing of the internal signal Sy. .
- the discharge controller 175 generates an internal signal Sz in response to the internal signal Sx. More specifically, the discharge controller 175 sets the internal signal Sz to a high level over a predetermined discharge period Tdchg at the rising timing of the internal signal Sx.
- the NMOSFET 176 is turned on when the internal signal Sz is at a high level, and turned off when the internal signal Sz is at a low level.
- the capacitor 177 is connected between the external terminal DLY and the ground terminal GND outside the semiconductor integrated circuit device 1.
- the charging current Id is supplied from the current source 172 when the NMOSFET 176 is turned off, the charging voltage Vd of the capacitor 177 increases.
- NMOSFET 176 is on, capacitor 177 is discharged through NMOSFET 176, so that charging voltage Vd decreases.
- FIG. 11 is a timing chart showing an example of the overcurrent protection operation.
- the external control signal Si the first current Iref, the second current Iset, the sense voltage Vs, the comparison signal VCMP, the charge voltage Vd, and the internal signal Sx to Sz, threshold control signal S170, threshold voltage Vth, and state notification signal So are depicted.
- a predetermined activation delay period Tdly for example, 5 ⁇ s
- the shutdown of the semiconductor integrated circuit device 1 is released.
- the NMOSFET 10 is turned on and the output current Io starts to flow, so that the sense voltage Vs starts to rise.
- the comparison signal VCMP since the sense voltage Vs is lower than the reference voltage VIset, the comparison signal VCMP becomes low level. Therefore, since the threshold control signal S170 becomes low level, the internal set value VthH is selected as the threshold voltage Vth.
- the comparison signal VCMP becomes high level.
- the internal signal Sy goes high, and the charging voltage Vd begins to rise.
- the internal signal Sx becomes high level. Therefore, since the threshold control signal S170 is set to a high level, the threshold voltage Vth is switched to the external set value VthL. As a result, after time t14, overcurrent protection is applied so that the sense voltage Vs does not exceed the external set value VthL.
- the internal signal Sx rises to a high level, the internal signal Sz also becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.
- the discharge period Tdchg is desirably shorter (for example, 3 ⁇ s) than the above-described start delay period Tdly.
- the threshold voltage Vth is set to the internal set value VthH
- Vth is switched to the external set value VthL. Therefore, overcurrent protection according to the load 3 can be realized.
- the threshold voltage Vth is set to the internal set value VthH
- the sense voltage Vs exceeds the internal set value VthH
- overcurrent protection is applied without delay at that time. Therefore, when a short circuit abnormality of the load 3 or the like occurs, the NMOSFET 10 can be forcibly turned off quickly, so that the semiconductor integrated circuit device 1 itself can be prevented from being destroyed.
- the mask period Tmask is a variable value that can be arbitrarily adjusted using the external capacitor 177. More specifically, the mask period Tmask increases as the capacitance value of the capacitor 177 increases, and decreases as the capacitance value of the capacitor 177 decreases. However, the longer the mask period Tmask, the later the start timing of overcurrent protection using the external set value VthL. Therefore, it is desirable to set the mask period Tmask to the minimum necessary length in consideration of the duration of the instantaneous current at the time of startup.
- the mask period Tmask it is also possible to arbitrarily use whether or not to provide the mask period Tmask according to the use of the semiconductor integrated circuit device 1 (type of load 3). For example, if the external terminal DLY is left open, the mask period Tmask is substantially zero, which is equivalent to the case where only the external set value VthL is provided. For example, if the external terminal DLY is short-circuited to the ground terminal GND, the mask period Tmask becomes infinite, which is equivalent to the case where only the internal set value VthH is provided.
- the comparison signal VCMP becomes low level
- the internal signal Sy becomes low level.
- the threshold control signal S170 is reset to a low level, and the threshold voltage Vth is switched to the internal set value VthH.
- the threshold voltage Vth is switched to the internal set value VthH when the sense voltage Vs falls below the reference voltage VIset. That is, when the overcurrent protection operation using the external set value VthL is canceled, the overcurrent protection circuit 71 is returned to the initial state at the time of startup.
- the output detection voltage V80 (see also the broken line in the figure) corresponding to the detection result of the output current Io is selectively output in the overcurrent non-detection period (other than times t14 to t15). ing.
- the overcurrent detection period time t14 to t15
- a constant voltage V90 corresponding to an abnormality flag is selectively output.
- FIG. 12 is a flowchart showing an example of the threshold value switching operation.
- step S102 it is determined whether or not the sense voltage Vs is higher than the reference voltage VIset. If the determination is yes, the flow proceeds to step S103. On the other hand, if a negative determination is made, the flow returns to step S102, and the determination in this step is repeated (corresponding to times t12 to t13 in FIG. 11).
- step S103 in response to a YES determination in step S102, charging of the capacitor 177 is started (corresponding to time t13 in FIG. 11).
- step S104 it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S105. On the other hand, if a negative determination is made, the flow returns to step S104 and the determination in this step is repeated (corresponding to times t13 to t14 in FIG. 11).
- step S105 the capacitor 177 is discharged in response to a yes determination in step S104.
- FIG. 13 is a schematic diagram illustrating a first usage example of the overcurrent protection circuit 71.
- the load 3 is a bulb lamp, as shown by the solid line in the figure, an instantaneous current larger than that during steady operation flows as the output current Io at the time of startup.
- Tmask mask period
- the instantaneous current can be excluded from the detection target, so that unintended overcurrent protection is not applied.
- the output current Io and the first set value IocpH are compared at the time of start-up where an excessive instantaneous current flows, and the output current Io and the second set value IocpL are compared at the time of steady operation. Therefore, the drive area of the output current Io can be expressed as a hatched area in the drawing.
- FIG. 14 is a schematic diagram showing a second usage example of the overcurrent protection circuit 71.
- the load 3 is a motor, as indicated by a solid line in the figure, an instantaneous current larger than that during steady operation flows as the output current Io at the time of locking.
- Tmask the mask period
- the instantaneous current can be excluded from the detection target, so that unintended overcurrent protection is not applied. That is, the output current Io and the first set value IocpH are compared during lock when an excessive instantaneous current flows, and the output current Io and the second set value IocpL are compared during steady operation. Therefore, the drive area of the output current Io can be expressed as a hatched area in the drawing.
- the overcurrent protection circuit 71 as the overcurrent set value Iocp to be compared with the output current Io, the two-stage first set value IocpH and second set value IocpL are prepared. In addition, a predetermined mask period Tmask is provided as a grace period until switching from the first set value IocpH to the second set value IocL.
- the second set value IocpL which is sufficiently lower than the first set value IocpH, is compared with the output current Io, so that a large current far from the drive current of the load 3 is the output current Io. It will not continue to flow. Therefore, it is possible to make the harness connected to the load 3 thinner than before.
- FIG. 15 is a block diagram showing a second embodiment of the semiconductor integrated circuit device 1.
- the semiconductor integrated circuit device 1 of the present embodiment has been described so far so that the two-channel loads 3X and 3Y can be individually driven while being based on the first embodiment (FIG. 1).
- Elements functional blocks 10 to 90, external terminals T1 to T4, and various voltages, currents, signals, etc. are provided for each channel.
- components related to driving of the load 3X are suffixed with “X”
- components related to driving of the load 3Y are suffixed with “Y”.
- Each operation and function is basically the same as the above-described components not suffixed with “X” and “Y”.
- the operations and functions of the NMOSFETs 10X and 10Y are basically the same as those of the NMOSFET 10 described above. The same applies to other components. Therefore, unless there is a matter to be noted, the description of the operation and function of each component is omitted.
- the output current detection part 80 and the signal output part 90 are not shown clearly, these functional blocks are separately mentioned later.
- the activation timing for each channel may be different. Therefore, in order to achieve both instantaneous current securing and overcurrent protection according to the load in each channel, the above-described mask period Tmask must be set correctly for each channel without depending on the difference in the start timing.
- the simplest configuration for realizing this is to prepare the above-described overcurrent protection circuit 71 (see FIG. 4) for two channels, and each of them as overcurrent protection circuits 71X and 71Y for each channel in parallel. Is to provide. However, in such a configuration, two external terminals DLY for setting the mask period Tmask are required, which may lead to a package change or an increase in cost of the semiconductor integrated circuit device 1.
- an overcurrent protection circuit 71 is proposed in which the mask period Tmask can be set correctly for each channel without requiring the addition of the external terminal DLY.
- FIG. 16 is a block diagram illustrating a configuration example of the overcurrent protection circuit 71 having two channels.
- the overcurrent protection circuit 71 of this configuration example includes a first current generation unit 110, a second current generation unit 120, threshold voltage generation units 130X and 130Y, overcurrent detection units 140X and 140Y, and a reference voltage generation unit 150X. And 150Y, comparison units 160X and 160Y, and a threshold control unit 170.
- the first current generation unit 110, the second current generation unit 120, the threshold voltage generation unit 130X, the overcurrent detection unit 140X, the reference voltage generation unit 150X, the comparison unit 160X, and the threshold control unit 170 are: It functions as an overcurrent detection circuit 71X for the first channel.
- the first current generation unit 110 Functions as an overcurrent detection circuit 71Y for the second channel.
- the first current generation unit 110, the second current generation unit 120, and the threshold control unit 170 are shared by the first channel and the second channel.
- the first current generator 110 generates the first current Iref and outputs it to the threshold voltage generators 130X and 130Y.
- the current value of the first current Iref is fixed inside the semiconductor integrated circuit device 1.
- the configuration of the first current generator 110 is basically the same as that shown in FIG.
- a current mirror having two systems of current output terminals may be used.
- the second current generator 120 generates the second current Iset and outputs it to the threshold voltage generators 130X and 130Y.
- the current value of the second current Iset can be arbitrarily adjusted from the outside of the semiconductor integrated circuit device 1.
- the configuration of the second current generator 120 is basically the same as that shown in FIG.
- a current mirror having two systems of current output terminals may be used.
- the threshold voltage generation unit 130X switches whether the threshold voltage VthX is set to the internal set value VthXH or the external set value VthXL (where VthXH> VthXL) according to the threshold control signal S170X.
- the threshold voltage generation unit 130Y switches whether the threshold voltage VthY is set to the internal setting value VthYH or the external setting value VthYL (however, VthYH> VthYL) according to the threshold control signal S170Y.
- the internal set value VthYH is a fixed value (corresponding to the third set value) set according to the first current Iref.
- the overcurrent detection unit 140X compares the sense voltage VsX corresponding to the output current IoX and the threshold voltage VthX to generate an overcurrent protection signal S71X.
- the overcurrent detection unit 140Y compares the sense voltage VsY corresponding to the output current IoY and the threshold voltage VthY to generate an overcurrent protection signal S71Y.
- the comparison unit 160X compares the sense voltage VsX and the reference voltage VIsetX to generate a comparison signal VCMPX.
- the comparison unit 160Y compares the sense voltage VsY with the reference voltage VIsetY to generate a comparison signal VCMPY.
- the threshold control unit 170 monitors both the comparison signals VCMPX and VCMPY and generates threshold control signals S170X and S170Y.
- the threshold control signal S170X is at a low level when, for example, the internal set value VthXH is to be selected as the threshold voltage VthX, and is at a high level when the external set value VthXL is to be selected as the threshold voltage VthX.
- the threshold control signal S170Y is, for example, low level when the internal set value VthYH is to be selected as the threshold voltage VthY, and is high level when the external set value VthYL is to be selected as the threshold voltage VthY.
- FIG. 17 is a block diagram illustrating a first embodiment of the threshold control unit 170.
- the threshold control unit 170 of the present embodiment is based on the previous FIG. 10, and as means for realizing the two-channel, the comparator 171, the current source 172, the level shifters 173X and 173Y, the RS flip-flops 174X and 174Y, Discharge controller 175, NMOSFET 176, capacitor 177, charge controller 178, and external terminal DLY.
- the internal signal Sx is generated by comparison.
- the internal signal Sx becomes high level when the charging voltage Vd is higher than the mask period expiration voltage Vdref, and becomes low level when the charging voltage Vd is lower than the mask period expiration voltage Vdref. This is the same as FIG. 10 above.
- the current source 172 generates a charging current Id according to the charging control signal S178. Specifically, the current source 172 outputs the charging current Id when the current control signal S178 is at a high level, and stops the charging current Id when the charging control signal S178 is at a low level.
- the level shifter 173X shifts the level of the comparison signal VCMPX to generate the internal signal SyX.
- the level shifter 173Y generates the internal signal SyY by shifting the level of the comparison signal VCMPY.
- the RS flip-flop 174X outputs a threshold control signal S170X from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal SyX input to the reset terminal (R). More specifically, the RS flip-flop 174X sets the threshold control signal S170X to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170X to a low level at the falling timing of the internal signal SyX. .
- the RS flip-flop 174Y outputs a threshold control signal S170Y from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal SyY input to the reset terminal (R). More specifically, the RS flip-flop 174Y sets the threshold control signal S170Y to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170Y to a low level at the falling timing of the internal signal SyY. .
- the discharge controller 175 generates an internal signal Sz in response to the internal signal Sx. More specifically, the discharge controller 175 sets the internal signal Sz to a high level over a predetermined discharge period Tdchg at the rising timing of the internal signal Sx. This is the same as FIG. 10 above.
- the NMOSFET 176 is turned on when the internal signal Sz is at a high level, and turned off when the internal signal Sz is at a low level. This is also the same as in FIG.
- the capacitor 177 is connected between the external terminal DLY and the ground terminal GND outside the semiconductor integrated circuit device 1.
- the charging current Id is supplied from the current source 172 when the NMOSFET 176 is turned off, the charging voltage Vd of the capacitor 177 increases.
- NMOSFET 176 is on, capacitor 177 is discharged through NMOSFET 176, so that charging voltage Vd decreases. This is also the same as in FIG.
- FIG. 18 is a timing chart showing the threshold value switching operation of the first embodiment. From the top, the sense voltages VsX and VsY, the comparison signals VCMPX and VCMPY (equivalent to the internal signals SyX and SyY), the charging voltage Vd, and the internal signal Sx and Sz, threshold control signals S170X and S170Y, and threshold voltages VthX and VthY are depicted, respectively.
- the sense voltage VsX starts to rise.
- the NMOSFET 10Y remains off and the sense voltage VsY is maintained at 0V.
- the NMOSFET 10Y remains off and the sense voltage VsY is maintained at 0V.
- the NMOSFET 10Y is turned on and the sense voltage VsY starts to rise.
- the internal signal Sx becomes high level.
- the internal signal Sx becomes high level
- the internal signal Sz also becomes high level for a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.
- the threshold control signal S170X is reset to a low level, so that the threshold voltage VthX is switched to the internal set value VthXH.
- the threshold voltage VthX when the threshold voltage VthX is set to the external set value VthXL, the threshold voltage VthX is switched to the internal set value VthXH when the sense voltage VsX falls below the reference voltage VsetX.
- the internal signal Sx becomes high level.
- the internal signal Sx becomes high level
- the internal signal Sz also becomes high level for a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.
- the threshold control signal S170Y is reset to a low level, so that the threshold voltage VthY is switched to the internal set value VthYH.
- the threshold voltage VthY is switched to the internal set value VthYH when the sense voltage VsY falls below the reference voltage VsetY.
- the threshold value control unit 170 of the present embodiment does not require the addition of the external terminal DLY, and mask period Tmask (time t22 to t23 and time t25 to t25) for each channel. It becomes possible to set t27) correctly.
- FIG. 19 is a timing chart showing the problems of the first embodiment. From the top, the comparison signals VCMPX and VCMPY, the internal signal Sx, and the threshold control signals S170X and S170Y are behaviors when Tshift ⁇ Tmask. Is depicted.
- the mask period Tmask is shortened by the shift period Tshift, which may hinder the securing of the instantaneous current.
- the 2nd Example of the threshold-value control part 170 which can eliminate this problem is proposed.
- FIG. 20 is a block diagram illustrating a second embodiment of the threshold control unit 170.
- the threshold value controller 170 of this embodiment is based on the first embodiment (FIG. 17), and in the discharge controller 175, not only the internal signal Sx but also the internal signals SyX and SyY (comparison signals VCMPX and VCMPY). Equivalent) and threshold control signals S170X and S170Y are also received. Therefore, hereinafter, the configuration and operation of the discharge control unit 175 will be mainly described.
- FIG. 21 is a block diagram showing a configuration example of the discharge control unit 175.
- the discharge control unit 175 in the figure includes a negative OR operator NOR1, an AND operator AND1 to AND3, an OR operator OR1, an inverter INV1 to INV3, a pulse generator PG1, a resistor R1, and a capacitor. And C1.
- the NOR circuit NOR1 generates a logic signal SA by performing a NOR operation on the threshold control signals S170X and S170Y. Accordingly, the logic signal SA is at a high level when both the threshold control signals S170X and S170Y are at a low level, and is at a low level when at least one of the threshold control signals S170X and S170Y is at a high level.
- the AND operator AND1 generates a logic signal SB by AND operation of the internal signals SyX and SyY. Accordingly, the logic signal SB is at a high level when both the internal signals SyX and SyY are at a high level, and is at a low level when at least one of the internal signals SyX and SyY is at a low level.
- the logical product operator AND2 generates a logical signal SC by a logical product operation of the logical signals SA and SB. Accordingly, the logic signal SC is at a high level when both of the logic signals SA and SB are at a high level, and is at a low level when at least one of the logic signals SA and SB is at a low level.
- the inverter INV1 inverts the logic signal SC to generate an inverted logic signal SCB.
- the AND operator AND3 generates a logic signal SF by the AND operation of the logic signals SC and SE. Therefore, the logic signal SF is at a high level when both the logic signals SC and SE are at a high level, and is at a low level when at least one of the logic signals SC and SE is at a low level.
- the OR operator OR1 generates an internal signal Sz by performing an OR operation of the logic signals SF and SG. Therefore, the internal signal Sz becomes a low level when both of the logic signals SF and SG are at a low level, and becomes a high level when at least one of the logic signals SF and SG is at a high level.
- FIG. 22 is a timing chart showing the threshold value switching operation of the second embodiment. From the top, the comparison signals VCMPX and VCMPY (equivalent to the internal signals SyX and SyY), the logic signals SA to SG, the internal signal Sz, the charging voltage are shown. For Vd, the internal signal Sx, and the threshold control signals S170X and S170Y, the behavior when Tshift ⁇ Tmask is depicted.
- the comparison signal VCMPY rises to the high level at time t42 before the mask period Tmask elapses. That is, at time t42, the charging voltage Vd has not reached the mask period expiration voltage Vdref, and the internal signal Sx has not risen to a high level.
- the logic signal SA is at the high level.
- the comparison signals CMPX and CMPY (and hence the internal signals SyX and SyY) are both at the high level, so that the logic signal SB rises to the high level. Therefore, the logic signal SC rises to a high level, and the logic signal SD starts to decrease with the time constant ⁇ .
- the logic signal SE is maintained at the high level.
- the comparison signals CMPX and CMPY rises to a high level and the charging operation of the capacitor 177 is started, before the charging voltage Vd exceeds the mask period expiration voltage Vdref, the comparison signals CMPX and CMPY When the other rises to a high level, the capacitor 177 is discharged once, so that the timing operation of the mask period Tmask is reset.
- the logic signal SE falls to a low level.
- the logic signal SF falls to the low level, and eventually the internal signal Sz falls to the low level, so that the discharging operation is stopped and the charging voltage Vd starts to rise again.
- the discharge period Tdchg2 can be arbitrarily set according to the time constant ⁇ of the resistor R1 and the capacitor C1, and may be set to the same value (for example, 3 ⁇ s) as the above-described discharge period Tdchg.
- the internal signal Sx rises to a high level.
- the threshold control signals S170X and S170Y are simultaneously at the high level.
- the logic signal SA falls to a low level
- the logic signal SC falls to a low level.
- the logic signal SD starts to rise with a time constant ⁇ , and when the logic signal SD exceeds the logic inversion threshold of the inverter INV2, the logic signal SE rises to a high level.
- the logic signal SC is already at the low level, the logic signal SF is maintained at the low level.
- the threshold control unit 170 of the present embodiment even if Tshift ⁇ Tmask, the masking period of the subsequent channel is not shortened, so that there is no possibility of hindering the securing of the instantaneous current.
- the threshold control signals S170X and S170Y are At the same time, it becomes high level. As a result, the masking period of the subsequent channel becomes zero, so that an instantaneous current cannot be secured.
- the 3rd Example of the threshold-value control part 170 which can eliminate this problem is proposed.
- FIG. 24 is a block diagram showing a third embodiment of the threshold control unit 170.
- the threshold control unit 170 of the present embodiment is characterized in that delay units 179X and 179Y are provided while being based on the second embodiment (FIG. 20). Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 20, and redundant descriptions are omitted. In the following, the delay units 179X and 179Y are mainly described.
- the delay unit 179X delays the internal signal SyX (equivalent to the comparison signal VCMPX) to generate a delay signal SyXd. Note that the delay unit 179X delays only the rising timing of the delay signal SyXd, and does not delay the falling timing of the delay signal SyXd. More specifically, the delay signal SyXd rises to a high level after a delay time td (eg, 3 ⁇ s) after the internal signal SyX rises to a high level, and at the same time the internal signal SyX falls to a low level. To fall.
- a delay time td eg, 3 ⁇ s
- the delay unit 179Y delays the internal signal SyY (equivalent to the comparison signal VCMPY) to generate a delay signal SyYd. Note that the delay unit 179Y delays only the rising timing of the delay signal SyYd, and does not delay the falling timing of the delay signal SyYd. More specifically, the delay signal SyYd rises to a high level after a delay time td after the internal signal SyY rises to a high level, and falls to a low level at the same time that the internal signal SyY falls to a low level.
- delayed signals SyXd and SyYd are input to the RS flip-flops 174X and 174Y in place of the internal signals SyX and SyY, respectively.
- FIG. 25 is a timing chart showing the threshold value switching operation of the third embodiment.
- the comparison signal VCMPX equivalent to the internal signal SyX
- the delay signal SyXd the comparison signal VCMPY (equivalent to the internal signal SyY)
- the threshold control signal S170X is set to a high level at time t62.
- the internal signal Sx rises to a high level
- the internal signal Sz becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.
- the discharging operation is stopped and the charging voltage Vd starts to rise again.
- the threshold control signal S170Y is set to a high level at time t64.
- the internal signal Sx rises to a high level
- the internal signal Sz becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.
- the above discharge operation is stopped. Note that the charging operation for two channels is completed at this point, and therefore the charging voltage Vd does not start to rise again.
- the delay signal SyXd also falls to the low level without delay.
- the threshold control signal S170X is reset to a low level.
- the threshold control unit 170 generates the threshold control signals S170X and S170Y using the internal signal Sx and the delay signals SyXd and SyYd. Therefore, when Tshift ⁇ Tmask, the charging voltage Vd is always discharged at the rising timing of the comparison signals VCMPX and VCMPY before the delay signals SyXd and SyYd rise to the high level.
- the threshold control signals S170X and S170Y do not become high at the same time, so that the mask period Tmask can be set correctly for each channel.
- FIG. 26 is a flowchart showing an example of the threshold switching operation with two channels.
- the threshold voltage Vth * of the activated channel is set to the internal set value Vth * H (where “*” is at least one of “X” and “Y”, and so on). (Corresponding to times t21 and t23 in FIG. 18).
- step S202 it is determined whether one of the comparison signals VCMPX and VCMPY is at a high level (that is, whether only one of the channels is activated). If the determination is yes, the flow proceeds to step S203 (corresponding to time t22 in FIG. 18). On the other hand, if a negative determination is made, the flow proceeds to step S208.
- step S203 in response to a yes determination in step S202, charging of the capacitor 177 is started (corresponding to time t22 in FIG. 18).
- step S204 it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S205 (corresponding to time t24 in FIG. 18). On the other hand, if a negative determination is made, the flow returns to step S204, and the determination in this step is repeated (corresponding to times t22 to t24 in FIG. 18).
- step S205 the capacitor 177 is discharged in response to a yes determination in step S204.
- step S206 the threshold voltage Vth * of the activated channel is switched to the external set value Vth * L.
- step S207 it is determined whether or not the sense voltage Vs * of the activated channel is lower than the reference voltage VIset *. If the determination is yes, the flow returns to step S201, and the threshold voltage Vth * is switched to the internal set value Vth * H again (corresponding to time t26 in FIG. 18). On the other hand, if a negative determination is made, the flow returns to step S207 and the determination in this step is repeated (corresponding to times t24 to t26 in FIG. 18).
- step S208 it is determined whether or not both comparison signals VCMPX and VCMPY are at a high level in response to a negative determination in step S202 (that is, whether both channels are activated). A determination is made. If the determination is yes, the flow proceeds to step S209 (corresponding to time t23 in FIG. 18, time t42 in FIG. 22, or time t62 in FIG. 25). On the other hand, if no determination is made, since no channel is activated, the flow returns to step S201.
- step S209 in response to a YES determination in step S208, whether or not one of the threshold control signals S170X and S170Y is at a high level (that is, the threshold voltage Vth * of the previous channel has already been switched to the external set value Vth * L). Is determined). If the determination is yes, the flow proceeds to step S203, and the threshold value switching operation for the subsequent channel is performed in steps S203 to S207 (corresponding to times t25 to t28 in FIG. 18). On the other hand, if a negative determination is made, the flow proceeds to step S210.
- step S210 in response to the no determination in step S209, whether or not the threshold control signals S170X and S170Y are both at the low level (that is, the start timing of the subsequent channel is set before the mask period Tmask of the previous channel elapses). A determination is made as to whether or not it has arrived. If the determination is yes, the flow proceeds to step S211 (corresponding to time t42 in FIG. 22). On the other hand, if a negative determination is made, the flow proceeds to step S214.
- step S211 in response to a YES determination in step S210, the capacitor 177 is once discharged, and then recharging is started (corresponding to times t42 to t43 in FIG. 22).
- step S212 it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S213 (corresponding to time t44 in FIG. 22). On the other hand, if a negative determination is made, the flow returns to step S212, and the determination in this step is repeated (corresponding to times t43 to t44 in FIG. 22).
- step S213 the capacitor 177 is discharged in response to a yes determination in step S212.
- step S214 the threshold voltages VthX and VthYL of both channels are simultaneously switched to the external setting values VthXL and VthYL.
- step S215 it is determined whether or not the sense voltages VsX and VsY of both channels are lower than the reference voltages VIsetX and VIsetY.
- the flow returns to step S201 to enter a state of waiting for the next activation.
- the flow is returned to step S215, and the determination in this step is repeated.
- FIG. 27 is a block diagram showing an example in which a multiplexer is introduced as the output stage of the status notification signal So in accordance with the two-channel semiconductor integrated circuit device 1 described so far.
- output current detection units 80X and 80Y, signal output units 90X and 90Y, a multiplexer 100, and an external terminal T5 are integrated.
- the output current detection unit 80X generates a sense current IsX ′ corresponding to the output current IoX and outputs it to the signal output unit 90X.
- the output current detection unit 80Y generates a sense current IsY ′ corresponding to the output current IoY and outputs it to the signal output unit 90Y.
- the selector 91X selectively outputs the sense current IsX ′ as the first state notification signal SoX when the output selection signal S2X is at the logic level (eg, low level) when no abnormality is detected, and the output selection signal S2X is abnormal.
- the logic level at the time of detection for example, high level
- the fixed voltage V90 is output as the first state notification signal SoX.
- the selector 91Y selectively outputs the sense current IsY ′ as the second state notification signal SoY when the output selection signal S2Y is at the logic level (eg, low level) when no abnormality is detected, and the output selection signal S2Y is abnormal.
- the fixed voltage V90 is output as the second state notification signal SoY.
- the output detection voltage V80X increases as the output current IoX increases, and decreases as the output current IoX decreases.
- the output detection voltage V80Y increases as the output current IoY increases, and decreases as the output current IoY decreases.
- the fixed voltage V90 when the fixed voltage V90 is selectively output to the external terminal T4, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So.
- the fixed voltage V90 may be set to a voltage value higher than the upper limit values of the output detection voltages V80X and V80Y.
- FIG. 28 is an external view showing a configuration example of a vehicle.
- the vehicle X of this configuration example includes a battery (not shown in the figure) and various electronic devices X11 to X18 that operate by receiving power supply from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from actual ones for convenience of illustration.
- the electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, etc.).
- the electronic device X12 is a lamp control unit that controls turning on and off such as HID [high intensity discharged lamp] and DRL [daytime running lamp].
- the electronic device X13 is a transmission control unit that performs control related to the transmission.
- the electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the movement of the vehicle X.
- control ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.
- the electronic device X15 is a security control unit that performs drive control such as door locks and security alarms.
- the electronic device X16 is an electronic device that is built into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.
- the electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product, such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].
- a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].
- the electronic device X18 is an electronic device equipped with a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.
- a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.
- the semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.
- the invention disclosed in this specification can be used for in-vehicle IPD.
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Abstract
Description
図1は、半導体集積回路装置の第1実施形態を示すブロック図である。本実施形態の半導体集積回路装置1は、ECU[electronic control unit]2からの指示に応じて電源電圧VBBの印加端と負荷3との間を導通/遮断する車載用ハイサイドスイッチIC(=車載IPDの一種)である。
図2は、信号出力部90の一構成例を示すブロック図である。本構成例の信号出力部90はセレクタ91を含む。セレクタ91は、出力選択信号S2が異常未検出時の論理レベル(例えばローレベル)であるときに、センス電流Is’を外部端子T4に選択出力し、出力選択信号S2が異常検出時の論理レベル(例えばハイレベル)であるときに、固定電圧V90を外部端子T4に選択出力する。なお、固定電圧V90は、先述した出力検出電圧V80の上限値よりも高い電圧値に設定されている。
図3は、ゲート制御部30の一構成例を示すブロック図である。本構成例のゲート制御部30は、ゲートドライバ31と、オシレータ32と、チャージポンプ33と、クランパ34と、NMOSFET35と、を含む。
図4は、過電流保護回路71の一構成例を示すブロック図である。本構成例の過電流保護回路71は、第1電流生成部110と、第2電流生成部120と、閾値電圧生成部130と、過電流検出部140と、参照電圧生成部150と、比較部160と、閾値制御部170と、を含む。
図5は、第1電流生成部110の一構成例を示す回路図である。本構成例の第1電流生成部110は、オペアンプ111と、NMOSFET112と、抵抗113(抵抗値:R113)と、を含む。
図6は、第2電流生成部120の一構成例を示す回路図である。本構成例の第2電流生成部120は、オペアンプ121と、NMOSFET122と、抵抗123(抵抗値:R123)と、外部端子SETと、を含む。
図7は、閾値電圧生成部130と過電流検出部140の一構成例を示す回路図である。閾値電圧生成部130は、電流源131と、抵抗132と、カレントミラー133と、を含む。一方、過電流検出部140は、コンパレータ141を含む。
図9は、参照電圧生成部150と比較部160の一構成例を示す回路図である。参照電圧生成部150は、電流源151と抵抗152(抵抗値:R152)を含む。また、比較部160は、コンパレータ161を含む。
図10は、閾値制御部170の一構成例を示す回路図である。閾値制御部170は、コンパレータ171と、電流源172と、レベルシフタ173と、RSフリップフロップ174と、放電制御部175と、NMOSFET176と、キャパシタ177と、外部端子DLYと、を含む。
図11は、過電流保護動作の一例を示すタイミングチャートであり、上から順に、外部制御信号Si、第1電流Iref、第2電流Iset、センス電圧Vs、比較信号VCMP、充電電圧Vd、内部信号Sx~Sz、閾値制御信号S170、閾値電圧Vth、並びに、状態報知信号Soが描写されている。
図13は、過電流保護回路71の第1使用例を示す模式図である。例えば、負荷3がバルブランプである場合には、本図中の実線で示したように、起動時の出力電流Ioとして定常動作時よりも大きい瞬時電流が流れる。ただし、先述のマスク期間Tmaskを適切に設定しておけば、上記の瞬時電流を検出対象から除外することができるので、意図しない過電流保護が掛かることはない。すなわち、過大な瞬時電流が流れる起動時には、出力電流Ioと第1設定値IocpHとが比較されることになり、定常動作時には出力電流Ioと第2設定値IocpLとが比較されることになる。従って、出力電流Ioの駆動エリアは、本図中のハッチングを付した領域として表すことができる。
これまでに説明してきたように、過電流保護回路71では、出力電流Ioと比較される過電流設定値Iocpとして、2段階の第1設定値IocpHと第2設定値IocpLが用意されており、かつ、第1設定値IocpHから第2設定値IocpLに切り替えるまでの猶予期間として、所定のマスク期間Tmaskが設けられている。
図15は、半導体集積回路装置1の第2実施形態を示すブロック図である。本実施形態の半導体集積回路装置1は、第1実施形態(図1)をベースとしつつ、2チャンネルの負荷3X及び3Yをそれぞれ個別に駆動することができるように、これまでに説明してきた構成要素(機能ブロック10~90、外部端子T1~T4、及び、各種の電圧、電流、信号など)をチャンネル毎に有している。
図17は、閾値制御部170の第1実施例を示すブロック図である。本実施例の閾値制御部170は、先の図10をベースとしつつ、2チャンネル化を実現する手段として、コンパレータ171と、電流源172と、レベルシフタ173X及び173Yと、RSフリップフロップ174X及び174Yと、放電制御部175と、NMOSFET176と、キャパシタ177と、充電制御部178と、外部端子DLYと、を含む。
図20は、閾値制御部170の第2実施例を示すブロック図である。本実施例の閾値制御部170は、先出の第1実施例(図17)をベースとしつつ、放電制御部175において、内部信号Sxだけでなく、内部信号SyX及びSyY(比較信号VCMPX及びVCMPYと等価)と閾値制御信号S170X及びS170Yの入力も受け付ける点に特徴を有する。そこで、以下では、放電制御部175の構成と動作について重点的に説明する。
図24は、閾値制御部170の第3実施例を示すブロック図である。本実施例の閾値制御部170は、先出の第2実施例(図20)をベースとしつつ、遅延部179X及び179Yが設けられている点に特徴を有する。そこで、第2実施例と同様の構成要素については、図20と同一の符号を付すことにより重複した説明を割愛し、以下では、遅延部179X及び179Yについて重点的な説明を行う。
図26は、2チャンネル化された閾値切替動作の一例を示すフローチャートである。フローが開始されると、まず、ステップS201では、起動しているチャンネルの閾値電圧Vth*が内部設定値Vth*H(ただし「*」は「X」及び「Y」の少なくとも一方、以下も同様)に設定される(図18の時刻t21及びt23に相当)。
図27は、これまでに説明してきた半導体集積回路装置1の2チャンネル化に伴い、状態報知信号Soの出力段として、マルチプレクサを導入した例を示すブロック図である。本構成例の半導体集積回路装置1には、出力電流検出部80X及び80Yと、信号出力部90X及び90Yと、マルチプレクサ100と、外部端子T5と、が集積化されている。
図28は、車両の一構成例を示す外観図である。本構成例の車両Xは、バッテリ(本図では不図示)と、バッテリから電力供給を受けて動作する種々の電子機器X11~X18とを搭載している。なお、本図における電子機器X11~X18の搭載位置については、図示の便宜上、実際とは異なる場合がある。
また、上記の実施形態では、車載用ハイサイドスイッチICを例に挙げて説明を行ったが、本明細書中に開示されている発明の適用対象は、これに限定されるものではなく、例えば、その他の車載用IPD(車載用ローサイドスイッチICや車載用電源ICなど)はもちろん、車載用途以外の半導体集積回路装置にも広く適用することが可能である。
2 ECU
3、3X、3Y 負荷
4 外部センス抵抗
10、10X、10Y NMOSFET
20、20X、20Y 出力電流監視部
21、21’ NMOSFET
22 センス抵抗
30、30X、30Y ゲート制御部
31 ゲートドライバ
32 オシレータ
33 チャージポンプ
34 クランパ
35 NMOSFET
40、40X、40Y 制御ロジック部
50、50X、50Y 信号入力部
60、60X、60Y 内部電源部
70、70X、70Y 異常保護部
71、71X、71Y 過電流保護回路
72 オープン保護回路
73 温度保護回路
74 減電圧保護回路
80、80X、80Y 出力電流検出部
90、90X、90Y 信号出力部
91、91X、91Y セレクタ
100 マルチプレクサ
110 第1電流生成部
111 オペアンプ
112 NMOSFET
113 抵抗
120 第2電流生成部
121 オペアンプ
122 NMOSFET
123 抵抗
130、130X、130Y 閾値電圧生成部
131 電流源
132 抵抗
133 カレントミラー
140、140X、140Y 過電流検出部
141 コンパレータ
150、150X、150Y 参照電圧生成部
151 電流源
152 抵抗
160、160X、160Y 比較部
161 コンパレータ
170 閾値制御部
171 コンパレータ
172 電流源
173、173X、173Y レベルシフタ
174、174X、174Y RSフリップフロップ
175 放電制御部
176 NMOSFET
177 キャパシタ
178 充電制御部
179X、179Y 遅延部
NOR1 否定論理和演算器
AND1~AND3 論理積演算器
OR1 論理和演算器
INV1~INV3 インバータ
PG1 パルス生成部
R1 抵抗
C1 キャパシタ
T1~T5、SET、DLY 外部端子
X 車両
X11~X18 電子機器
Claims (20)
- 閾値制御信号に応じて過電流検出閾値を第1設定値とするか前記第1設定値よりも低い第2設定値とするかを切り替える閾値生成部と、
監視対象電流に応じたセンス信号と前記過電流検出閾値とを比較して過電流保護信号を生成する過電流検出部と、
前記第2設定値に応じた参照値を生成する参照値生成部と、
前記センス信号と前記参照値とを比較して比較信号を生成する比較部と、
前記比較信号を監視して前記閾値制御信号を生成する閾値制御部と、
を有することを特徴とする過電流保護回路。 - 前記閾値制御部は、前記過電流検出閾値が前記第1設定値とされているときに前記センス信号が前記参照値を上回ったままマスク期間が経過した時点で前記過電流検出閾値を前記第2設定値に切り替えるように前記閾値制御信号を生成することを特徴とする請求項1に記載の過電流保護回路。
- 前記閾値制御部は、前記過電流検出閾値が前記第2設定値とされているときに前記センス信号が前記参照値を下回った時点で前記過電流検出閾値を前記第1設定値に切り替えるように前記閾値制御信号を生成することを特徴とする請求項2に記載の過電流保護回路。
- 前記マスク期間は可変値であることを特徴とする請求項2または請求項3に記載の過電流保護回路。
- 前記第1設定値は固定値であり、前記第2設定値は可変値であることを特徴とする請求項1~請求項4のいずれか一項に記載の過電流保護回路。
- 出力電流の流れる電流経路を導通/遮断するパワートランジスタと、
前記出力電流に応じたセンス信号を生成する出力電流監視部と、
制御信号に応じて前記パワートランジスタの駆動信号を生成するゲート制御部と、
前記センス信号を監視して過電流保護信号を生成する請求項1~請求項5のいずれか一項に記載の過電流保護回路と、
を集積化して成り、
前記ゲート制御部は、前記過電流保護信号に応じて前記パワートランジスタを強制的にオフさせる機能を備えていることを特徴とする半導体集積回路装置。 - 前記出力電流の検出結果と異常フラグの一方を状態報知信号として装置外部に選択出力する信号出力部をさらに集積化して成ることを特徴とする請求項6に記載の半導体集積回路装置。
- 請求項6または請求項7に記載の半導体集積回路装置と、
前記半導体集積回路装置に接続される負荷と、
を有することを特徴とする電子機器。 - 前記負荷は、バルブランプ、リレーコイル、ソレノイド、発光ダイオード、または、モータであることを特徴とする請求項8に記載の電子機器。
- 請求項8または請求項9に記載の電子機器を有することを特徴とする車両。
- 第1閾値制御信号に応じて第1過電流検出閾値を第1設定値とするか前記第1設定値よりも低い第2設定値とするかを切り替える第1閾値生成部と、
第2閾値制御信号に応じて第2過電流検出閾値を第3設定値とするか前記第3設定値よりも低い第4設定値とするかを切り替える第2閾値生成部と、
第1監視対象電流に応じた第1センス信号と前記第1過電流検出閾値とを比較して第1過電流保護信号を生成する第1過電流検出部と、
第2監視対象電流に応じた第2センス信号と前記第2過電流検出閾値とを比較して第2過電流保護信号を生成する第2過電流検出部と、
前記第2設定値に応じた第1参照値を生成する第1参照値生成部と、
前記第4設定値に応じた第2参照値を生成する第2参照値生成部と、
前記第1センス信号と前記第1参照値を比べて第1比較信号を生成する第1比較部と、
前記第2センス信号と前記第2参照値を比べて第2比較信号を生成する第2比較部と、
前記第1比較信号と前記第2比較信号の双方を監視して前記第1閾値制御信号及び前記第2閾値制御信号を生成する閾値制御部と、
を有することを特徴とする過電流保護回路。 - 前記閾値制御部は、
キャパシタを外付けするための外部端子と、
前記外部端子に現れる充電電圧と所定の基準電圧とを比較して内部信号を生成するコンパレータと、
前記内部信号と前記第1比較信号に応じて前記第1閾値制御信号を生成する第1フリップフロップと、
前記内部信号と前記第2比較信号に応じて前記第2閾値制御信号を生成する第2フリップフロップと、
前記内部信号に応じて前記キャパシタの放電制御を行う放電制御部と、
前記第1比較信号と前記第2比較信号の双方に応じて前記キャパシタの充電制御を行う充電制御部と、
を含むことを特徴とする請求項11に記載の過電流保護回路。 - 前記放電制御部は、前記内部信号だけでなく、前記第1比較信号、前記第2比較信号、前記第1閾値制御信号、及び、前記第2閾値制御信号の入力を受け付けており、前記第1比較信号及び前記第2比較信号の一方に論理レベル変化が生じて前記キャパシタの充電動作が開始された後、前記充電電圧が前記基準電圧を上回るよりも先に、前記第1比較信号及び前記第2比較信号の他方に論理レベル変化が生じたときには、前記キャパシタを一旦放電することを特徴とする請求項12に記載の過電流保護回路。
- 前記閾値制御部は、
前記第1比較信号に遅延を与えて第1遅延信号を生成する第1遅延部と、
前記第2比較信号に遅延を与えて第2遅延信号を生成する第2遅延部と、
をさらに含み、
前記第1フリップフロップ及び前記第2フリップフロップには、それぞれ、前記第1比較信号及び前記第2比較信号に代えて、前記第1遅延信号及び前記第2遅延信号が入力されていることを特徴とする請求項13に記載の過電流保護回路。 - 前記第1設定値と前記第3設定値はいずれも固定値であり、前記第2設定値と前記第4設定値はいずれも可変値であることを特徴とする請求項11~請求項14のいずれか一項に記載の過電流保護回路。
- 第1出力電流の流れる第1電流経路を導通/遮断する第1パワートランジスタと、
第2出力電流の流れる第2電流経路を導通/遮断する第2パワートランジスタと、
前記第1出力電流に応じた第1センス信号を生成する第1出力電流監視部と、
前記第2出力電流に応じた第2センス信号を生成する第2出力電流監視部と、
第1制御信号に応じて前記第1パワートランジスタの第1駆動信号を生成する第1ゲート制御部と、
第2制御信号に応じて前記第2パワートランジスタの第2駆動信号を生成する第2ゲート制御部と、
前記第1センス信号と前記第2センス信号を監視して第1過電流保護信号と第2過電流保護信号を生成する請求項11~請求項15のいずれか一項に記載の過電流保護回路と、
を集積化して成り、
前記第1ゲート制御部と前記第2ゲート制御部は、それぞれ前記第1過電流保護信号及び前記第2過電流保護信号に応じて前記第1パワートランジスタ及び前記第2パワートランジスタを強制的にオフさせる機能を備えていることを特徴とする半導体集積回路装置。 - 前記第1出力電流の検出結果と異常フラグの一方を第1状態報知信号として生成する第1信号出力部と、
前記第2出力電流の検出結果と異常フラグの一方を第2状態報知信号として生成する第2信号出力部と、
前記第1状態報知信号と前記第2状態報知信号の一方を装置外部に選択出力するマルチプレクサと、
をさらに集積化して成ることを特徴とする請求項16に記載の半導体集積回路装置。 - 請求項16または請求項17に記載の半導体集積回路装置と、
第1パワートランジスタに接続される第1負荷と、
第2パワートランジスタに接続される第2負荷と、
を有することを特徴とする電子機器。 - 前記第1負荷及び前記第2負荷は、バルブランプ、リレーコイル、ソレノイド、発光ダイオード、または、モータであることを特徴とする請求項18に記載の電子機器。
- 請求項18または請求項19に記載の電子機器を有することを特徴とする車両。
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US17/007,662 US11183829B2 (en) | 2016-04-28 | 2020-08-31 | Overcurrent protection circuit |
US17/503,907 US11637420B2 (en) | 2016-04-28 | 2021-10-18 | Overcurrent protection circuit |
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