WO2017185877A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

Info

Publication number
WO2017185877A1
WO2017185877A1 PCT/CN2017/075596 CN2017075596W WO2017185877A1 WO 2017185877 A1 WO2017185877 A1 WO 2017185877A1 CN 2017075596 W CN2017075596 W CN 2017075596W WO 2017185877 A1 WO2017185877 A1 WO 2017185877A1
Authority
WO
WIPO (PCT)
Prior art keywords
photoresist
passivation layer
region
height
array substrate
Prior art date
Application number
PCT/CN2017/075596
Other languages
English (en)
French (fr)
Inventor
刘玉东
刘荣铖
万云海
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/567,786 priority Critical patent/US10332807B2/en
Publication of WO2017185877A1 publication Critical patent/WO2017185877A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same.
  • Liquid crystal display is a widely used display device.
  • the liquid crystal display mainly includes an array substrate (Array Substrate), an opposite substrate (Opposed Substrate), and a liquid crystal layer (LC) interposed therebetween.
  • a thin film transistor (TFT) is disposed in the array substrate.
  • the liquid crystal display can realize driving control of the liquid crystal layer by an electric field generated between the pixel electrode and the common electrode connected to the thin film transistor, thereby realizing image display.
  • Embodiments of the present invention provide an array substrate and a method of fabricating the same, which can realize etching vias and planarizing a passivation layer without increasing the number of masks, thereby not significantly increasing the cost.
  • the passivation layer is made flater under the premise, and various risks due to uneven height of the array substrate are reduced.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a passivation layer on a substrate; forming a photoresist on the passivation layer, and forming a photolithography by exposure and development processes a first photoresist pattern of the glue completely reserved region, the photoresist portion remaining region, and the photoresist completely removed region; the passivation layer is etched by using the first photoresist pattern as a mask to Forming a first via in the passivation layer; ashing the first photoresist pattern to remove the photoresist of the photoresist portion remaining region and thinning the photoresist completely reserved region Determining a photoresist to form a second photoresist pattern; and etching the passivation layer with the second photoresist pattern as a mask to thin the blunt portion of the photoresist portion remaining region
  • the photoresist completely removed region of the first photoresist pattern corresponds to a region of the passivation
  • the passivation layer includes a region having a first height and has a height according to a height from the base substrate to an upper surface of the passivation layer. a region of a second height, the first height being greater than the second height, the first photoresist pattern The photoresist portion remaining region corresponds to a region having the first height, and the photoresist completely reserved region of the first photoresist pattern corresponds to a region having the second height.
  • the passivation layer of the photoresist portion remaining region is thinned such that the passivation layer has a region of the first height.
  • the upper surface is the same height as the upper surface of the region of the passivation layer having the second height.
  • the method for fabricating an array substrate according to at least one embodiment of the present invention further includes: determining, according to a height difference between the first height and the second height, an area of the passivation layer having the first height to be thinned Thinning thickness.
  • the thinned thickness is less than the thickness of the passivation layer.
  • the method for fabricating an array substrate provided by at least one embodiment of the present invention further includes: calculating an etching rate and an etching time required for etching the passivation layer having the thinned thickness according to the thinned thickness. .
  • the photoresist is exposed and developed by using a gray tone mask or a halftone mask as a mask to form the photoresist. a first photoresist pattern of the remaining region, the photoresist portion remaining region, and the photoresist completely removed region.
  • the all-transmission region of the gray tone mask or the halftone mask corresponds to the photoresist of the first photoresist pattern. Removing a region, the semi-transmissive region of the gray tone mask or the halftone mask corresponding to the photoresist portion remaining region of the first photoresist pattern, the gray tone mask or the halftone mask
  • the opaque region corresponds to the photoresist completely reserved region of the first photoresist.
  • the method before forming the passivation layer, the method further includes: forming a thin film transistor, wherein the region of the passivation layer having the first height corresponds to forming The area of the thin film transistor.
  • the method for fabricating an array substrate according to at least one embodiment of the present invention further includes: forming a first electrode on the passivation layer, wherein the first electrode is formed on the passivation layer at least Two height areas.
  • the passivation layer of the photoresist portion remaining region is thinned such that the passivation layer has a region of the first height.
  • the upper surface is the same height as the upper surface of the first electrode.
  • the method for fabricating an array substrate according to at least one embodiment of the present invention further includes: forming an insulating layer on the first electrode; and forming a second electrode on the insulating layer.
  • the passivation layer of the photoresist portion remaining region is thinned to have a height of the upper surface and a completely reserved region of the photoresist.
  • the difference in height of the upper surface of the passivation layer is equal to the sum of the thicknesses of the first electrode and the second electrode.
  • At least one embodiment of the present invention also provides an array substrate fabricated using the method of fabricating the array substrate as described above.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of forming a passivation layer on a substrate according to an embodiment of the invention
  • FIG. 3 is a schematic diagram of forming a photoresist on a passivation layer according to an embodiment of the invention
  • FIG. 4 is a schematic diagram of exposing and developing a photoresist to form a first photoresist pattern according to an embodiment of the invention
  • FIG. 5 is a schematic structural diagram of an array substrate formed with a first photoresist pattern according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of forming a first via hole according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of an array substrate formed with a second photoresist pattern according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an etch passivation layer according to an embodiment of the invention.
  • FIG. 9 is a schematic structural diagram of another array substrate formed with a second photoresist pattern according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of an array substrate formed with a first electrode according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of an array substrate formed with a second electrode according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of another array substrate formed with a second electrode according to an embodiment of the present invention. Schematic;
  • FIG. 13 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • the layer has a first height H 1 region; the 1092-passivation layer has a second height H 2 region; 1101 - first via; 1102 - second via; 111 - first electrode; 112 - second electrode / common electrode; 113 - insulating layer; 114 - common electrode line; 150 - halftone mask / dual tone mask; 180 - thin film transistor.
  • the array substrate is an important component in a liquid crystal display, and generally includes a gate layer, a gate insulating layer, an active layer, a source/drain electrode layer, a passivation layer, an electrode layer, and the like.
  • the inventors of the present application found that the film layers stacked on different regions on the array substrate are not the same, so there are different heights on the array substrate, so that the array substrate is in an uneven state, thereby affecting the efficiency of the liquid crystal and even Poor black distribution may occur.
  • the thickness of the passivation layer can be increased to cover the unevenness of the array substrate.
  • the thickness of the passivation layer not only causes problems such as an increase in cost, but also increases the thickness of the array substrate, which is disadvantageous for the thinness of the liquid crystal display. Chemical. After research, the inventor of this application believes that it does not increase By adding the thickness of the passivation layer and the number of masks, by implementing the etch via and planarizing the passivation layer, the array substrate can be made flater without significantly increasing the cost, thereby reducing the uneven height of the array substrate. Various bad.
  • Embodiments of the present invention provide an array substrate and a method of fabricating the same.
  • the method for fabricating the array substrate comprises: forming a passivation layer on the base substrate; forming a photoresist on the passivation layer and forming a photoresist completely reserved region, a photoresist portion remaining region, and light by an exposure and development process
  • the first photoresist pattern of the region is completely removed; the passivation layer is etched with the first photoresist pattern as a mask to form a first via in the passivation layer; the first photoresist pattern is ashed Removing the photoresist in the remaining portion of the photoresist and thinning the photoresist in the completely remaining region of the photoresist to form a second photoresist pattern; and using the second photoresist pattern as a mask to perform the passivation layer Etching to thin the passivation layer of the remaining portion of the photoresist.
  • the height difference of different regions of the passivation layer can be reduced, and the degree of planarization can be increased.
  • the number of times the mask is used can be reduced, and the cost can be reduced.
  • This embodiment provides a method for fabricating an array substrate, as shown in FIG. 1 , which includes the following steps 110-150.
  • Step 110 As shown in FIG. 2, a base substrate 101 is provided, and a passivation layer 109 is formed on the base substrate 101.
  • the base substrate 101 may be a glass substrate, a quartz substrate, a resin substrate or other substrate;
  • the material of the passivation layer 102 may be inorganic insulation such as silicon nitride (SiNx), silicon oxide (SiOX) or silicon oxynitride (SiNxOy).
  • Material or organic insulating material such as polyimide.
  • the thickness of the passivation layer 109 can be any suitable thickness.
  • the thickness of the passivation layer 109 can be any suitable thickness.
  • the passivation layer 109 may be formed on the base substrate 101 by an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process, or the like.
  • Step 120 As shown in FIG. 5, a photoresist 1070 is formed on the passivation layer 109, and a photoresist-retained region 1071, a photoresist portion-retained region 1072, and a photoresist are completely removed by an exposure and development process.
  • the thickness of the photoresist 1070 can be
  • a photoresist 1070 is first formed on the passivation layer 109, and then the photoresist 1070 is exposed by using the gray tone mask 150 or the halftone mask 150 as a mask. Development is performed to form a first photoresist pattern 107 having a photoresist completely remaining region 1071, a photoresist portion remaining region 1072, and a photoresist completely removed region 1073.
  • the all-transmission region 1503 of the gray tone mask 150 or the halftone mask 150 may correspond to the photoresist completely removed region 1073 of the first photoresist pattern 107, the gray tone mask 150 or a half.
  • the semi-transmissive region 1502 of the tone mask 150 corresponds to the photoresist portion remaining region 1072 of the first photoresist pattern 107, and the opaque region 1501 of the gray tone mask 150 or the halftone mask 150 corresponds to the first photoresist.
  • the photoresist of 107 completely retains the area 1071.
  • the positive photoresist is taken as an example here, but the embodiment includes but is not limited thereto.
  • Step 130 As shown in FIG. 6, the passivation layer 109 is etched using the first photoresist pattern 107 as a mask to form a first via 1101 in the passivation layer 109.
  • Step 140 As shown in FIG. 7, the first photoresist pattern 107 is ashed to remove the photoresist 1070 of the photoresist portion remaining region 1072 and the photoresist 1070 of the photoresist completely remaining region 1071 is thinned to form a first Two photoresist patterns 108.
  • Step 150 As shown in FIG. 8, the passivation layer 109 is etched with the second photoresist pattern 108 as a mask to thin the passivation layer 109 of the photoresist portion remaining region 1072.
  • the method of fabricating the array substrate by reducing the passivation layer 109 of the photoresist portion remaining region 1072, the height difference of different regions of the passivation layer 109 can be reduced, and the surface of the passivation layer 109 can be improved.
  • various defects such as low liquid crystal efficiency and uneven distribution of black states due to unevenness of the array substrate are reduced.
  • the method for fabricating the array substrate provided in this embodiment forms a first photoresist including a photoresist completely remaining region 1071, a photoresist portion remaining region 1072, and a photoresist completely removed region 1073 on the passivation layer 109.
  • the pattern 107 can form the first via 1101 and the thinned portion of the passivation layer 109 in one mask process, thereby reducing the number of times the mask is used and reducing the cost.
  • the manufacturing method further includes: removing the second photoresist pattern.
  • the photoresist completely removed region 1073 of the first photoresist pattern 107 corresponds to the first via hole to be formed on the passivation layer 109.
  • the photoresist portion remaining region 1072 of the first photoresist pattern 107 corresponds to the region to be thinned on the passivation layer 109.
  • a first via hole may be formed on the passivation layer 109 corresponding to the region of the photoresist completely removed region 1073 of the first photoresist pattern 107 by an etching process, and the first photoresist pattern is removed by an ashing process.
  • the photoresist portion of 107 is reserved for the region 1072, and the passivation layer is thinned by an etching process.
  • a region of the photoresist portion 1072 corresponding to the photoresist portion 107 of the first photoresist pattern 107 is reserved.
  • the above etching process includes dry etching or wet etching, and the embodiment is not limited herein.
  • the passivation layer 109 includes a first height H according to the height from the base substrate 101 to the upper surface of the passivation layer 109.
  • the region 1091 of 1 and the region 1092 having the second height H 2 , the first height H 1 being greater than the second height H 2 , the photoresist portion retention region 1072 of the first photoresist pattern 107 may have a first height H 1
  • the region 1091, the photoresist completely remaining region 1073 of the first photoresist pattern 107 corresponds to the region 1092 having the second height H 2 .
  • the region 1091 of the passivation layer 109 having the first height H 1 can be thinned to approach the region 1092 of the passivation layer 109 having the second height, thereby planarizing the passivation layer 109.
  • the first height H 1 and the second height H 2 described above are used to determine the area where the passivation layer 109 needs to be thinned for the purpose of planarization, the first height H 1 and the second height H 2 . It can be set according to the actual situation.
  • first height H 1 or second height H 2 may not only refer to a height having a certain value, but also may have a height within a certain numerical range, and the above-mentioned first height H 1 numerical range The difference in the different heights within is much smaller than the difference between the first height H 1 and the second height H 2 .
  • the passivation layer 109 of the photoresist portion retention region 1072 is thinned so that the upper surface of the region 1091 of the passivation layer 109 having the first height H 1 is
  • the upper surface of the region 1092 of the passivation layer 109 having the second height H 2 has the same height, so that the flatness of the passivation layer 109 can be greatly increased.
  • the passivation layer 109 has a first thickness over the height H 1 of the thinned region 1091 is h 1, h 1 is equal to the second height H 2, thereby greatly increasing the passivation layer 109 flatness.
  • the first height H 1 refers to a height within a certain numerical range, that is, the passivation layer 109 has a region 1091 of a first height H 1 .
  • the difference between the different heights described above is much smaller than the difference between the first height H 1 and the second height H 2 ; in this case, one of the corresponding ones of the corresponding passivation layers having different heights may be larger
  • the upper surface is flush with the upper surface of the region 1092 having the second height H 2 so that the flatness of the passivation layer 109 can be optimized.
  • the height of the portion of the passivation layer having a larger area in the region can be selected as a measure to be made with the passivation layer.
  • the upper surface of the region having the second height H 2 is flush.
  • the height of the portion of the passivation layer having a larger area in the region may be selected as a measure so as to have the first height. The height after the area is thinned is equal.
  • the method for fabricating the array substrate provided in the first embodiment may further include: determining, according to the height difference between the first height H 1 and the second height H 2 , the region 1091 of the passivation layer 109 having the first height H 1 to be thinned. Thinning thickness.
  • the thinned thickness of the region 1091 of the passivation layer 109 having the first height H 1 to be thinned may be equal to the height difference of the first height H 1 and the second height H 2 .
  • the thickness is reduced to be smaller than the thickness of the passivation layer. It should be noted that since the passivation layer needs to be insulated and protected from the underlying structure, the thinned passivation layer needs a certain thickness, and therefore, the thinned thickness is smaller than the thickness of the passivation layer itself.
  • the method for fabricating the array substrate provided in the first embodiment may further include: calculating an etching rate and an etching time required for etching the passivation layer having a reduced thickness according to the thinned thickness, thereby accurately etching the blunt Layer to achieve the purpose of flattening.
  • the thickness of the passivation layer and the etchant may be tested for different thicknesses to determine the etching rate and etching time required for the unit thickness, and then the etching thickness is calculated according to the thinned thickness described above. Etching rate and etching time required for the passivation layer.
  • the method for fabricating the array substrate provided in the first embodiment may further include: forming a thin film transistor 180 having a first height H 1 region 10 1 before forming the passivation layer. Corresponding to the region in which the thin film transistor 180 is formed.
  • the step of forming the thin film transistor 180 includes: forming a gate electrode 102 on the substrate substrate 101; forming a gate insulating layer on the gate electrode 102; a layer 103; an active layer 104 is formed on the gate insulating layer 103; and a source electrode 1051 and a drain electrode 1052 connected to the active layer 104 are formed on the active layer 104, and the passivation layer 109 is formed at the source electrode 1051 and the drain On the pole 1052, a first via 1101 is formed on the drain 1052 to expose the drain 1052.
  • the passivation layer 109 formed on the source electrode 1051 and the drain electrode 1052 on the active layer 104 may have a higher height.
  • the passivation layer 109 on the channel region of the active layer 104 may have a relatively low height. Since the difference between the two heights is much smaller than the difference between the first height H 1 and the second height H 2 , the passivation layer 109 formed on the source electrode 1051 and the drain electrode 1052 on the active layer 104 and formed the passivation layer 109 on the channel region of the active layer 104 may be considered to have a first height H region of 10,911.
  • the thickness of the thinned layer can be set larger, and the height of the upper surface of the passivation layer 109 formed on the source electrode 1051 and the drain electrode 1052 on the active layer 104 can be regarded as The first height H 1 is measured to be the same as the height of the upper surface of the region 1092 of the passivation layer 109 having the second height H 2 ; when the thickness of the passivation layer 109 is thin, it is not sufficient to thin the above thinning In the case of thickness, the thickness to be thinned may be set small, and the height of the upper surface of the passivation layer 109 formed on the channel region of the active layer 104 may be taken as a measure of the first height H 1 to make it blunt The height of the upper surface of the region 1092 of the layer 109 having the second height H 2 is the same.
  • the passivation layer formed on the source and the drain on the active layer may also be regarded as a region where the passivation layer has the first height H 1 and will be formed on the active region channel region.
  • the passivation layer is regarded as a region of the passivation layer having the second height H 2 , thereby planarizing the passivation layer formed over the thin film transistor. That is, the present embodiment can be used to planarize two regions having any different heights on the passivation layer, which is not limited herein.
  • the height difference between the region of the passivation layer 109 having the first height H 1 and the passivation layer 109 having the second height H 2 is substantially
  • the upper portion may be determined by the thickness of the gate electrode 102, the thickness of the active layer 104, or the thickness of the source electrode 1051 and the drain electrode 1052. Therefore, the thickness of the thinned thickness can also be set according to the thickness of the gate electrode 102, the thickness of the active layer 104, or the thickness of the source electrode 1051 and the drain electrode 1052 in actual conditions.
  • the step of forming the thin film transistor 180 includes: forming the active layer 104 on the substrate 101; forming a gate on the active layer 104. a permanent insulating layer 103; a gate 102 formed on the gate insulating layer 103; a dielectric layer 106 formed on the gate; and a second via exposing the active layer 104 in the dielectric layer 106 and the gate insulating layer 103 1102; and forming a source electrode 1051, a drain electrode 1052 on the dielectric layer 106, the source electrode 1051 and the drain electrode 1052 are respectively connected to the active layer 104 through the second via hole 1102, and the passivation layer 109 is formed at the source electrode 1051 and the drain On the pole 1052, a first via 1101 is formed on the drain 1052 to expose the drain 1052.
  • a first region passivation layer 109 has a height H corresponding to the region 10911 formed of a thin film transistor 180.
  • the above-mentioned thin film transistor 180 is a bottom gate type thin film transistor.
  • the etching of the formation of the passivation layer, the formation of the photoresist pattern, and the ashing can be referred to the aforementioned related contents. Let me repeat.
  • the method for fabricating the array substrate provided in the example of the embodiment may further include: on the passivation layer 109, as shown in FIG.
  • the first electrode 111 is formed, and the first electrode 111 is formed at least in the region 1092 where the passivation layer 109 has the second height H 2 .
  • the first electrode 111 may also be partially formed in the via 1101 to be electrically connected to the drain 1052.
  • the passivation layer is thinned photoresist portions 109 reserved region 1072 such that the passivation layer 109 has a first height H 1 of the region
  • the upper surface of 1091 is the same height as the upper surface of the first electrode 111.
  • the region 1091 of the passivation layer 109 having the first height H 1 with respect to the second height H 2 can reserve the height of one first electrode 111, thereby making the overall flatness of the array substrate after the first electrode 111 is formed.
  • the array substrate having the bottom gate type thin film transistor as shown in FIG. 9 may also include the first electrode, and the specific forming steps, configurations, and effects thereof will not be described herein.
  • the array substrate formed with the top-gate thin film transistor shown in FIG. 10 is taken as an example.
  • the method for fabricating the array substrate provided in the example of the embodiment may further include: on the first electrode 111 An insulating layer 113 is formed; and a second electrode 112 is formed on the insulating layer 113.
  • the passivation layer 109 of the photoresist portion remaining region 1072 is thinned, and the passivation layer is opposite to the second height H 2 .
  • the region 1091 having the first height H 1 may reserve a height of the first electrode 111 and a height of the second electrode 112 so as to be on the array substrate of the region 1091 where the passivation layer 109 has the first height H 1
  • the surface is the same height as the upper surface of the second electrode 112, so that the flatness of the entire array substrate after the formation of the first electrode 111 and the second electrode 112 is further increased.
  • the array substrate having the bottom gate type thin film transistor as shown in FIG. 9 may also include the first electrode, and the specific forming steps, configurations, and effects thereof will not be described herein.
  • the method for fabricating the array substrate provided in the first embodiment of the present invention may further include: on the substrate substrate 101, as shown in FIG.
  • the second electrode 112 is formed, and the second electrode 112 is formed in a region 1092 having the second height H 2 of the passivation layer 109 and formed between the passivation layer 109 and the base substrate 101. That is, the passivation layer 109 of the photoresist portion remaining region is thinned so that the difference between the height of the upper surface and the upper surface of the passivation layer 109 of the photoresist completely remaining region is equal to the first electrode 111 and the second The sum of the thicknesses of the electrodes 112.
  • the array substrate having the bottom gate type thin film transistor as shown in FIG. 9 can also include the second electrode, and the specific forming steps, configurations, and effects thereof will not be described herein.
  • the first electrode 111 includes a pixel electrode
  • the second electrode 112 includes a common electrode
  • the first electrode 111 includes a common electrode
  • the second electrode 112 includes a pixel electrode
  • the method for fabricating the array substrate provided in the example of the embodiment may further include: forming a common electrode line 114 connected to the common electrode 112.
  • This embodiment provides an array substrate which is fabricated by the method for fabricating the array substrate in the first embodiment.
  • the passivation layer 109 is formed with a thin film transistor 180 on the array substrate.
  • the area has a small thickness, so that the height unevenness caused by the film layers superposed on different regions under the passivation layer 109 can be reduced, so that the flatness of the entire array substrate is increased, thereby reducing the unevenness of the array substrate.
  • the liquid crystal efficiency is low and the black state is unevenly distributed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制作方法。该阵列基板的制作方法包括：在衬底基板(101)上形成钝化层(109)；在钝化层(109)上形成光刻胶(1070)，并通过曝光和显影工艺形成包括光刻胶完全保留区域(1071)、光刻胶部分保留区域(1072)以及光刻胶完全去除区域(1073)的第一光刻胶图案(107)；以第一光刻胶图案(107)作为掩膜对钝化层(109)进行刻蚀以在钝化层(109)中形成第一过孔(1101)；灰化第一光刻胶图案(107)以去除光刻胶部分保留区域(1072)的光刻胶并减薄光刻胶完全保留区域(1071)的光刻胶以形成第二光刻胶图案(108)；以及以第二光刻胶图案(108)为掩膜对钝化层(109)进行刻蚀以减薄光刻胶部分保留区域(1072)的钝化层(109)。

Description

阵列基板及其制作方法 技术领域
本发明的实施例涉及一种阵列基板及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，简称：LCD)是一种广泛应用的显示装置。液晶显示器的主要包括阵列基板(Array Substrate)、对置基板(Opposed Substrate)、以及夹设在两者之间的液晶层(LC)。阵列基板中设置有薄膜晶体管(Thin Film Transistor，简称：TFT)。液晶显示器可通过与薄膜晶体管相连的像素电极和公共电极之间产生的电场来实现对液晶层的驱动控制，从而实现图像显示。
发明内容
本发明实施例提供一种阵列基板及其制作方法，该阵列基板的制作方法可在不增加掩模板的数目的前提下实现刻蚀过孔以及平坦化钝化层，从而可在不大幅增加成本的前提下使得钝化层更加平坦，降低因阵列基板高度不均带来的各种风险。
本发明至少一实施例提供一种阵列基板的制作方法，其包括：在衬底基板上形成钝化层；在所述钝化层上形成光刻胶，并通过曝光和显影工艺形成包括光刻胶完全保留区域、光刻胶部分保留区域以及光刻胶完全去除区域的第一光刻胶图案；以所述第一光刻胶图案作为掩膜对所述钝化层进行刻蚀以在所述钝化层中形成第一过孔；灰化所述第一光刻胶图案以去除所述光刻胶部分保留区域的所述光刻胶并减薄所述光刻胶完全保留区域的所述光刻胶以形成第二光刻胶图案；以及以所述第二光刻胶图案为掩膜对所述钝化层进行刻蚀以减薄所述光刻胶部分保留区域的所述钝化层，所述第一光刻胶图案的所述光刻胶完全去除区域对应所述钝化层上待形成所述第一过孔的区域；所述第一光刻胶图案的所述光刻胶部分保留区域对应所述钝化层上待减薄的区域。
例如，在本发明一实施例提供的阵列基板的制作方法中，根据从所述衬底基板到所述钝化层的上表面的高度，所述钝化层包括具有第一高度的区域和具有第二高度的区域，所述第一高度大于所述第二高度，所述第一光刻胶图案的 所述光刻胶部分保留区域对应具有所述第一高度的区域，所述第一光刻胶图案的所述光刻胶完全保留区域对应具有所述第二高度的区域。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，减薄所述光刻胶部分保留区域的所述钝化层以使得所述钝化层具有所述第一高度的区域的上表面与所述钝化层具有所述第二高度的区域的上表面的高度相同。
例如，本发明至少一实施例提供的阵列基板的制作方法还包括：根据所述第一高度和所述第二高度的高度差确定所述钝化层具有所述第一高度的区域待减薄的减薄厚度。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，所述减薄厚度小于所述钝化层的厚度。
例如，在本发明至少一实施例提供的阵列基板的制作方法还包括：根据所述减薄厚度计算刻蚀具有所述减薄厚度的所述钝化层所需要的刻蚀速率和刻蚀时间。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，利用灰色调掩模板或半色调掩模板作为掩模对所述光刻胶进行曝光、显影以形成具有所述光刻胶完全保留区域、所述光刻胶部分保留区域以及所述光刻胶完全去除区域的所述第一光刻胶图案。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，所述灰色调掩模板或半色调掩模板的全透光区域对应所述第一光刻胶图案的所述光刻胶完全去除区域，所述灰色调掩模板或半色调掩模板的半透光区域对应所述第一光刻胶图案的所述光刻胶部分保留区域，所述灰色调掩模板或半色调掩模板的不透光区域对应所述第一光刻胶的所述光刻胶完全保留区域。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，在形成所述钝化层之前，还包括：形成薄膜晶体管，所述钝化层具有所述第一高度的区域对应于形成所述薄膜晶体管的区域。
例如，在本发明至少一实施例提供的阵列基板的制作方法还包括：在所述钝化层上形成第一电极，其中，所述第一电极至少形成在所述钝化层具有所述第二高度的区域。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，减薄所述光刻胶部分保留区域的所述钝化层以使得所述钝化层具有所述第一高度的区域的上表面与所述第一电极的上表面的高度相同。
例如，在本发明至少一实施例提供的阵列基板的制作方法还包括：在所述第一电极上形成绝缘层；以及在所述绝缘层上形成第二电极。
例如，在本发明至少一实施例提供的阵列基板的制作方法中，减薄所述光刻胶部分保留区域的所述钝化层以使其上表面的高度与所述光刻胶完全保留区域的所述钝化层的上表面高度之差等于所述第一电极和所述第二电极的厚度之和。
本发明至少一个实施例还提供一种阵列基板，其采用如上述的阵列基板的制作方法制作。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本发明一实施例提供的一种阵列基板的制作方法的流程图；
图2为本发明一实施例提供的在衬底基板上形成钝化层的示意图；
图3为本发明一实施例提供的在钝化层上形成光刻胶的示意图；
图4为本发明一实施例提供的曝光、显影光刻胶以形成第一光刻胶图案的示意图；
图5为本发明一实施例提供的一种形成有第一光刻胶图案的阵列基板的结构示意图；
图6为本发明一实施例提供的形成第一过孔的示意图；
图7为本发明一实施例提供的一种形成有第二光刻胶图案的阵列基板的结构示意图；
图8为本发明一实施例提供的刻蚀钝化层的示意图；
图9为本发明一实施例提供的另一种形成有第二光刻胶图案的阵列基板的结构示意图；
图10为本发明一实施例提供的一种形成有第一电极的阵列基板的结构示意图；
图11为本发明一实施例提供的一种形成有第二电极的阵列基板的结构示意图；
图12为本发明一实施例提供的另一种形成有第二电极的阵列基板的结构 示意图；以及
图13为本发明一实施例提供的一种阵列基板的结构示意图。
附图标记
101-衬底基板；102-栅极；103-栅极绝缘层；104-有源层；1051-源极；1052-漏极；106-介电层；1070-光刻胶；1071-光刻胶完全保留部分；1072-光刻胶部分保留部分；1073-光刻胶完全去除部分；107-第一光刻胶图案；108-第二光刻胶图案；109-钝化层；1091-钝化层具有第一高度H1的区域；1092-钝化层具有第二高度H2的区域；1101-第一过孔；1102-第二过孔；111-第一电极；112-第二电极/公共电极；113-绝缘层；114-公共电极线；150-半色调掩模板/双色调掩模板；180-薄膜晶体管。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
阵列基板是液晶显示器中重要的部件，其通常包括栅极层、栅极绝缘层、有源层、源漏电极层、钝化层和电极层等。在研究中，本申请的发明人发现由于阵列基板上不同区域所叠加的膜层并不相同，因此，阵列基板上存在不同的高度，使得阵列基板呈现不平坦的状态，从而影响液晶的效率甚至可能出现黑态分布不均等不良。通常，可通过增加钝化层的厚度来掩盖阵列基板的不平坦，然而，增加钝化层的厚度不仅会带来成本增加等问题，还会导致阵列基板的厚度增加，不利于液晶显示器的轻薄化。经过研究，本申请的发明人认为在不增 加钝化层厚度以及掩模板的数目的前提下通过实现刻蚀过孔以及平坦化钝化层可在不大幅增加成本的前提下使得阵列基板更加平坦，从而降低因阵列基板高度不均带来的各种不良。
本发明的实施例提供一种阵列基板及其制作方法。该阵列基板的制作方法包括：在衬底基板上形成钝化层；在钝化层上形成光刻胶并通过曝光和显影工艺形成包括光刻胶完全保留区域、光刻胶部分保留区域以及光刻胶完全去除区域的第一光刻胶图案；以第一光刻胶图案作为掩膜对钝化层进行刻蚀以在钝化层中形成第一过孔；灰化第一光刻胶图案以去除光刻胶部分保留区域的光刻胶并减薄光刻胶完全保留区域的光刻胶以形成第二光刻胶图案；以及以第二光刻胶图案为掩膜对钝化层进行刻蚀以减薄光刻胶部分保留区域的钝化层。通过减薄部分钝化层，可使得钝化层不同区域的高度差减小，增加平坦化程度。另一方面，由于减薄部分钝化层和在钝化层刻蚀过孔是在一次掩膜工艺中进行，可减少掩模板使用的次数，降低成本。
下面结合附图，对本发明实施例提供的阵列基板及其制作方法进行说明。
实施例一
本实施例提供一种阵列基板的制作方法，如图1所示，其包括以下步骤110～150。
步骤110：如图2所示，提供衬底基板101，在衬底基板101上形成钝化层109。
例如，衬底基板101可为玻璃基板、石英基板、树脂基板或其他基板；钝化层102的材料可为氮化硅(SiNx)、氧化硅(SiOX)或氮氧化硅(SiNxOy)等无机绝缘材料或聚酰亚胺等有机绝缘材料。
例如，钝化层109的厚度可为
Figure PCTCN2017075596-appb-000001
例如，钝化层109可采用蒸镀工艺、化学气相沉积工艺、涂覆工艺、溶胶-凝胶工艺或其他工艺形成在衬底基板101上。
步骤120：如图5所示，在钝化层109上形成光刻胶1070，并通过曝光和显影工艺形成包括光刻胶完全保留区域1071、光刻胶部分保留区域1072以及光刻胶完全去除区域1073的第一光刻胶图案107。例如，光刻胶1070的厚度可为
Figure PCTCN2017075596-appb-000002
例如，如图3-4所示，先在钝化层109上形成一层光刻胶1070，然后利用灰色调掩模板150或半色调掩模板150作为掩模板对光刻胶1070进行曝光、 显影以形成具有光刻胶完全保留区域1071、光刻胶部分保留区域1072以及光刻胶完全去除区域1073的第一光刻胶图案107。
例如，如图4所示，灰色调掩模板150或半色调掩模板150的全透光区域1503可对应第一光刻胶图案107的光刻胶完全去除区域1073，灰色调掩模板150或半色调掩模板150的半透光区域1502对应第一光刻胶图案107的光刻胶部分保留区域1072，灰色调掩模板150或半色调掩模板150的不透光区域1501对应第一光刻胶107的光刻胶完全保留区域1071。当然，这里是以正性光刻胶为例进行了描述，但本实施例包括但不限于此。
步骤130：如图6所示，以第一光刻胶图案107作为掩膜对钝化层109进行刻蚀以在钝化层109中形成第一过孔1101。
步骤140：如图7所示，灰化第一光刻胶图案107以去除光刻胶部分保留区域1072的光刻胶1070并减薄光刻胶完全保留区域1071的光刻胶1070以形成第二光刻胶图案108。
步骤150：如图8所示，以第二光刻胶图案108为掩膜对钝化层109进行刻蚀以减薄光刻胶部分保留区域1072的钝化层109。
在本实施例提供的阵列基板的制作方法中，通过减薄光刻胶部分保留区域1072的钝化层109可使得钝化层109不同区域的高度差减小，提高钝化层109表面的平坦度，从而提高钝化层109所在的阵列基板的平坦度，进而降低因阵列基板不平坦带来的液晶效率低以及黑态分布不均等各种不良。另外，本实施例提供的阵列基板的制作方法通过在钝化层109上形成包括光刻胶完全保留区域1071、光刻胶部分保留区域1072以及光刻胶完全去除区域1073的第一光刻胶图案107可在一次掩膜工艺中形成第一过孔1101以及减薄部分钝化层109，从而可减少掩模板使用的次数，降低成本。
例如，在本实施例一示例提供的阵列基板的制作方法中，该制作方法还包括：去除第二光刻胶图案。
例如，在本实施例一示例提供的阵列基板的制作方法中，如图5所示，第一光刻胶图案107的光刻胶完全去除区域1073对应钝化层109上待形成第一过孔的区域；第一光刻胶图案107的光刻胶部分保留区域1072对应钝化层109上待减薄的区域。由此，可通过刻蚀工艺在钝化层109上对应于第一光刻胶图案107的光刻胶完全去除区域1073的区域形成第一过孔，通过灰化工艺去除第一光刻胶图案107的光刻胶部分保留区域1072，再通过刻蚀工艺减薄钝化层 109上对应于第一光刻胶图案107的光刻胶部分保留区域1072的区域。需要说明的是，上述的刻蚀工艺包括干法刻蚀或湿法刻蚀，本实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板的制作方法中，如图6所示，根据从衬底基板101到钝化层109的上表面的高度，钝化层109包括具有第一高度H1的区域1091和具有第二高度H2的区域1092，第一高度H1大于第二高度H2，第一光刻胶图案107的光刻胶部分保留区域1072可对应具有第一高度H1的区域1091，第一光刻胶图案107的光刻胶完全保留区域1073对应具有第二高度H2的区域1092。由此，可将钝化层109具有第一高度H1的区域1091减薄，以接近钝化层109具有第二高度的区域1092，从而平坦化钝化层109。需要说明的是，由于上述的第一高度H1和第二高度H2用于确定钝化层109需要减薄的区域以达到平坦化的目的，因此第一高度H1和第二高度H2可根据实际情况进行设置。需要说明的是，上述的第一高度H1或第二高度H2不仅可指具有某一特定的值的高度，还可指具有一定数值范围内的高度，上述的第一高度H1数值范围内的不同高度的差值远小于第一高度H1与第二高度H2的差值。
例如，在本实施例一示例提供的阵列基板的制作方法中，减薄光刻胶部分保留区域1072的钝化层109以使得钝化层109具有第一高度H1的区域1091的上表面与钝化层109具有第二高度H2的区域1092的上表面的高度相同，从而可使得钝化层109的平坦度大大增加。例如，如图8所示，钝化层109具有第一高度H1的区域1091经减薄后的厚度为h1，h1与第二高度H2相等，从而大大增加了钝化层109的平坦度。
例如，在本实施例一示例提供的阵列基板的制作方法中，上述的第一高度H1指具有一定数值范围内的高度，也就是说，钝化层109具有第一高度H1的区域1091具有不同的高度，并且上述不同的高度的差值远小于第一高度H1与第二高度H2的差值；此时，可将具有不同高度的对应钝化层中面积较大的一个的上表面与具有第二高度H2的区域1092的上表面平齐，从而可优化钝化层109的平坦程度。也就是说，在钝化层具有第一高度H1的区域具有多个高度的情况下，可以选取该区域内钝化层的面积较大的部分的高度作为衡量标准，使之与钝化层的具有第二高度H2的区域的上表面齐平。同样，在钝化层具有第二高度H2的区域具有多个高度的情况下，也可以选取该区域内钝化层的面积较大的部分的高度作为衡量标准，从而使得具有第一高度的区域减薄后的高度与之相等。
例如，本实施例一示例提供的阵列基板的制作方法还可包括：根据第一高度H1和第二高度H2的高度差确定钝化层109具有第一高度H1的区域1091待减薄的减薄厚度。例如，钝化层109具有第一高度H1的区域1091待减薄的减薄厚度可等于第一高度H1和第二高度H2的高度差。
例如，本实施例一示例提供的阵列基板的制作方法中，减薄厚度小于钝化层的厚度。需要说明的是，因为钝化层需要对其下的结构进行绝缘保护，减薄后的钝化层需要一定的厚度，因此，减薄厚度小于钝化层本身的厚度。
例如，本实施例一示例提供的阵列基板的制作方法还可包括：根据减薄厚度计算刻蚀具有减薄厚度的钝化层所需要的刻蚀速率和刻蚀时间，从而精确地刻蚀钝化层，以达到平坦化的目的。
例如，可根据钝化层和刻蚀剂的材料针对不同厚度进行试验，从而确定出单位厚度所需要的刻蚀速率和刻蚀时间，再根据上述的减薄厚度，计算刻蚀具有减薄厚度的钝化层所需要的刻蚀速率和刻蚀时间。
例如，如图7所示，本实施例一示例提供的阵列基板的制作方法，在形成钝化层之前，还可包括：形成薄膜晶体管180，钝化层109具有第一高度H1的区域1091对应于形成有薄膜晶体管180的区域。
例如，如图7所示，本实施例一示例提供的阵列基板的制作方法中，形成薄膜晶体管180的步骤包括：在衬底基板101上形成栅极102；在栅极102上形成栅极绝缘层103；在栅极绝缘层103上形成有源层104；以及在有源层104上形成与有源层104相连的源极1051和漏极1052，钝化层109形成在源极1051和漏极1052上，第一过孔1101形成在漏极1052上以暴露漏极1052。
需要说明的是，在钝化层109具有第一高度H1的区域1091中，形成在有源层104上的源极1051和漏极1052上的钝化层109可具有较高的高度，形成在有源层104沟道区上的钝化层109可具有较矮的高度。由于这两个高度的差值远小于第一高度H1和第二高度H2的差值，因此，形成在有源层104上的源极1051和漏极1052上的钝化层109和形成在有源层104沟道区上的钝化层109可视为具有第一高度H1的区域1091。当钝化层109的厚度较厚时，可将减薄厚度设置的较大，可将形成在有源层104上的源极1051和漏极1052上的钝化层109的上表面的高度作为第一高度H1的衡量标准，使之与钝化层109具有第二高度H2的区域1092的上表面的高度相同；当钝化层109的厚度较薄，不足以减薄上述的减薄厚度时，可将将减薄厚度设置的较小，可将形成在有源层 104沟道区上的钝化层109的上表面的高度作为第一高度H1的衡量标准，使之与钝化层109具有第二高度H2的区域1092的上表面的高度相同。另外，根据实际需求，也可将形成在有源层上的源极和漏极上的钝化层视为钝化层具有第一高度H1的区域，将形成在有源层沟道区上的钝化层视为钝化层具有第二高度H2的区域，从而使形成在薄膜晶体管上方的钝化层平坦化。也就是说，本实施例可用于将钝化层上具有任意不同高度的两个区域平坦化，本实施例在此不作限制。
例如，在本实施例一示例提供的阵列基板的制作方法中，如图7所示，钝化层109具有第一高度H1的区域与钝化层109具有第二高度H2的高度差大体上可由栅极102的厚度、有源层104的厚度、或源极1051和漏极1052的厚度决定。因此，也可根据实际情况中栅极102的厚度、有源层104的厚度、或源极1051和漏极1052的厚度来设定减薄厚度的大小。
例如，如图9所示，本实施例一示例提供的阵列基板的制作方法中，形成薄膜晶体管180的步骤包括：在衬底基板101上形成有源层104；在有源层104上形成栅极绝缘层103；在栅极绝缘层103上形成栅极102；在栅极上形成介电层106；在介电层106和栅极绝缘层103中形成暴露有源层104的第二过孔1102；以及在介电层106上形成源极1051、漏极1052，源极1051和漏极1052分别通过第二过孔1102与有源层104相连，钝化层109形成在源极1051和漏极1052上，第一过孔1101形成在漏极1052上以暴露漏极1052。如图9所示，钝化层109具有第一高度H1的区域1091对应于形成有薄膜晶体管180的区域。需要说明的是，上述的薄膜晶体管180为底栅型薄膜晶体管，在此情形下，钝化层的形成的刻蚀、光刻胶图案的形成和灰化可参照前述的相关内容，在此不再赘述。
例如，以图7中所示的形成有顶栅型薄膜晶体管的阵列基板为例，如图10所示，本实施例一示例提供的阵列基板的制作方法还可包括：在钝化层109上形成第一电极111，第一电极111至少形成在钝化层109具有第二高度H2的区域1092。当然，第一电极111也可部分形成在过孔1101中以与漏极1052电性相连。
例如，本实施例一示例提供的阵列基板的制作方法中，如图10所示，减薄光刻胶部分保留区域1072的钝化层109以使得钝化层109具有第一高度H1的区域1091的上表面与第一电极111的上表面的高度相同。由此，相对于第 二高度H2，钝化层109具有第一高度H1的区域1091可预留一个第一电极111的高度，从而使得形成第一电极111后的阵列基板整体的平坦度进一步增加。显然，如图9所示的具有底栅型薄膜晶体管的阵列基板同样可包括第一电极，其具体形成步骤、配置以及效果在此不再赘述。
例如，以图10中所示的形成有顶栅型薄膜晶体管的阵列基板为例，如图11所示，本实施例一示例提供的阵列基板的制作方法还可包括：在第一电极111上形成绝缘层113；以及在绝缘层113上形成第二电极112。
例如，本实施例一示例提供的阵列基板的制作方法中，如图11所示，减薄光刻胶部分保留区域1072的钝化层109，并且，相对于第二高度H2，钝化层109具有第一高度H1的区域1091可预留一个第一电极111的高度和一个第二电极112的高度，从而使得在钝化层109具有第一高度H1的区域1091的阵列基板的上表面与第二电极112的上表面的高度相同，从而使得形成第一电极111和第二电极112后的阵列基板整体的平坦度进一步增加。显然，如图9所示的具有底栅型薄膜晶体管的阵列基板同样可包括第一电极，其具体形成步骤、配置以及效果在此不再赘述。
例如，以图7中所示的形成有顶栅型薄膜晶体管的阵列基板为例，如图12所示，本实施例一示例提供的阵列基板的制作方法还可包括：在衬底基板101上形成第二电极112，第二电极112形成在钝化层109具有第二高度H2的区域1092并形成在钝化层109与衬底基板101之间。也就是说，减薄光刻胶部分保留区域的钝化层109以使其上表面的高度与光刻胶完全保留区域的钝化层109的上表面高度之差等于第一电极111和第二电极112的厚度之和。显然，如图9所示的具有底栅型薄膜晶体管的阵列基板同样可包括第二电极，其具体形成步骤、配置以及效果在此不再赘述。
例如，本实施例一示例提供的阵列基板的制作方法中，第一电极111包括像素电极，第二电极112包括公共电极，或者，第一电极111包括公共电极，第二电极112包括像素电极。
例如，如图12所示，本实施例一示例提供的阵列基板的制作方法还可包括：形成与公共电极112相连的公共电极线114。
实施例二
本实施例提供一种阵列基板，其通过上述实施例一中的阵列基板的制作方法制作而成。如图13所示，钝化层109在阵列基板上形成有薄膜晶体管180 的区域具有较小的厚度，从而可减小钝化层109之下不同区域所叠加的膜层并不相同导致的高度不均，使得整个阵列基板的平坦度增加，进而降低因阵列基板不平坦带来的液晶效率低以及黑态分布不均等各种不良。
有以下几点需要说明：
(1)本发明实施例附图中，只涉及到与本发明实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本发明同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年04月29日递交的中国专利申请第201610284394.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上形成钝化层；
    在所述钝化层上形成光刻胶，并通过曝光和显影工艺形成包括光刻胶完全保留区域、光刻胶部分保留区域以及光刻胶完全去除区域的第一光刻胶图案；
    以所述第一光刻胶图案作为掩膜对所述钝化层进行刻蚀以在所述钝化层中形成第一过孔；
    灰化所述第一光刻胶图案以去除所述光刻胶部分保留区域的所述光刻胶并减薄所述光刻胶完全保留区域的所述光刻胶以形成第二光刻胶图案；以及
    以所述第二光刻胶图案为掩膜对所述钝化层进行刻蚀以减薄所述光刻胶部分保留区域的所述钝化层，
    其中，所述第一光刻胶图案的所述光刻胶完全去除区域对应所述钝化层上待形成所述第一过孔的区域；所述第一光刻胶图案的所述光刻胶部分保留区域对应所述钝化层上待减薄的区域。
  2. 根据权利要求1所述的阵列基板的制作方法，其中，根据从所述衬底基板到所述钝化层的上表面的高度，所述钝化层包括具有第一高度的区域和具有第二高度的区域，所述第一高度大于所述第二高度，所述第一光刻胶图案的所述光刻胶部分保留区域对应具有所述第一高度的区域，所述第一光刻胶图案的所述光刻胶完全保留区域对应具有所述第二高度的区域。
  3. 根据权利要求2所述的阵列基板的制作方法，其中，减薄所述光刻胶部分保留区域的所述钝化层以使得所述钝化层具有所述第一高度的区域的上表面与所述钝化层具有所述第二高度的区域的上表面的高度相同。
  4. 根据权利要求2所述的阵列基板的制作方法，还包括：
    根据所述第一高度和所述第二高度的高度差确定所述钝化层具有所述第一高度的区域待减薄的减薄厚度。
  5. 根据权利要求4所述的阵列基板的制作方法，其中，所述减薄厚度小于所述钝化层的厚度。
  6. 根据权利要求4或5所述的阵列基板的制作方法，还包括：
    根据所述减薄厚度计算刻蚀具有所述减薄厚度的所述钝化层所需要的刻蚀速率和刻蚀时间。
  7. 根据权利要求1-5中任一项所述的阵列基板的制作方法，其中，利用灰色调掩模板或半色调掩模板作为掩模板对所述光刻胶进行曝光、显影以形成具有所述光刻胶完全保留区域、所述光刻胶部分保留区域以及所述光刻胶完全去除区域的所述第一光刻胶图案。
  8. 根据权利要求7所述的阵列基板的制作方法，其中，所述灰色调掩模板或半色调掩模板的全透光区域对应所述第一光刻胶图案的所述光刻胶完全去除区域，所述灰色调掩模板或半色调掩模板的半透光区域对应所述第一光刻胶图案的所述光刻胶部分保留区域，所述灰色调掩模板或半色调掩模板的不透光区域对应所述第一光刻胶的所述光刻胶完全保留区域。
  9. 根据权利要求2所述的阵列基板的制作方法，在形成所述钝化层之前，还包括：
    形成薄膜晶体管，其中，所述钝化层具有所述第一高度的区域对应于形成有所述薄膜晶体管的区域。
  10. 根据权利要求2所述的阵列基板的制作方法，还包括：
    在所述钝化层上形成第一电极，其中，所述第一电极至少形成在所述钝化层具有所述第二高度的区域。
  11. 根据权利要求10所述的阵列基板的制作方法，其中，减薄所述光刻胶部分保留区域的所述钝化层以使得所述钝化层具有所述第一高度的区域的上表面与所述第一电极的上表面的高度相同。
  12. 根据权利要求10所述的阵列基板的制作方法，还包括：
    在所述第一电极上形成绝缘层；以及
    在所述绝缘层上形成第二电极。
  13. 根据权利要求12所述的阵列基板的制作方法，其中，减薄所述光刻胶部分保留区域的所述钝化层以使其上表面的高度与所述光刻胶完全保留区域的所述钝化层的上表面高度之差等于所述第一电极和所述第二电极的厚度之和。
  14. 一种阵列基板，采用如权利要求1-13中任一项所述的阵列基板的制作方法制作。
PCT/CN2017/075596 2016-04-29 2017-03-03 阵列基板及其制作方法 WO2017185877A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/567,786 US10332807B2 (en) 2016-04-29 2017-03-03 Array substrate and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610284394.7 2016-04-29
CN201610284394.7A CN105931995B (zh) 2016-04-29 2016-04-29 阵列基板及其制作方法

Publications (1)

Publication Number Publication Date
WO2017185877A1 true WO2017185877A1 (zh) 2017-11-02

Family

ID=56837779

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/075596 WO2017185877A1 (zh) 2016-04-29 2017-03-03 阵列基板及其制作方法

Country Status (3)

Country Link
US (1) US10332807B2 (zh)
CN (1) CN105931995B (zh)
WO (1) WO2017185877A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10332807B2 (en) * 2016-04-29 2019-06-25 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106653764A (zh) * 2016-10-19 2017-05-10 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板、显示装置
CN106684037B (zh) * 2017-03-22 2019-09-24 深圳市华星光电半导体显示技术有限公司 优化4m制程的tft阵列制备方法
CN108155196B (zh) * 2017-12-28 2020-11-03 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN108538855B (zh) * 2018-03-30 2020-06-30 深圳市华星光电半导体显示技术有限公司 一种阵列基板的制作方法
US11476451B2 (en) * 2019-03-27 2022-10-18 Chengdu Boe Optoelectronics Technology Co., Ltd. Display device and manufacturing method thereof for reducing color cast between view angles
WO2024127225A1 (en) * 2022-12-12 2024-06-20 Ecole Polytechnique Federale De Lausanne (Epfl) Duv photolithography electrode fabrication method and electrode produced using the method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002341382A (ja) * 2001-05-21 2002-11-27 Sharp Corp 液晶用マトリクス基板およびその製造方法
US20080012017A1 (en) * 2006-06-28 2008-01-17 Lg.Philips Lcd Co., Ltd. Array substrate for liquid crystal display device and method of fabricating the same
CN101556417A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
CN104752344A (zh) * 2015-04-27 2015-07-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN105931995A (zh) * 2016-04-29 2016-09-07 京东方科技集团股份有限公司 阵列基板及其制作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699987B1 (ko) * 2001-08-06 2007-03-26 삼성에스디아이 주식회사 높은 캐패시턴스를 갖는 평판표시소자 및 그의 제조방법
US6753804B2 (en) 2002-05-21 2004-06-22 Visteon Global Technologies, Inc. Target vehicle identification based on the theoretical relationship between the azimuth angle and relative velocity
KR100886241B1 (ko) * 2002-09-10 2009-02-27 엘지디스플레이 주식회사 액정표시소자의 제조방법
JP4593094B2 (ja) * 2003-08-21 2010-12-08 日本電気株式会社 液晶表示装置及びその製造方法
KR101086477B1 (ko) * 2004-05-27 2011-11-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 제조 방법
TWI287869B (en) * 2005-02-16 2007-10-01 Hannstar Display Corp Structure and manufacturing method of imager array unit
JP4805587B2 (ja) * 2005-02-24 2011-11-02 エーユー オプトロニクス コーポレイション 液晶表示装置とその製造方法
KR100957614B1 (ko) * 2005-10-17 2010-05-13 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조 방법
TWI306668B (en) * 2006-08-16 2009-02-21 Au Optronics Corp Display panel and method of manufacturing the same
KR101579846B1 (ko) * 2008-12-24 2015-12-24 주식회사 이엔에프테크놀로지 포토레지스트 패턴 제거용 조성물 및 이를 이용한 금속 패턴의 형성 방법
CN101995709B (zh) * 2009-08-27 2012-10-03 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板及其制造方法
CN103123910B (zh) * 2012-10-31 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103208491B (zh) * 2013-02-25 2015-12-02 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
JP2014170829A (ja) * 2013-03-04 2014-09-18 Sony Corp 半導体装置およびその製造方法、並びに表示装置の製造方法および電子機器の製造方法
CN103236419B (zh) * 2013-04-26 2014-12-17 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板以及显示装置
CN103560088B (zh) * 2013-11-05 2016-01-06 京东方科技集团股份有限公司 阵列基板的制作方法
US20150187825A1 (en) * 2013-12-31 2015-07-02 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method of Manufacturing Array Substrate of LCD
CN104157613B (zh) * 2014-07-31 2017-03-08 京东方科技集团股份有限公司 一种阵列基板的制备方法
CN104218041B (zh) * 2014-08-15 2017-12-08 京东方科技集团股份有限公司 阵列基板及制备方法和显示装置
CN104638017B (zh) * 2015-02-04 2017-10-13 京东方科技集团股份有限公司 薄膜晶体管、像素结构及其制作方法、阵列基板、显示装置
CN104867942B (zh) * 2015-04-29 2018-03-06 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN105161504B (zh) * 2015-09-22 2019-01-04 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN106094366B (zh) * 2016-08-23 2019-02-01 深圳市华星光电技术有限公司 Ips型阵列基板的制作方法及ips型阵列基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002341382A (ja) * 2001-05-21 2002-11-27 Sharp Corp 液晶用マトリクス基板およびその製造方法
US20080012017A1 (en) * 2006-06-28 2008-01-17 Lg.Philips Lcd Co., Ltd. Array substrate for liquid crystal display device and method of fabricating the same
CN101556417A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
CN104752344A (zh) * 2015-04-27 2015-07-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN105931995A (zh) * 2016-04-29 2016-09-07 京东方科技集团股份有限公司 阵列基板及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10332807B2 (en) * 2016-04-29 2019-06-25 Boe Technology Group Co., Ltd. Array substrate and manufacturing method thereof

Also Published As

Publication number Publication date
US20180211888A1 (en) 2018-07-26
US10332807B2 (en) 2019-06-25
CN105931995B (zh) 2018-11-23
CN105931995A (zh) 2016-09-07

Similar Documents

Publication Publication Date Title
WO2017185877A1 (zh) 阵列基板及其制作方法
WO2017054384A1 (zh) 一种阵列基板及其制作方法、显示面板
CN105514125B (zh) 一种阵列基板、其制备方法及显示面板
US10128281B2 (en) Array substrate, fabrication method thereof and display device
US10192905B2 (en) Array substrates and the manufacturing methods thereof, and display devices
US11189646B2 (en) Display substrate including signal line electrically connected to conductive pattern through the plurality of via holes
WO2013189160A1 (zh) 阵列基板及其制作方法、显示装置
WO2017049780A1 (zh) 液晶显示面板、阵列基板及其制造方法
WO2018166190A1 (zh) 阵列基板及其制备方法、显示面板
CN108962948B (zh) 一种阵列基板及其制作方法
WO2014205998A1 (zh) Coa基板及其制造方法、显示装置
WO2015043282A1 (zh) 阵列基板及其制造方法和显示装置
WO2018120691A1 (zh) 阵列基板及其制造方法、显示装置
WO2014005404A1 (zh) 薄膜晶体管的制造方法及阵列基板的制造方法
CN108538855B (zh) 一种阵列基板的制作方法
WO2017020480A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2016106876A1 (zh) 薄膜晶体管阵列基板及其制造方法、显示装置
WO2013181915A1 (zh) Tft阵列基板及其制造方法和显示装置
WO2013189144A1 (zh) 阵列基板及其制造方法、以及显示装置
WO2016065780A1 (zh) 显示基板及其制作方法、显示装置
CN109037241B (zh) Ltps阵列基板及其制造方法、显示面板
WO2018145465A1 (zh) 阵列基板以及显示装置
US9494837B2 (en) Manufacturing method of TFT array substrate, TFT array substrate and display device
WO2015024332A1 (zh) 显示装置、阵列基板、像素结构及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15567786

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17788532

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17788532

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 15/03/2019)