WO2017049780A1 - 液晶显示面板、阵列基板及其制造方法 - Google Patents

液晶显示面板、阵列基板及其制造方法 Download PDF

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Publication number
WO2017049780A1
WO2017049780A1 PCT/CN2015/097901 CN2015097901W WO2017049780A1 WO 2017049780 A1 WO2017049780 A1 WO 2017049780A1 CN 2015097901 W CN2015097901 W CN 2015097901W WO 2017049780 A1 WO2017049780 A1 WO 2017049780A1
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Prior art keywords
contact hole
electrode layer
layer
array substrate
passivation layer
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PCT/CN2015/097901
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English (en)
French (fr)
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王勐
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深圳市华星光电技术有限公司
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Priority to KR1020187011025A priority Critical patent/KR102057821B1/ko
Priority to US14/903,356 priority patent/US9904132B2/en
Priority to GB1806512.8A priority patent/GB2557844B/en
Publication of WO2017049780A1 publication Critical patent/WO2017049780A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate, a method of manufacturing the same, and a liquid crystal display panel having the array substrate.
  • the pixel electrode layer 11 needs to be electrically connected to the metal layer M of a TFT (Thin Film Transistor) through a contact hole (Via) 13 formed in the passivation layer 12.
  • the thickness of the pixel electrode layer 11 is 40 to 60 nm
  • the thickness of the passivation layer 12 is 1.5 to 3 ⁇ m
  • the opening of the contact hole 13 is small, which causes the pixel electrode layer 11 formed in the contact hole 13 to be broken.
  • the film probability is large or the thickness is small, resulting in high resistance at the contact hole 13 and affecting display quality.
  • the prior art provides a pixel structure as shown in FIG.
  • a floating electrode layer 14 is added to the contact hole 13, and the pixel electrode layer 11 is bridged by the floating electrode layer 14 and then the metal of the TFT.
  • the layer M is electrically connected, thereby reducing the resistance of the pixel electrode layer 11 at the contact hole 13 and the probability of film breakage.
  • BM Black Matrix
  • embodiments of the present invention provide a liquid crystal display panel, an array substrate, and a method of fabricating the same, which can not only reduce the resistance at the contact hole and the probability of breaking the pixel electrode layer in the contact hole, but also ensure the pixel aperture ratio.
  • the array substrate includes: a substrate; a metal layer formed on the substrate; a first passivation layer on the metal layer, and the first passivation layer is formed with a first contact hole exposing a surface of the metal layer a floating electrode layer covering a bottom surface of the first contact hole and a portion of a sidewall of the first contact hole connected to the bottom surface; the common electrode layer being located on the first passivation layer and located at a periphery of the first contact hole; a passivation layer on the first passivation layer exposed by the common electrode layer and the common electrode layer, and the second passivation layer is formed with a second contact hole exposing a surface of the floating electrode layer;
  • the pole layer is located on the second passivation layer and in the first contact hole and the second contact hole to be electrically connected to the metal layer through the first contact hole and the second contact hole.
  • the metal layer is one of a source and a drain of the thin film transistor of the array substrate.
  • the upper edge of the floating electrode layer is spaced apart from the first contact hole by a predetermined distance.
  • the floating electrode layer and the common electrode layer are formed by the same mask process.
  • the liquid crystal display panel of the present invention includes a weight array substrate and a color filter substrate spaced apart from the array substrate, the array substrate includes: a substrate; a metal layer formed on the substrate; and a first passivation layer located at a metal layer, and the first passivation layer is formed with a first contact hole exposing a surface of the metal layer; the floating electrode layer covers a bottom surface of the first contact hole and a portion of a sidewall of the first contact hole connected to the bottom surface a common electrode layer on the first passivation layer and located on the periphery of the first contact hole; a second passivation layer on the common electrode layer and the first passivation layer exposed by the common electrode layer, and the second passivation layer Forming a second contact hole exposing a surface of the floating electrode layer; the pixel electrode layer is located on the second passivation layer and in the first contact hole and the second contact hole to pass through the first contact hole and the second contact hole The metal layer is electrically connected.
  • the metal layer is one of a source and a drain of the thin film transistor of the array substrate.
  • the upper edge of the floating electrode layer is spaced apart from the first contact hole by a predetermined distance.
  • the floating electrode layer and the common electrode layer are formed by the same mask process.
  • the color filter substrate comprises a black matrix layer, and an edge of the common electrode layer close to the metal layer overlaps an edge of the black matrix layer in a direction perpendicular to the array substrate.
  • a method for fabricating an array substrate includes: forming a metal layer on a substrate; forming a first passivation layer on the metal layer, and forming a first contact on a surface of the first passivation layer exposing the metal layer Forming a floating electrode layer in the first contact hole, and forming a common electrode layer on the first passivation layer, the floating electrode layer covering the bottom surface of the first contact hole and the sidewall of the first contact hole connected to the bottom surface a portion of the common electrode layer is located at a periphery of the first contact hole; a second passivation layer is formed on the first contact hole, on the common electrode layer, and on the first passivation layer exposed by the common electrode layer, and is in the second blunt Forming a second contact hole exposing a surface of the floating electrode layer; forming a pixel electrode layer on the second passivation layer and in the first contact hole and the second contact hole to pass the pixel electrode layer through the first contact hole And the second contact hole is electrically connected to the metal
  • the metal layer is one of a source and a drain of the thin film transistor of the array substrate.
  • the upper edge of the floating electrode layer is spaced apart from the first contact hole by a predetermined distance.
  • the floating electrode layer and the common electrode layer are formed by the same mask process.
  • the floating electrode layer is added to the contact hole for electrically connecting the metal layer of the TFT and the pixel electrode layer, so that the pixel electrode layer is bridged by the floating electrode layer.
  • the electrical connection with the metal layer can reduce the resistance at the contact hole and the probability of breaking the pixel electrode layer in the contact hole, and the edge of the floating electrode layer is located in the contact hole, which can reduce the size of the corresponding black matrix layer. Increase the pixel aperture ratio.
  • 1 is a cross-sectional view showing the structure of an array substrate of the prior art
  • FIG. 2 is a cross-sectional view showing the structure of another embodiment of the prior art array substrate
  • Figure 3 is a cross-sectional view showing the structure of an array substrate of the present invention.
  • Figure 4 is a cross-sectional view showing the structure of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention.
  • Figure 6 is a schematic view showing the formation of an array substrate by the method shown in Figure 5.
  • Figure 3 is a cross-sectional view showing the structure of an array substrate of the present invention.
  • the array substrate 30 includes a substrate 31, a metal layer 32, a first passivation layer 33, a floating electrode layer 34, a common electrode layer 35, a second passivation layer 36, and a pixel electrode layer 37.
  • the metal layer 32 is formed on the substrate 31; the first passivation layer 33 is formed on the metal layer 32 and is formed with a first contact hole O 1 exposing the surface of the metal layer 32; the floating electrode layer 34 covers the first contact hole a bottom surface portion of the sidewall of the O 1 and O with the first contact hole connected to the bottom surface 1; and the common electrode layer 35 is located at the periphery of the first contact hole O 1 on the first passivation layer 33, i.e., a first obtuse
  • the layer 33 does not cover the common electrode layer 35 within a predetermined range (the size is b 2 shown in the drawing) around the first contact hole O 1 ; the second passivation layer 36 is exposed at the common electrode layer 35 and the common electrode layer 35 on the first passivation layer 33, and the second passivation layer 36 is formed with a surface of the floating electrode layer is exposed and a second contact hole 34 O 2, O 2, and the second contact hole of the first contact hole communicate to form O 1 a contact hole according to the prior art;
  • the metal layer 32 may be one of the source and the drain of the thin film transistor of the array substrate 30.
  • the embodiment of the present invention implements the metal layer 32 and the pixel electrode layer of the TFT.
  • the floating electrode layer 34 is added to the contact hole of the electrically connected 37, so that the pixel electrode layer 37 is electrically connected to the metal layer 32 through the bridge of the floating electrode layer 34, so that the film of the pixel electrode layer 37 in the contact hole can be reduced. There is a possibility, and it is possible to prevent the resistance at the contact hole from being lowered due to the small thickness of the pixel electrode layer 37 in the contact hole.
  • the floating electrode layer 34 of the array substrate of the present invention an embodiment of the contact hole 30 is located entirely, i.e. the floating upper edge of the first electrode layer 34 O contact hole spaced a predetermined distance 1, this time corresponding to the black matrix layer disposed
  • the size of 38 on the right side of the second contact hole O 2 is b 2 + c, where b 2 is the edge distance of the common electrode layer 35 and the contact hole (second contact hole O 2 ), and c is a pre-increasing distance for preventing light leakage.
  • the size of the black matrix layer 16 shown in FIG. 2 on the right side of the contact hole is a+b 1 +c, where a is the size of the floating electrode layer 34 on the surface of the second passivation layer 17, and b 1 is common.
  • the embodiment of the present invention is equivalent to the reduction of the distance a as compared with the prior art shown in Fig. 2, so that the size of the black matrix layer 38 can be reduced, and the pixel aperture ratio can be improved.
  • the present invention also provides a liquid crystal display panel 40 as shown in FIG. 4, which includes the array substrate 30 and a color filter substrate 41 disposed at a distance from the array substrate.
  • the black matrix layer 38 may be disposed on the array substrate 30 or on the color filter substrate 41, and only the edge of the black matrix layer 38 may overlap the edge of the common electrode layer 35 adjacent to the metal layer 32. The overlap should be understood as the structure shown in FIG.
  • the floating electrode layer 34 and the common electrode layer 35 of the embodiment of the present invention can be formed by the same (mask) process, so that the manufacturing process of the entire array substrate 30 can be reduced. A method of manufacturing the array substrate 30 will be described below with reference to FIGS. 5 and 6.
  • Figure 5 is a flow chart showing a method of fabricating an embodiment of the array substrate of the present invention. As shown in FIG. 5, the manufacturing method of this embodiment includes the following steps:
  • the substrate 31 is used to form the array substrate 30 of the liquid crystal display panel 40, and the substrate 31 may be a glass substrate, a plastic substrate or a flexible substrate.
  • a metal is formed on the substrate 31 by, for example, chemical vapor deposition (CVD), vacuum evaporation, plasma enhanced chemical vapor deposition (PECVD), sputtering, or low pressure chemical vapor deposition.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • sputtering or low pressure chemical vapor deposition.
  • the layer 32 that is, the source or the drain of the thin film transistor forming the array substrate 30 having a predetermined pattern, correspondingly, also needs to form the gate of the thin film transistor having a gate insulating layer between the gate and the source and the drain (Gate Insulation Layer, GI).
  • GI Gate Insulation Layer
  • an entire first passivation layer 33 formed on the metal layer 32 can be etched by using an etchant containing phosphoric acid, nitric acid, acetic acid, and deionized water to obtain a first contact hole O 1 .
  • a passivation layer 33 can of course also be dry etched.
  • S53 forming a floating electrode layer in the first contact hole, and forming a common electrode layer on the first passivation layer, the floating electrode layer covering a bottom surface of the first contact hole and a sidewall of the first contact hole connected to the bottom surface A portion of the common electrode layer is located at the periphery of the first contact hole.
  • the floating electrode layer 34 and the common electrode layer 35 may be formed by the same mask process. Specifically, a whole electrode layer 345 is formed on the first passivation layer 33 and covers the first contact hole O 1 ; layer 345 is formed on the photoresist layer 346; 347 pairs using the photoresist mask layer 346 is exposed to remove the photoresist layer is disposed in the first contact hole portions 346 O 1, and the remaining photoresist layer 346 covers the first contact and the bottom surface of the hole 1 O O first contact hole and the bottom surface is connected to a portion of the sidewall; etching the electrode layer not covered by the remaining photoresist layer 346 346; removing the remaining photoresist layer 346; etching to give The floating electrode layer 34 and the common electrode layer 35.
  • the thickness d 1 of the photoresist layer 346 on the first passivation layer 33 is smaller than the thickness d 2 of the bottom surface of the first contact hole O 1 , that is, d 1 ⁇ d 2 .
  • the photoresist layer 346 can be exposed by using a full-tone mask.
  • the thickness d 3 of the bottom surface of the first contact hole O 1 after exposure of the photoresist layer 346 is smaller than the bottom surface of the first contact hole O 1 before exposure.
  • the thickness d 2 that is, d 3 ⁇ d 2 .
  • the photoresist layer 346 can also be exposed using a half-tone mask.
  • S54 forming a second passivation layer on the first contact hole, on the common electrode layer, and on the first passivation layer exposed by the common electrode layer, and forming a surface on the second passivation layer exposing the surface of the floating electrode layer Second contact hole.
  • S55 forming a pixel electrode layer on the second passivation layer and in the first contact hole and the second contact hole, so that the pixel electrode layer is electrically connected to the metal layer through the first contact hole and the second contact hole.
  • the second contact hole O 2 , the common electrode layer 35 having a predetermined pattern, and the pixel electrode 37 can be obtained by exposure, development, and etching, and the pixel electrode 37 can pass through the first contact hole O 1 and the second contact hole O 2 is electrically connected to the metal layer 32 of the thin film transistor.
  • the gate of the thin film transistor is electrically connected to the gate line formed on the array substrate 30.
  • the source of the thin film transistor is electrically connected to the data line formed on the array substrate 30, and the gate line and the data line are vertically intersected to form an array substrate. 30 pixel display area.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
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Abstract

一种阵列基板（30），制造该阵列基板（30）的方法以及具有该阵列基板（30）的液晶显示面板（40），在实现TFT的金属层（32）和像素电极层（37）电连接的接触孔（O1，O2）中增加浮置电极层（34），使得像素电极层（37）通过浮置电极层（34）的桥接再与金属层（32）电连接，能够降低接触孔（O1，O2）处的电阻以及在接触孔（O1，O2）内的像素电极层（37）的断膜几率，另外该浮置电极层（34）的边缘位于接触孔（O1，O2）内，能够减小对应黑矩阵层（38）的尺寸，提高像素开口率。

Description

液晶显示面板、阵列基板及其制造方法 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种阵列基板及其制造方法和具有该阵列基板的液晶显示面板。
【背景技术】
如图1所示的阵列基板的像素结构中，像素电极层11需要通过形成于钝化层12中的接触孔(Via)13与TFT(Thin Film Transistor，薄膜晶体管)的金属层M电连接。但像素电极层11的厚度为40～60纳米，钝化层12的厚度为1.5～3微米，且接触孔13的开口较小，这使得形成于在接触孔13内的像素电极层11的断膜几率较大或者厚度较小，从而导致接触孔13处的电阻较高，影响显示品质。为了改善该问题，现有技术提供一种如图2所示的像素结构，在接触孔13中增加一浮置电极层14，像素电极层11通过浮置电极层14的桥接再与TFT的金属层M电连接，从而降低像素电极层11在接触孔13处的电阻及断膜几率。但由于需要避免浮置电极层14与公共电极层15短路，需要增大公共电极层15和浮置电极层14的边缘距离，这无疑会增大黑矩阵(Black Matrix，BM)层16的尺寸，从而降低像素开口率。
【发明内容】
鉴于此，本发明实施例提供一种液晶显示面板、阵列基板及其制造方法，不仅能够降低接触孔处的电阻以及在接触孔内的像素电极层的断膜几率，而且能够确保像素开口率。
本发明实施例提供的阵列基板，包括：基板；金属层，形成于基板上；第一钝化层，位于金属层上，且第一钝化层形成有暴露金属层的表面的第一接触孔；浮置电极层，覆盖于第一接触孔的底面以及与底面相连的第一接触孔的侧壁的一部分；公共电极层，位于第一钝化层上且位于第一接触孔外围；第二钝化层，位于公共电极层以及公共电极层所暴露的第一钝化层上，且第二钝化层形成有暴露浮置电极层的表面的第二接触孔；像素电 极层，位于第二钝化层上以及第一接触孔和第二接触孔内，以通过第一接触孔和第二接触孔与金属层电连接。
其中，金属层为阵列基板的薄膜晶体管的源极和漏极的一者。
其中，浮置电极层的上边缘与第一接触孔之间间隔预定距离。
其中，浮置电极层和公共电极层经同一光罩制程形成。
本发明实施例提供的液晶显示面板，包括权阵列基板以及与所述阵列基板相对间隔的彩膜基板，所述阵列基板包括：基板；金属层，形成于基板上；第一钝化层，位于金属层上，且第一钝化层形成有暴露金属层的表面的第一接触孔；浮置电极层，覆盖于第一接触孔的底面以及与底面相连的第一接触孔的侧壁的一部分；公共电极层，位于第一钝化层上且位于第一接触孔外围；第二钝化层，位于公共电极层以及公共电极层所暴露的第一钝化层上，且第二钝化层形成有暴露浮置电极层的表面的第二接触孔；像素电极层，位于第二钝化层上以及第一接触孔和第二接触孔内，以通过第一接触孔和第二接触孔与金属层电连接。
其中，金属层为阵列基板的薄膜晶体管的源极和漏极的一者。
其中，浮置电极层的上边缘与第一接触孔之间间隔预定距离。
其中，浮置电极层和公共电极层经同一光罩制程形成。
其中，彩膜基板包括黑矩阵层，沿垂直于阵列基板的方向，公共电极层的靠近金属层的边缘与黑矩阵层的边缘重叠。
本发明实施例提供的阵列基板的制造方法，包括：在基板上形成一金属层；在金属层上形成第一钝化层，且在第一钝化层形成暴露金属层的表面的第一接触孔；在第一接触孔内形成浮置电极层，且在第一钝化层上形成公共电极层，浮置电极层覆盖第一接触孔的底面以及与底面相连的第一接触孔的侧壁的一部分，公共电极层位于第一接触孔的外围；在第一接触孔内、公共电极层上以及公共电极层所暴露的第一钝化层上形成第二钝化层，且在第二钝化层上形成暴露浮置电极层的表面的第二接触孔；在第二钝化层上以及第一接触孔和第二接触孔内形成像素电极层，以使像素电极层通过第一接触孔和第二接触孔与金属层电连接。
其中，金属层为阵列基板的薄膜晶体管的源极和漏极的一者。
其中，浮置电极层的上边缘与第一接触孔之间间隔预定距离。
其中，浮置电极层和公共电极层经同一光罩制程形成。
本发明实施例的液晶显示面板、阵列基板及其制造方法，在实现TFT的金属层和像素电极层电连接的接触孔中增加浮置电极层，使得像素电极层通过浮置电极层的桥接再与金属层电连接，能够降低接触孔处的电阻以及在接触孔内的像素电极层的断膜几率，另外该浮置电极层的边缘位于接触孔内，能够减小对应黑矩阵层的尺寸，提高像素开口率。
【附图说明】
图1是现有技术的阵列基板一实施例的结构剖视图；
图2是现有技术的阵列基板另一实施例的结构剖视图；
图3是本发明的阵列基板一实施例的结构剖视图；
图4是本发明的液晶显示面板一实施例的结构剖视图；
图5是本发明的阵列基板的制造方法一实施例的流程示意图；
图6是采用图5所示方法形成阵列基板的示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图3是本发明的阵列基板一实施例的结构剖视图。如图3所示，所述阵列基板30包括基板31、金属层32、第一钝化层33、浮置电极层34、公共电极层35、第二钝化层36以及像素电极层37。
其中，金属层32形成于基板31上；第一钝化层33形成于金属层32上且形成有暴露金属层32的表面的第一接触孔O1；浮置电极层34覆盖第一接触孔O1的底面以及与所述底面相连的第一接触孔O1的侧壁的一部分；公共电极层35位于第一钝化层33上且位于第一接触孔O1的外围，即第一钝化层33在第一接触孔O1周围的预定范围(尺寸为图中所示b2)内未覆盖公共电极层35；第二钝化层36位于公共电极层35以及公共电极层35所暴露的第一钝化层33上，且第二钝化层36形成有暴露浮置电极层34的表面的第二接触孔O2，第二接触孔O2和第一接触孔O1相通以构成现有技术所述的接触孔；像素电极层37位于第二钝化层36上以及第一接触孔O1和 第二接触孔O2内，以使像素电极层37通过第一接触孔O1和第二接触孔O2与金属层32电连接。
所述金属层32可以为阵列基板30的薄膜晶体管的源极和漏极的一者，则与图1所示现有技术相比，本发明实施例在实现TFT的金属层32和像素电极层37电连接的接触孔中增加浮置电极层34，使得像素电极层37通过浮置电极层34的桥接再与金属层32电连接，从而能够降低在接触孔内的像素电极层37的断膜几率，并且可以防止因接触孔内的像素电极层37的厚度较小，降低接触孔处的电阻。
本发明实施例的阵列基板30的浮置电极层34完全位于接触孔内，即浮置电极层34的上边缘与第一接触孔O1之间间隔预定距离，此时对应设置的黑矩阵层38在第二接触孔O2右侧的尺寸为b2+c，其中b2为公共电极层35和接触孔(第二接触孔O2)的边缘距离，c为防止漏光的预增距离。而图2所示的黑矩阵层16在接触孔右侧的尺寸为a+b1+c，其中a为浮置电极层34在第二钝化层17的表面上的尺寸，b1为公共电极层15和浮置电极层34的边缘距离。可以看出，在b1＝b2时，与图2所示现有技术相比，本发明实施例相当于减少了距离a，因此能够减小黑矩阵层38的尺寸，提高像素开口率。
本发明还提供一种如图4所示的液晶显示面板40，该液晶显示面板40包括上述阵列基板30以及与阵列基板相对间隔设置的彩膜基板41。其中，黑矩阵层38既可以设置于阵列基板30上，也可以设置于彩膜基板41，只需黑矩阵层38的边缘与公共电极层35的靠近金属层32的边缘重叠即可，所述重叠应理解为图3所示结构。
本发明实施例的浮置电极层34和公共电极层35可以经同一(光罩)制程形成，从而能够减少整个阵列基板30的制造工序。以下结合图5和图6介绍所述阵列基板30的制造方法。
图5是本发明的阵列基板一实施例的制造方法的流程图。如图5所示，本实施例的制造方法包括以下步骤：
S51：在基板上形成一金属层。
S52：在金属层上形成第一钝化层，且在第一钝化层形成暴露金属层的表面的第一接触孔。
如图6所示，基板31用于形成前述液晶显示面板40的阵列基板30，所述基板31可为玻璃基体、塑料基体或可挠式基体。
本实施例通过例如采用化学气相沉积(Chemical vapor deposition，CVD)、真空蒸镀、等离子化学气相沉积(Plasma Enhanced Chemical vapor deposition，PECVD)、溅射或低压化学气相沉积等方法在基板31上形成金属层32，即形成具有预定图案的阵列基板30的薄膜晶体管的源极或漏极，对应地，还需要形成薄膜晶体管的栅极，该栅极和源极与漏极之间具有栅极绝缘层(Gate Insulation Layer，GI)。
本实施例可以利用包含有磷酸、硝酸、醋酸以及去离子水的蚀刻液对形成于金属层32上的一整片第一钝化层33进行蚀刻，从而得到具有第一接触孔O1的第一钝化层33，当然也可以采用干法蚀刻。
S53：在第一接触孔内形成浮置电极层，且在第一钝化层上形成公共电极层，浮置电极层覆盖第一接触孔的底面以及与底面相连的第一接触孔的侧壁的一部分，公共电极层位于第一接触孔的外围。
继续参阅图6，浮置电极层34的上边缘与第一接触孔O1之间间隔预定距离。浮置电极层34和公共电极层35可以经同一光罩制程形成，具体地，在第一钝化层上33上形成一整片电极层345，且其覆盖第一接触孔O1；在电极层345上形成光阻层346；采用光罩347对光阻层346进行曝光，以除去光阻层346的位于第一接触孔O1中的部分，且剩余的光阻层346覆盖第一接触孔O1的底面以及与所述底面相连的第一接触孔O1的侧壁的一部分；蚀刻未被剩余的光阻层346覆盖的电极层346；除去剩余的光阻层346；刻蚀得到浮置电极层34和公共电极层35。
其中，光阻层346在第一钝化层33上的厚度d1小于在第一接触孔O1的底面的厚度d2，即d1＜d2。本发明实施例可以采用全色调光罩对光阻层346进行曝光，光阻层346曝光后在第一接触孔O1的底面的厚度d3小于曝光前在第一接触孔O1的底面的厚度d2，即d3＜d2。当然，也可以采用半色调光罩(half-tone mask)对光阻层346进行曝光。
S54：在第一接触孔内、公共电极层上以及公共电极层所暴露的第一钝化层上形成第二钝化层，且在第二钝化层上形成暴露浮置电极层的表面的第二接触孔。
S55：在第二钝化层上以及第一接触孔和第二接触孔内形成像素电极层，以使像素电极层通过第一接触孔和第二接触孔与金属层电连接。
本实施例可以利用曝光、显影、刻蚀得到第二接触孔O2、具有预定图案的公共电极层35以及像素电极37，并且像素电极37可通过第一接触孔O1和第二接触孔O2与薄膜晶体管的金属层32电连接。薄膜晶体管的栅极与形成于阵列基板30上的栅极线对应电连接，薄膜晶体管的源极与形成于阵列基板30上的数据线对应电连接，栅极线和数据线垂直交叉形成阵列基板30的像素显示区域。
在此基础上，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    金属层，形成于所述基板上；
    第一钝化层，位于所述金属层上，且所述第一钝化层形成有暴露所述金属层的表面的第一接触孔；
    浮置电极层，覆盖于所述第一接触孔的底面以及与所述底面相连的所述第一接触孔的侧壁的一部分；
    公共电极层，位于所述第一钝化层上且位于所述第一接触孔外围；
    第二钝化层，位于所述公共电极层以及所述公共电极层所暴露的所述第一钝化层上，且所述第二钝化层形成有暴露所述浮置电极层的表面的第二接触孔；
    像素电极层，位于所述第二钝化层上以及所述第一接触孔和所述第二接触孔内，以使所述像素电极层通过所述第一接触孔和所述第二接触孔与所述金属层电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述金属层为所述阵列基板的薄膜晶体管的源极和漏极的一者。
  3. 根据权利要求1所述的阵列基板，其中，所述浮置电极层的上边缘与所述第一接触孔之间间隔预定距离。
  4. 根据权利要求1所述的阵列基板，其中，所述浮置电极层和所述公共电极层经同一光罩制程形成。
  5. 一种液晶显示面板，其中，包括阵列基板以及与所述阵列基板相对间隔的彩膜基板，所述阵列基板包括：
    基板；
    金属层，形成于所述基板上；
    第一钝化层，位于所述金属层上，且所述第一钝化层形成有暴露所述金属层的表面的第一接触孔；
    浮置电极层，覆盖于所述第一接触孔的底面以及与所述底面相连的所述第一接触孔的侧壁的一部分；
    公共电极层，位于所述第一钝化层上且位于所述第一接触孔外围；
    第二钝化层，位于所述公共电极层以及所述公共电极层所暴露的所述第一钝化层上，且所述第二钝化层形成有暴露所述浮置电极层的表面的第二接触孔；
    像素电极层，位于所述第二钝化层上以及所述第一接触孔和所述第二接触孔内，以使所述像素电极层通过所述第一接触孔和所述第二接触孔与所述金属层电连接。
  6. 根据权利要求5所述的液晶显示面板，其中，所述金属层为所述阵列基板的薄膜晶体管的源极和漏极的一者。
  7. 根据权利要求5所述的液晶显示面板，其中，所述浮置电极层的上边缘与所述第一接触孔之间间隔预定距离。
  8. 根据权利要求5所述的液晶显示面板，其中，所述浮置电极层和所述公共电极层经同一光罩制程形成。
  9. 根据权利要求5所述的液晶显示面板，其中，所述彩膜基板包括黑矩阵层，沿垂直于所述阵列基板的方向，所述公共电极层的靠近所述金属层的边缘与所述黑矩阵层的边缘重叠。
  10. 一种阵列基板的制造方法，其中，所述方法包括：
    在基板上形成一金属层；
    在所述金属层上形成第一钝化层，且在所述第一钝化层形成暴露所述金属层的表面的第一接触孔；
    在所述第一接触孔内形成浮置电极层，且在所述第一钝化层上形成公共电极层，其中，所述浮置电极层覆盖所述第一接触孔的底面以及与所述底面相连的所述第一接触孔的侧壁的一部分，所述公共电极层位于所述第一接触孔的外围；
    在所述第一接触孔内、所述公共电极层上以及所述公共电极层所暴露的所述第一钝化层上形成第二钝化层，且在所述第二钝化层上形成暴露所述浮置电极层的表面的第二接触孔；
    在所述第二钝化层上以及所述第一接触孔和所述第二接触孔内形成像素电极层，以使所述像素电极层通过所述第一接触孔和所述第二接触孔与所述金属层电连接。
  11. 根据权利要求10所述的方法，其中，所述金属层为所述阵列基板的薄膜晶体管的源极和漏极的一者。
  12. 根据权利要求10所述的方法，其中，所述浮置电极层的上边缘与所述第一接触孔之间间隔预定距离。
  13. 根据权利要求10所述的方法，其中，所述浮置电极层和所述公共电极层经同一光罩制程形成。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109270733A (zh) * 2018-11-13 2019-01-25 成都中电熊猫显示科技有限公司 一种显示面板、阵列基板和显示装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105116655B (zh) * 2015-09-22 2017-04-12 深圳市华星光电技术有限公司 液晶显示面板、阵列基板及其制造方法
CN105467703B (zh) * 2015-12-11 2019-08-13 厦门天马微电子有限公司 阵列基板、显示面板以及阵列基板的制造方法
CN105810692A (zh) * 2016-04-18 2016-07-27 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及阵列基板制作方法
CN105826329B (zh) * 2016-05-09 2019-04-02 深圳市华星光电技术有限公司 一种阵列基板的制作方法、阵列基板及液晶面板
CN106206617A (zh) * 2016-08-29 2016-12-07 武汉华星光电技术有限公司 基于低温多晶硅的阵列基板及其制作方法
EP3534208A4 (en) * 2016-11-17 2020-02-12 Huawei Technologies Co., Ltd. ARRAY SUBSTRATE AND MANUFACTURING METHOD AND LIQUID CRYSTAL DISPLAY PANEL
CN107490911B (zh) * 2017-08-15 2021-07-13 昆山龙腾光电股份有限公司 阵列基板及其制作方法和显示面板
CN108761944B (zh) * 2018-08-22 2023-06-02 武汉华星光电技术有限公司 一种阵列面板
CN110187531B (zh) * 2019-05-29 2020-12-08 深圳市华星光电半导体显示技术有限公司 显示面板及其检测方式
CN113433724B (zh) * 2021-07-05 2022-09-09 武汉华星光电技术有限公司 显示面板及显示装置
CN114488638A (zh) * 2022-03-01 2022-05-13 福建华佳彩有限公司 一种可避免有源层开孔过刻的阵列基板及其制造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515590A (zh) * 2009-03-30 2009-08-26 友达光电股份有限公司 薄膜晶体管数组基板
CN102073181A (zh) * 2009-10-21 2011-05-25 三星电子株式会社 显示基板、其制造方法以及具有该显示基板的显示设备
US20110299022A1 (en) * 2010-06-04 2011-12-08 Au Optronics Corporation Display panel
CN103454819A (zh) * 2012-05-31 2013-12-18 乐金显示有限公司 用于液晶显示器的阵列基板及其制造方法
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN104360529A (zh) * 2014-11-26 2015-02-18 深圳市华星光电技术有限公司 一种tft基板及其制造方法
CN104701328A (zh) * 2015-03-25 2015-06-10 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN105116655A (zh) * 2015-09-22 2015-12-02 深圳市华星光电技术有限公司 液晶显示面板、阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103488013A (zh) * 2012-06-12 2014-01-01 瀚宇彩晶股份有限公司 液晶显示面板及其像素阵列基板
US20150316802A1 (en) * 2012-08-31 2015-11-05 Sharp Kabushiki Kaisha Semiconductor apparatus, display panel, and method of manufacturing semiconductor apparatus
CN104360557B (zh) * 2014-11-26 2017-04-26 京东方科技集团股份有限公司 阵列基板及其制造方法，以及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515590A (zh) * 2009-03-30 2009-08-26 友达光电股份有限公司 薄膜晶体管数组基板
CN102073181A (zh) * 2009-10-21 2011-05-25 三星电子株式会社 显示基板、其制造方法以及具有该显示基板的显示设备
US20110299022A1 (en) * 2010-06-04 2011-12-08 Au Optronics Corporation Display panel
CN103454819A (zh) * 2012-05-31 2013-12-18 乐金显示有限公司 用于液晶显示器的阵列基板及其制造方法
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN104360529A (zh) * 2014-11-26 2015-02-18 深圳市华星光电技术有限公司 一种tft基板及其制造方法
CN104701328A (zh) * 2015-03-25 2015-06-10 京东方科技集团股份有限公司 一种阵列基板及其制造方法、显示装置
CN105116655A (zh) * 2015-09-22 2015-12-02 深圳市华星光电技术有限公司 液晶显示面板、阵列基板及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109270733A (zh) * 2018-11-13 2019-01-25 成都中电熊猫显示科技有限公司 一种显示面板、阵列基板和显示装置
CN109270733B (zh) * 2018-11-13 2022-11-08 成都中电熊猫显示科技有限公司 一种显示面板、阵列基板和显示装置

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