Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/5226—Via connections in a multilevel interconnection structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
  • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
  • H01L2223/5446—Located in scribe lines
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/549—Organic PV cells

Definitions

• the present invention relates to an object, a method, or a manufacturing method.
• the present invention relates to a process, a machine, manufacture, or a composition of matter.
• One embodiment of the present invention particularly relates to an oxide semiconductor or a manufacturing method of the oxide semiconductor.
• One embodiment of the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.
• semiconductor device means all devices which can operate by utilizing semiconductor characteristics.
• a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device.
• An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may have a semiconductor device.
• Non-Patent Document 1 discloses a homologous series represented by
• Non-Patent Document 1 discloses a solid solution range of the homologous series.
• x ranges from -0.33 to 0.08
• x ranges from -0.68 to 0.32.
• Patent Document 1 A technique for forming a transistor using an In-Ga-Zn-based oxide semiconductor is disclosed (see, for example, Patent Document 1).
• Patent Document 1 Japanese Published Patent Application No. 2007-96055
• Non-Patent Document 1 M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In 2 0 3 -Ga 2 Zn0 4 -ZnO System at 1350 °C," J. Solid State Chem., 1991, Vol. 93, pp. 298-315
• Non-Patent Document 1 discloses an example of In x Zn,Xja z O w , and when x, y, and z are set such that a composition in the neighborhood of ZnGa 2 0 4 is obtained, that is, when x, y, and z are close to 0, 1, and 2, respectively, a spinel crystal structure is likely to be formed or mixed.
• a compound represented by AB 2 O 4 (A and B are metals) is known as a compound having a spinel crystal structure.
• an object of one embodiment of the present invention is to provide a novel oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with a novel structure. Another object is to provide a display device having a novel structure.
• One embodiment of the present invention is a composite oxide semiconductor in which a first region and a plurality of second regions are mixed.
• the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc.
• the plurality of second regions contain indium and zinc.
• the plurality of second regions have a higher concentration of indium than the first region.
• the plurality of second regions have a higher conductivity than the first region.
• An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions.
• the plurality of second regions are three-dimensionally surrounded with the first region.
• the atomic ratio of indium to the elementMand zinc (In:M:Zn) is 5: 1 :6 or a neighborhood thereof.
• the atomic ratio of indium to the element M and zinc (InM:Zn) in the first region is 4:2:3 or a neighborhood thereof.
• the atomic ratio of indium to the element M and zinc (InM:Zn) in the plurality of second regions is 2:0:3 or a neighborhood thereof.
• the atomic ratio of indium to the elementMand zinc (In:M:Zn) is 4:2:3 or a neighborhood thereof.
• the atomic ratio of indium to the element M and zinc (InMZn) in the first region is 1 : 1 : 1 or a neighborhood thereof.
• the atomic ratio of indium to the element M and zinc (InMZn) in the plurality of second regions is 2:0: 1 or a neighborhood thereof.
• the thickness of each of the plurality of second regions in the c-axis direction is more than or equal to 0.1 nm and less than 1 nm.
• the first region is non-single-crystal.
• the first region includes a crystal portion and includes a portion where the c-axis of the crystal portion is parallel to a normal vector to a surface on which a film of the composite oxide semiconductor is formed.
• the plurality of second regions are non-single-crystal.
• Another embodiment of the present invention is a transistor characterized by containing the composite oxide semiconductor of the above-described embodiment.
• Another embodiment of the present invention is a display device including the oxide semiconductor in any of the above embodiments and a display element.
• a display module including the display device and a touch sensor.
• Another embodiment of the present invention is an electronic device including the oxide semiconductor in any of the above embodiments, the semiconductor device, the display device, or the display module and an operation key or a battery.
• a novel oxide semiconductor can be provided.
• a semiconductor device can be provided with favorable electrical characteristics.
• a highly reliable semiconductor device can be provided.
• a semiconductor device with a novel structure can be provided.
• a display device with a novel structure can be provided.
• FIGS. lA and IB are conceptual diagrams of a structure of an oxide semiconductor.
• FIGS. 2 A and 2B are conceptual diagrams of a structure of an oxide semiconductor.
• FIGS. 3 A and 3B are conceptual diagrams of a structure of an oxide semiconductor.
• FIGS. 4 A and 4B are conceptual diagrams of a structure of an oxide semiconductor.
• FIG. 5 illustrates an atomic ratio of an oxide semiconductor.
• FIGS. 6 A and 6B illustrate a sputtering apparatus.
• FIGS. 7 A and 7B illustrate a sputtering apparatus.
• FIGS. 8A to 8C illustrate a sputtering apparatus.
• FIGS. 9 A and 9B illustrate a sputtering apparatus.
• FIG. 10 is a top view illustrating an example of a deposition apparatus.
• FIGS. 11 A to 11C are cross-sectional views illustrating an example of a deposition apparatus.
• FIGS. 12A to 12C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 13A to 13C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 14A to 14C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 15A to 15C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 16A to 16C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 17A to 17C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 18A to 18C illustrate a top view and a cross-sectional structure of a transistor of one embodiment.
• FIGS. 19A to 19E illustrate an example of a method for manufacturing a transistor of one embodiment.
• FIGS. 20A to 20D illustrate an example of a method for manufacturing a transistor of one embodiment.
• FIGS. 21A to 21C illustrate an example of a method for manufacturing a transistor of one embodiment.
• FIGS. 22A to 22C illustrate an example of a method for manufacturing a transistor of one embodiment.
• FIG. 23 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 24 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 25 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 26 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 27 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 28 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIGS. 29 A and 29B each illustrate a cross-sectional structure of a semiconductor device of one embodiment.
• FIGS. 30A and 30B are circuit diagrams of semiconductor devices of one embodiment.
• FIGS. 31A and 3 IB illustrate a cross-sectional structure of a semiconductor device of one embodiment.
• FIGS. 32A and 32B illustrate a circuit diagram and a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 33 illustrates a cross-sectional structure of a semiconductor device of one embodiment.
• FIG. 34 is a circuit diagram illustrating a memory device of one embodiment of the present invention.
• FIG. 35 is a circuit diagram illustrating a memory device of one embodiment of the present invention.
• FIGS. 36A to 36C are circuit diagrams and a timing chart illustrating one embodiment of the present invention.
• FIGS. 37A to 37C are a graph and circuit diagrams illustrating one embodiment of the present invention.
• FIGS. 38A and 38B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.
• FIGS. 39A and 39B are a circuit diagram and a timing chart illustrating one embodiment of the present invention.
• FIGS. 40 A to 40E are a block diagram, circuit diagrams, and waveform charts illustrating one embodiment of the present invention.
• FIGS. 41 A and 4 IB are a circuit diagram and a timing chart illustrating one embodiment of the present invention.
• FIGS. 42 A and 42B are circuit diagrams each illustrating one embodiment of the present invention.
• FIGS. 43A to 43C are circuit diagrams each illustrating one embodiment of the present invention.
• FIGS. 44 A and 44B are circuit diagrams each illustrating one embodiment of the present invention.
• FIGS. 45A to 45C are circuit diagrams each illustrating one embodiment of the present invention.
• FIGS. 46 A and 46B are circuit diagrams each illustrating one embodiment of the present invention.
• FIG. 47 is a block diagram illustrating a semiconductor device of one embodiment of the present invention.
• FIG. 48 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
• FIGS. 49 A and 49B are top views each illustrating a semiconductor device of one embodiment of the present invention.
• FIGS. 50A and 50B are block diagrams illustrating a semiconductor device of one embodiment of the present invention.
• FIGS. 51 A and 5 IB are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention.
• FIG. 52 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
• FIGS. 53A and 53B are top views illustrating a semiconductor device of one embodiment of the present invention.
• FIGS. 54A and 54B are a flow chart illustrating one embodiment of the present invention and a perspective view illustrating a semiconductor device.
• FIGS. 55 A to 55F are perspective views each illustrating an electronic device of one embodiment of the present invention.
• FIG. 56 is an EDX mapping image of a cross section of a sample of one example.
• FIGS. 57A and 57B are BF-STEM images of cross sections of samples of one example.
• FIGS. 58A and 58B illustrate XRD measurement results and XRD analysis positions of samples of one example.
• a transistor is an element having at least three terminals of a gate, a drain, and a source.
• the transistor includes a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow between the source and the drain through the channel region.
• a channel region refers to a region through which current mainly flows.
• Source and drain Functions of a "source” and a “drain” are sometimes interchanged with each other when a transistor of opposite polarity is used or when the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be interchanged with each other in this specification and the like.
• the term "electrically connected” includes the case where components are connected through an "object having any electric function.”
• an object having any electric function there is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object.
• Examples of an "object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions, as well as an electrode and a wiring.
• a "silicon oxynitride film” refers to a film that contains oxygen at a higher proportion than nitrogen
• a "silicon nitride oxide film” refers to a film that contains nitrogen at a higher proportion than oxygen
• the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to -5° and less than or equal to 5°.
• the term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to -30° and less than or equal to 30°.
• the term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.
• the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.
• film and “layer” can be interchanged with each other depending on the case.
• conductive layer can be changed into the term “conductive film” in some cases.
• insulating film can be changed into the term “insulating layer” in some cases.
• a “semiconductor” includes characteristics of an “insulator” in some cases when, for example, the conductivity is sufficiently low. Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because the border between the "semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.
• An oxide semiconductor preferably contains at least indium.
• indium and zinc are preferably contained.
• aluminum, gallium, yttrium, tin, or the like is preferably contained.
• one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.
• an oxide semiconductor contains indium, an element , and zinc
• the element M is aluminum, gallium, yttrium, tin, or the like.
• the element M ean be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like.
• two or more of the above elements may be used in combination as the element M.
• the terms of the atomic ratio of indium to the element M and zinc in the oxide semiconductor are denoted by [In], [M], and [Zn], respectively.
• FIGS. lA and IB Conceptual diagrams of oxide semiconductors of the present invention are illustrated in FIGS. lA and IB, FIGS. 2A and 2B, FIGS. 3A and 3B, and FIGS. 4A and 4B.
• FIGS. 1A to 4B Conceptual diagrams of oxide semiconductors of the present invention are illustrated in FIGS. 1A to 4B.
• FIGS. 1A, 2A, 3A, and 4A are each a conceptual diagram of an upper surface (here, referred to as a-b plane direction) of an oxide semiconductor
• FIGS. IB, 2B, 3B, and 4B are each a conceptual diagram of a cross section (here, referred to as c-axis direction) of the oxide semiconductor formed over a substrate Sub.
• FIGS. 1A to 4B each illustrate the case where the oxide semiconductor is formed over the substrate; however, one embodiment of the present invention is not limited to this example.
• An insulating film such as a base film or an interlayer film or another semiconductor film such as an oxide semiconductor may be formed between the substrate and the oxide semiconductor.
• the oxide semiconductor of the present invention is a composite oxide semiconductor having a structure in which a region Al and a region Bl are mixed as illustrated in FIGS. 1 A and IB.
• the region Al when the atomic ratio of In to the element M in the region Al is greater than the atomic ratio of In to the element M in the region Bl, the region Al has a higher In concentration than the region B l . Therefore, in this specification, the region Al is also referred to as an In-rich region, and the region Bl is also referred to as an In-poor region.
• the In concentration in the region Al is 1.1 or more times, preferably 2 to 10 times that in the region B l .
• the region Al is an oxide containing at least In and does not necessarily contain the element M and Zn.
• a phase diagram in FIG. 5 can be used to show the atomic ratio of elements in the case where the region Al in the oxide semiconductor of the present invention contains In, the element , and Zn.
• the atomic ratio of In to the element M and Zn is denoted by x:y.z. This atomic ratio can be shown as coordinates (x:y:z) in FIG. 5. Note that the proportion of oxygen atoms is not illustrated in FIG. 5.
• a region A2 in FIG. 5 represents an example of a preferred range of atomic ratios of indium to the element M and zinc contained in the region Al .
• a region B2 in FIG. 5 represents an example of a preferred range of atomic ratios of indium to the element M and zinc contained in the region B 1.
• the region A2 with high In concentrations provides a higher conductivity than the region B2 and has a function of increasing carrier mobility (field-effect mobility). Therefore, the on-state current and carrier mobility of a transistor using an oxide semiconductor including the region Al can be increased.
• the region B2 with low In concentrations provides a lower conductivity than the region A2 and has a function of decreasing leakage current. Therefore, the off-state current of a transistor using an oxide semiconductor including the region Bl can be decreased.
• the region Al and the region Bl form a composite. That is, carrier movement occurs easily in the region Al, whereas carrier movement does not occur easily in the region Bl . Therefore, the oxide semiconductor of the present invention can be used as a material with high carrier mobility, excellent switching characteristics, and favorable semiconductor characteristics.
• the region Al is basically formed in a shape close to a circle in the a-b plane direction.
• the region Al is basically formed in a shape close to an ellipse in the c-axis direction. Therefore, the region Al has an island-like shape and can exist in a state of being three-dimensionally surrounded with the region B 1. That is, the region Al is enclosed by the region B 1.
• the region Al is distributed unevenly and irregularly in the region B l . Therefore, a plurality of regions Al connected to each other may exist. That is, in some cases, the plurality of regions Al may have a shape of overlapping circles in the a-b plane direction or a shape of ellipses whose end portions are connected in the c-axis direction. In the case where all the regions Al are connected in the a-b plane direction, the switching characteristics of a transistor, e.g., the off-state current of the transistor, are increased. Thus, the regions Al are preferably scattered in the region Bl as illustrated in FIGS. lA and IB.
• the proportion of scattered regions Al can be adjusted by changing formation conditions or composition of the composite oxide semiconductor. For example, it is possible to form a composite oxide semiconductor with a low proportion of regions Al as illustrated in FIGS. 2A and 2B or a composite oxide semiconductor with a high proportion of regions Al as illustrated in FIGS. 3A and 3B.
• the composite oxide semiconductor of the present invention does not necessarily have a low proportion of regions Al to the region Bl . In a composite oxide semiconductor with a very high proportion of regions Al, depending on the observation range, the region B l is sometimes formed in the region Al .
• the size of the island-like shape of the region Al can be adjusted as appropriate by changing, for example, the formation conditions or composition of the composite oxide semiconductor.
• the island-like regions have various sizes in the conceptual diagrams in FIGS. 1A to 3B, the regions Al with substantially the same size are scattered as shown in FIGS. 4A and 4B in some cases.
• the thickness (also referred to as diameter) of the region Al is greater than or equal to 0.1 nm and less than or equal to 5 nm, or greater than or equal to 0.3 nm and less than or equal to 3 nm in a cross-sectional EDX mapping image in some cases.
• the thickness of the region Al is preferably greater than or equal to 0.1 nm and less than or equal to 1 nm.
• an oxide semiconductor of one embodiment of the present invention is a composite oxide semiconductor in which the region Al and the region Bl are mixed and have different functions that are complementary to each other.
• an oxide semiconductor of one embodiment of the present invention is an In-Ga-Zn oxide (hereinafter referred to as IGZO), in which Ga is used as the element , the oxide semiconductor can be called complementary IGZO (abbreviation: C/IGZO).
• the oxide semiconductor is deposited with a sputtering apparatus
• a film having an atomic ratio deviated from the atomic ratio of the target is formed.
• [Zn] in the atomic ratio of a deposited film is smaller than that in the atomic ratio of the target in some cases depending on the substrate temperature during deposition.
• the illustrated regions represent preferred atomic ratios of the region Al and the region B l of the composite oxide semiconductor; a boundary therebetween is not clear.
• Oxide semiconductors can be classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
• the non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
• the CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion.
• nc-OS In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. [0070]
• the a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.
• the a-like OS has a void or a low-density region. That is, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
• Oxide semiconductors have various structures and various properties.
• the oxide semiconductor of the present invention may be a composite oxide semiconductor including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
• the region Al is preferably non-single-crystal.
• the region Bl preferably includes at least one of regions of the CAAC-OS, the polycrystalline oxide semiconductor, the nc-OS, and the like.
• the region Al and the region Bl may include different crystals.
• the transistor when the composite oxide semiconductor is used for a transistor, the transistor can have high carrier mobility and excellent switching characteristics. In addition, the transistor can have high reliability.
• An oxide semiconductor with low carrier density is preferably used for the transistor.
• an oxide semiconductor whose carrier density is lower than 8 x 10 11 /cm 3 , preferably lower than 1 x 10 11 /cm 3 , further preferably lower than 1 x 10 10 /cm 3 , and greater than or equal to 1 x 10 ⁇ 9 /cm 3 is used.
• a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density.
• a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases.
• the transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.
• the concentration of impurities in the oxide semiconductor is effective to reduce the concentration of impurities in the oxide semiconductor.
• the concentration of impurities in a film that is adjacent to the oxide semiconductor is preferably reduced.
• impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.
• the concentration of silicon or carbon in the oxide semiconductor and around an interface with the oxide semiconductor is set lower than or equal to 2 x 10 18 atoms/cm 3 , and preferably lower than or equal to 2 x 10 17 atoms/cm 3 .
• the oxide semiconductor contains alkali metal or alkaline earth metal
• defect states are formed and carriers are generated, in some cases.
• a transistor including an oxide semiconductor which contains alkali metal or alkaline earth metal is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
• the concentration of alkali metal or alkaline earth metal in the oxide semiconductor which is measured by SIMS, is lower than or equal to 1 x 10 18 atoms/cm 3 , preferably lower than or equal to 2 x 10 16 atoms/cm 3 .
• the oxide semiconductor contains nitrogen
• the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density.
• a transistor including an oxide semiconductor which contains nitrogen is likely to be normally-on.
• nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration measured by SIMS is set, for example, lower than 5 10 19 atoms/cm 3 , preferably lower than or equal to 5 18 toms/cm 3
• x x 10 a further preferably lower than or equal to 1 x 10 18 atoms/cm 3 , and still further preferably lower than or equal to 5 x 10 17 atoms/cm 3 .
• Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy (Vo), in some cases. Due to entry of hydrogen into the oxygen vacancy (Vo), an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor that contains hydrogen is likely to be normally-on. Accordingly, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
• the hydrogen concentration measured by SIMS is set lower than 1 x 10 20 atoms/cm 3 , preferably lower than 1 19 3 , further preferably lower than 5 18 oms/cm 3
• x 10 atoms/cm x 10 at and still further preferably lower than 1 x 10 18 atoms/cm 3 .
• oxygen vacancies (Vo) in the oxide semiconductor can be reduced by introduction of oxygen into the oxide semiconductor. That is, the oxygen vacancies (Vo) in the oxide semiconductor disappear when the oxygen vacancies (Vo) are filled with oxygen. Accordingly, diffusion of oxygen in the oxide semiconductor can reduce the oxygen vacancies (Vo) in a transistor and improve the reliability of the transistor.
• an oxide in which oxygen content is higher than that in the stoichiometric composition is provided in contact with the oxide semiconductor. That is, in the oxide, a region including oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as an excess-oxygen region) is preferably formed.
• an oxide including an excess-oxygen region is provided in a base film, an interlayer film, or the like in the vicinity of the transistor, whereby oxygen vacancies in the transistor are reduced, and the reliability can be improved.
• the transistor When an oxide semiconductor with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.
• the oxide semiconductor is preferably deposited at a temperature higher than or equal to room temperature and lower than 140 °C.
• room temperature includes not only the case where temperature control is not performed but also the case where temperature control is performed.
• a rare gas typically argon
• oxygen or a mixed gas of a rare gas and oxygen
• the proportion of oxygen to the rare gas is more than or equal to 5% and less than or equal to 30%, preferably more than or equal to 7% and less than or equal to 20%.
• the sputtering gas contains oxygen
• oxygen can be added to a film under the oxide semiconductor and an excess-oxygen region can be provided at the same time as the deposition of the oxide semiconductor.
• increasing the purity of a sputtering gas is necessary.
• a gas which is highly purified to have a dew point of -40 °C or lower, preferably -80 °C or lower, further preferably -100 °C or lower, still further preferably -120 °C or lower is used as a sputtering gas, i.e., the oxygen gas or the argon gas, entry of moisture or the like into the oxide semiconductor can be minimized.
• a chamber in a sputtering apparatus is preferably evacuated to be a high vacuum state (to the degree of about 5 x 10 ⁇ 7 Pa to 1 x 10 ⁇ 4 Pa) with an adsorption vacuum evacuation pump such as a cryopump in order to remove water or the like, which serves as an impurity for the oxide semiconductor, as much as possible.
• an adsorption vacuum evacuation pump such as a cryopump
• a turbo molecular pump and a cold trap are preferably combined so as to prevent a backflow of a gas, especially a gas containing carbon or hydrogen from an exhaust system to the inside of the chamber.
• an In-Ga-Zn metal oxide target can be used as a target.
• the target may be rotated or moved.
• a magnet unit is oscillated vertically and/or horizontally during the deposition, whereby the composite oxide semiconductor of the present invention can be formed.
• the target may be rotated or moved with a beat (also referred to as rhythm, pulse, frequency, period, cycle, or the like) of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• the magnet unit may be oscillated with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz. Note that the details of the sputtering apparatus will be described in a later embodiment.
• the rare gas or the oxygen gas is ionized to be separated into cations and electrons, and plasma is created.
• the cations in the plasma are accelerated toward the target by a potential applied to a target holder.
• Sputtered particles are generated when the cations collide with the In-Ga-Zn metal oxide target, and the sputtered particles are deposited on the substrate.
• Ga and Zn which have lower relative atomic masses than In, are preferentially sputtered from the target.
• the sputtered In, Ga, and Zn are bonded to oxygen and then deposited to the substrate, whereby the region Bl is deposited.
• In is segregated at the surface of the target.
• the segregated In having a structure like a plurality of particles is bonded to oxygen, collides with the region B 1 deposited earlier, and spreads into a shape close to a circle, whereby the region Al having an island-like shape is deposited. Note that since the segregated In is sputtered, In, Ga, and Zn exist at the surface of the target in a state close to the original atomic ratio.
• Ga and Zn which have lower relative atomic masses than In, are preferentially sputtered from the target.
• In is segregated at the surface of the target.
• the region Bl is deposited again over the regions Bl and Al deposited earlier, whereby the region B l is formed such that the region Al is surrounded therewith.
• FIGS. 1 A and IB The composite oxide semiconductor in which the region Al and the region B l are mixed as illustrated in FIGS. 1 A and IB, FIGS. 2A and 2B, FIGS. 3A and 3B, or FIGS. 4A and 4B is presumed to be formed after the above-described deposition model.
• the region Al which is high in In and has an atomic ratio shown in the region A2 and the region B l which is low in In and has an atomic ratio shown in the region B2 are mixed to form a composite oxide semiconductor. That is, carrier movement occurs easily in the region Al, whereas carrier movement does not occur easily in the region Bl . Therefore, the oxide semiconductor of the present invention can be used as a material with high carrier mobility, excellent switching characteristics, and favorable semiconductor characteristics.
• sputtering apparatuses and a deposition apparatus with which the oxide of one embodiment of the present invention can be deposited are described with reference to FIGS. 6A and 6B, FIGS. 7A and 7B, FIGS. 8A to 8C, FIGS. 9A and 9B, FIG. 10, and FIGS. 11A to l lC.
• the following descriptions of the sputtering apparatuses are made for easy understanding or the explanation of the operation during deposition, on the assumption that a substrate, a target, and the like are provided. Note that the substrate, the target, and the like are provided by a user; thus, the sputtering apparatus of one embodiment of the present invention does not necessarily include the substrate and the target.
• Examples of sputtering apparatuses include a parallel-plate-type sputtering apparatus and a facing-targets sputtering apparatus. Note that deposition using a parallel-plate-type sputtering apparatus can also be referred to as parallel electrode sputtering (PESP), and deposition using a facing-targets sputtering apparatus can also be referred to as vapor deposition sputtering (VDSP).
• PESP parallel electrode sputtering
• VDSP vapor deposition sputtering
• FIG. 6A is a cross-sectional view of a deposition chamber 601 that is a parallel-plate-type sputtering apparatus.
• the deposition chamber 601 in FIG. 6 A includes a target holder 620, a backing plate 610, a target 600, a magnet unit 630, and a substrate holder 670.
• the target 600 is placed over the backing plate 610.
• the backing plate 610 is placed over the target holder 620.
• the magnet unit 630 is placed under the target 600 with the backing plate 610 positioned therebetween.
• the substrate holder 670 faces the target 600.
• a magnet unit means a group of magnets.
• the term “magnet unit” can be replaced with “cathode,” “cathode magnet,” “magnetic member,” “magnetic part,” or the like.
• the magnet unit 630 includes a magnet 630N, a magnet 630S, and a magnet holder 632. Note that in the magnet unit 630, the magnet 630N and the magnet 630S are placed over the magnet holder 632. The magnet 630N and the magnet 630S are spaced. When a substrate 660 is transferred into the deposition chamber 601, the substrate 660 is placed on the substrate holder 670.
• the target holder 620 and the backing plate 610 are fixed to each other with a screw (e.g., a bolt) and have the same potential.
• the target holder 620 has a function of supporting the target 600 with the backing plate 610 positioned therebetween.
• the target 600 is fixed to the backing plate 610.
• the target 600 can be fixed to the backing plate 610 with a bonding member containing a low-melting-point metal such as indium.
• FIG. 6A illustrates a magnetic line of force 680a and a magnetic line of force 680b formed by the magnet unit 630.
• the magnetic line of force 680a is one of magnetic lines of force that form a horizontal magnetic field in the vicinity of the top surface of the target 600.
• the vicinity of the top surface of the target 600 corresponds to a region in which the vertical distance from the target 600 is, for example, greater than or equal to 0 mm and less than or equal to 10 mm, in particular, greater than or equal to 0 mm and less than or equal to 5 mm.
• the magnetic line of force 680b is one of magnetic lines of force that form a horizontal magnetic field in a plane apart from the top surface of the magnet unit 630 by a vertical distance d.
• the vertical distance d is, for example, greater than or equal to 0 mm and less than or equal to 20 mm or greater than or equal to 5 mm and less than or equal to 15 mm.
• the magnetic flux density of the horizontal magnetic field on the top surface of the substrate 660 can be greater than or equal to 10 G and less than or equal to 100 G, preferably greater than or equal to 15 G and less than or equal to 60 G, further preferably greater than or equal to 20 G and less than or equal to 40 G.
• the magnetic flux density of the horizontal magnetic field may be measured when the magnetic flux density of the vertical magnetic field is 0 G.
• the magnetic flux density of the magnetic field in the deposition chamber 601 By setting the magnetic flux density of the magnetic field in the deposition chamber 601 to be in the above range, an oxide with high density and high crystallinity can be deposited.
• the deposited oxide hardly includes a plurality of kinds of crystalline phases and has a substantially single crystalline phase.
• FIG. 6B is a top view of the magnet unit 630.
• the magnet 630N having a circular or substantially circular shape and the magnet 630S having a circular or substantially circular shape are fixed to the magnet holder 632.
• the magnet unit 630 can be rotated about a normal vector at the center of the top surface of the magnet unit 630 or a normal vector substantially at the center of the top surface of the magnet unit 630.
• the magnet unit 630 may be rotated with a beat (also referred to as rhythm, pulse, frequency, period, cycle, or the like) of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• a beat also referred to as rhythm, pulse, frequency, period, cycle, or the like
• a region where a magnetic field on the target 600 is intense changes as the magnet unit 630 is rotated.
• the region with an intense magnetic field is a high-density plasma region; thus, sputtering of the target 600 easily occurs in the vicinity of the region.
• the region with an intense magnetic field is fixed, only a specific region of the target 600 is used.
• plasma 640 is generated between the target 600 and the substrate 660, and the target 600 can be uniformly used. By rotating the magnet unit 630, a film with a uniform thickness and uniform quality can be deposited.
• the direction of the magnetic line of force on the top surface of the substrate 660 can also be changed.
• the magnet unit 630 is rotated in this example, one embodiment of the present invention is not limited to this example.
• the magnet unit 630 may be oscillated vertically and/or horizontally.
• the magnet unit 630 may be oscillated with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• the target 600 may be rotated or moved.
• the target 600 may be rotated or moved with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• the direction of a magnetic line of force on the top surface of the substrate 660 may be changed relatively by rotating the substrate 660.
• the deposition chamber 601 may have a water channel inside or under the backing plate
• the backing plate 610 and the target 600 are preferably adhered to each other with a bonding member because the cooling capability is increased.
• a gasket is preferably provided between the target holder 620 and the backing plate 610, in which case an impurity is less likely to enter the deposition chamber 601 from the outside, the water channel, or the like.
• the magnet 63 ON and the magnet 63 OS are placed such that their surfaces on the target 600 side have opposite polarities.
• the case where the pole of the magnet 630N on the target 600 side is the north pole and the pole of the magnet 630S on the target 600 side is the south pole is described. Note that the layout of the magnets and the poles in the magnet unit 630 is not limited to that described here or that illustrated in FIG. 6A.
• a potential VI applied to a terminal VI connected to the target holder 620 is, for example, lower than a potential V2 applied to a terminal V2 connected to the substrate holder 670.
• the potential V2 applied to the terminal V2 connected to the substrate holder 670 is, for example, the ground potential.
• a potential V3 applied to a terminal V3 connected to the magnet holder 632 is, for example, the ground potential. Note that the potentials applied to the terminals VI, V2, and V3 are not limited to the above description. Not all the target holder 620, the substrate holder 670, and the magnet holder 632 are necessarily supplied with potentials. For example, the substrate holder 670 may be electrically floating.
• the potential VI is applied to the terminal VI connected to the target holder 620 (i.e., a DC sputtering method is employed) in the example illustrated in FIG. 6A
• a DC sputtering method is employed
• one embodiment of the present invention is not limited thereto.
• FIG. 6 A illustrates an example where the backing plate 610 and the target holder 620 are not electrically connected to the magnet unit 630 and the magnet holder 632, but electrical connection is not limited thereto.
• the backing plate 610 and the target holder 620 may be electrically connected to the magnet unit 630 and the magnet holder 632, and the backing plate 610, the target holder 620, the magnet unit 630, and the magnet holder 632 may have the same potential.
• the temperature of the substrate 660 may be set high. By setting the temperature of the substrate 660 high, migration of sputtered particles on the top surface of the substrate 660 can be promoted. Thus, an oxide with higher density and higher crystallinity can be deposited.
• the temperature of the substrate 660 is, for example, higher than or equal to 100 °C and lower than or equal to 450 °C, preferably higher than or equal to 150 °C and lower than or equal to 400 °C, more preferably higher than or equal to 170 °C and lower than or equal to 350 °C.
• a mixed gas of oxygen and a rare gas such as argon is preferably used as the deposition gas.
• the proportion of oxygen in the whole deposition gas is less than 50 vol%, preferably less than or equal to 33 vol%, further preferably less than or equal to 20 vol%, and still further preferably less than or equal to 15 vol%.
• the vertical distance between the target 600 and the substrate 660 is greater than or equal to 10 mm and less than or equal to 600 mm, preferably greater than or equal to 20 mm and less than or equal to 400 mm, more preferably greater than or equal to 30 mm and less than or equal to 200 mm, further more preferably greater than or equal to 40 mm and less than or equal to 100 mm.
• the vertical distance between the target 600 and the substrate 660 can be, in some cases, small enough to suppress a decrease in the energy of the sputtered particles until the sputtered particles reach the substrate 660.
• the vertical distance between the target 600 and the substrate 660 can be, in some cases, large enough to make the incident direction of the sputtered particle substantially vertical to the substrate 660, so that damage to the substrate 660 caused by collision of the sputtered particles can be reduced.
• FIG. 7 A illustrates an example of a deposition chamber different from that in FIG. 6A.
• the deposition chamber 601 in FIG. 7 A includes a target holder 620a, a target holder 620b, a backing plate 610a, a backing plate 610b, a target 600a, a target 600b, a magnet unit 630a, a magnet unit 630b, a member 642, and the substrate holder 670.
• the target 600a is placed over the backing plate 610a.
• the backing plate 610a is placed over the target holder 620a.
• the magnet unit 630a is placed under the target 600a with the backing plate 610a positioned therebetween.
• the target 600b is placed over the backing plate 610b.
• the backing plate 610b is placed over the target holder 620b.
• the magnet unit 630b is placed under the target 600b with the backing plate 610b positioned therebetween.
• the magnet unit 630a includes a magnet 630N1, a magnet 630N2, the magnet 630S, and the magnet holder 632. Note that in the magnet unit 630a, the magnet 630N1, the magnet 630N2, and the magnet 630S are placed over the magnet holder 632. The magnet 630N1, the magnet 630N2, and the magnet 630S are spaced. Note that the magnet unit 630b has a structure similar to that of the magnet unit 630a. When the substrate 660 is transferred into the deposition chamber 601, the substrate 660 is placed on the substrate holder 670.
• the target 600a, the backing plate 610a, and the target holder 620a are separated from the target 600b, the backing plate 610b, and the target holder 620b by the member 642.
• the member 642 is preferably an insulator.
• the member 642 may be a conductor or a semiconductor.
• the member 642 may be a conductor or a semiconductor whose surface is covered with an insulator.
• the target holder 620a and the backing plate 610a are fixed to each other with a screw (e.g., a bolt) and have the same potential.
• the target holder 620a has a function of supporting the target 600a with the backing plate 610a positioned therebetween.
• the target holder 620b and the backing plate 610b are fixed to each other with a screw (e.g., a bolt) and have the same potential.
• the target holder 620b has a function of supporting the target 600b with the backing plate 610b positioned therebetween.
• the backing plate 610a has a function of fixing the target 600a.
• the backing plate 610b has a function of fixing the target 600b.
• FIG. 7 A illustrates the magnetic line of force 680a and the magnetic line of force 680b formed by the magnet unit 630a.
• the magnetic line of force 680a is one of magnetic lines of force that form a horizontal magnetic field in the vicinity of the top surface of the target 600a.
• the vicinity of the top surface of the target 600a corresponds to a region in which the vertical distance from the target 600a is, for example, greater than or equal to 0 mm and less than or equal to 10 mm, in particular, greater than or equal to 0 mm and less than or equal to 5 mm.
• the magnetic line of force 680b is one of magnetic lines of force that form a horizontal magnetic field in a plane apart from the top surface of the magnet unit 630a by a vertical distance d.
• the vertical distance d is, for example, greater than or equal to 0 mm and less than or equal to 20 mm or greater than or equal to 5 mm and less than or equal to 15 mm.
• the magnetic flux density of the horizontal magnetic field on the top surface of the substrate 660 can be greater than or equal to 10 G and less than or equal to 100 G, preferably greater than or equal to 15 G and less than or equal to 60 G, further preferably greater than or equal to 20 G and less than or equal to 40 G.
• the magnetic flux density of the magnetic field in the deposition chamber 601 By setting the magnetic flux density of the magnetic field in the deposition chamber 601 to be in the above range, an oxide with high density and high crystallinity can be deposited.
• the deposited oxide hardly includes a plurality of kinds of crystalline phases and has a substantially single crystalline phase.
• magnet unit 630b forms magnetic lines of force similar to those formed by the magnet unit 630a.
• FIG. 7B is a top view of the magnet units 630a and 630b.
• the magnet 630N1 having a rectangular or substantially rectangular shape
• the magnet 630N2 having a rectangular or substantially rectangular shape
• the magnet 630S having a rectangular or substantially rectangular shape are fixed to the magnet holder 632.
• the magnet unit 630a can be oscillated horizontally as shown in FIG. 7B.
• the magnet unit 630a may be oscillated with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• a region where a magnetic field on the target 600a is intense changes as the magnet unit 630a is oscillated.
• the region with an intense magnetic field is a high-density plasma region; thus, sputtering of the target 600a easily occurs in the vicinity of the region.
• the region with an intense magnetic field is fixed, only a specific region of the target 600a is used.
• the magnet unit 630a is oscillated as shown in FIG. 7B, plasma 640 is generated between the target 600a and the substrate 660, and the target 600a can be uniformly used.
• a film with a uniform thickness and uniform quality can be deposited.
• the state of the magnetic lines of force on the top surface of the substrate 660 can also be changed.
• the magnet unit 630a and the magnet unit 630b are oscillated in this example, one embodiment of the present invention is not limited to this example.
• the magnet unit 630a and the magnet unit 630b may be rotated.
• the magnet unit 630a and the magnet unit 630b may be rotated with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• the target 600 may be rotated or moved.
• the target 600 may be rotated or moved with a beat of greater than or equal to 0.1 Hz and less than or equal to 1 kHz.
• the state of magnetic lines of force on the top surface of the substrate 660 can be changed relatively by rotating the substrate 660. These methods may be combined.
• the deposition chamber 601 may have a water channel inside or under the backing plate 610a and the backing plate 610b.
• a fluid air, nitrogen, a rare gas, water, oil, or the like
• the backing plate 610a and the target 600a are preferably adhered to each other with a bonding member because the cooling capability is increased.
• the backing plate 610b and the target 600b are preferably adhered to each other with a bonding member because the cooling capability is increased.
• a gasket is preferably provided between the target holder 620a and the backing plate 610a, in which case an impurity is less likely to enter the deposition chamber 601 from the outside, the water channel, or the like.
• a gasket is preferably provided between the target holder 620b and the backing plate 610b, in which case an impurity is less likely to enter the deposition chamber 601 from the outside, the water channel, or the like.
• the magnets 630N1 and 630N2 and the magnet 630S are placed such that their surfaces on the target 600a side have opposite polarities.
• the case where the pole of each of the magnets 630N1 and 630N2 on the target 600a side is the north pole and the pole of the magnet 630S on the target 600a side is the south pole is described.
• the layout of the magnets and the poles in the magnet unit 630a is not limited to that described here or that illustrated in FIG. 7 A. The same applies to the magnet unit 630b.
• a potential applied to the terminal VI connected to the target holder 620a and a potential applied to the terminal V4 connected to the target holder 620b may be alternately switched between a high level and a low level.
• the potential applied to the terminal VI is one of the high level and the low level
• the potential applied to the terminal V4 is the other of the high level and the low level.
• a potential applied to the terminal V2 connected to the substrate holder 670 is, for example, the ground potential.
• a potential applied to the terminal V3 connected to the magnet holder 632 is, for example, the ground potential. Note that the potentials applied to the terminals VI, V2, V3, and V4 are not limited to the above description.
• the substrate holder 670 may be electrically floating.
• the potential applied to the terminal VI connected to the target holder 620a and the potential applied to the terminal V4 connected to the target holder 620b are alternately switched between the high level and the low level (i.e., an AC sputtering method) in the example illustrated in FIG. 7A; however, one embodiment of the present invention is not limited thereto.
• FIG. 7 A illustrates an example where the backing plate 610a and the target holder 620a are not electrically connected to the magnet unit 630a and the magnet holder 632, but electrical connection is not limited thereto.
• the backing plate 610a and the target holder 620a may be electrically connected to the magnet unit 630a and the magnet holder 632, and the backing plate 610a, the target holder 620a, the magnet unit 630a, and the magnet holder 632 may have the same potential.
• the backing plate 610b and the target holder 620b are not electrically connected to the magnet unit 630b and the magnet holder 632 in the example, but electrical connection is not limited thereto.
• the backing plate 610b and the target holder 620b may be electrically connected to the magnet unit 630b and the magnet holder 632, and the backing plate 610b, the target holder 620b, the magnet unit 630b, and the magnet holder 632 may have the same potential.
• the temperature of the substrate 660 may be set high. By setting the temperature of the substrate 660 high, migration of sputtered particles on the top surface of the substrate 660 can be promoted. Thus, an oxide with higher density and higher crystallinity can be deposited.
• the temperature of the substrate 660 is, for example, higher than or equal to 100 °C and lower than or equal to 450 °C, preferably higher than or equal to 150 °C and lower than or equal to 400 °C, more preferably higher than or equal to 170 °C and lower than or equal to 350 °C.
• a mixed gas of oxygen and a rare gas such as argon is preferably used as the deposition gas.
• the proportion of oxygen in the whole deposition gas is less than 50 vol%, preferably less than or equal to 33 vol%, further preferably less than or equal to 20 vol%, and still further preferably less than or equal to 15 vol%.
• the vertical distance between the target 600a and the substrate 660 is greater than or equal to 10 mm and less than or equal to 600 mm, preferably greater than or equal to 20 mm and less than or equal to 400 mm, more preferably greater than or equal to 30 mm and less than or equal to 200 mm, further more preferably greater than or equal to 40 mm and less than or equal to 100 mm.
• the vertical distance between the target 600a and the substrate 660 can be, in some cases, small enough to suppress a decrease in the energy of the sputtered particles until the sputtered particles reach the substrate 660.
• the vertical distance between the target 600a and the substrate 660 can be, in some cases, large enough to make the incident direction of the sputtered particle substantially vertical to the substrate 660, so that damage to the substrate 660 caused by collision of the sputtered particles can be reduced.
• the vertical distance between the target 600b and the substrate 660 is greater than or equal to 10 mm and less than or equal to 600 mm, preferably greater than or equal to 20 mm and less than or equal to 400 mm, more preferably greater than or equal to 30 mm and less than or equal to 200 mm, further more preferably greater than or equal to 40 mm and less than or equal to 100 mm.
• the vertical distance between the target 600b and the substrate 660 can be, in some cases, small enough to suppress a decrease in the energy of the sputtered particles until the sputtered particles reach the substrate 660.
• the vertical distance between the target 600b and the substrate 660 can be, in some cases, large enough to make the incident direction of the sputtered particle substantially vertical to the substrate 660, so that damage to the substrate 660 caused by collision of the sputtered particles can be reduced.
• FIG. 8A is a cross-sectional view of a deposition chamber in a facing-targets sputtering apparatus.
• the deposition chamber illustrated in FIG. 8 A includes the target 600a, the target 600b, the backing plate 610a for holding the target 600a, the backing plate 610b for holding the target 600b, the magnet unit 630a placed behind the target 600a with the backing plate 610a positioned therebetween, and the magnet unit 630b placed behind the target 600b with the backing plate 610b positioned therebetween.
• the substrate holder 670 is placed between the target 600a and the target 600b.
• the substrate holder 670 is placed above a region where the target 600a and the target 600b face each other (also referred to as a region between targets).
• the substrate 660 is transferred into the deposition chamber, and then the substrate 660 is fixed to the substrate holder 670.
• the substrate holder 670 is placed above the region between targets, but may be placed below the region. Alternatively, the substrate holders 670 may be placed above and below the region. Providing the substrate holders 670 above and below the region allows deposition on two or more substrates at once, leading to an increase in productivity.
• a power source 690 and a power source 691 for applying potentials are connected to the backing plates 610a and 610b. It is preferable to use AC power sources, which alternately apply a high-level potential and a low-level potential to the backing plate 610a and the backing plate 610b.
• AC power sources are used as the power sources 690 and 691 illustrated in FIG. 8 A, one embodiment of the present invention is not limited thereto.
• RF power sources, DC power sources, or the like can be used as the power sources 690 and 691.
• different kinds of power sources may be used as the power sources 690 and 691.
• the substrate holder 670 is preferably connected to GND.
• the substrate holder 670 may be in a floating state.
• FIGS. 8B and 8C each show potential distribution of plasma 640 along dashed-dotted line A-B in FIG. 8A.
• FIG. 8B shows the potential distribution in the case where a high potential is applied to the backing plate 610a and a low potential is applied to the backing plate 610b. In that case, a cation is accelerated toward the target 600b.
• FIG. 8C shows the potential distribution in the case where a low potential is applied to the backing plate 610a and a high potential is applied to the backing plate 610b. In that case, a cation is accelerated toward the target 600a.
• the deposition can be performed by alternating the state in FIG. 8B and the state in FIG. 8C.
• the target 600a and the target 600b are parallel to each other.
• the magnet unit 630a and the magnet unit 630b are placed so that opposite poles face each other. Magnetic lines of force run from the magnet unit 630b to the magnet unit 630a. Therefore, in the deposition, the plasma 640 is confined in the magnetic field formed by the magnet units 630a and 630b.
• the substrate holder 670 and the substrate 660 are located outside the plasma 640. The substrate 660 is not exposed to a high electric field region of the plasma 640, leading to a reduction in damage due to the plasma 640.
• the facing-targets sputtering apparatus can stably generate plasma even in a high vacuum.
• deposition can be performed at a pressure higher than or equal to 0.005 Pa and lower than or equal to 0.09 Pa, for example. As a result, the concentration of impurities contained during deposition can be reduced.
• the use of the facing-targets sputtering apparatus allows deposition in a high vacuum or deposition with less plasma damage and thus can provide a film with high crystallinity even when the temperature of the substrate 660 is low (e.g., higher than or equal to 10 °C and lower than 100 °C).
• FIG. 9 A A structure illustrated in FIG. 9 A is different from that illustrated in FIG. 8 A in that the target 600a and the target 600b that face each other are not parallel but inclined to each other (in V-shape).
• the description for FIG. 8A is referred to for the description except for the arrangement of the targets.
• the magnet unit 630a and the magnet unit 630b are placed so that opposite poles face each other.
• the substrate holder 670 and the substrate 660 are placed above the region between targets. With the targets 600a and 600b placed as illustrated in FIG. 9A, the proportion of sputtered particles that reach the substrate 660 can be increased; accordingly, the deposition rate can be increased.
• FIG. 9B illustrates another example of a facing-targets sputtering apparatus.
• FIG. 9B is a schematic cross-sectional view of a deposition chamber of a facing-targets sputtering apparatus. Unlike in the deposition chamber illustrated in FIG. 8A, a target shield 622 and a target shield 623 are provided. The power source 691 connected to the backing plates 610a and 610b is also provided. The substrate holder 670 is placed above the region between targets. Thus, the substrate 660 is not exposed to a high electric field region of the plasma 640, leading to a reduction in damage due to the plasma 640.
• the substrate holder 670 is placed above the region between targets, but may be placed below the region. Alternatively, the substrate holders 670 may be placed above and below the region. Providing the substrate holders 670 above and below the region allows deposition on two or more substrates at once, leading to an increase in productivity.
• the target shields 622 and 623 are connected to GND as illustrated in FIG. 9B. This means that the plasma 640 is generated by a potential difference between the backing plates 610a and 610b to which a potential of the power source 691 is applied and the target shields 622 and 623 to which GND is applied.
• plasma is confined by magnetic fields between targets; thus, plasma damage to a substrate can be reduced. Furthermore, a deposited film can provide improved step coverage because an incident angle of a sputtered particle to a substrate can be made smaller by the inclination of the target. Moreover, deposition in a high vacuum enables the concentration of impurities contained in the film to be reduced.
• a parallel-plate-type sputtering apparatus or an ion beam sputtering apparatus may be provided in the deposition chamber.
• a deposition apparatus of one embodiment of the present invention including a deposition chamber in which a sputtering target can be placed will be described below.
• FIG. 10 is a schematic top view of a single wafer multi-chamber deposition apparatus 2700.
• the deposition apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 including a cassette port 2761 for storing substrates and an alignment port 2762 for performing alignment of substrates, an atmosphere-side substrate transfer chamber 2702 through which a substrate is transferred from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a where a substrate is carried in and the pressure is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b where a substrate is carried out and the pressure is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 where a substrate is transferred in a vacuum, a substrate heating chamber 2705 where a substrate is heated, and deposition chambers 2706a, 2706b, and 2706c in each of which a sputtering target is placed for deposition. Note that for the deposition chambers 2706a, 2706b, and 2706c, the structure of the
• the atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the substrate heating chamber 2705 and the deposition chambers 2706a, 2706b, and 2706c.
• gate valves 2764 are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702 can be independently kept in a vacuum state.
• a transfer robot 2763 is provided, which is capable of transferring substrates.
• the substrate heating chamber 2705 also serve as a plasma treatment chamber.
• substrates can be transferred without being exposed to the air between treatments, and adsorption of impurities to substrates can be suppressed.
• the order of deposition, heat treatment, or the like can be freely determined. Note that the number of the transfer chambers, the number of the deposition chambers, the number of the load lock chambers, the number of the unload lock chambers, and the number of the substrate heating chambers are not limited to the above, and the numbers thereof can be set as appropriate depending on the space for placement and the process conditions.
• FIG. 11 A, FIG. 11B, and FIG. 11C are a cross-sectional view taken along dashed-dotted line X1-X2, a cross-sectional view taken along dashed-dotted line Y1-Y2, and a cross-sectional view taken along dashed-dotted line Y2-Y3, respectively, in the deposition apparatus 2700 illustrated in FIG. 10.
• FIG. 11 A illustrates a cross section of the substrate heating chamber 2705 and the transfer chamber 2704, and the substrate heating chamber 2705 includes a plurality of heating stages 2765 which can hold a substrate.
• the substrate heating chamber 2705 is connected to a vacuum pump 2770 through a valve.
• a vacuum pump 2770 a dry pump and a mechanical booster pump can be used, for example.
• a resistance heater may be used for heating, for example.
• heat conduction or heat radiation from a medium such as a heated gas may be used as the heating mechanism.
• rapid thermal annealing RTA
• GRTA gas rapid thermal annealing
• LRTA lamp rapid thermal annealing
• the LRTA is a method for heating an object by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.
• heat treatment is performed using a high-temperature gas.
• An inert gas is used as the gas.
• the substrate heating chamber 2705 is connected to a refiner 2781 through a mass flow controller 2780.
• the mass flow controller 2780 and the refiner 2781 can be provided for each of a plurality of kinds of gases, only one mass flow controller 2780 and one refiner 2781 are provided for easy understanding.
• a gas whose dew point is -80 °C or lower, preferably -100 °C or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used.
• the transfer chamber 2704 includes the transfer robot 2763.
• the transfer robot 2763 can transfer a substrate to each chamber.
• the transfer chamber 2704 is connected to the vacuum pump 2770 and a cryopump 2771 through valves. Owing to such a structure, exhaust is performed using the vacuum pump 2770 from the atmospheric pressure to low or medium vacuum (approximately 0.1 Pa to several hundred pascals) and then the valves are switched and exhaust is performed using the cryopump 2771 from the medium vacuum to high or ultra-high vacuum (0.1 Pa to 1 x 10 ⁇ 7 Pa).
• cryopumps 2771 may be connected in parallel to the transfer chamber 2704.
• exhaust can be performed using any of the other cryopumps.
• the above regeneration refers to treatment for discharging molecules (or atoms) entrapped in the cryopump.
• molecules (or atoms) are entrapped too much in a cryopump, the exhaust capability of the cryopump is lowered; therefore, regeneration is performed regularly.
• FIG. 11B illustrates a cross section of the deposition chamber 2706b, the transfer chamber 2704, and the load lock chamber 2703a.
• the deposition chamber 2706b illustrated in FIG. 11B includes a target 2766a, a target 2766b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, and power sources 2791.
• each of the targets 2766a and 2766b is fixed to a target holder with a backing plate provided therebetween.
• the power source 2791 is electrically connected to each of the targets 2766a and 2766b.
• the magnet unit 2790a is placed on a back side of the target 2766a, and the magnet unit 2790b is placed on a back side of the target 2766b.
• the target shield 2767a is provided so as to surround an end portion of the target 2766a, and the target shield 2767b is provided so as to surround an end portion of target 2766b.
• a substrate 2769 is supported by the substrate holder 2768.
• the substrate holder 2768 is fixed to the deposition chamber 2706b by an adjustment member 2784. Owing to the adjustment member 2784, the substrate holder 2768 can be moved.
• the substrate holder 2768 is placed above a region between the target 2766a and the target 2766b (also referred to as a region between targets).
• the substrate holder 2768 may include a substrate holding mechanism which holds the substrate 2769, a heater which heats the substrate 2769 from the back side, or the like.
• the substrate holder 2768 is placed above the region between targets, but may be placed below the region. Alternatively, the substrate holders 2768 may be placed above and below the region. Providing the substrate holders 2768 above and below the region allows deposition on two or more substrates at once, leading to an increase in productivity.
• the target shields 2767 can suppress deposition of a particle which is sputtered from the target 2766 on a region where deposition is not needed. Moreover, the target shields 2767 are preferably processed to prevent accumulated sputtered particles from being separated. For example, blasting treatment which increases surface roughness may be performed, or roughness may be formed on the surfaces of the target shields 2767.
• the deposition chamber 2706b is connected to the mass flow controller 2780 through a gas heating mechanism 2782, and the gas heating mechanism 2782 is connected to the refiner 2781 through the mass flow controller 2780.
• a gas which is introduced to the deposition chamber 2706b can be heated to a temperature higher than or equal to 40 °C and lower than or equal to 400 °C.
• the gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2781 can be provided for each of a plurality of kinds of gases, only one gas heating mechanism 2782, one mass flow controller 2780, and one refiner 2781 are provided for easy understanding.
• a gas whose dew point is -80 °C or lower, preferably -100 °C or lower can be used; for example, an oxygen gas, a nitrogen gas, and a rare gas (e.g., an argon gas) are used.
• the length of a pipe between the refiner and the deposition chamber 2706b is less than or equal to 10 m, preferably less than or equal to 5 m, and further preferably less than or equal to 1 m.
• the length of the pipe is less than or equal to 10 m, less than or equal to 5 m, or less than or equal to 1 m, the effect of the release of gas from the pipe can be reduced accordingly.
• a metal pipe the inside of which is covered with iron fluoride, aluminum oxide, chromium oxide, or the like can be used.
• the amount of released gas containing impurities is made small and the entry of impurities into the gas can be reduced as compared with a SUS316L-EP pipe, for example.
• a high-performance ultra-compact metal gasket joint may be used as a joint of the pipe.
• a structure where all the materials of the pipe are metals is preferable because the effect of the generated released gas or the external leakage can be reduced as compared with a structure where a resin or the like is used.
• the deposition chamber 2706b is connected to a turbo molecular pump 2772 and the vacuum pump 2770 through valves.
• the deposition chamber 2706b is provided with a cryotrap 2751.
• the cryotrap 2751 is a mechanism which can adsorb a molecule (or an atom) having a relatively high melting point, such as water.
• the turbo molecular pump 2772 is capable of stably removing a large-sized molecule (or atom), needs low frequency of maintenance, and thus enables high productivity, whereas it has a low capability in removing hydrogen and water.
• the cryotrap 2751 is connected to the deposition chamber 2706b so as to have a high capability in removing water or the like.
• the temperature of a freezer of the cryotrap 2751 is set to be lower than or equal to 100 K, preferably lower than or equal to 80 K.
• the cryotrap 2751 includes a plurality of freezers
• the temperature of a first-stage freezer may be set to be lower than or equal to 100 K and the temperature of a second-stage freezer may be set to be lower than or equal to 20 K.
• a titanium sublimation pump is used instead of the cryotrap, a higher vacuum can be achieved in some cases.
• Using an ion pump instead of a cryopump or a turbo molecular pump can also achieve higher vacuum in some cases.
• the exhaust method of the deposition chamber 2706b is not limited to the above, and a structure similar to that in the exhaust method described above for the transfer chamber 2704 (the exhaust method using the cryopump and the vacuum pump) may be employed. Needless to say, the exhaust method of the transfer chamber 2704 may have a structure similar to that of the deposition chamber 2706b (the exhaust method using the turbo molecular pump and the vacuum pump).
• the back pressure (total pressure) and the partial pressure of each gas molecule (atom) are preferably set as follows.
• the back pressure and the partial pressure of each gas molecule (atom) in the deposition chamber 2706b need to be noted because impurities might enter a film to be formed.
• the back pressure (total pressure) is less than or equal to
• the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 18 is less than or equal to 3 x 10 ⁇ 5 Pa, preferably less than or equal to 1 x 10 ⁇ 5 Pa, and further preferably less than or equal to 3 x 10 ⁇ 6 Pa.
• the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 28 is less than or equal to 3 x 10 ⁇ 5 Pa, preferably less than or equal to 1 x 10 ⁇ 5 Pa, and further preferably less than or equal to 3 x 10 ⁇ 6 Pa.
• the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 44 is less than or equal to 3 x 10 ⁇ 5 Pa, preferably less than or equal to 1 x 10 ⁇ 5 Pa, and further preferably less than or equal to 3 x 10 ⁇ 6 Pa.
• a total pressure and a partial pressure in a vacuum chamber can be measured using a mass analyzer.
• a mass analyzer for example, Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) manufactured by ULVAC, Inc. may be used.
• the transfer chamber 2704, the substrate heating chamber 2705, and the deposition chamber 2706b which are described above preferably have a small amount of external leakage or internal leakage.
• the leakage rate is less than or equal to 3 x 10 ⁇ 6 Pa-m 3 /s, preferably less than or equal to 1 x 10 ⁇ 6 Pa-m 3 /s.
• the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 18 is less than or equal to 1 x 10 ⁇ 7 Pa-m 3 /s, preferably less than or equal to 3 x 10 ⁇ 8 Pa-m 3 /s.
• the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 28 is less than or equal to 1 x 10 ⁇ 5 Pa-m 3 /s, preferably less than or equal to 1 x 10 ⁇ 6 Pa-m 3 /s.
• the leakage rate of a gas molecule (atom) having a mass-to-charge ratio (mlz) of 44 is less than or equal to 3 x 10 ⁇ 6 Pa-m 3 /s, preferably less than or equal to 1 x 10 ⁇ 6 Pa-m 3 /s.
• a leakage rate can be derived from the total pressure and partial pressure measured using the mass analyzer.
• the leakage rate depends on external leakage and internal leakage.
• the external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like.
• the internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or due to released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to be less than or equal to the above value.
• an open/close portion of the deposition chamber 2706b can be sealed with a metal gasket.
• metal gasket metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used.
• the metal gasket realizes higher adhesion than an O-ring, and can reduce the external leakage.
• the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like which is in the passive state, the release of gas containing impurities released from the metal gasket is suppressed, so that the internal leakage can be reduced.
• a member of the deposition apparatus 2700 aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a smaller amount of gas containing impurities, is used.
• an alloy containing iron, chromium, nickel, and the like covered with the above material may be used.
• the alloy containing iron, chromium, nickel, and the like is rigid, resistant to heat, and suitable for processing.
• surface unevenness of the member is decreased by polishing or the like to reduce the surface area, the release of gas can be reduced.
• the above member of the deposition apparatus 2700 may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.
• the member of the deposition apparatus 2700 is preferably formed using only metal when possible.
• a viewing window formed with quartz or the like it is preferable that the surface of the viewing window be thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like so as to suppress release of gas.
• the adsorbed substance When an adsorbed substance is present in the deposition chamber, the adsorbed substance does not affect the pressure in the deposition chamber because it is adsorbed onto an inner wall or the like; however, the adsorbed substance causes gas to be released when the inside of the deposition chamber is evacuated. Therefore, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the deposition chamber be desorbed as much as possible and exhaust be performed in advance with the use of a pump with high exhaust capability.
• the deposition chamber may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold.
• the baking can be performed at a temperature in the range of 100 °C to 450 °C.
• the desorption rate of water or the like which is difficult to desorb simply by exhaust, can be further increased.
• the inert gas which is introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased.
• a rare gas is preferably used as an inert gas.
• oxygen or the like may be used instead of an inert gas.
• the use of oxygen which is a main component of the oxide is preferable in some cases.
• the baking is preferably performed using a lamp.
• treatment for evacuating the inside of the deposition chamber is preferably performed for a certain period of time after heated oxygen, a heated inert gas such as a heated rare gas, or the like is introduced to increase a pressure in the deposition chamber.
• a heated inert gas such as a heated rare gas, or the like is introduced to increase a pressure in the deposition chamber.
• the introduction of the heated gas can desorb the adsorbed substance in the deposition chamber, and the impurities present in the deposition chamber can be reduced. Note that an advantageous effect can be achieved when this treatment is repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times.
• an inert gas, oxygen, or the like with a temperature higher than or equal to 40 °C and lower than or equal to 400 °C, preferably higher than or equal to 50 °C and lower than or equal to 200 °C is introduced to the deposition chamber, so that the pressure therein can be kept to be greater than or equal to 0.1 Pa and less than or equal to 10 kPa, preferably greater than or equal to 1 Pa and less than or equal to 1 kPa, further preferably greater than or equal to 5 Pa and less than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes.
• the inside of the deposition chamber is evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.
• the desorption rate of the adsorbed substance can be further increased also by dummy deposition.
• the dummy deposition refers to deposition on a dummy substrate by a sputtering method or the like, in which a film is deposited on the dummy substrate and the inner wall of the deposition chamber so that impurities in the deposition chamber and an adsorbed substance on the inner wall of the deposition chamber are confined in the film.
• a substrate which releases a smaller amount of gas is preferably used.
• the concentration of impurities in a film to be formed later can be reduced. Note that the dummy deposition may be performed at the same time as the baking of the deposition chamber.
• FIG. 11C illustrates a cross section of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.
• the load lock chamber 2703a includes a substrate delivery stage 2752.
• a pressure in the load lock chamber 2703a becomes atmospheric pressure by being increased from reduced pressure
• the substrate delivery stage 2752 receives a substrate from the transfer robot 2763 provided in the atmosphere-side substrate transfer chamber 2702.
• the load lock chamber 2703a is evacuated into vacuum so that the pressure therein becomes reduced pressure and then the transfer robot 2763 provided in the transfer chamber 2704 receives the substrate from the substrate delivery stage 2752.
• the load lock chamber 2703a is connected to the vacuum pump 2770 and the cryopump 2771 through valves.
• the description of the method for connecting the transfer chamber 2704 can be referred to, and the description thereof is omitted here.
• the unload lock chamber 2703b illustrated in FIG. 10 can have a structure similar to that of the load lock chamber 2703a.
• the atmosphere-side substrate transfer chamber 2702 includes the transfer robot 2763.
• the transfer robot 2763 can deliver a substrate from the cassette port 2761 to the load lock chamber 2703a or deliver a substrate from the load lock chamber 2703a to the cassette port 2761.
• a mechanism for suppressing entry of dust or a particle such as a high-efficiency particulate air (FIEPA) filter, may be provided above the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.
• FIEPA high-efficiency particulate air
• the atmosphere-side substrate supply chamber 2701 includes a plurality of cassette ports 2761.
• the cassette port 2761 can hold a plurality of substrates.
• the surface temperature of the target is set to be lower than or equal to 100 °C, preferably lower than or equal to 50 °C, and further preferably about room temperature (typified by 25 °C).
• a large target is often used in a sputtering apparatus for a large substrate.
• a plurality of targets are arranged so that there is as little space as possible therebetween to obtain a large shape; however, a slight space is inevitably generated.
• zinc or the like is volatilized from such a slight space and the space might be expanded gradually.
• a metal of a backing plate or a metal of a bonding material used for adhesion between the backing plate and the target might be sputtered and might cause an increase in impurity concentration.
• the target it is preferable that the target be cooled sufficiently.
• a metal having high conductivity and a high heat dissipation property (specifically copper) is used for the backing plate, or a sufficient amount of cooling water is made to flow through a water channel formed in the backing plate.
• the target includes zinc
• plasma damage is alleviated by the deposition in an oxygen gas atmosphere; thus, an oxide in which zinc is unlikely to be volatilized can be obtained.
• the above-described deposition apparatus enables deposition of an oxide semiconductor whose hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is lower
• 19 3 19 3 is lower than 5 x 10 atoms/cm , preferably lower than or equal to 1 x 10 atoms/cm , further preferably lower than or equal to 5 x 10 18 atoms/cm 3 , and still further preferably lower than or equal to 1 x 10 18 atoms/cm 3 can be deposited.
• An oxide having few impurities and oxygen vacancies is an oxide with low carrier density (specifically, lower than 8 x 10 11 /cm 3 , preferably lower than 1 x 10 11 /cm 3 , further preferably lower than 1 x 10 10 /cm 3 , and higher than or equal to 1 x 10 ⁇ 9 /cm 3 ).
• Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
• a CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be regarded as an oxide having stable characteristics.
• an oxide semiconductor can be deposited in which the released amount of each of the following gas molecules (atoms) measured by TDS is less than or equal to 1 x 10 19 /cm 3 and preferably less than or equal to 1 x 10 18 /cm 3 : a gas molecule (atom) having a mass-to-charge ratio (m/z) of 2 (e.g., a hydrogen molecule), a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18, a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28, and a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44.
• a gas molecule (atom) having a mass-to-charge ratio (m/z) of 2 e.g., a hydrogen molecule
• a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 e.g., a hydrogen molecule
• FIGS. 12A to 12C one embodiment of a semiconductor device is described with reference to FIGS. 12A to 12C, FIGS. 13 A to 13C, FIGS. 14A to 14C, FIGS. 15A to 15C, FIGS.
• FIGS. 16A to 16C FIGS. 17A to 17C, FIGS. 18A to 18C, FIGS. 19A to 19E, FIGS. 20A to 20D, FIGS.
• FIGS. 22Ato 22C are identical to FIGS. 21A to 21C, and FIGS. 22Ato 22C.
• FIGS. 12A to 12C are a top view and cross-sectional views of the transistor of one embodiment of the present invention.
• FIG. 12A is a top view.
• FIG. 12B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 12A.
• FIG. 12C is a cross-sectional view taken along dashed-dotted line Y1-Y2 in FIG. 12A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 12 A.
• a transistor 200 includes a conductor 205 (conductors 205a and 205b) and a conductor 260 which function as gate electrodes, insulators 220, 222, and 224 and an insulator 250 which function as gate insulating layers, an oxide 230 having a region where a channel is formed (oxides 230a, 230b, and 230c), a conductor 240a functioning as one of a source and a drain, a conductor 240b functioning as the other of the source and the drain, an insulator 280 containing excess oxygen, and an insulator 282 having a barrier property.
• the oxide 230 includes the oxide 230a, the oxide 230b over the oxide 230a, and the oxide 230c over the oxide 230b.
• the transistor 200 When the transistor 200 is turned on, current flows (a channel is formed) mainly in the oxide 230b.
• a current might flow in the vicinity of the interface (a mixed region in some cases) between the oxide 230b and the oxide 230a or 230c, the rest of the oxides 230a and 230c might function as insulators.
• the oxide 230c is preferably provided to cover side surfaces of the oxides 230a and 230b.
• the oxide 230c which is provided between the insulator 280 and the oxide 230b including the region where the channel is formed, can prevent impurities such as hydrogen, water, and halogen from diffusing from the insulator 280 into the oxide 230b.
• the conductor 205 is formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (e.g., a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like.
• a metal nitride film such as a tantalum nitride film is preferable because it has a barrier property against hydrogen or oxygen and is difficult to oxidize (has a high oxidation resistance).
• a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
• a conductor having a barrier property against hydrogen e.g., tantalum nitride
• tungsten which has high conductivity
• the use of the combination of the materials can prevent diffusion of hydrogen into the oxide 230 while the conductivity of a wiring is ensured.
• a two-layer structure of the conductors 205a and 205b is illustrated in FIGS. 12A to 12C; however, one embodiment of the present invention is not limited thereto, and a single-layer structure or a stacked-layer structure of three or more layers may be used.
• a conductor which is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.
• the insulator 224 is preferably an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film.
• the insulator 224 is preferably an insulator containing excess oxygen (containing oxygen in excess of that in the stoichiometric composition). In the case where such an insulator containing excess oxygen is provided in contact with the oxide 230 in the transistor 200, oxygen vacancies in the oxide 230 can be filled.
• the insulator 224 includes an excess-oxygen region
• the insulator 222 preferably has a barrier property against oxygen, hydrogen, and water.
• oxygen in the excess-oxygen region is not diffused to the transistor 300 side but supplied to the oxide 230 efficiently.
• the conductor 205 can be inhibited from reacting with oxygen of the excess-oxygen region of the insulator 224.
• the insulator 222 preferably has a single-layer structure or a stacked-layer structure using an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi0 3 ), or (Ba,Sr)Ti0 3 (BST).
• an insulating film having a barrier property against oxygen or hydrogen e.g., an aluminum oxide film or a hafnium oxide film, is preferably used.
• the insulator 222 formed of such a material functions as a layer which prevents release of oxygen from the oxide 230 and entry of an impurity such as hydrogen from the outside.
• aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example.
• the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
• the insulators 220, 222, and 224 each may have a stacked-layer structure of two or more layers.
• the stacked layers are not necessarily formed of the same material but may be formed of different materials.
• the insulator 222 including a high-k material is provided between the insulator 220 and the insulator 224, electrons can be trapped in the insulator 222 under specific conditions, and the threshold voltage can be increased. As a result, the insulator 222 is negatively charged in some cases.
• the state where the potential of the conductor 205 is higher than the potential of the source electrode or the drain electrode is kept at a temperature higher than the operating temperature or the storage temperature of the semiconductor device (e.g., at a temperature of 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower) for 10 milliseconds or longer, typically one minute or longer.
• the semiconductor device e.g., at a temperature of 125 °C or higher and 450 °C or lower, typically 150 °C or higher and 300 °C or lower
• the threshold voltage is shifted in the positive direction.
• the amount of electrons to be trapped can be controlled, and thus the threshold voltage can be controlled.
• the transistor 200 having the structure is a normally-off transistor which is in a non-conduction state (also referred to as an off state) even when the gate voltage is 0 V.
• the treatment for trapping the electrons may be performed in the manufacturing process of the transistor.
• the treatment is preferably performed at any step before factory shipment, such as after the formation of a conductor connected to the source conductor or the drain conductor of the transistor, after pretreatment (wafer processing), after a wafer-dicing step, after packaging, or the like.
• the threshold voltage can be controlled by appropriate adjustment of the thicknesses of the insulators 220, 222, and 224. For example, when the total thickness of the insulators 220, 222, and 224 is small, a voltage is efficiently applied from the conductor 205, resulting in low power consumption of the transistor.
• the total thickness of the insulators 220, 222, and 224 is less than or equal to 65 nm, preferably less than or equal to 20 nm.
• a transistor having a low leakage current in an off state can be provided.
• a transistor with stable electrical characteristics can be provided.
• a transistor having a high on-state current can be provided.
• a transistor with a small subthreshold swing value can be provided.
• a highly reliable transistor can be provided.
• the oxides 230a, 230b, and 230c are each formed using a metal oxide such as In- -Zn oxide (Mis Al, Ga, Y, or Sn).
• a metal oxide such as In- -Zn oxide (Mis Al, Ga, Y, or Sn).
• An In-Ga oxide or an In-Zn oxide may be used as the oxide 230.
• oxide semiconductor described in the above embodiment can be used as the oxide 230b.
• the oxides 230a and 230b or the oxides 230b and 230c contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed.
• the oxide 230b is an In-Ga-Zn oxide
• the oxide 230b serves as a main carrier path. Since the density of defect states at the interface between the oxides 230a and 230b and the interface between the oxides 230b and 230c can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.
• the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor is shifted in the positive direction.
• the oxides 230a and 230c can make the trap state apart from the oxide 230b. This structure can prevent the positive shift of the threshold voltage of the transistor.
• a material whose conductivity is sufficiently lower than that of the oxide 230b is used for the oxides 230a and 230c.
• the oxide 230b, the interface between the oxides 230b and 230a, and the interface between the oxides 230b and 230c mainly function as a channel region.
• FIG. 5 form a composite is used as the oxide 230b, it is preferable to use an oxide with [ ]/[In] of greater than or equal to 1, preferably greater than or equal to 2, as each of the oxides 230a and 230c. In addition, it is preferable to use an oxide with sufficiently high insulation performance and [AJJ/([Zn]+[In]) of greater than or equal to 1 as the oxide 230c.
• an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi0 3 ), or (Ba,Sr)Ti0 3 (BST) can be used, for example.
• the insulator may have a single-layer structure or a stacked-layer structure.
• aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example.
• the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
• an oxide insulator that contains more oxygen than that in the stoichiometric composition is preferably used.
• an oxide insulator containing excess oxygen is provided in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced.
• an insulating film formed of aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitnde, hafnium oxide, hafnium oxynitride, silicon nitride, or the like, which has barrier properties against oxygen or hydrogen, can be used.
• the insulator 250 formed of such a material serves as a layer that prevents release of oxygen from the oxide 230 and entry of an impurity such as hydrogen from the outside.
• the insulator 250 may have a stacked-layer structure similar to that of the insulator 220, the insulator 222, and the insulator 224.
• the threshold voltage of the transistor 200 can be shifted in the positive direction.
• the transistor 200 having the structure is a normally-off transistor which is in a non-conduction state (also referred to as an off state) even when the gate voltage is 0 V.
• a barrier film may be provided between the oxide 230 and the conductor 260 in the transistor illustrated in FIGS. 12A to 12C.
• the oxide 230c may have a barrier property.
• an insulating film containing excess oxygen is provided in contact with the oxide 230 and enclosed with a barrier film, whereby the composition of the oxide can be substantially the same as the stoichiometric composition or can be in a supersaturated state containing more oxygen than that in the stoichiometric composition. It is also possible to prevent entry of impurities such as hydrogen into the oxide 230.
• One of the conductors 240a and 240b functions as a source electrode, and the other thereof functions as a drain electrode.
• any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of the metals as its main component can be used for each of the conductors 240a and 240b.
• a metal nitride film such as a tantalum nitride film is preferable because it has a barrier property against hydrogen or oxygen and has a high oxidation resistance.
• a stacked-layer structure of two or more layers may be used.
• a tantalum nitride film and a tungsten film may be stacked.
• a titanium film and an aluminum film may be stacked.
• Other examples include a two-layer structure where an aluminum film is stacked over a tungsten film, a two-layer structure where a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure where a copper film is stacked over a titanium film, and a two-layer structure where a copper film is stacked over a tungsten film.
• Other examples include a three-layer structure where a titanium film or a titanium nitride film is formed, an aluminum film or a copper film is stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed over the aluminum film or the copper film; and a three-layer structure where a molybdenum film or a molybdenum nitride film is formed, an aluminum film or a copper film is stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed over the aluminum film or the copper film.
• a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
• the conductor 260 functioning as a gate electrode can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these metals as its component, an alloy containing any of these metals in combination, or the like.
• a metal nitride film such as a tantalum nitride film is preferable because it has a barrier property against hydrogen or oxygen and has a high oxidation resistance.
• manganese and zirconium may be used.
• a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
• a single-layer structure is shown in FIGS. 12A to 12C, a stacked-layer structure of two or more layers may be used.
• a two-layer structure where a titanium film is stacked over an aluminum film may be employed, for example.
• Other examples include a two-layer structure where a titanium film is stacked over a titanium nitride film, a two-layer structure where a tungsten film is stacked over a titanium nitride film, and a two-layer structure where a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film.
• examples include a three-layer structure where a titanium film is formed, an aluminum film is stacked over the titanium film, and a titanium film is formed over the aluminum film.
• an alloy film or a nitride film that contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
• the conductor 260 can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
• the conductor 260 can have a stacked-layer structure using any of the above-described light-transmitting conductive materials and any of the above-described metals.
• the insulator 280 and the insulator 282 are provided over the transistor 200.
• the insulator 280 preferably includes an oxide containing oxygen in excess of that in the stoichiometric composition. That is, in the insulator 280, a region containing oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as excess-oxygen region) is preferably formed.
• excess-oxygen region a region containing oxygen in excess of that in the stoichiometric composition
• oxygen vacancies in the transistor 200 are reduced, whereby the reliability can be improved.
• an oxide material that releases part of oxygen by heating is preferably used as the insulator including the excess-oxygen region.
• An oxide that releases part of oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0 x 10 18 atoms/cm 3 , preferably greater than or equal to 3.0 x 10 20 atoms/cm 3 in TDS analysis.
• the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100 °C and lower than or equal to 700 °C, or higher than or equal to 100 °C and lower than or equal to 500 °C.
• silicon oxide a material containing silicon oxide or silicon oxynitride is preferably used.
• a metal oxide can be used. Note that in this specification, “silicon oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “silicon nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.
• the insulator 280 that covers the transistor 200 may function as a planarization film that covers a roughness thereunder.
• the insulator 282 is preferably formed using an insulating film having a barrier property against oxygen or hydrogen, e.g., an aluminum oxide film or a hafnium oxide film.
• the insulator 282 formed of such a material functions as a layer which prevents release of oxygen from the oxide 230 and entry of an impurity such as hydrogen from the outside.
• the above structure makes it possible to provide a transistor including an oxide semiconductor with high on-state current. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, when the transistor with the above structure is used in a semiconductor device, variation in the electrical characteristics of the semiconductor device can be reduced, and the reliability thereof can be improved. Alternatively, the power consumption of the semiconductor device can be reduced.
• FIGS. 13A to 13C illustrate another example applicable to the transistor 200.
• FIG. 13 A illustrates a top surface of the transistor 200.
• FIG. 13B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 13A
• FIG. 13C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 13 A.
• the conductor 260 has a two-layer structure.
• a conductor 260a can be formed using an oxide typified by an In-Ga-Zn oxide.
• An oxide semiconductor typified by an In-Ga-Zn oxide has an increased carrier density by being supplied with nitrogen or hydrogen.
• the oxide semiconductor functions as an oxide conductor (OC).
• a metal nitride is provided as a conductor 260b, the oxide semiconductor has a higher carrier density and thus, the conductor 260a functions as a gate electrode.
• An oxide semiconductor typified by an In-Ga-Zn oxide can be used as the conductor 260a.
• the conductor 260a can also be formed using a light-transmitting conductive material such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon (also referred to as an In-Sn-Si oxide or ITSO).
• ITO indium tin oxide
• ITSO indium tin oxide
• the use of a metal nitride for the conductor 260b produces either of the following effects: the resistance of the conductor 260a is reduced by the diffusion of the constituent element (especially, nitrogen) of the metal nitride into the conductor 260a; and the resistance is reduced by damage (e.g., sputtering damage) during the deposition of the conductor 260b.
• the conductor 260b may have a stacked-layer structure of two or more layers. For example, by stacking a low-resistance metal film over a metal nitride, a transistor driven by a low voltage can be provided.
• the conductor 260a is preferably formed by a sputtering method in an atmosphere containing an oxygen gas.
• a sputtering method in an atmosphere containing an oxygen gas
• an excess-oxygen region can be formed in the insulator 250.
• a method for forming the conductor 260a is not limited to a sputtering method, and other methods such as an ALD method may be used.
• an insulator 270 is provided to cover the conductor 260.
• the insulator 280 is formed using an oxide material from which oxygen is released
• the insulator 270 is formed using a substance having a barrier property against oxygen. With this structure, oxygen vacancies in the conductor 260a are filled, which inhibits a reduction in carrier density and prevents oxidation of the conductor 260b due to diffused oxygen.
• the insulator 270 can be formed using a metal oxide such as aluminum oxide.
• the insulator 270 is formed to a thickness with which the oxidation of the conductor 260 is prevented.
• a structure may be employed in which the insulator 220 and the insulator 222 are not provided and the conductor 205c is provided using a conductor with a barrier property.
• the conductor 205b can be inhibited from reacting with oxygen of the excess-oxygen region and from generating an oxide.
• an insulator 243a and an insulator 243b may be provided over the conductor 240a and the conductor 240b.
• the insulator 243a and the insulator 243b are formed using a substance having a barrier property against oxygen. With this structure, the conductor 240a and the conductor 240b can be inhibited from being oxidized when the oxide 230c is deposited. Oxygen of the excess-oxygen region in the insulator 280 can be prevented from reacting with the conductor 240a and the conductor 240b and from oxidizing them.
• the insulator 243a and the insulator 243b can be formed using a metal oxide, for example.
• a metal oxide for example.
• an insulating film having a barrier property against oxygen or hydrogen e.g., an aluminum oxide film, a hafnium oxide film, or a gallium oxide film, is preferably used.
• silicon nitride deposited by a CVD method may be used.
• the above structure allows expansion of the range of choices for the materials for the conductor 240a, the conductor 240b, the conductor 205, and the conductor 260.
• the conductor 205b and the conductor 260b can be formed using a material with a low oxidation resistance and high conductivity, e.g., aluminum.
• a conductor that can be easily deposited or processed can be used, for example.
• the oxidation of the conductor 205 and the conductor 260 can be prevented, and oxygen released from the insulator 224 and the insulator 280 can be supplied to the oxide 230 efficiently.
• a conductor that has high conductivity is used for the conductor 205 and the conductor 260, whereby the transistor 200 with low power consumption can be provided.
• FIGS. 14A to 14C illustrate another example applicable to the transistor 200.
• FIG. 14A illustrates a top surface of the transistor 200.
• FIG. 14B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 14A
• FIG. 14C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 14A.
• the conductor 260 has a two-layer structure.
• the conductor 260a is formed by a thermal CVD method, an MOCVD method, or an ALD method.
• the conductor 260a is preferably formed by an ALD method.
• damage to the insulator 250 at the time of the deposition can be reduced.
• the conductor 260a capable of providing high step coverage can be deposited.
• the transistor 200 having high reliability can be provided.
• the conductor 260b is formed by a sputtering method. At that time, since the conductor 260a is provided over the insulator 250, damage caused during deposition of the conductor 260b can be prevented from affecting the insulator 250. Since the deposition rate in a sputtering method is higher than that in an ALD method, the productivity can be improved with a high yield.
• the insulator 270 is provided to cover the conductor 260.
• the insulator 280 is formed using an oxide material from which oxygen is released
• the insulator 270 is formed using a substance having a barrier property against oxygen. With this structure, oxygen vacancies in the conductor 260a are filled, which inhibits a reduction in carrier density and prevents oxidation of the conductor 260b due to diffused oxygen.
• the insulator 270 can be formed using a metal oxide such as aluminum oxide.
• the insulator 270 is formed to a thickness with which the oxidation of the conductor 260 is prevented.
• FIGS. 15A to 15C illustrate another example applicable to the transistor 200.
• FIG. 15A illustrates a top surface of the transistor 200.
• FIG. 15B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 15 A
• FIG. 15C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 15 A.
• the conductor 260 functioning as a gate electrode includes the conductor 260a, the conductor 260b, and a conductor 260c.
• the oxide 230c may be cut over the insulator 224 as long as the oxide 230c covers a side surface of the oxide 230b.
• the conductor 260 has a three-layer structure.
• the conductor 260 may have a single-layer structure, a two-layer structure, or a stacked-layer structure of four or more layers. Note that in the case of the two-layer structure, layers formed using the same material may be stacked.
• the conductor 260a is formed by a thermal CVD method, an MOCVD method, or an ALD method.
• the conductor 260a is preferably formed by an ALD method.
• damage to the insulator 250 at the time of the deposition can be reduced.
• the conductor 260a capable of providing high step coverage can be deposited.
• the transistor 200 having high reliability can be provided.
• the conductor 260b is formed by a sputtering method. At that time, since the conductor 260a is provided over the insulator 250, damage caused during deposition of the conductor 260b can be prevented from affecting the insulator 250. Since the deposition rate in a sputtering method is higher than that in an ALD method, the productivity can be improved with a high yield.
• the conductor 260b is formed using a material having high conductivity such as tantalum, tungsten, copper, or aluminum.
• the conductor 260c formed over the conductor 260b is preferably formed using a conductor with a high oxidation resistance, such as tungsten nitride.
• the use of a conductor with a high oxidation resistance for the conductor 260c, which is in contact with the insulator 280 having an excess-oxygen region in a large area, can inhibit oxygen released from the excess-oxygen region from being absorbed by the conductor 260.
• the oxidation of the conductor 260 can be prevented, and oxygen released from the insulator 280 can be supplied to the oxide 230 efficiently.
• a conductor that has high conductivity is used for the conductor 260b, whereby the transistor 200 with low power consumption can be provided.
• the oxide 230b is covered with the conductor 260 in the channel width direction of the transistor 200.
• the insulator 224 has a projection, whereby the side surface of the oxide 230b is also covered with the conductor 260.
• the bottom surface of the conductor 260 in a region where the insulator 224 and the oxide 230c are in contact with each other is preferably positioned closer to the substrate than the bottom surface of the oxide 230b by adjusting the shape of the projection of the insulator 224.
• the transistor 200 has a structure where the oxide 230b can be electrically surrounded by an electric field of the conductor 260.
• a structure where the oxide 230b is electrically surrounded by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure.
• the channel can be formed in the whole oxide 230b (bulk).
• the drain current of the transistor can be increased, so that a larger amount of on-state current (current which flows between the source and the drain when the transistor is turned on) can be obtained.
• the entire channel formation region of the oxide 230b can be depleted by the electric field of the conductor 260. Accordingly, the off-state current of the s-channel transistor can be further reduced.
• the effects of the s-channel structure such as an increase in on-state current and a reduction in off-state current, can be enhanced.
• FIGS. 16A to 16C illustrate another example applicable to the transistor 200.
• FIG. 16A illustrates a top surface of the transistor 200. For simplification of the drawing, some films are not illustrated in FIG. 16A.
• FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A
• FIG. 16C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 16A.
• the conductors functioning as the source and the drain each have a stacked-layered structure. It is preferable that a conductor which is highly adhesive to the oxide 230b be used as the conductors 240a and 240b, and a material with high conductivity be used as conductors 241a and 241b.
• the conductors 240a and 240b are preferably formed by an ALD method. The use of an ALD method or the like can improve the coverage.
• the transistor 200 when a metal oxide including indium is used as the oxide 230b, titanium nitride or the like may be used as the conductors 240a and 240b.
• a material with high conductivity such as tantalum, tungsten, copper, or aluminum, is used as the conductors 241a and 241b, the transistor 200 with high reliability and low power consumption can be provided.
• the oxide 230b is covered with the conductor 260 in the channel width direction of the transistor 200.
• the insulator 222 has a projection, whereby the side surface of the oxide 230b is also covered with the conductor 260.
• the equivalent oxide (Si0 2 ) thickness (EOT) of the insulator 222 can be small because the insulator 222 has a high relative permittivity. Accordingly, the distance between the conductor 205 and the oxide 230 can be increased owing to the physical thickness of the insulator 222, without a reduction in the influence of the electric field which is applied from the conductor 205 to the oxide 230. Thus, the distance between the conductor 205 and the oxide 230 can be adjusted by changing the thickness of the insulator 222.
• the bottom surface of the conductor 260 in a region where the insulator 222 and the oxide 230c are in contact with each other is preferably positioned closer to the substrate than the bottom surface of the oxide 230b by adjusting the shape of the projection of the insulator 222.
• the transistor 200 has a structure where the oxide 230b can be electrically surrounded by an electric field of the conductor 260.
• a structure where the oxide 230b is electrically surrounded by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure.
• the channel can be formed in the whole oxide 230b (bulk).
• the drain current of the transistor can be increased, so that a larger amount of on-state current (current which flows between the source and the drain when the transistor is turned on) can be obtained. Furthermore, the entire channel formation region of the oxide 230b can be depleted by the electric field of the conductor 260. Accordingly, the off-state current of the s-channel transistor can be further reduced. When the channel width is shortened, the effects of the s-channel structure, such as an increase in on-state current and a reduction in off-state current, can be enhanced. [0298]
• FIGS. 17A to 17C illustrate another example applicable to the transistor 200.
• FIG. 17A illustrates a top surface of the transistor 200.
• FIG. 17B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 17A
• FIG. 17C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 17A.
• the oxide 230c, the insulator 250, and the conductor 260 are formed in an opening formed in the insulator 280. Furthermore, one end portion of each of the conductors 240a and 240b is aligned with an end portion of the opening formed in the insulator 280. Furthermore, three end portions of each of the conductors 240a and 240b are aligned with parts of end portions of each of the oxides 230a and 230b. Therefore, the conductors 240a and 240b can be formed concurrently with the oxide 230 or the opening in the insulator 280. Accordingly, the number of masks and steps can be reduced, and yield and productivity can be improved.
• the conductor 240a, the conductor 240b, and the oxide 230b are in contact with the insulator 280 having the excess-oxygen region with an oxide 23 Od positioned therebetween.
• the oxide 23 Od which is provided between the insulator 280 and the oxide 230b including the region where the channel is formed, can prevent impurities such as hydrogen, water, and halogen from diffusing from the insulator 280 into the oxide 230b.
• the transistor 200 illustrated in FIGS. 17A to 17C has a structure in which the conductors 240a and 240b hardly overlap with the conductor 260, the parasitic capacitance generated between the conductor 260 and the conductors 240a and 240b can be reduced. Thus, the transistor 200 with a high operation frequency can be provided.
• FIGS. 18A to 18C illustrate another example applicable to the transistor 200.
• FIG. 18A illustrates a top surface of the transistor 200.
• FIG. 18B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 18 A
• FIG. 18C is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG. 18 A.
• the transistor 200 illustrated in FIGS. 18A to 18C does not have the oxide 230d.
• the oxide 230d is not necessarily provided. Accordingly, the number of masks and steps can be reduced, and yield and productivity can be improved.
• the insulator 224 may be provided in only the region overlapping with the oxide 230a and the oxide 230b. In that case, the oxide 230a, the oxide 230b, and the insulator 224 can be processed using the insulator 222 as an etching stopper. As a result, yield and productivity can be improved.
• the transistor 200 illustrated in FIGS. 18A to 18C has a structure in which the conductors 240a and 240b hardly overlap with the conductor 260, the parasitic capacitance generated between the conductor 260 and the conductors 240a and 240b can be reduced. Thus, the transistor 200 with a high operation frequency can be provided.
• FIGS. 19A to 19E is described below with reference to FIGS. 19A to 19E, FIGS. 20A to 20D, FIGS. 21 A to 21C, and FIGS. 22A to 22C.
• a substrate is prepared (not illustrated). Although there is no particular limitation on the substrate, it preferably has heat resistance high enough to withstand heat treatment performed later.
• a glass substrate of barium borosilicate glass, aluminoborosilicate glass, or the like, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used.
• a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon, silicon carbide, or the like; a compound semiconductor substrate of silicon germanium, gallium arsenide, indium arsenide, or indium gallium arsenide; a silicon-on-insulator (SOI) substrate; a germanium-on-insulator (GOI) substrate; or the like can be used.
• any of these substrates provided with a semiconductor element may be used as the substrate.
• a flexible substrate may be used as the substrate to manufacture the semiconductor device.
• a transistor may be directly formed over a flexible substrate; alternatively, a transistor may be formed over a manufacturing substrate and then separated from the manufacturing substrate and transferred to a flexible substrate. In order that the transistor be separated from the manufacturing substrate to be transferred to the flexible substrate, it is preferable to provide a separation layer between the manufacturing substrate and the transistor including an oxide semiconductor.
• an insulator 214 and an insulator 216 are formed.
• a resist mask 290 is formed over the insulator 216 by a lithography process or the like to remove unnecessary portions of the insulators 214 and 216 (FIG. 19A). After that, the resist mask 290 is removed; thus, an opening can be formed.
• a method for processing a film is described.
• a variety of fine processing techniques can be used. For example, it is possible to use a method in which a resist mask formed by a lithography process or the like is subjected to slimming treatment.
• a dummy pattern is formed by a lithography process or the like, the dummy pattern is provided with a sidewall and is then removed, and a film is etched using the remaining sidewall as a resist mask.
• anisotropic dry etching is preferably used for etching of a film.
• a hard mask formed of an inorganic film or a metal film may be used.
• light with an i-line (with a wavelength of 365 nm), light with a g-line (with a wavelength of 436 nm), light with an h-line (with a wavelength of 405 nm), or light in which the i-line, the g-line, and the h-line are mixed
• ultraviolet light, KrF laser light, ArF laser light, or the like can be used.
• Exposure may be performed by liquid immersion exposure technique.
• extreme ultra-violet light (EUV) or X-rays may be used.
• an electron beam can be used.
• EUV extreme ultra-violet light
• X-rays X-rays
• electron beam an electron beam because extremely minute processing can be performed. Note that in the case of performing exposure by scanning with a beam such as an electron beam, a photomask is not needed.
• An organic resin film having a function of improving the adhesion between a film and a resist film may be formed before the resist film serving as a resist mask is formed.
• the organic resin film can be formed to planarize a surface by covering a step under the film by a spin coating method or the like, and thus can reduce variation in thickness of the resist mask over the organic resin film.
• a material serving as a film preventing reflection of light for the exposure is preferably used for the organic resin film.
• the organic resin film having such a function include a bottom anti -reflection coating (BARC) film.
• BARC bottom anti -reflection coating
• the organic resin film may be removed at the same time as the removal of the resist mask or after the removal of the resist mask.
• a conductor 205 A and a conductor 205B are deposited over the insulator 214 and the insulator 216.
• the conductor 205 A and the conductor 205B can be deposited by, for example, a sputtering method, an evaporation method, or a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, and the like). It is preferable to use a thermal CVD method, an MOCVD method, or an ALD method in order to reduce plasma damage (FIG. 19B).
• unnecessary portions of the conductors 205A and 205B are removed.
• part of the conductor 205A and part of the conductor 205B are removed by etch-back process, a chemical mechanical polishing (CMP) process, or the like until the insulator 216 is exposed, whereby the conductor 205 is formed (FIG. 19C).
• CMP chemical mechanical polishing
• the insulator 216 can be used as a stopper layer, and the thickness of the insulator 216 is reduced in some cases.
• the CMP process is a process for planarizing a surface of an object to be processed by a combination of chemical and mechanical actions. More specifically, the CMP process is a process in which a polishing cloth is attached to a polishing stage, the polishing stage and the object to be processed are each rotated or swung while a slurry (an abrasive) is supplied between the object to be processed and the polishing cloth, and the surface of the object to be processed is polished by chemical reaction between the slurry and the surface of the object to be processed and by action of mechanical polishing between the object to be processed and the polishing cloth.
• a slurry an abrasive
• the CMP process may be performed only once or a plurality of times.
• first polishing be performed at a high polishing rate and final polishing be performed at a low polishing rate. In this manner, polishing processes using different polishing rates may be used in combination.
• the insulator 220, the insulator 222, and the insulator 224 are formed (FIG. 19D).
• the insulator 220 and the insulator 222 are not necessarily provided.
• a conductor with a barrier property may be formed over the conductor 205.
• the conductor with a barrier property can inhibit the conductor 205 from reacting with oxygen in the excess-oxygen region and from generating an oxide.
• the insulators 220, 222, and 224 can each be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like. It is particularly preferable to use a high-k material such as hafnium oxide as the insulator 222.
• the insulators 220, 222, and 224 can be formed using a sputtering method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic CVD (MOCVD) method, a plasma-enhanced CVD (PECVD) method, and the like), a molecular beam epitaxy (MBE) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, or the like.
• CVD chemical vapor deposition
• MOCVD metal organic CVD
• PECVD plasma-enhanced CVD
• MBE molecular beam epitaxy
• ALD atomic layer deposition
• PLD pulsed laser deposition
• the insulators can also be formed using a silicon oxide film capable of providing high step coverage that is formed by reacting tetraethyl orthosilicate (TEOS), silane, or the like with oxygen, nitrous oxide, or the like.
• TEOS tetraethyl orthosilicate
• the insulators 220, 222, and 224 are preferably deposited successively. By successive deposition, impurities do not attach to the interfaces between the insulators 220 and 222 and between the insulators 222 and 224, resulting in high reliability of the insulators.
• an oxide 23 OA to be the oxide 230a and an oxide 230B to be the oxide 230b are sequentially deposited.
• the oxides are preferably deposited successively without exposure to the air.
• a conductive film 240A to be the conductors 240a and 240b is formed over the oxide 23 OA.
• a material which has a barrier property against hydrogen or oxygen and has a high oxidation resistance is preferably used.
• the conductive film 240A has a single-layer structure in the drawing, it may have a structure of two or more stacked layers.
• a resist mask 292 is formed by a method similar to that described above (FIG. 19E).
• An unnecessary portion of the conductive film 240A is removed by etching using the resist mask 292 to form a conductive layer 240B having an island shape (FIG. 20A). After that, unnecessary portions of the oxides 23 OA and 23 OB are removed by etching using the conductive layer 240B as a mask.
• the insulator 224 may also be processed into an island-shape.
• the use of the insulator 222 with a barrier property as an etching stopper film can prevent over-etching of the wiring layer positioned below the insulators.
• a voltage is efficiently applied from the conductor 205; therefore, the transistor with low power consumption can be obtained.
• heat treatment is preferably performed (arrows in FIG. 20C denote the heat treatment).
• the heat treatment may be performed at a temperature higher than or equal to 250 °C and lower than or equal to 400 °C, preferably higher than or equal to 320 °C and lower than or equal to 380 °C, in an inert gas atmosphere, in an atmosphere containing an oxidizing gas at 10 ppm or more, or under reduced pressure.
• the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidization gas at 10 ppm or more, in order to compensate for released oxygen.
• the heat treatment can remove hydrogen that is an impurity for the oxides 230a and 230b.
• oxygen is supplied from the insulator formed below the oxide 230a to the oxides 230a and 230b, so that oxygen vacancies in the oxides can be reduced.
• a resist mask 294 is formed over the island-shaped conductive layer 240B by a method similar to that described above (FIG. 20D). Then, an unnecessary portion of the conductive layer 240B is removed by etching, and then the resist mask 294 is removed, whereby the conductor 240a and the conductor 240b are formed (FIG. 21 A). At that time, part of the insulator 222 or the insulator 224 may be thinned by etching to obtain an s-channel structure.
• heat treatment may be performed.
• the heat treatment may be performed under the conditions similar to those of the heat treatment described with reference to FIG. 20C.
• the heat treatment can remove hydrogen that is an impurity for the oxides 230a and 230b.
• oxygen can be supplied from the insulator formed below the oxide 230a to the oxides 230a and 230b, so that oxygen vacancies in the oxides can be reduced.
• an oxidizing gas is in direct contact with the region where the channel is formed, whereby oxygen vacancies included in the region where the channel is formed can be reduced efficiently.
• the oxide 230c is deposited.
• heat treatment may be performed (the arrows in FIG. 2 IB denote the heat treatment).
• the heat treatment may be performed under the conditions similar to those of the heat treatment described with reference to FIG. 21C.
• the heat treatment can remove hydrogen that is an impurity for the oxides 230a and 230b.
• oxygen can be supplied from the insulator formed below the oxide 230a to the oxides 230a and 230b, so that oxygen vacancies in the oxides can be reduced.
• an oxidizing gas is in direct contact with the region where the channel is formed, whereby oxygen vacancies included in the region where the channel is formed can be reduced efficiently.
• the insulator 250 and a conductive film 260A to be the conductor 260 are sequentially deposited.
• a material which has a barrier property against hydrogen or oxygen and has a high oxidation resistance is preferably used.
• the conductive film 260A has a single-layer structure in the drawing, it may have a structure of two or more stacked layers.
• the stacked two layers may be formed of the same material.
• a first conductive film is formed by a thermal CVD method, an MOCVD method, or an ALD method, for example.
• an ALD method is preferably used.
• damage to the insulator 250 at the time of the deposition can be reduced.
• the conductive film 260 A capable of providing high step coverage can be deposited.
• the transistor 200 having high reliability can be provided.
• a second conductive film is formed by a sputtering method.
• the first conductive film is provided over the insulator 250, damage caused during deposition of the second conductive film can be prevented from affecting the insulator 250.
• the deposition rate in a sputtering method is higher than that in an ALD method, the productivity can be improved with a high yield. Note that it is preferable to use a deposition gas which does not contain chlorine in deposition of the conductive film 260A.
• a resist mask 296 is formed over the conductive film 260A by a method similar to that described above (FIG. 21C). Then, an unnecessary portion of the conductive film 260A is removed by etching to form the conductor 260. After that, the resist mask 296 is removed (FIG. 22A).
• the insulator 280 is an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film.
• oxygen may be added by an ion implantation method, an ion doping method, or plasma treatment.
• oxygen plasma treatment is preferably performed (arrows in FIG. 22B denote the plasma treatment).
• the surface of an oxide semiconductor is processed by radicals generated from an oxygen gas by glow discharge plasma.
• a mixed gas of an oxygen gas and a rare gas may be used, as well as oxygen.
• oxygen plasma treatment may be performed at a temperature higher than or equal to 250 °C and lower than or equal to 400 °C, preferably higher than or equal to 300 °C and lower than or equal to 400 °C, in an atmosphere containing an oxidizing gas or under reduced pressure.
• the oxygen plasma treatment dehydrates or dehydrogenates the insulator 280 and the oxide 230 and introduces excess oxygen to the insulator 280; as a result, an excess-oxygen region can be formed.
• oxygen vacancies are generated in the dehydrated or dehydrogenated oxide 230 and the resistance of the oxide 230 is reduced.
• the excess oxygen of the insulator 280 fills oxygen vacancies of the oxide 230. Therefore, owing to the oxygen plasma treatment, hydrogen and water that serve as impurities can be removed from the insulator 280 while an excess-oxygen region is formed in the insulator 280.
• hydrogen and water that serve as impurities can be removed from the oxide 230 while oxygen vacancies in the oxide 230 are filled.
• the electrical characteristics of the transistor 200 can be improved and variation in the electrical characteristics thereof can be reduced.
• the insulator 282 is formed over the insulator 280 (FIG. 22C).
• the insulator 282 is preferably formed with a sputtering apparatus. By using a sputtering method, an excess-oxygen region can be formed easily in the insulator 280 positioned under the insulator 282.
• ions and sputtered particles exist between a target and a substrate.
• a potential E 0 is supplied to the target, to which a power source is connected.
• a potential E ⁇ such as a ground potential is supplied to the substrate.
• the substrate may be electrically floating.
• the ions in plasma are accelerated by a potential difference (E 2 - E 0 ) and collide with the target; accordingly, sputtered particles are ejected from the target. These sputtered particles attach to a deposition surface and deposited thereover; as a result, a film is formed.
• the ions in the plasma are accelerated by a potential difference (E 2 - E ) and collide with the deposition surface. At that time, some ions reach the inside of the insulator 280.
• the ions are taken into the insulator 280; accordingly, a region into which the ions are taken is formed in the insulator 280. That is, an excess-oxygen region is formed in the insulator 280 in the case where the ions include oxygen.
• excess oxygen in the insulator 280 can form an excess-oxygen region.
• the excess oxygen in the insulator 280 is supplied to the oxide 230 and can fill oxygen vacancies in the oxide 230.
• excess oxygen in the insulator 280 is not absorbed by the conductor 260 and the conductors 240a and 240b but can be efficiently supplied to the oxide 230.
• the electrical characteristics of the transistor 200 can be improved and variation in the electrical characteristics thereof can be reduced.
• the transistor 200 of one embodiment of the present invention can be manufactured.
• FIGS. 23 to 28 FIGS. 29A and 29B, FIGS. 30A and 30B, FIGS. 31 A and 3 IB, FIGS. 32A and 32B, and FIG. 33.
• FIGS. 23 to 28 Examples of a semiconductor device (a memory device) of one embodiment of the present invention are shown in FIGS. 23 to 28, FIGS. 29A and 29B, and FIGS. 30A and 30B.
• FIG. 30A is a circuit diagram of FIGS. 23 to 26.
• FIGS. 29A and 29B show end portions of regions where semiconductor devices shown in FIGS. 23 to 26 are formed.
• Semiconductor devices shown in FIG. 30A and FIGS. 23 to 28 each include a transistor 300, a transistor 200, and a capacitor 100.
• the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is low, by using the transistor 200 in a semiconductor device (a memory device), stored data can be retained for a long time. In other words, such a semiconductor device (a memory device) does not require refresh operation or has an extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption.
• a wiring 3001 is electrically connected to a source of the transistor 300.
• a wiring 3002 is electrically connected to a drain of the transistor 300.
• a wiring 3003 is electrically connected to one of a source and a drain of the transistor 200.
• a wiring 3004 is electrically connected to a gate of the transistor 200.
• a gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100.
• a wiring 3005 is electrically connected to the other electrode of the capacitor 100.
• the semiconductor device in FIG. 30A has a feature that the potential of the gate of the transistor 300 can be retained, and thus enables writing, retaining, and reading of data as follows.
• the potential of the wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 3003 is supplied to a node FG where the gate of the transistor 300 and the one electrode of the capacitor 100 are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor 300 (writing).
• a predetermined charge is supplied to the gate of the transistor 300 (writing).
• one of two kinds of charges providing different potential levels hereinafter referred to as a low-level charge and a high-level charge
• the potential of the wiring 3004 is set to a potential at which the transistor 200 is turned off, so that the transistor 200 is turned off.
• the charge is retained at the node FG (retaining).
• An appropriate potential (a reading potential) is supplied to the wiring 3005 while a predetermined potential (a constant potential) is supplied to the wiring 3001, whereby the potential of the wiring 3002 varies depending on the amount of charge retained in the node FG.
• a reading potential is supplied to the wiring 3005 while a predetermined potential (a constant potential) is supplied to the wiring 3001, whereby the potential of the wiring 3002 varies depending on the amount of charge retained in the node FG.
• an apparent threshold voltage refers to the potential of the wiring 3005 which is needed to make the transistor 300 be in "on state.”
• the potential of the wiring 3005 is set to a potential Vo which is between 3 ⁇ 4 ⁇ and Vth , whereby charge supplied to the node FG can be determined.
• the transistor 300 is brought into "on state.”
• the transistor 300 in the case where the high-level charge is supplied to the node FG in writing and the potential of the wiring 3005 is Vo (> ⁇ 3 ⁇ 4 ⁇ ), the transistor 300 is brought into "on state.”
• the transistor 300 in the case where the low-level charge is supplied to the node FG in writing, even when the potential of the wiring 3005 is V 0 ( ⁇ !3 ⁇ 4_]_), the transistor 300 remains in "off state.”
• the data retained in the node FG can be read by determining the potential of the wiring 3002.
• a memory device (a memory cell array) can be formed.
• the memory cell has a NOR-type structure.
• the memory cell has a NAND-type structure.
• a semiconductor device in FIG. 30B is different from the semiconductor device in FIG.
• Reading of data in the semiconductor device in FIG. 30B is described.
• the wiring 3003 which is in a floating state and the capacitor 100 are electrically connected to each other, and the charge is redistributed between the wiring 3003 and the capacitor 100.
• the potential of the wiring 3003 is changed.
• the amount of change in the potential of the wiring 3003 varies depending on the potential of the one electrode of the capacitor 100 (or the charge accumulated in the capacitor 100).
• the potential of the wiring 3003 after the charge redistribution is (C B x V B o + C x V) I (C B + C), where J 7 is the potential of the one electrode of the capacitor 100, C is the capacitance of the capacitor 100, C B is the capacitance component of the wiring 3003, and J3 ⁇ 4o is the potential of the wiring 3003 before the charge redistribution.
• a transistor using silicon may be used for a driver circuit for driving a memory cell, and a transistor using an oxide semiconductor may be stacked as the transistor 200 over the driver circuit.
• the semiconductor device described above can retain stored data for a long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).
• the semiconductor device high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, unlike a conventional nonvolatile memory, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, and the reliability thereof is drastically improved. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be achieved.
• the semiconductor device of one embodiment of the present invention includes the transistor 300, the transistor 200, and the capacitor 100 as shown in FIG. 23.
• the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.
• the transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 314, a semiconductor region 312 that is a part of the substrate 311, and low-resistance regions 318a and 318b functioning as a source region and a drain region.
• the transistor 300 may be a p-channel transistor or an n-channel transistor.
• a region of the semiconductor region 312 where a channel is formed, a region in the vicinity thereof, the low-resistance regions 318a and 318b functioning as a source region and a drain region, and the like contain a semiconductor such as a silicon-based semiconductor, more preferably single crystal silicon.
• a material including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be contained. Silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing may be contained.
• the transistor 300 may be a high-electron-mobility transistor (HEMT) with GaAs and GaAlAs, or the like.
• HEMT high-electron-mobility transistor
• the low-resistance regions 318a and 318b contain an element which imparts n-type conductivity, such as arsenic or phosphorus, or an element which imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region 312.
• the conductor 316 functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.
• a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron
• a conductive material such as a metal material, an alloy material, or a metal oxide material.
• a work function of a conductor is determined by a material of the conductor, whereby the threshold voltage can be adjusted. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like as the conductor. Furthermore, in order to ensure the conductivity and embeddability of the conductor, it is preferable to use a stacked layer of metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferable in terms of heat resistance.
• the transistor 300 shown in FIG. 23 is just an example and is not limited to the structure shown therein; an appropriate transistor may be used in accordance with a circuit configuration or a driving method. In the case of using the circuit configuration shown in FIG. 30B, the transistor 300 may be omitted. [0371]
• An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked sequentially so as to cover the transistor 300.
• the insulator 320, the insulator 322, the insulator 324, and the insulator 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.
• the insulator 322 may function as a planarization film for eliminating a level difference caused by the transistor 300 or the like underlying the insulator 322.
• a top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity.
• CMP chemical mechanical polishing
• the insulator 324 is preferably formed using a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 311, the transistor 300, or the like into a region where the transistor 200 is formed.
• the barrier property herein refers to a high oxidation resistance and a function of inhibiting the diffusion of oxygen and impurities typified by hydrogen, and water.
• the diffusion length of oxygen or hydrogen in a film with a barrier property in an atmosphere at 350 °C or 400 °C is less than or equal to 50 nm per hour.
• the diffusion length of oxygen or hydrogen in the film with a barrier property at 350 °C or at 400 °C is preferably less than or equal to 30 nm per hour, further preferably less than or equal to 20 nm per hour.
• silicon nitride formed by a CVD method can be given. Diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the transistor 200 and the transistor 300. Specifically, the film that prevents hydrogen diffusion is a film from which hydrogen is less likely to be released.
• the amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example.
• TDS thermal desorption spectroscopy
• the amount of hydrogen released from the insulator 324 that is converted into hydrogen atoms per unit area of the insulator 324 is less than or equal to 10 x 10 15 atoms/cm 2 , preferably less than or equal to 5 x 10 15 atoms/cm 2 in TDS analysis in the range of 50 °C to 500 °C, for example.
• the permittivity of the insulator 326 is preferably lower than that of the insulator 324.
• the relative permittivity of the insulator 324 is preferably lower than 4, more preferably lower than 3.
• the relative permittivity of the insulator 326 is preferably 0.7 times or less that of the insulator 324, more preferably 0.6 times or less that of the insulator 324.
• the parasitic capacitance between wirings can be reduced.
• a conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326.
• the conductor 328 and the conductor 330 each function as a plug or a wiring.
• a plurality of structures of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases, as described later.
• a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where a part of a conductor functions as a wiring and a part of a conductor functions as a plug.
• a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.
• a wiring layer may be provided over the insulator 326 and the conductor 330.
• an insulator 350, an insulator 352, and an insulator 354 are stacked sequentially.
• a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
• the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be formed using a material similar to that used for forming the conductor 328 and the conductor 330.
• the insulator 350 is preferably formed using an insulator having a barrier property against hydrogen, like the insulator 324.
• the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
• the conductor having a barrier property against hydrogen is formed particularly in an opening in the insulator 350 having a barrier property against hydrogen.
• the transistor 300 and the transistor 200 can be separated by a barrier layer, so that diffusion of hydrogen from the transistor 300 into the transistor 200 can be prevented.
• tantalum nitride may be used, for example. By stacking tantalum nitride and tungsten, which has high conductivity, diffusion of hydrogen from the transistor 300 can be prevented while the conductivity of a wiring is ensured.
• a tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.
• An insulator 358, an insulator 210, an insulator 212, an insulator 213, an insulator 214, and an insulator 216 are stacked sequentially over the insulator 354.
• a material having a barrier property against oxygen or hydrogen is preferably used for any of the insulators 358, 210, 212, 213, 214, and 216.
• the insulators 358 and 212 are preferably formed using, for example, a film having a barrier property that prevents impurities such as hydrogen from diffusing from the substrate 311, a region where the transistor 300 is formed, or the like into a region where the transistor 200 is formed. Therefore, the insulators 358 and 212 can be formed using a material similar to that used for forming the insulator 324.
• silicon nitride formed by a CVD method can be given. Diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that prevents hydrogen diffusion is preferably provided between the transistor 200 and the transistor 300. Specifically, the film that prevents hydrogen diffusion is a film from which hydrogen is less likely to be released.
• a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.
• aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 200 in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide in the transistor 200 can be prevented. Therefore, aluminum oxide is suitably used as a protective film for the transistor 200.
• the insulators 210 and 216 can be formed using a material similar to that used for forming the insulator 320.
• a material with a relatively low permittivity is used as an interlayer film, the parasitic capacitance between wirings can be reduced.
• a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 216.
• a conductor 218, a conductor (the conductor 205) included in the transistor 200, and the like are embedded in the insulators 358, 210, 212, 213, 214, and 216.
• the conductor 218 functions as a plug or a wiring that is electrically connected to the capacitor 100 or the transistor 300.
• the conductor 218 can be formed using a material similar to that used for forming the conductor 328 and the conductor 330.
• the conductor 218 in a region in contact with the insulators 358, 212, 213, and 214 is preferably a conductor having a barrier property against oxygen, hydrogen, and water.
• the transistor 300 and the transistor 200 can be completely separated by a layer having a barrier property against oxygen, hydrogen, and water, so that diffusion of hydrogen from the transistor 300 into the transistor 200 can be prevented.
• the conductor in contact with the insulator 224 is preferably a conductor with a high oxidation resistance.
• a conductor 219 with a barrier property may be provided over the conductor 218 and the conductor (the conductor 205) included in the transistor 200.
• the transistor 200 is provided over the insulator 224. Note that any of the transistor structures described in the above-described embodiment can be used as the structure of the transistor 200.
• the transistor 200 shown in FIG. 23 is just an example and is not limited to the structure shown therein; an appropriate transistor may be used in accordance with a circuit configuration or a driving method.
• the insulator 280 is provided over the transistor 200.
• an excess-oxygen region is preferably formed.
• oxygen vacancies in the transistor 200 are reduced, whereby the reliability can be improved.
• an oxide material that releases part of oxygen by heating is preferably used as the insulator including the excess-oxygen region.
• An oxide that releases part of oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0 x 10 18 atoms/cm 3 , preferably greater than or equal to 3.0 x 10 20 atoms/cm 3 in TDS analysis.
• the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100 °C and lower than or equal to 700 °C, or higher than or equal to 100 °C and lower than or equal to 500 °C.
• silicon oxide a material containing silicon oxide or silicon oxynitride is preferably used.
• a metal oxide can be used. Note that in this specification, “silicon oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “silicon nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.
• the insulator 280 that covers the transistor 200 may function as a planarization film that covers a roughness thereunder.
• a conductor 244 and the like are embedded in the insulator 280.
• the conductor 244 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
• the conductor 244 can be formed using a material similar to that used for forming the conductor 328 and the conductor 330.
• the conductor 244 when the conductor 244 is formed to have a stacked-layer structure, the conductor 244 preferably includes a conductor that is unlikely to be oxidized (that has a high oxidation resistance).
• a conductor with a high oxidation resistance is preferably provided in a region in contact with the insulator 280 including the excess-oxygen region.
• the conductor 244 preferably includes a conductor having a barrier property against hydrogen.
• a conductor having a barrier property against an impurity such as hydrogen is provided in a region in contact with the insulator 280 including the excess-oxygen region, whereby diffusion of the impurity of the conductor 244, diffusion of part of the conductor 244, and diffusion of an impurity from the outside through the conductor 244 can be prevented.
• a conductor 246, a conductor 124, a conductor 112a, and a conductor 112b may be provided over the conductor 244.
• the conductor 246 and the conductor 124 function as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
• the conductor 112a and the conductor 112b function as an electrode of the capacitor 100.
• the conductor 246 and the conductor 112a can be formed at the same time.
• the conductor 124 and the conductor 112b can be formed at the same time.
• a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.
• a metal nitride film such as a tantalum nitride film for the conductor 246 and the conductor 112a because such a metal nitride film has a barrier property against hydrogen or oxygen and is not easily oxidized (has a high oxidation resistance).
• the conductor 124 and the conductor 112b are preferably formed by stacking a material with high conductivity such as tungsten. The use of the combination of the materials can prevent diffusion of hydrogen into the insulator 280 and the transistor 200 while the conductivity of the wiring is ensured.
• a two-layer structure of the conductor 246 and the conductor 124 is shown in FIG.
• the structure is not limited thereto, and a single-layer structure or a stacked-layer structure of three or more layers may be used.
• a conductor which is highly adhesive to the conductor having a barrier property and the conductor with high conductivity may be formed.
• a barrier layer 281 may be provided over the conductor 124. With the barrier layer 281, the conductor 124 can be inhibited from being oxidized in a later step. In addition, diffusion of impurities contained in the conductor 124 and diffusion of part of the conductor 124 can be inhibited. Impurities can be inhibited from penetrating the conductor 124, the conductor 246, and the conductor 244 to be diffused into the insulator 280.
• the barrier layer 281 can be formed using an insulating material. In that case, the barrier layer 281 may function as part of the dielectric of the capacitor 100.
• the barrier layer 281 may be formed using a conductive material. In that case, the barrier layer 281 may function as part of a wiring or an electrode.
• a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide, a metal nitride such as tantalum nitride, or the like is preferably used for the barrier layer 281.
• aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of the conductor 124 and impurities such as hydrogen and moisture into the transistor 200 in and after a manufacturing process of the semiconductor device.
• the insulator 282 is provided over the barrier layer 281 and the insulator 280.
• a material having a barrier property against oxygen or hydrogen is preferably used for the insulator 282.
• the insulator 282 can be formed using a material similar to that used for forming the insulator 214.
• a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.
• aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 200 in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide in the transistor 200 can be prevented. Therefore, aluminum oxide is suitably used as a protective film for the transistor 200.
• the transistor 200 and the insulator 280 including the excess-oxygen region can be positioned between a stacked-layer structure of the insulators 212, 213, and 214 and the insulator 282.
• the insulators 212, 213, 214, and 282 each have a barrier property that prevents diffusion of oxygen or impurities such as hydrogen and water.
• Oxygen released from the insulator 280 and the transistor 200 can be prevented from diffusing into the layer where the capacitor 100 is formed or the layer where the transistor 300 is formed. Furthermore, impurities such as hydrogen and water can be prevented from diffusing from a layer above the insulator 282 and a layer below the insulator 214 into the transistor 200.
• oxygen can be efficiently supplied from the excess-oxygen region of the insulator 280 to the oxide where the channel is formed in the transistor 200, so that oxygen vacancies can be reduced. Moreover, oxygen vacancies can be prevented from being formed by impurities in the oxide where the channel is formed in the transistor 200.
• the oxide where the channel is formed in the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor 200 can be prevented and the reliability can be improved.
• a dicing line (also referred to as a scribe line, a dividing line, or a cutting line) that is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each formed in a chip form
• a dividing method for example, a groove (a dicing line) for separating the semiconductor elements is formed on the substrate and then, the substrate is cut along the dicing line so that a plurality of semiconductor devices that are separated are obtained.
• FIGS. 29A and 29B are each a cross-sectional view of the vicinity of a dicing line.
• an opening is provided in the insulators 212, 213, 214, 216, 224, and 280 in the vicinity of a region overlapping with the dicing line (shown by a dashed-dotted line in FIG. 29 A) formed in an edge of a memory cell including the transistor 200.
• the insulator 282 is provided to cover the side surfaces of the insulators 212, 213, 214, 216, 224, and 280.
• the insulator 282 is preferably provided in the opening with the barrier layer 281 positioned between the insulator 282 and the inner surface of the opening. Diffusion of impurities can be more inhibited owing to the barrier layer 281.
• the insulators 212, 213, and 214 are in contact with the barrier layer 281.
• at least one of the insulators 212, 213, and 214 is formed using the same material and method as those used for forming the insulator 282, whereby adhesion therebetween can be improved.
• the barrier layer 281 and the insulator 282 are preferably formed using the same material. Aluminum oxide can be used, for example.
• the barrier layer 281 is formed by a method by which a dense film can be formed, e.g., an ALD method, and then the insulator 282 is formed by a method with a high deposition rate such as a sputtering method, high productivity and a high barrier property can be achieved.
• the insulator 280 and the transistor 200 can be enclosed with the insulators 212, 213, 214, and 282. Since the insulators 212, 213, 214, and 282 each have a function of preventing diffusion of oxygen, hydrogen, and water, entry and diffusion of impurities such as hydrogen or water from the direction of the side surface of the divided substrate into the transistor 200 can be prevented even when the substrate is divided into circuit regions each of which is provided with the semiconductor element in this embodiment to form a plurality of chips.
• excess oxygen in the insulator 280 can be prevented from diffusing into the outside of the insulators 282 and 214. Accordingly, excess oxygen in the insulator 280 is efficiently supplied to the oxide where the channel is formed in the transistor 200.
• the oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor 200.
• the oxide where the channel is formed in the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor 200 can be prevented and the reliability can be improved.
• openings may be provided in the insulators 212, 213, 214, 216, 224, and 280 on both sides of the dicing line (shown by the dashed-dotted line in FIG. 29B). Although the number of the openings in the drawing is two, a plurality of openings may be provided as needed.
• the insulators 212, 213, and 214 are in contact with the barrier layer 281 in at least two regions in the openings provided on both sides of the dicing line, higher adhesion is obtained. Note that also in that case, when at least one of the insulators 212, 213, and 214 is formed using the same material and method as those used for forming the insulator 282, the adhesion therebetween can be improved.
• the insulator 282 can be in contact with the insulators 212, 213, and 214 in a plurality of regions. Therefore, impurities that enter from the dicing line can be prevented from reaching the transistor 200.
• the transistor 200 and the insulator 280 can be sealed tightly.
• the oxide where the channel is formed in the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor 200 can be prevented and the reliability can be improved.
• the capacitor 100 is provided above the transistor 200.
• the capacitor 100 includes a conductor 112 (the conductor 112a and the conductor 112b), the barrier layer 281, the insulator 282, an insulator 130, and a conductor 116.
• the conductor 112 functions as the electrode of the capacitor 100.
• part of the conductor 244 functioning as a plug or a wiring that is connected to the transistor 200 and the transistor 300 functions as the conductor 112.
• the barrier layer 281 when the barrier layer 281 has conductivity, the barrier layer 281 functions as part of the electrode of the capacitor 100.
• the barrier layer 281 When the barrier layer 281 has an insulating property, the barrier layer 281 functions as part of the dielectric of the capacitor 100.
• Such a structure can increase the productivity owing to a reduction of the number of steps in the process as compared to the case where the electrode and the wiring are formed separately.
• a region of the insulator 282 which is located between the conductor 112 and the conductor 116 functions as a dielectric.
• a high dielectric constant (high-k) material such as aluminum oxide, for the insulator 282 can ensure a sufficient capacitance of the capacitor 100.
• the insulator 130 may be provided as part of the dielectric.
• the insulator 130 can be formed to have a single-layer structure or a stacked-layer structure using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like.
• a high dielectric constant (high-k) material such as aluminum oxide
• a material with high dielectric strength such as silicon oxynitride
• the dielectric strength can be increased and the electrostatic breakdown of the capacitor 100 can be prevented because of the insulator 130.
• the conductor 116 is provided so as to cover the top and side surfaces of the conductor 112 with the barrier layer 281, the insulator 282, and the insulator 130 located therebetween.
• capacitance is also formed on the side surfaces of the conductor 112, resulting in an increase in the capacitance per unit projected area of the capacitor.
• the semiconductor device can be reduced in area, highly integrated, and miniaturized.
• the conductor 116 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 116 is formed concurrently with another component such as a conductor, Cu (copper), Al (aluminum), or the like which is a low-resistance metal material may be used.
• An insulator 150 is provided over the conductor 116 and the insulator 130.
• the insulator 150 can be formed using a material similar to that used for forming the insulator 320.
• the insulator 150 may function as a planarization film that covers roughness due to underlying layers.
• a change in electrical characteristics can be prevented and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor.
• a transistor including an oxide semiconductor with high on-state current can be provided.
• a transistor including an oxide semiconductor with low off-state current can be provided.
• a semiconductor device with low power consumption can be provided.
• the conductor 244 serving as a plug or a wiring and the conductor 112 serving as part of the electrode of the capacitor 100 may be embedded in the insulator 280, and the barrier layer 281 may be formed using a conductor or an insulator with a barrier property over the conductor 244.
• the barrier layer 281 is preferably formed using a conductor with not only a high barrier property but also a high oxidation resistance. Since part of the conductor 244 functions as the electrode (the conductor 112) of the capacitor in this structure, a separate conductor does not need to be provided.
• the capacitor 100 includes the conductor 112 that is a region of the conductor 244, the insulator 282, the insulator 130, and the conductor 116.
• the conductor 112 functioning as the electrode of the capacitor 100 can be formed concurrently with the conductor 244. Such a structure can increase the productivity. Furthermore, the number of steps in the process can be reduced because a mask for forming the electrode of the capacitor is not needed.
• the insulator 220, the insulator 222, and the insulator 224 are stacked in this order over the insulator 216.
• a material having a barrier property against oxygen or hydrogen is preferably used for any of the insulators 220, 222, and 224. Note that the insulator 220, the insulator 222, and the insulator 224 function as part (a gate insulator) of the transistor 200 in some cases.
• the insulator 224 preferably includes an oxide containing oxygen in excess of that in the stoichiometric composition. That is, in the insulator 224, a region containing oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as excess-oxygen region) is preferably formed.
• excess-oxygen region a region containing oxygen in excess of that in the stoichiometric composition
• oxygen vacancies in the transistor 200 are reduced, whereby the reliability can be improved.
• an oxide material that releases part of oxygen by heating is preferably used as the insulator including the excess-oxygen region.
• An oxide that releases part of oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0 x 10 18 atoms/cm 3 , preferably greater than or equal to 3.0 x 10 20 atoms/cm 3 in TDS analysis.
• the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100 °C and lower than or equal to 700 °C, or higher than or equal to 100 °C and lower than or equal to 500 °C.
• silicon oxide a material containing silicon oxide or silicon oxynitride is preferably used.
• a metal oxide can be used. Note that in this specification, “silicon oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “silicon nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.
• the insulator 224 includes an excess-oxygen region
• the insulator 222 or the insulator 220 preferably has a barrier property against oxygen, hydrogen, and water.
• oxygen in the excess-oxygen region is not diffused to the transistor 300 side but supplied to the oxide 230 of the transistor 200 efficiently.
• the conductor 218 and the conductor (the conductor 205) included in the transistor 200 can be inhibited from reacting with oxygen of the excess-oxygen region and from generating an oxide.
• the conductor 219, the conductor 244, and the conductor 246 with a barrier property may be formed as illustrated in FIG. 25.
• the conductor 244 serving as a plug or a wiring may be embedded in the insulator 280, and the conductor 246 with a barrier property may be formed over the conductor 244.
• the conductor 246 is preferably formed using a conductor with not only a high barrier property but also a high oxidation resistance.
• the conductor 246 and the conductor 112 serving as the electrode of the capacitor can be formed at the same time.
• the conductor 246 also functions as a barrier layer in this structure, a separate barrier layer does not need to be provided.
• the capacitor 100 includes the conductor 112, the insulator 282, the insulator 130, and the conductor 116.
• the conductor 112 functioning as the electrode of the capacitor 100 can be formed concurrently with the conductor 246.
• the capacitor 100 as illustrated in FIG. 26 may be provided. That is, the conductor 244 serving as a plug or a wiring is embedded in the insulator 280, the barrier layer 281 with a barrier property is provided over the conductor 244, and then the insulator 282 with a barrier property and an insulator 284 are provided. After that, an insulator 286 with high planarity is formed over the insulator 284, whereby the capacitor 100 can be provided over the insulator 286 with high planarity.
• the capacitor 100 is provided over the insulator 286 and includes the conductor 112 (the conductor 112a and the conductor 112b), the insulator 130, an insulator 132, an insulator 134, and the conductor 116.
• the conductor 124 functions as a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
• the conductor 112 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 112 is formed concurrently with another component such as a conductor, Cu (copper), Al (aluminum), or the like which is a low-resistance metal material may be used. [0445]
• the insulators 130, 132, and 134 are provided over the conductor 112.
• the insulators 130, 132, and 134 can each be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like.
• the three-layer structure is illustrated in the drawing, a single-layer structure, a stacked-layer structure of two layers, or a stacked-layer structure of four or more layers may be employed.
• a material with high dielectric strength such as silicon oxynitride, is preferably used for the insulators 130 and 134, and a high dielectric constant (high-k) material, such as aluminum oxide, is preferably used for the insulator 132.
• high-k high dielectric constant
• a sufficient capacitance can be provided because of the high dielectric constant (high-k) insulator, and the dielectric strength can be increased and the electrostatic breakdown of the capacitor 100 can be prevented because of the insulator with high dielectric strength.
• the conductor 116 is provided over the conductor 112 with the insulators 130, 132, and 134 positioned therebetween.
• the conductor 116 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material which has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 116 is formed concurrently with another component such as a conductor, Cu (copper), Al (aluminum), or the like which is a low-resistance metal material may be used.
• the conductor 112 which functions as one electrode, includes a projecting structure body like the conductor 112b, the capacitance of the capacitor per projected area can be increased.
• the semiconductor device can be reduced in area, highly integrated, and miniaturized.
• a change in electrical characteristics can be prevented and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor.
• a transistor including an oxide semiconductor with high on-state current can be provided.
• a transistor including an oxide semiconductor with low off-state current can be provided.
• a semiconductor device with low power consumption can be provided.
• FIG. 27 illustrates another modification example of this embodiment.
• FIG. 27 is different from FIG. 23 in the structures of the transistors 300 and 200.
• the semiconductor region 312 (part of the substrate 311) in which the channel is formed has a projecting shape. Furthermore, the conductor 316 is provided to cover top and side surfaces of the semiconductor region 312 with the insulator 314 positioned therebetween. Note that the conductor 316 may be formed using a material for adjusting the work function.
• the transistor 300 having such a structure is also referred to as a FIN transistor because the projection of the semiconductor substrate is utilized. An insulator serving as a mask for forming the projection may be provided in contact with a top surface of the projection.
• a semiconductor film having a projection may be formed by processing an SOI substrate.
• An oxide, a gate insulator, and a conductor serving as a gate are formed in an opening formed in the insulator 280.
• the conductor 112 has a stacked-layer structure of a conductor having a barrier property against oxygen, hydrogen, or water (e.g., tantalum nitride) and a conductor having high conductivity (e.g., tungsten or copper)
• the conductor having high conductivity e.g., tungsten or copper
• the conductor having high conductivity is completely sealed with tantalum nitride and the barrier layer 281.
• the capacitor 100 is provided above the transistor 200.
• the capacitor 100 includes the conductor 112, the conductor 246 having a barrier property, the insulator 282, the insulator 130, and the conductor 116.
• the conductor 112 functions as the electrode of the capacitor 100.
• part of the conductor 244 functioning as a plug or a wiring that is connected to the transistor 200 and the transistor 300 functions as the conductor 112.
• the barrier layer 281 when the barrier layer 281 has conductivity, the barrier layer 281 functions as part of the electrode of the capacitor 100.
• the barrier layer 281 When the barrier layer 281 has an insulating property, the barrier layer 281 functions as a dielectric of the capacitor 100.
• Such a structure can increase the productivity owing to a reduction of the number of steps in the process as compared to the case where the electrode and the wiring are formed separately.

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