WO2017148144A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017148144A1
WO2017148144A1 PCT/CN2016/100815 CN2016100815W WO2017148144A1 WO 2017148144 A1 WO2017148144 A1 WO 2017148144A1 CN 2016100815 W CN2016100815 W CN 2016100815W WO 2017148144 A1 WO2017148144 A1 WO 2017148144A1
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Prior art keywords
layer
region
electrode layer
goa
photoresist
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PCT/CN2016/100815
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English (en)
French (fr)
Inventor
卢彦春
蒋学兵
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/522,861 priority Critical patent/US10147644B2/en
Publication of WO2017148144A1 publication Critical patent/WO2017148144A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/12—Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of fabricating the same, and a display device.
  • GOA Gate Driver IC
  • the design process of the twisted nematic (TN) type display panel due to the characteristics of the liquid crystal deflection principle, it is necessary to use the Au ball in the sealant to laminate the indium tin oxide (ITO) electrode layer and the array on the color filter substrate side.
  • the pixel electrode on the substrate side is turned on.
  • the driving circuit of the GOA area is designed with many via holes, and if the array substrate is electrically connected to the ITO electrode layer on the color film substrate side in the via hole of the GOA area, display defects may occur.
  • the design method of the related TN type display panel is: coating the encapsulant at a certain distance in the GOA area, thus causing the TN type display panel frame to be higher than the Advanced Super Dimension Switch (ADS) type display panel.
  • ADS Advanced Super Dimension Switch
  • the present disclosure provides an array substrate, a method for fabricating the same, and a display device, which can solve the problem that the array substrate in the GOA region is easily separated from the color filter substrate side in the related art.
  • the ITO electrode layer is turned on, causing a problem of poor display.
  • the present disclosure provides a method of fabricating an array substrate, the array substrate including a display area and a GOA area, and the method includes:
  • the TFT structure of the GOA region includes a gate line metal layer and a data line metal layer;
  • the thickness of the photoresist is greater than the thickness of the remaining photoresist on the display region electrode layer;
  • the GOA region electrode layer is connected to the gate line metal layer through the first via hole, and the GOA region electrode layer is connected to the data line metal layer through the second via hole.
  • the photoresist is exposed and developed by using a halftone mask, and the ITO layer is etched to form a GOA region electrode layer and a display region electrode layer, including:
  • the photoresist layer is exposed by using a halftone mask, and after the development, a photoresist completely removed region and a photoresist completely reserved region are formed in the GOA region, and photoresist is completely removed in the display region. a region and a photoresist portion reserved area;
  • the halftone mask comprises: an opaque sub-mask corresponding to the GOA area electrode layer, a corresponding full-transmission sub-mask of the GOA area except the electrode layer, and the display a semi-transmissive sub-mask corresponding to the regional electrode layer and a corresponding full-transmission sub-mask of the display region except the electrode layer.
  • the method further includes:
  • the sealant is used to bond the array substrate and the color filter substrate.
  • the TFT structure of the GOA region further includes a gate insulating layer, and the TFT structure of the display region includes a source/drain electrode layer; and the TFT structure in the display region and the TFT structure of the GOA region sequentially form a first An insulating layer, an ITO layer and a photoresist layer, including:
  • An ITO layer and a photoresist layer are sequentially formed on the first via, the second via, the third via, and the first insulating layer.
  • the display area electrode layer is a pixel electrode.
  • the method further includes:
  • the photoresist remaining on the electrode layer of the GOA region is thermally cured by an annealing process.
  • the method further includes:
  • the sealant is used to bond the array substrate and the color filter substrate.
  • the present disclosure provides an array substrate, the array substrate comprising:
  • a GOA region comprising a GOA region TFT structure, and a first insulating layer, a GOA region electrode layer, and a second insulating layer sequentially formed over the GOA region TFT structure;
  • the GOA region electrode layer passing through the first insulating layer And a first via hole of the gate insulating layer of the TFT structure of the GOA region is connected to a gate line metal layer of the TFT structure of the GOA region, and the GOA region electrode layer passes through a second via hole penetrating the first insulating layer a data line metal layer connection of the TFT structure of the GOA region;
  • a display area including a display area TFT structure, and a TFT structure sequentially formed in the display area a first insulating layer and a display region electrode layer; the display region electrode layer is connected to the source/drain electrode layer of the display region TFT structure through a third via hole penetrating the first insulating layer;
  • the second insulating layer completely covers the GOA region electrode layer.
  • the second insulating layer is a photoresist.
  • the second insulating layer of the GOA region is covered with a sealant.
  • the display area electrode layer is a pixel electrode.
  • the present disclosure provides a display device comprising any of the above array substrate and color film substrate.
  • the photoresist layer is exposed and developed by the halftone mask, so that the thickness of the residual photoresist of the GOA region electrode layer on the array substrate is greater than that of the remaining photoresist layer on the display region electrode layer.
  • the thickness of the glue as such, after the ashing of the remaining photoresist, a portion of the photoresist over the GOA region can be retained to enable the photoresist to cover the vias on the GOA region to provide protection to the via regions.
  • the sealant can be coated on the GOA region, the array substrate is not electrically connected to the ITO electrode layer on the side of the color filter substrate at the via hole, thereby further reducing the frame of the panel to form a TN-type narrow.
  • a border display panel is available.
  • the present disclosure only needs to use a halftone mask as an ITO mask, and it is possible to realize the photoresist in the via position of the GOA region as an insulating layer to isolate the GOA region without adding an additional Mask. Holes and sealant.
  • FIG. 1 is a schematic view showing a typical via design of a GOA region in the related art
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure
  • FIG. 3 is a schematic diagram of forming a gate electrode layer and a gate line metal layer in an array substrate according to some embodiments of the present disclosure
  • FIG. 4 is a schematic diagram of forming a gate insulating layer in an array substrate according to some embodiments of the present disclosure
  • FIG. 5 is a schematic diagram of forming an active layer in an array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of forming a source/drain electrode layer and a data line metal layer in an array substrate according to some embodiments of the present disclosure
  • FIG. 7 is a schematic diagram of forming a first insulating layer in an array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of forming a first via, a second via, and a third via in an array substrate according to some embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of forming an ITO metal layer in an array substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of forming a photoresist layer in an array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a developed substrate in an array substrate according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic diagram of forming a GOA region electrode layer and a display region electrode layer in an array substrate according to some embodiments of the present disclosure
  • FIG. 13 is a schematic diagram of an array substrate provided by some embodiments of the present disclosure.
  • FIG. 14 is a schematic diagram of forming a sealant in an array substrate according to some embodiments of the present disclosure.
  • Figure 15 is a schematic view showing the sealing of the array substrate and the color filter substrate in the related art
  • 16 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure
  • 3 to 15 illustrate: 1-substrate; 2-gate electrode layer; 3-gate line metal layer; 4-gate insulating layer; 5-active layer; 6-source drain electrode layer; 7-data line Metal layer; 8-first insulating layer; 9-ITO metal layer; 10-photoresist layer; 11-GOA region electrode layer; 12-display region electrode layer; 13-sealant; 14-ITO electrode layer; 15- a light shielding layer; 16 - a second insulating layer.
  • FIG. 2 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure.
  • the array substrate in this embodiment includes a display area and a GOA area.
  • the method for fabricating the array substrate in this embodiment specifically includes the following steps:
  • S201 a TFT structure in which a display region is formed on a substrate, and a TFT structure of the GOA region.
  • the TFT structure of the display region may include a gate electrode layer, a gate insulating layer, an active layer, and a source/drain electrode layer.
  • the TFT structure of the GOA region may specifically include: a gate line metal layer, a gate insulating layer, and a data line metal layer.
  • S202 sequentially forming a first insulating layer, an ITO layer, and a photoresist layer on the TFT structure of the display region and the TFT structure of the GOA region.
  • S203 performing exposure and development on the photoresist layer by using a halftone mask, and etching the ITO layer to form a GOA region electrode layer and a display region electrode layer; and remaining light on the GOA region electrode layer
  • the thickness of the glue is greater than the thickness of the remaining photoresist on the electrode layer of the display area.
  • S204 Perform ashing treatment on the remaining photoresist to completely remove the photoresist on the electrode layer of the display region, and thin the photoresist on the electrode layer of the GOA region.
  • the GOA region electrode layer is connected to the gate line metal layer through the first via hole, and the GOA region electrode layer is connected to the data line metal layer through the second via hole.
  • the embodiment of the present disclosure exposes and develops the photoresist layer through a halftone mask, so that the thickness of the residual photoresist of the GOA region electrode layer on the array substrate is greater than that of the remaining photoresist layer on the display region electrode layer.
  • the thickness of the glue such that after the remaining photoresist is ashed, a portion of the photoresist over the GOA region can be retained so that the photoresist can cover the vias on the GOA region, so that if the sealant can be coated
  • the array substrate is not electrically connected to the ITO electrode layer on the side of the color filter substrate at the via hole, thereby providing a possibility to further reduce the frame of the panel to form a TN-type narrow bezel display panel.
  • the display region electrode layer may be a pixel electrode.
  • step S203 is specifically implemented by the following steps, including:
  • A01 exposing the photoresist layer by using a halftone mask, forming a photoresist completely removed region and a photoresist completely remaining region in the GOA region after development, forming a photoresist in the display region The area and the photoresist portion retention area are completely removed.
  • the halftone mask includes: an opaque sub-mask corresponding to the GOA region electrode layer, a corresponding full-transmission sub-mask outside the electrode layer of the GOA region, and the display region electrode The semi-transmissive sub-mask of the layer and the corresponding full-transmission sub-mask of the display area except the electrode layer.
  • the photoresist completely reserved region of the GOA region corresponds to the opaque sub-mask
  • the photoresist completely removed region of the GOA region corresponds to the fully transparent sub-mask
  • the resist portion of the display region corresponds to the reserved region.
  • the semi-transmissive sub-mask, and the photoresist completely removed region of the display region corresponds to the full-transmission sub-mask.
  • the photoresist layer in the remaining portion of the photoresist portion is thinned after exposure and development.
  • A02 etching the ITO layer, forming the GOA region electrode layer in the photoresist completely reserved region, and forming the display region electrode layer in the photoresist portion remaining region.
  • the thickness of the photoresist on the electrode layer of the GOA region is made larger than the thickness of the photoresist on the electrode layer of the display region.
  • step S202 is specifically implemented by the following steps, including:
  • B01 forming a first insulating layer on the TFT structure of the display region and the TFT structure of the GOA region;
  • B02 forming a first via hole penetrating the first insulating layer and the gate insulating layer and exposing the gate line metal layer in the GOA region, and forming a metal penetrating through the first insulating layer and exposing the data line a second via of the layer;
  • the GOA region is provided with at least one first via and at least one second via, the bottom of the first via being a gate metal layer of the TFT structure of the GOA region, and the bottom of the second via being a GOA region
  • the data line metal layer of the TFT structure a photoresist remains on the GOA region electrode layer, and a photoresist remains on the first via and the second via of the GOA region.
  • the GOA region is formed with via holes, and the photoresist can cover the via holes of the GOA region, the sealant is coated on the GOA region, and the ITO layer of the array substrate at the via hole and the color filter substrate side is not caused. Turn on.
  • the method for fabricating the array substrate in the embodiment further includes the following steps not shown in FIG. 2:
  • S205 The photoresist remaining on the electrode layer of the GOA region is thermally cured by an annealing process.
  • the method for fabricating the array substrate in this embodiment may further include the following steps:
  • the sealant is used to bond the array substrate and the color filter substrate.
  • a sealant is further coated on the GOA region electrode layer of the array substrate to paste the array substrate and the color filter substrate.
  • this embodiment directly applies the sealant on the GOA region without causing a via hole and a color filter substrate.
  • the side ITO is turned on, further reducing the frame of the display panel.
  • the substrate includes a display area and a GOA area.
  • the array substrate may further include other structures, and details are not described herein again. It is to be understood that the structures shown herein are illustrative and that other configurations are possible in accordance with the scope and spirit of the claims.
  • the manufacturing method of the array substrate in this embodiment may specifically include the following steps:
  • the substrate 1 can be a material such as glass, plastic or silicon.
  • Depositing such as molybdenum by sputtering Mo, aluminum/ ⁇ Al/Nd, aluminum/ ⁇ /molybdenum Al/Nd/Mo, molybdenum/aluminum/niobium/molybdenum Mo/Al/Nd/Mo, gold/titanium Au/Ti, platinum/titanium Pt/Ti Or the alloy forms a metal layer, and the metal layer is photolithographically etched to form the gate electrode layer 2 and the gate line metal layer 3.
  • atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition or sputtering such as silicon oxide SiO X , silicon nitride SiN X , silicon oxynitride SiON, aluminum oxide Al 2 O 3, hafnium oxide HfO 2, zirconium oxide ZrO 2, titanium oxide TiO 2, yttrium oxide Y 2 O 3, a single layer structure or a multilayer structure of lanthanum oxide La 2 O 3, tantalum oxide Ta 2 O 5 is formed of oxides such as Gate insulating layer 4.
  • sputtering, sol-gel, vacuum evaporation, spray coating or inkjet printing such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), indium tin zinc oxide (ITZO), zinc oxide
  • IGZO indium gallium zinc oxide
  • ZnON zinc oxynitride
  • ITZO indium tin zinc oxide
  • ZTO tin
  • ZIO zinc indium
  • IGO indium gallium oxide
  • AZTO aluminum zinc oxychloride
  • a sputtering method such as molybdenum Mo, aluminum/germanium Al/Nd, aluminum/germanium/molybdenum Al/Nd/Mo, molybdenum/aluminum/niobium/molybdenum Mo/Al/Nd/Mo, gold/titanium Au may be employed.
  • a metal or alloy such as /Ti, platinum/titanium Pt/Ti forms a second metal layer, and the second metal layer is photolithographically etched to form a drain-source electrode layer 6 and a data line metal layer 7.
  • the first insulating layer 8 may be a passivation layer, and may be a method of thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, or the like.
  • the GOA region is provided with at least one first via hole and at least one second via hole.
  • the bottom of the first via hole is the gate line metal layer 3 of the TFT structure of the GOA region, and the bottom of the second via hole is GOA.
  • the data line metal layer 7 of the TFT structure of the region is provided with at least one first via hole and at least one second via hole.
  • the display area is provided for electrically connecting the display area electrode layer (such as the pixel electrode) and the source/drain electrode layer 6 to the third via hole, and the bottom of the third via hole is the source/drain electrode layer 6.
  • a photoresist layer 10 is formed on the ITO metal layer 9, and the photoresist layer 10 is exposed using a halftone mask, as shown in FIG.
  • the halftone mask comprises an opaque mask corresponding to the GOA region electrode layer, a semi-transmissive mask corresponding to the display region electrode layer, and a full transmissive mask corresponding to other regions.
  • the semi-transmissive mask plate causes the photoresist on the display region electrode layer to be thinned after exposure and development, and the non-transmissive mask plate makes the thickness of the photoresist on the GOA region electrode layer unchanged after exposure and development. The photoresist of other regions is completely removed after exposure and development.
  • the ITO metal layer 9 is etched to form the GOA region electrode layer 11 and the display region electrode layer 12.
  • the remaining photoresist thickness above the developed GOA region electrode layer is greater than the remaining photoresist thickness above the display region electrode layer, as shown in FIG. 11 , and the GOA region electrode layer and Outside the display area electrode layer, the photoresist of other areas is completely removed.
  • the ITO metal layer 9 is subjected to wet etching to form the GOA region electrode layer 11 and the display region electrode layer 12 as shown in FIG.
  • the sealant 13 includes an Au ball, and the portion of the color filter substrate corresponding to the sealant 13 includes an ITO electrode layer 14 and a light shielding layer 15.
  • FIG. 1 shows a typical via design of a GOA region in the related art, in which 101 is a gate line metal, 102 is a data line metal, and 103 is a via hole (GI/PVX via) penetrating the gate insulating layer and the passivation layer.
  • 104 is an ITO layer that conducts two layers of metal 101 and 102. Since a plurality of via holes 103 are present in the GOA region, if the array substrate is electrically connected to the ITO electrode layer on the color filter substrate side at the via hole, display defects may occur. In view of this, as shown in FIG. 15, in the related art, the sealant coating position is spaced apart from the GOA region by a certain distance, so that the display panel frame is wider.
  • the method for fabricating the array substrate directly applies the sealant 13 over the photoresist on the GOA region electrode layer, which can greatly reduce the width of the display panel frame. It is advantageous to form a narrow frame panel of the TN type.
  • the array substrate in this embodiment includes: a GOA area and a display area. among them:
  • a GOA region including a GOA region TFT structure, and a first insulating layer 8, a GOA region electrode layer 11, and a second insulating layer 16 sequentially formed over the GOA region TFT structure;
  • the GOA region electrode layer 11 passes through
  • the first vias of the first insulating layer 8 and the gate insulating layer 4 are connected to the gate line metal layer 3 of the TFT structure of the GOA region, and the GOA region electrode layer 11 passes through the second through the first insulating layer 8.
  • the holes are connected to the data line metal layer 7 of the TFT structure of the GOA region.
  • a display region including a display region TFT structure, and a first insulating layer 8 and a display region electrode layer 12 sequentially formed over the display region TFT structure; the display region electrode layer 12 passing through the first insulating layer 8
  • the third via is connected to the source/drain electrode layer 6 of the TFT structure of the display region.
  • the second insulating layer 16 completely covers the GOA region electrode layer 11.
  • the display region electrode layer 12 is a pixel electrode.
  • this embodiment forms a second insulating layer over the GOA region electrode layer so that the second insulating layer can cover the via holes of the GOA region.
  • the sealant can be coated on the GOA region, the via hole and the ITO electrode layer on the side of the color filter substrate are not turned on, thereby providing a TN-type narrow bezel display panel for further reducing the frame of the panel. may.
  • the second insulating layer 16 may be a photoresist.
  • the second insulating layer 16 of the GOA region is covered with a sealant 13 for bonding the array substrate and the color filter substrate.
  • array substrate provided by the embodiment of the present disclosure can be fabricated by any method for fabricating the above array substrate, and will not be described in detail herein.
  • some embodiments of the present disclosure provide a display device including any of the above array substrates, which may be: a liquid crystal display panel, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator. Since the display device includes the display device of any of the above array substrates, the same technical problem can be solved and the same technical effects can be obtained.
  • the orientation or positional relationship of the terms “upper”, “lower” and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present disclosure and simplified description. It is not intended to be a limitation or limitation of the invention.
  • the terms “mounted,” “connected,” and “connected” are used in a broad sense, and may be, for example, a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, It can also be an electrical connection; it can be directly connected, or it can be connected indirectly through an intermediate medium, which can be the internal connection of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.

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Abstract

一种阵列基板及其制作方法、显示装置。其中，方法包括：在衬底(1)上形成显示区域的薄膜晶体管(TFT)结构及阵列基板行驱动(GOA)区域的TFT结构；在TFT结构上依次形成第一绝缘层(8)、ITO层(9)及光刻胶层(10)；采用半色调掩膜板，对该光刻胶层进行曝光显影，并对该ITO层进行刻蚀，形成GOA区域电极层(11)及显示区域电极层(12)，该GOA区域电极层上剩余光刻胶的厚度大于该显示区域电极层上剩余光刻胶的厚度；对剩余光刻胶进行灰化处理，以完全去除该显示区域电极层上的光刻胶，及减薄该GOA区域电极层上的光刻胶。该GOA区域电极层通过第一过孔与GOA区域的TFT结构的栅线金属层(3)连接，该GOA区域电极层通过第二过孔与GOA区域的TFT结构的数据线金属层(7)连接。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2016年3月1日在中国提交的中国专利申请号No.201610115048.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、一种显示装置。
背景技术
随着薄膜晶体管液晶显示器(thin film transistor-liquid crystal display，简称TFT-LCD)的技术发展，特别是小尺寸屏幕对窄边框的要求越来越高，因而阵列基板行驱动(Gate Drive On Array，简称GOA)技术的使用更加频繁。GOA技术可以将栅极驱动电路(Gate Driver IC)集成在TFT基板上而不是设置在TFT基板所在区域外部，从而减小面板的边框，使得面板更加符合技术的发展趋势。
在扭曲向列(TN)型显示面板的设计过程中，由于其液晶偏转原理的特性，必须利用密封胶内的金球(Au ball)将彩膜基板侧氧化铟锡(ITO)电极层与阵列基板侧的像素电极导通。而对于具有GOA设计的TN型面板，GOA区域的驱动电路设计有许多过孔，而阵列基板若在GOA区域过孔处与彩膜基板侧ITO电极层导通会造成显示不良。相关TN型显示面板的设计方法是：在GOA区域一定距离外涂覆封装胶，如此，就造成了TN型显示面板边框比高级超维场转换技术(Advanced Super Dimension Switch，ADS)型显示面板的边框宽。
发明内容
针对相关技术的缺陷，本公开提供了一种阵列基板及其制作方法、一种显示装置，能够解决相关技术中阵列基板在GOA区域的过孔处容易与彩膜基板侧 ITO电极层导通，从而造成显示不良的问题。
第一方面，本公开提供了一种阵列基板的制作方法，所述阵列基板包括显示区域和GOA区域，该方法包括：
在衬底上形成显示区域的薄膜晶体管TFT结构及所述GOA区域的TFT结构，其中所述GOA区域的TFT结构包括栅线金属层和数据线金属层；
在所述显示区域的TFT结构和所述GOA区域的TFT结构上依次形成第一绝缘层、ITO层及光刻胶层；
采用半色调掩膜板，对所述光刻胶层进行曝光显影，并对所述ITO层进行刻蚀，形成GOA区域电极层及显示区域电极层；所述GOA区域电极层上剩余光刻胶的厚度大于所述显示区域电极层上剩余光刻胶的厚度；
对剩余光刻胶进行灰化处理，以完全去除所述显示区域电极层上的光刻胶，及减薄所述GOA区域电极层上的光刻胶；
其中，所述GOA区域电极层通过第一过孔与栅线金属层连接，所述GOA区域电极层通过第二过孔与数据线金属层连接。
可选的，所述采用半色调掩膜板，对所述光刻胶进行曝光显影，并对所述ITO层进行刻蚀，形成GOA区域电极层及显示区域电极层，包括：
采用半色调掩膜板，对所述光刻胶层进行曝光，显影后在所述GOA区域形成光刻胶完全去除区域和光刻胶完全保留区域，在所述显示区域形成光刻胶完全去除区域和光刻胶部分保留区域；
对所述ITO层进行刻蚀，在所述GOA区域的光刻胶完全保留区域形成所述GOA区域电极层，在所述显示区域的光刻胶部分保留区域形成所述显示区域电极层。
可选的，所述半色调掩膜板包括：所述GOA区域电极层对应的不透光子掩膜板、所述GOA区域除电极层外对应的全透光子掩膜板、所述显示区域电极层对应的半透光子掩膜板以及所述显示区域除电极层外对应的全透光子掩膜板。
可选的，所述方法还包括：
在所述GOA区域电极层的光刻胶上方涂覆密封胶；
其中，所述密封胶用于粘接所述阵列基板与彩膜基板。
可选的，所述GOA区域的TFT结构还包括栅绝缘层，显示区域的TFT结构包括源漏电极层；所述在所述显示区域的TFT结构和所述GOA区域的TFT结构上依次形成第一绝缘层、ITO层及光刻胶层，包括：
在所述显示区域的TFT结构和所述GOA区域的TFT结构上形成第一绝缘层；
在所述GOA区域，形成贯穿所述第一绝缘层及所述栅绝缘层且暴露出栅线金属层的第一过孔，及形成贯穿所述第一绝缘层且暴露出所述数据线金属层的第二过孔；以及
在所述显示区域，形成贯穿所述第一绝缘层且暴露出源漏电极层的第三过孔；
在所述第一过孔、所述第二过孔、所述第三过孔及所述第一绝缘层上依次形成ITO层及光刻胶层。
可选的，所述显示区域电极层为像素电极。
可选的，所述方法还包括：
采用退火工艺，对所述GOA区域电极层上剩余的光刻胶进行热固化。
可选的，所述方法还包括：
在所述GOA区域电极层的光刻胶上方涂覆密封胶；
其中，所述密封胶用于粘接所述阵列基板与彩膜基板。
第二方面，本公开提供了一种阵列基板，所述阵列基板包括：
GOA区域，包括GOA区域TFT结构，及依次形成于所述GOA区域TFT结构上方的第一绝缘层、GOA区域电极层及第二绝缘层；所述GOA区域电极层通过贯穿所述第一绝缘层和所述GOA区域TFT结构的栅绝缘层的第一过孔与所述GOA区域TFT结构的栅线金属层连接，所述GOA区域电极层通过贯穿所述第一绝缘层的第二过孔与所述GOA区域TFT结构的数据线金属层连接；
显示区域，包括显示区域TFT结构，及依次形成于所述显示区域TFT结构 上方的第一绝缘层及显示区域电极层；所述显示区域电极层通过贯穿所述第一绝缘层的第三过孔与所述显示区域TFT结构的源漏电极层连接；
其中，所述第二绝缘层完全覆盖所述GOA区域电极层。
可选的，所述第二绝缘层为光刻胶。
可选的，所述GOA区域的第二绝缘层上方覆盖有密封胶。
可选的，所述显示区域电极层为像素电极。
第三方面，本公开提供了一种显示装置，包括上述任意一种阵列基板和彩膜基板。
由上述技术方案可知，本公开实施例通过半色调掩膜板对光刻胶胶层进行曝光显影，使得阵列基板上的GOA区域电极层剩余光刻胶的厚度大于显示区域电极层上剩余光刻胶的厚度，如此，对剩余光刻胶进行灰化处理后，能够保留GOA区域上方的部分光刻胶，以使光刻胶能够覆盖GOA区域上的过孔，对过孔区域形成保护。进一步地，若将密封胶能够涂覆在GOA区域上后，不会造成阵列基板在过孔处与彩膜基板侧的ITO电极层导通，从而为进一步减小面板的边框以形成TN型窄边框显示面板提供了可能。
与相关技术相比，本公开只需使用半色调掩膜板作为ITO Mask，无需增加额外的Mask就能够实现在GOA区域的过孔位置保留光刻胶而作为绝缘层，以隔离GOA区域的过孔与密封胶。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些图获得其他的附图。
图1是相关技术中GOA区域典型的过孔设计的示意图；
图2是本公开一些实施例提供的一种阵列基板的制作方法的流程示意图；
图3是本公开一些实施例提供的阵列基板中形成栅电极层及栅线金属层的示意图；
图4是本公开一些实施例提供的阵列基板中形成栅绝缘层的示意图；
图5是本公开一些实施例提供的阵列基板中形成有源层的示意图；
图6是本公开一些实施例提供的阵列基板中形成源漏电极层及数据线金属层的示意图；
图7是本公开一些实施例提供的阵列基板中形成第一绝缘层的示意图；
图8是本公开一些实施例提供的阵列基板中形成第一过孔、第二过孔及第三过孔的示意图；
图9是本公开一些实施例提供的阵列基板中形成ITO金属层的示意图；
图10是本公开一些实施例提供的阵列基板中形成光刻胶层的示意图；
图11是本公开一些实施例提供的阵列基板中显影后的示意图；
图12是本公开一些实施例提供的阵列基板中形成GOA区域电极层及显示区域电极层的示意图；
图13是本公开一些实施例提供的阵列基板的示意图；
图14是本公开一些实施例提供的阵列基板中形成密封胶的示意图；
图15相关技术中阵列基板与彩膜基板密封的示意图；
图16是本公开一些实施例提供的一种阵列基板的制作方法的流程示意图；
图3～图15中标记说明：1-衬底；2-栅电极层；3-栅线金属层；4-栅绝缘层；5-有源层；6-源漏电极层；7-数据线金属层；8-第一绝缘层；9-ITO金属层；10-光刻胶层；11-GOA区域电极层；12-显示区域电极层；13-密封胶；14-ITO电极层；15-遮光层；16-第二绝缘层。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是 全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图2是本公开一些实施例提供的一种阵列基板的制作方法的流程示意图，本实施例中的阵列基板包括显示区域和GOA区域。如图2所示，本实施例中的阵列基板的制作方法具体包括如下步骤：
S201：在衬底上形成显示区域的TFT结构，及所述GOA区域的TFT结构。
例如，显示区域的TFT结构可包括：栅电极层、栅绝缘层、有源层及源漏电极层。而GOA区域的TFT结构具体可包括：栅线金属层、栅绝缘层及数据线金属层等。
S202：在所述显示区域的TFT结构和所述GOA区域的TFT结构上依次形成第一绝缘层、ITO层及光刻胶层。
S203：采用半色调掩膜板，对所述光刻胶层进行曝光显影，并对所述ITO层进行刻蚀，形成GOA区域电极层及显示区域电极层；所述GOA区域电极层上剩余光刻胶的厚度大于所述显示区域电极层上剩余光刻胶的厚度。
S204：对剩余光刻胶进行灰化处理，以完全去除所述显示区域电极层上的光刻胶，及减薄所述GOA区域电极层上的光刻胶。
其中，所述GOA区域电极层通过第一过孔与栅线金属层连接，所述GOA区域电极层通过第二过孔与数据线金属层连接。
与相关技术相比，本公开实施例通过半色调掩膜板对光刻胶胶层进行曝光显影，使得阵列基板上的GOA区域电极层剩余光刻胶的厚度大于显示区域电极层上剩余光刻胶的厚度，如此，对剩余光刻胶进行灰化处理后，能够保留GOA区域上方的部分光刻胶，以使光刻胶能够覆盖GOA区域上的过孔，如此，若将密封胶能够涂覆在GOA区域上后，不会造成阵列基板在过孔处与彩膜基板侧的ITO电极层导通，从而为进一步减小面板的边框以形成TN型窄边框显示面板提供了可能。
本实施例中，所述显示区域电极层可为像素电极。
本实施例中，步骤S203，具体可通过如下步骤实现，包括：
A01、采用半色调掩膜板，对所述光刻胶层进行曝光，显影后在所述GOA区域形成光刻胶完全去除区域和光刻胶完全保留区域，在所述显示区域形成光刻胶完全去除区域和光刻胶部分保留区域。
其中，所述半色调掩膜板包括：所述GOA区域电极层对应的不透光子掩膜板、所述GOA区域除电极层外对应的全透光子掩膜板、所述显示区域电极层对应的半透光子掩膜板以及所述显示区域除电极层外对应的全透光子掩膜板。
可理解地，GOA区域的光刻胶完全保留区域对应不透光子掩膜板，GOA区域的光刻胶完全去除区域对应全透光子掩膜板，显示区域的光刻胶部分保留区域对应半透光子掩膜板，而显示区域的光刻胶完全去除区域对应全透光子掩膜板。
其中，光刻胶部分保留区域内的光刻胶层在曝光显影后有所减薄。
A02、对所述ITO层进行刻蚀，在所述光刻胶完全保留区域形成所述GOA区域电极层，在所述光刻胶部分保留区域形成所述显示区域电极层。
如此，通过上述步骤，使得GOA区域电极层上的光刻胶厚度大于显示区域电极层上的光刻胶厚度。使得后续对光刻胶进一步进行灰化处理后，能够在GOA区域电极层上保留有光刻胶，将GOA区域的过孔用光刻胶进行隔离。
本实施例中，步骤S202，具体可通过如下步骤实现，包括：
B01：在所述显示区域的TFT结构和所述GOA区域的TFT结构上形成第一绝缘层；
B02：在所述GOA区域，形成贯穿所述第一绝缘层及栅绝缘层且暴露出栅线金属层的第一过孔，及形成贯穿所述第一绝缘层且暴露出所述数据线金属层的第二过孔；以及
B03：在所述显示区域，形成贯穿所述第一绝缘层且暴露出所述源漏电极层的第三过孔；
B04：在所述第一过孔、所述第二过孔、所述第三过孔及所述第一绝缘层 上依次形成ITO层及光刻胶层。
具体而言，GOA区域设置有至少一个第一过孔和至少一个第二过孔，第一过孔的底部为GOA区域的TFT结构的栅线金属层，第二过孔的底部为GOA区域的TFT结构的数据线金属层。如此，GOA区域电极层上保留有光刻胶，则GOA区域的第一过孔和第二过孔的上方保留有光刻胶。由此可见，由于GOA区域形成有过孔，而光刻胶能够覆盖GOA区域的过孔，从而密封胶涂覆在GOA区域，不会造成阵列基板在过孔处与彩膜基板侧的ITO层导通。
进一步地，本实施例中的阵列基板的制作方法在步骤S204之后，还包括图2未出的如下步骤：
S205：采用退火工艺，对所述GOA区域电极层上剩余的光刻胶进行热固化。
进一步地，本实施例中的阵列基板的制作方法还可包括如下步骤：
在所述GOA区域电极层的光刻胶上方涂覆密封胶；
其中，所述密封胶用于粘接所述阵列基板与彩膜基板。
由此可见，本实施例中在阵列基板的GOA区域电极层上进一步涂覆密封胶，以粘贴所述阵列基板与彩膜基板。与相关技术中需在GOA区域及密封胶涂覆区域之间留出200um左右的距离相比，本实施例直接将密封胶涂覆于GOA区域之上，并不会造成过孔与彩膜基板侧ITO导通，进一步减小了显示面板的边框。
为了更清楚地说明本公开的技术方案，下面结合各步骤形成的器件结构的剖面示意图说明本公开的一些具体实施例，该实施例中，如图14所示出的最后产品结构所示，阵列基板包括显示区域及GOA区域，当然，阵列基板还可以包括其他结构，在此不再赘述。应该理解，这里示出的结构是示例性的，根据本公开权利要求限定的范围和精神，还可以具有其他结构形式。
如图16所示，该实施例中阵列基板的制作方法可具体包括如下步骤：
S1：在衬底1上形成第一金属层，并刻蚀第一金属层形成显示区域的栅电极层2及GOA区域的栅线金属层3，如图3所示。
一般来说，衬底1可为玻璃、塑料或硅等材料。采用溅射方法沉积如钼 Mo、铝/钕Al/Nd、铝/钕/钼Al/Nd/Mo、钼/铝/钕/钼Mo/Al/Nd/Mo、金/钛Au/Ti、铂/钛Pt/Ti等金属或合金形成金属层，并对金属层进行光刻刻蚀，形成栅电极层2及栅线金属层3。
S2：形成覆盖所述栅电极层2、栅线金属层3及衬底1的栅绝缘层4，如图4所示。
举例来说，采用常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相沉积或溅射等方法，沉积如氧化硅SiOX、氮化硅SiNX、氮氧化硅SiON、氧化铝Al2O3、氧化铪HfO2、氧化锆ZrO2、氧化钛TiO2、氧化钇Y2O3、氧化镧La2O3、氧化钽Ta2O5等氧化物形成的单层结构或多层结构的栅绝缘层4。
S3：形成覆盖所述栅绝缘层4的半导体层，并刻蚀该半导体层形成有源层5，如图5所示。
例如，采用溅射、溶胶-凝胶、真空蒸镀、喷涂或喷墨打印等方法，沉积如氧化铟镓锌(IGZO)、氮氧化锌(ZnON)，氧化铟锡锌(ITZO)，氧化锌锡(ZTO)、氧化锌铟(ZIO)、氧化铟镓(IGO)、氧化铝锌锡(AZTO)等氧化物形成半导体层，并刻蚀半导体层形成有源层5。
S4：在栅绝缘层4及有源层5上形成第二金属层，刻蚀第二金属层形成显示区域的源漏电极层6及GOA区域的数据线金属层7，如图6所示。
具体地，可采用溅射方法沉积如钼Mo、铝/钕Al/Nd、铝/钕/钼Al/Nd/Mo、钼/铝/钕/钼Mo/Al/Nd/Mo、金/钛Au/Ti、铂/钛Pt/Ti等金属或合金形成第二金属层，并对该第二金属层进行光刻刻蚀，形成漏源电极层6及数据线金属层7。
S5：形成覆盖源漏电极层6、数据线金属层7及栅绝缘层4的第一绝缘层8，如图7所示。
具体地，第一绝缘层8可为钝化层，可采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等方法。
S6：在GOA区域形成贯穿第一绝缘层8及栅绝缘层4且暴露出栅线金属层 3的第一过孔，形成贯穿第一绝缘层8且暴露出数据线金属层7的第二过孔，如图8所示。
可理解的是，GOA区域设置有至少一个第一过孔和至少一个第二过孔，第一过孔的底部为GOA区域的TFT结构的栅线金属层3，第二过孔的底部为GOA区域的TFT结构的数据线金属层7。
S7：在显示区域形成贯穿第一绝缘层8且暴露出源漏电极层6的第三过孔，如图8所示。
可理解地，显示区域设置有用于将显示区域电极层(如像素电极)与源漏电极层6电连接第三过孔，则第三过孔的底部为源漏电极层6。
S8：形成覆盖第一绝缘层8、第一过孔、第二过孔及第三过孔的ITO金属层9，如图9所示。
S9：在ITO金属层9上形成光刻胶层10，并采用半色调掩膜板对光刻胶层10进行曝光，如图10所示。
在本实施例中，半色调掩膜板包括GOA区域电极层对应的不透光掩膜板、显示区域电极层对应的半透光掩膜板，以及其他区域对应的全透光掩膜板，如图10所示。半透光掩膜板使得显示区域电极层上的光刻胶在曝光显影后有所减薄，而不透光掩膜板使得GOA区域电极层上的光刻胶在曝光显影后厚度不变，其他区域的光刻胶在曝光显影后则被完全去除。
S10：显影后对ITO金属层9进行刻蚀，形成GOA区域电极层11及显示区域电极层12。
需要说明的是，在本实施例中，显影后GOA区域电极层上方的剩余光刻胶厚度大于显示区域电极层上方的剩余光刻胶厚度，如图11所示，且除GOA区域电极层及显示区域电极层外，其他区域的光刻胶均被完全去除。
进一步地，对ITO金属层9进行湿法刻蚀，形成GOA区域电极层11及显示区域电极层12，如图12所示。
S11：对剩余光刻胶进行灰化，完全去除显示区域电极层12上方的光刻胶， 且减薄GOA区域电极层11上方的光刻胶，如图13所示。
如此，在GOA区域会保留一层完全覆盖GOA区域电极层的光刻胶。
S12：在GOA区域的光刻胶上方涂覆密封胶13，以粘接阵列基板及彩膜基板，如图14所示。
如图14所示，密封胶13中包含有金球(Au ball)，而彩膜基板对应密封胶13的部分包括有ITO电极层14及遮光层15。
图1示出了相关技术中GOA区域典型的过孔设计，其中101为栅线金属，102为数据线金属，103为贯穿栅极绝缘层和钝化层的过孔(GI/PVX过孔)，104为将两层金属101和102导通的ITO层，由于GOA区域内存在许多过孔103，如果阵列基板在过孔处与彩膜基板侧ITO电极层导通会造成显示不良。有鉴于此，如图15所示，相关技术中密封胶涂覆位置与GOA区域间隔一定的距离，使得显示面板边框较宽。与相关技术相比，如图14所示，本实施例提出的阵列基板的制作方法将密封胶13直接涂覆于GOA区域电极层上的光刻胶上方，能够大大减小显示面板边框的宽度，有利于形成TN型的窄边框面板。
本公开一些实施例提供了一种阵列基板，如图13所示，该实施例中的阵列基板包括：GOA区域和显示区域。其中：
GOA区域，包括GOA区域TFT结构，及依次形成于所述GOA区域TFT结构上方的第一绝缘层8、GOA区域电极层11及第二绝缘层16；所述GOA区域电极层11通过贯穿所述第一绝缘层8和栅绝缘层4的第一过孔与所述GOA区域TFT结构的栅线金属层3连接，所述GOA区域电极层11通过贯穿所述第一绝缘层8的第二过孔与所述GOA区域TFT结构的数据线金属层7连接。
显示区域，包括显示区域TFT结构，及依次形成于所述显示区域TFT结构上方的第一绝缘层8及显示区域电极层12；所述显示区域电极层12通过贯穿所述第一绝缘层8的第三过孔与所述显示区域TFT结构的源漏电极层6连接。
其中，所述第二绝缘层16完全覆盖所述GOA区域电极层11。
其中，所述显示区域电极层12为像素电极。
由此可见，本实施例通过在GOA区域电极层的上方形成第二绝缘层，以使第二绝缘层能够覆盖GOA区域的过孔。如此，若将密封胶能够涂覆在GOA区域上后，不会造成过孔与彩膜基板侧的ITO电极层导通，从而为进一步减小面板的边框以形成TN型窄边框显示面板提供了可能。
可选的，上述第二绝缘层16可为光刻胶。
如图14所示，在本公开一些实施例中，所述GOA区域的第二绝缘层16上方覆盖有密封胶13，用于粘接阵列基板及彩膜基板。
另外，本公开实施例所提供的阵列基板可由上述任意一种阵列基板的制作方法制作得到，在此不再详述。
基于同样的公开构思，本公开一些实施例提供了一种包括上述任意一种阵列基板的显示装置，该显示装置可以为：液晶显示面板、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置由于包括上述任意一种阵列基板的显示装置，因而可以解决同样的技术问题，并取得相同的技术效果。
在本公开的描述中，需要说明的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、 “包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (13)

  1. 一种阵列基板的制作方法，所述阵列基板包括显示区域和阵列基板行驱动(GOA)区域，该方法包括：
    在衬底上形成显示区域的薄膜晶体管(TFT)结构及所述GOA区域的TFT结构，其中所述GOA区域的TFT结构包括栅线金属层和数据线金属层；
    在所述显示区域的TFT结构和所述GOA区域的TFT结构上依次形成第一绝缘层、氧化铟锡(ITO)层及光刻胶层；
    采用半色调掩膜板，对所述光刻胶层进行曝光显影，并对所述ITO层进行刻蚀，形成GOA区域电极层及显示区域电极层；所述GOA区域电极层上剩余光刻胶的厚度大于所述显示区域电极层上剩余光刻胶的厚度；
    对剩余光刻胶进行灰化处理，以完全去除所述显示区域电极层上的光刻胶，及减薄所述GOA区域电极层上的光刻胶；
    其中，所述GOA区域电极层通过第一过孔与所述栅线金属层连接，所述GOA区域电极层通过第二过孔与所述数据线金属层连接。
  2. 根据权利要求1所述的方法，其中，所述采用半色调掩膜板，对所述光刻胶进行曝光显影，并对所述ITO层进行刻蚀，形成GOA区域电极层及显示区域电极层，包括：
    采用半色调掩膜板，对所述光刻胶层进行曝光，显影后在所述GOA区域形成光刻胶完全去除区域和光刻胶完全保留区域，在所述显示区域形成光刻胶完全去除区域和光刻胶部分保留区域；
    对所述ITO层进行刻蚀，在所述GOA区域的光刻胶完全保留区域形成所述GOA区域电极层，在所述显示区域的光刻胶部分保留区域形成所述显示区域电极层。
  3. 根据权利要求2所述的方法，其中，所述半色调掩膜板包括：所述GOA区域电极层对应的不透光子掩膜板、所述GOA区域除电极层外对应的全透光子 掩膜板、所述显示区域电极层对应的半透光子掩膜板以及所述显示区域除电极层外对应的全透光子掩膜板。
  4. 根据权利要求1-3中任一项所述的方法，还包括：
    在所述GOA区域电极层的光刻胶上方涂覆密封胶；
    其中，所述密封胶用于粘接所述阵列基板与彩膜基板。
  5. 根据权利要求1所述的方法，其中，所述GOA区域的TFT结构还包括栅绝缘层，显示区域的TFT结构包括源漏电极层；所述在所述显示区域的TFT结构和所述GOA区域的TFT结构上依次形成第一绝缘层、ITO层及光刻胶层，包括：
    在所述显示区域的TFT结构和所述GOA区域的TFT结构上形成第一绝缘层；
    在所述GOA区域，形成贯穿所述第一绝缘层及所述栅绝缘层且暴露出所述栅线金属层的第一过孔，及形成贯穿所述第一绝缘层且暴露出所述数据线金属层的第二过孔；以及
    在所述显示区域，形成贯穿所述第一绝缘层且暴露出所述源漏电极层的第三过孔；
    在所述第一过孔、所述第二过孔、所述第三过孔及所述第一绝缘层上依次形成ITO层及光刻胶层。
  6. 根据权利要求1所述的方法，其中，所述显示区域电极层为像素电极。
  7. 根据权利要求1所述的方法，还包括：
    采用退火工艺，对所述GOA区域电极层上剩余的光刻胶进行热固化。
  8. 根据权利要求1所述的方法，还包括：
    在所述GOA区域电极层的光刻胶上方涂覆密封胶；
    其中，所述密封胶用于粘接所述阵列基板与彩膜基板。
  9. 一种阵列基板，包括：
    阵列基板行驱动(GOA)区域，包括GOA区域TFT结构，及依次形成于所述GOA区域TFT结构上方的第一绝缘层、GOA区域电极层及第二绝缘层；所述 GOA区域电极层通过贯穿所述第一绝缘层和所述GOA区域TFT结构的栅绝缘层的第一过孔与所述GOA区域TFT结构的栅线金属层连接，所述GOA区域电极层通过贯穿所述第一绝缘层的第二过孔与所述GOA区域TFT结构的数据线金属层连接；
    显示区域，包括显示区域TFT结构，及依次形成于所述显示区域TFT结构上方的第一绝缘层及显示区域电极层；所述显示区域电极层通过贯穿所述第一绝缘层的第三过孔与所述显示区域TFT结构的源漏电极层连接；
    其中，所述第二绝缘层完全覆盖所述GOA区域电极层。
  10. 根据权利要求9所述的阵列基板，其中，所述第二绝缘层为光刻胶。
  11. 根据权利要求9所述的阵列基板，其中，所述GOA区域的第二绝缘层上方覆盖有密封胶。
  12. 根据权利要求9所述的阵列基板，其中，所述显示区域电极层为像素电极。
  13. 一种显示装置，包括权利要求8-11中任一项所述的阵列基板和彩膜基板。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204964955U (zh) * 2015-07-28 2016-01-13 合肥鑫晟光电科技有限公司 电连接结构、阵列基板和显示装置
CN105702685B (zh) * 2016-03-01 2018-09-04 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107170757B (zh) * 2017-05-25 2019-09-24 深圳市华星光电技术有限公司 一种阵列基板及其制作方法
CN107808886B (zh) * 2017-11-01 2020-11-06 京东方科技集团股份有限公司 过孔连接结构及制造方法、阵列基板及制造方法、显示装置
CN110061058A (zh) * 2018-04-17 2019-07-26 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
KR102535148B1 (ko) 2018-07-18 2023-05-22 삼성전자주식회사 디스플레이 패널 및 이를 이용한 대형 디스플레이 장치
CN109637447B (zh) * 2019-02-27 2020-09-25 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示面板
CN109976049A (zh) * 2019-04-08 2019-07-05 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111103715B (zh) * 2019-12-23 2023-03-31 Tcl华星光电技术有限公司 显示面板及其制作方法
CN113380833B (zh) * 2021-05-31 2024-02-20 合肥维信诺科技有限公司 阵列基板、显示面板及阵列基板的制备方法
CN113808952A (zh) * 2021-08-13 2021-12-17 吉林建筑大学 一种薄膜晶体管及其制备方法
CN116676571B (zh) * 2023-04-26 2024-01-19 武汉敏芯半导体股份有限公司 一种电极制作方法、电极和半导体器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103022055A (zh) * 2012-12-28 2013-04-03 北京京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
CN104658981A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105280649A (zh) * 2015-09-17 2016-01-27 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制备方法
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100776768B1 (ko) * 2001-07-21 2007-11-16 삼성전자주식회사 액정표시패널용 기판 및 그 제조방법
TWI408812B (zh) * 2007-12-10 2013-09-11 Au Optronics Corp 畫素結構的製作方法
KR101490472B1 (ko) * 2008-07-28 2015-02-05 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치
KR20100019666A (ko) * 2008-08-11 2010-02-19 삼성전자주식회사 박막 트랜지스터 표시판, 이를 포함하는 액정 표시 장치, 그리고 액정 표시 장치의 제조 방법
CN102455553B (zh) * 2010-10-22 2016-05-04 京东方科技集团股份有限公司 Tft-lcd、阵列基板及其制造方法
JP5927873B2 (ja) * 2011-12-01 2016-06-01 三菱電機株式会社 画像検出器
CN102902095B (zh) * 2012-10-09 2015-01-07 京东方科技集团股份有限公司 一种液晶装置及其制造方法
KR102081107B1 (ko) * 2013-05-30 2020-02-25 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그의 제조방법
CN104538413B (zh) * 2015-02-03 2018-03-23 重庆京东方光电科技有限公司 阵列基板及其制作方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103022055A (zh) * 2012-12-28 2013-04-03 北京京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
CN104658981A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105280649A (zh) * 2015-09-17 2016-01-27 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制备方法
CN105702685A (zh) * 2016-03-01 2016-06-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

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