WO2017092082A1 - 阵列基板以及液晶显示装置 - Google Patents

阵列基板以及液晶显示装置 Download PDF

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Publication number
WO2017092082A1
WO2017092082A1 PCT/CN2015/097997 CN2015097997W WO2017092082A1 WO 2017092082 A1 WO2017092082 A1 WO 2017092082A1 CN 2015097997 W CN2015097997 W CN 2015097997W WO 2017092082 A1 WO2017092082 A1 WO 2017092082A1
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Prior art keywords
sub
pixels
line
lines
data
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Ceased
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PCT/CN2015/097997
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English (en)
French (fr)
Inventor
曾勉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1805416.3A priority Critical patent/GB2557160B/en
Priority to JP2018527868A priority patent/JP6621924B2/ja
Priority to US14/905,588 priority patent/US9857651B2/en
Priority to KR1020187013705A priority patent/KR20180069873A/ko
Priority to RU2018112968A priority patent/RU2681670C1/ru
Publication of WO2017092082A1 publication Critical patent/WO2017092082A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a liquid crystal display device.
  • liquid crystal display Liquid Crystal Display
  • flat panel displays such as Organic Light Emitting Diode (OLED)
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • FIG. 1 is a schematic structural view of a prior art array substrate.
  • the array substrate includes a plurality of data lines that are parallel to each other and are vertically arranged in sequence, such as D1, D2, D3, D4, and D5. And so on, a plurality of horizontal scanning lines arranged in parallel and sequentially, such as G1, G2, G3, G4, etc., and sub-pixels arranged in an array.
  • Each sub-pixel located in the same row passes through a thin film transistor TFT Electrically connected to a scan line located above the row of sub-pixels, for example, each sub-pixel of the first row is electrically connected to the scan line G1 through a TFT, and each sub-pixel of the second row passes through a TFT.
  • each sub-pixel located in the same column is electrically connected to the data line located on the left side of the column sub-pixel through a TFT, for example, each sub-pixel of the first column passes through a TFT Electrically connected to the data line D1, each sub-pixel of the second column is electrically connected to the data line D2 through a TFT, and so on.
  • the above conventional connection method needs to occupy a large arrangement space of the array substrate, occupies a blackout area, reduces the aperture ratio of the display panel, and the utilization ratio of the data line and the scan line is small, which causes waste of resources and increases liquid crystal display.
  • the manufacturing cost of the device needs to occupy a large arrangement space of the array substrate, occupies a blackout area, reduces the aperture ratio of the display panel, and the utilization ratio of the data line and the scan line is small, which causes waste of resources and increases liquid crystal display.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display device, which can reduce the number of data lines and reduce the manufacturing cost, and can save the arrangement space, further reduce the light-shielding area, and increase the aperture ratio of the pixel.
  • a technical solution adopted by the present invention is to provide an array substrate including a plurality of data lines and a plurality of scan lines, the data lines and the scan lines intersecting but not intersecting to form a pixel area.
  • the array substrate further includes a plurality of R, G, and B sub-pixels, and the R, G, and B sub-pixels are sequentially arranged in a direction parallel to the data line, and each of the sub-pixels passes through a thin film transistor.
  • the TFT is electrically connected to the corresponding scan line and the data line; at least one of the sub-pixels is disposed in each of the pixel regions, and scan lines forming two adjacent pixel regions are different; wherein, adjacent The two sub-pixels have opposite polarities; the sub-pixels arranged in the horizontal direction of the scan line have the same color.
  • the sub-pixels are arranged in a direction parallel to the data lines in each of the pixel regions, and each of the sub-pixels is respectively connected to the corresponding scan line and the data line through a corresponding FTF.
  • the data lines connected to two adjacent sub-pixels arranged in the direction parallel to the scanning line are different.
  • the data line is used to output column inversion driving data or row inversion driving data.
  • the sub-pixel is disposed in the pixel region of the odd column, and the sub-pixels arranged in the parallel direction of the scan line are disposed in the pixel region of the even column, and each of the sub-pixels Connected to the corresponding scan lines by corresponding FTFs respectively, and adjacent scan lines connected by two adjacent sub-pixels arranged in a direction parallel to the scan lines are different; adjacent to each other on both sides of the same data line Two of the sub-pixels are connected to the same data line.
  • an array substrate including a plurality of data lines and a plurality of scan lines, the data lines and the scan lines intersecting but not intersecting to form a pixel area.
  • the array substrate further includes a plurality of R, G, and B sub-pixels, and the R, G, and B sub-pixels are sequentially arranged in a direction parallel to the data line, and each of the sub-pixels passes through a thin film transistor TFT. Electrically connecting to the corresponding scan line and the data line; at least one of the sub-pixels is disposed in each of the pixel regions, and scan lines forming two adjacent pixel regions are different.
  • the sub-pixels are arranged in a direction parallel to the data lines in each of the pixel regions, and each of the sub-pixels is respectively connected to the corresponding scan line and the data line through a corresponding FTF.
  • the data lines connected to two adjacent sub-pixels arranged in the direction parallel to the scanning line are different.
  • the data line is used to output column inversion driving data or row inversion driving data.
  • the sub-pixel is disposed in the pixel region of the odd column, and the sub-pixels arranged in the parallel direction of the scan line are disposed in the pixel region of the even column, and each of the sub-pixels Connected to the corresponding scan lines by corresponding FTFs respectively, and adjacent scan lines connected by two adjacent sub-pixels arranged in a direction parallel to the scan lines are different; adjacent to each other on both sides of the same data line Two of the sub-pixels are connected to the same data line.
  • the adjacent two sub-pixels have opposite polarities.
  • the sub-pixels arranged in the horizontal direction of the scanning line have the same color.
  • the drain of the TFT is electrically connected to the sub-pixel, the gate is electrically connected to the scan line, and the source is electrically connected to the data line.
  • a liquid crystal display device including an array substrate, a color filter substrate, and liquid crystal molecules sandwiched between the array substrate and the color filter substrate.
  • the array substrate includes a plurality of data lines and a plurality of scan lines, the data lines and the scan lines intersecting but not intersecting to form a pixel area, and the array substrate further includes a plurality of R, G, and B sub-pixels.
  • the R, G, and B sub-pixels are sequentially arranged in a direction parallel to the data line, and each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT; At least one of the sub-pixels is disposed in the pixel region, and scan lines forming two adjacent pixel regions are different.
  • the sub-pixels are arranged in a direction parallel to the data lines in each of the pixel regions, and each of the sub-pixels is respectively connected to the corresponding scan line and the data line through a corresponding FTF.
  • the data lines connected to two adjacent sub-pixels arranged in the direction parallel to the scanning line are different.
  • the data line is used to output column inversion driving data or row inversion driving data.
  • the sub-pixel is disposed in the pixel region of the odd column, and the sub-pixels arranged in the parallel direction of the scan line are disposed in the pixel region of the even column, and each of the sub-pixels Connected to the corresponding scan lines by corresponding FTFs respectively, and adjacent scan lines connected by two adjacent sub-pixels arranged in a direction parallel to the scan lines are different; adjacent to each other on both sides of the same data line Two of the sub-pixels are connected to the same data line.
  • the adjacent two sub-pixels have opposite polarities.
  • the sub-pixels arranged in the horizontal direction of the scanning line have the same color.
  • the drain of the TFT is electrically connected to the sub-pixel, the gate is electrically connected to the scan line, and the source is electrically connected to the data line.
  • the beneficial effects of the present invention are as follows: different from the prior art, the plurality of data lines and the scan lines of the array substrate of the present embodiment cross each other but do not intersect to form a pixel area, and further include a plurality of along and data lines.
  • the R, G, and B sub-pixels arranged in parallel in the parallel direction are only 1/3 of the data lines required for sequentially arranging the R, G, and B sub-pixels along the data line direction with respect to the prior art arranged along the scanning line. Saving 2/3 of the data line can save the cost of the array substrate to a large extent.
  • Each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT, and at least one of the sub-pixels is disposed in each of the pixel regions, and the scan lines forming the adjacent two of the pixel regions are different. That is, at least two scan lines are arranged between adjacent two pixel regions arranged along the data line.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • FIG. 1 is a schematic structural view of an embodiment of a prior art array substrate
  • FIG. 2 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 3 is a schematic structural view of another embodiment of an array substrate of the present invention.
  • [Correct according to Rule 91 29.01.2016] 4 is a schematic view showing the structure of an embodiment of a liquid crystal display device of the present invention.
  • the array substrate of the present embodiment includes a plurality of data lines and a plurality of scan lines, wherein the scan lines and the data lines do not intersect at each other but form a plurality of pixel regions.
  • the plurality of data lines are parallel to each other, and the plurality of scanning lines are parallel to each other, and the data lines and the scanning lines are perpendicular to each other, which is not limited herein.
  • the array substrate further includes a plurality of R, G, and B sub-pixels, and the R, G, and B sub-pixels are sequentially arranged in a direction parallel to the data line, and each of the sub-pixels is electrically connected to the thin film transistor TFT to Corresponding to the scan line and the data line; at least one of the sub-pixels is disposed in each of the pixel regions, and scan lines forming two adjacent pixel regions are different.
  • FIG. 2 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • the scanning line 201 and the data line 202 of the present embodiment do not intersect each other but form a plurality of pixel regions 203.
  • the plurality of R, G, and B sub-pixels 2031 are sequentially arranged along the direction of the data line 202, and are arranged horizontally along the scanning line 201.
  • the sub-pixels 2031 have the same color, and the adjacent two sub-pixels 2031 have opposite polarities.
  • the R, G, B sub-pixels are sequentially arranged in the direction of the data line 202, and the required data line is only 1/3, which saves 2/3 of the data line, although it will increase relatively.
  • the number of scan lines 201 is small, but since the flip chip COF on the scan line 201 side is much cheaper than the flip chip COF on the data line 202 side, and in other embodiments, the scan line 201 may even be directly disposed on the substrate, The flip chip COF is not required. Therefore, the sequential arrangement of the R, G, and B sub-pixels 2031 in the direction of the data line 202 can largely save the cost of the array substrate.
  • the scanning lines 201 forming the two pixel regions 203 are different, that is, the adjacent two pixel regions 203 arranged along the data line 202 do not share any of the scanning lines 201. That is, at least two scan lines 201 are arranged between adjacent two pixel regions 203 arranged along the data line 202.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • each of the pixel regions 203 is provided with two sub-pixels 2031 arranged in a parallel direction of the data lines, and each of the sub-pixels 2031 is connected to the corresponding scan line 201 and data line 202 through a corresponding TFT 2032.
  • the TFT The drain of 2032 is electrically connected to the sub-pixel 2031, the gate is electrically connected to the scan line 201, and the source stage is electrically connected to the data line 202.
  • each sub-pixel 2031 is connected to its most adjacent scan line 201 and data line 202, respectively.
  • two adjacent scanning lines 201 are arranged between two adjacent pixel regions 203 of the present embodiment, and the sub-pixels 2031 distributed on both sides of the two scanning lines 201 are respectively connected to one of them.
  • the data lines 202 to which the adjacent sub-pixels 2031 arranged in parallel parallel to the scanning line 201 are also different. For example, when the data lines are arranged in the horizontal direction and the scanning lines are arranged in the vertical direction, as shown in FIG. 2, one sub-pixel 2031 and the pixel area of the upper side of the two sub-pixels 2031 arranged in parallel along the direction of the data line 202 are arranged.
  • the data line 202 on the right side of the 203 is connected, and the sub-pixel 2031 on the lower side is connected to the data line 202 on the left side of the pixel area 203, that is, the sub-pixel 2031 of the odd-numbered row and the sub-pixel 2031 of the even-numbered row are arranged in a misaligned arrangement, and the sub-pixels arranged in the array are arranged.
  • the sub-pixels 2031 of the same order of adjacent rows are respectively connected to two adjacent data lines 202, and the voltages supplied by the adjacent data lines are different, and can be realized when the data lines 202 output column inversion data. Point reversal. Not only can a large amount of power consumed by dot inversion be saved, the cost of the array substrate can be reduced, and a good display effect by the dot inversion method can be realized, and the quality of the screen display can be improved.
  • the horizontal arrangement of the scan lines 201 and the vertical arrangement of the data lines 202 are opposite arrangement directions.
  • the positions of the scan lines 201 and the data lines 202 may also occur.
  • the horizontal direction and the vertical direction are also alternately alternated, and the column inversion of the data line at this time also corresponds to the line inversion. The essence has not changed, the effect is the same, and then there is no limit.
  • the plurality of data lines and the scan lines of the array substrate of the present embodiment cross each other but do not intersect to form a pixel area, and further include a plurality of R and G arranged in a direction parallel to the data lines.
  • B sub-pixels relative to the prior art arranged along the scan line, the R, G, B sub-pixels are sequentially arranged in the data line direction, the required data line is only 1/3, saving 2 / 3 of the data line, The cost of the array substrate can be largely saved.
  • Each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT, and at least one of the sub-pixels is disposed in each of the pixel regions, and the scan lines forming the adjacent two of the pixel regions are different. That is, at least two scan lines are arranged between adjacent two pixel regions arranged along the data line.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • the two sub-pixels arranged in the parallel direction of the data line disposed in each pixel region are respectively connected to the corresponding scan lines and data lines through the corresponding TFTs, and the adjacent two sub-pixels arranged in the parallel direction of the scan lines are connected.
  • the data lines are also different.
  • the voltages supplied by the adjacent data lines are different, and the dot inversion can be realized when the data line output column inverts the data. Not only can a large amount of power consumed by dot inversion be saved, the cost of the array substrate can be reduced, and a good display effect by the dot inversion method can be realized, and the quality of the screen display can be improved.
  • FIG. 3 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • the scan line 301 and the data line 302 of the array substrate of the present embodiment do not intersect each other but form a plurality of pixel regions 303, and the plurality of R, G, and B sub-pixels 3031 are sequentially arranged along the direction of the data line 302 along the scan line 301.
  • the sub-pixels 3031 arranged in the horizontal direction have the same color, and the polarities of the adjacent two sub-pixels 3031 are opposite.
  • the R, G, B sub-pixels are sequentially arranged in the direction of the data line 302.
  • the required data line is only 1/3, which saves 2/3 of the data line, although it will increase relatively.
  • the number of scan lines 301 is small, but since the flip chip COF on the scan line 301 side is much cheaper than the flip chip COF on the data line 302 side, and in other embodiments, the scan line 301 may even be directly disposed on the substrate, The flip chip COF is not required. Therefore, the sequential arrangement of the R, G, and B sub-pixels 3031 in the direction of the data line 302 can largely save the cost of the array substrate.
  • the scanning lines 301 forming the two pixel regions 303 are different, that is, the adjacent two pixel regions 303 arranged along the data line 302 do not share any of the scanning lines 301. That is, at least two scan lines 301 are arranged between adjacent two pixel regions 303 arranged along the data line 302.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • the scanning lines 301 in the present embodiment are arranged in the horizontal direction, and the data lines 302 are arranged in the vertical direction.
  • the sub-pixel 3031 is disposed in the pixel region 303 of the odd-numbered column, and the sub-pixels 3031 arranged in the parallel direction of the scan line 301 are disposed in the pixel region 303 of the even-numbered column, each of the The sub-pixels 3031 are respectively connected to the corresponding scan lines through corresponding FTFs 3032, wherein the TFTs
  • the drain of 3032 is electrically connected to the sub-pixel 3031, the gate is electrically connected to the scan line 301, and the source stage is electrically connected to the data line 302.
  • the scanning lines 301 connected to the adjacent two sub-pixels 3031 arranged in the direction parallel to the scanning line 301 are different.
  • two scan lines 301 are arranged between two pixel regions 303 arranged along the data line 302 in the present embodiment, and odd row sub-pixels 3031 and even rows distributed on both sides of the two scan lines 201 are arranged.
  • Sub-pixels 3032 are respectively connected to one closest to itself.
  • the data lines of the array substrate of the present embodiment are only 1 in comparison with the prior art of FIG. /6, which saves 5/6 of the data line, can greatly save the manufacturing cost of the array substrate.
  • the plurality of data lines and the scan lines of the array substrate of the present embodiment cross each other but do not intersect to form a pixel area, and further include a plurality of R and G arranged in a direction parallel to the data lines.
  • B sub-pixels relative to the prior art arranged along the scan line, the R, G, B sub-pixels are sequentially arranged in the data line direction, the required data line is only 1/3, saving 2 / 3 of the data line, The cost of the array substrate can be largely saved.
  • Each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT, and at least one of the sub-pixels is disposed in each of the pixel regions, and the scan lines forming the adjacent two of the pixel regions are different. That is, at least two scan lines are arranged between adjacent two pixel regions arranged along the data line.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • connecting the two sub-pixels adjacent to each other on both sides of the same data line to the same data line can save the number of data lines by half, thereby further saving the cost of the array substrate.
  • FIG. 4 is a schematic structural view of an embodiment of a liquid crystal display device of the present invention.
  • the liquid crystal display device of the present embodiment includes an array substrate 401, a color filter substrate 402, and a sandwich between the array substrate and the color filter substrate.
  • the array substrate includes a plurality of data lines and a plurality of scan lines, wherein the scan lines and the data lines cross each other but do not intersect and form a plurality of pixel regions.
  • the plurality of data lines are parallel to each other, and the plurality of scanning lines are parallel to each other, and the data lines and the scanning lines are perpendicular to each other, which is not limited herein.
  • the array substrate further includes a plurality of R, G, and B sub-pixels, and the R, G, and B sub-pixels are sequentially arranged in a direction parallel to the data line, and each of the sub-pixels is electrically connected to the thin film transistor TFT to Corresponding to the scan line and the data line; at least one of the sub-pixels is disposed in each of the pixel regions, and scan lines forming two adjacent pixel regions are different.
  • each of the pixel regions is disposed with two sub-pixels arranged in a direction parallel to the data lines, and each of the sub-pixels respectively passes a corresponding FTF and a corresponding scan line. Connected to the data line, data lines connected by two adjacent sub-pixels arranged in a direction parallel to the scan line are different. Specifically, please refer to FIG. 2 and related text descriptions, which are not limited thereto.
  • the plurality of data lines and the scan lines of the array substrate of the present embodiment cross each other but do not intersect to form a pixel area, and further include a plurality of R and G arranged in a direction parallel to the data lines.
  • B sub-pixels relative to the prior art arranged along the scan line, the R, G, B sub-pixels are sequentially arranged in the data line direction, the required data line is only 1/3, saving 2 / 3 of the data line, The cost of the array substrate can be largely saved.
  • Each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT, and at least one of the sub-pixels is disposed in each of the pixel regions, and the scan lines forming the adjacent two of the pixel regions are different. That is, at least two scan lines are arranged between adjacent two pixel regions arranged along the data line.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • the two sub-pixels arranged in the parallel direction of the data line disposed in each pixel region are respectively connected to the corresponding scan lines and data lines through the corresponding TFTs, and the adjacent two sub-pixels arranged in the parallel direction of the scan lines are connected.
  • the data lines are also different.
  • the voltages supplied by the adjacent data lines are different, and the dot inversion can be realized when the data line output column inverts the data. Not only can save a lot of power consumed by dot inversion, reduce the cost of the array substrate, but also achieve good display effect brought by the dot inversion method, and improve the quality of the screen display.
  • one of the sub-pixels is disposed in the pixel region of the odd column, and the sub-pixels arranged in the parallel direction of the scan line are disposed in the pixel region of the even column, and each Each of the sub-pixels is connected to the corresponding scan line by a corresponding FTF, and adjacent scan lines connected by two adjacent sub-pixels arranged in a direction parallel to the scan line are different; separated by the same data line Two of the sub-pixels adjacent to each other are connected to the same data line.
  • the plurality of data lines and the scan lines of the array substrate of the present embodiment cross each other but do not intersect to form a pixel area, and further include a plurality of R and G arranged in a direction parallel to the data lines.
  • B sub-pixels relative to the prior art arranged along the scan line, the R, G, B sub-pixels are sequentially arranged in the data line direction, the required data line is only 1/3, saving 2 / 3 of the data line, The cost of the array substrate can be largely saved.
  • Each of the sub-pixels is electrically connected to the corresponding scan line and the data line through a thin film transistor TFT, and at least one of the sub-pixels is disposed in each of the pixel regions, and the scan lines forming the adjacent two of the pixel regions are different. That is, at least two scan lines are arranged between adjacent two pixel regions arranged along the data line.
  • the arrangement space of the array substrate can be saved, the area of the non-transparent area can be reduced, and the aperture ratio can be increased.
  • connecting the two sub-pixels adjacent to each other on both sides of the same data line to the same data line can save the number of data lines by half, thereby further saving the cost of the array substrate.

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Abstract

一种阵列基板以及液晶显示装置，包括多条数据线（202）和多条扫描线（201），所述数据线（202）和扫描线（201）两两交叉但不相交以形成像素区域（203），还包括多个R、G、B子像素（2031），所述R、G、B子像素（2031）沿着与所述数据线（202）平行的方向依次排列，每个所述子像素（2031）通过一薄膜晶体管TFT（2032）电连接至对应的所述扫描线（201）与所述数据线（202）；每个所述像素区域（203）中至少设置一所述子像素（2031），形成相邻的两个所述像素区域（203）的扫描线（201）不同。能够减少数据线（202）的数量，减小制作成本；而且能够节省排布空间，进一步减小遮光面积，提高像素的开口率。

Description

阵列基板以及液晶显示装置
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种阵列基板以及液晶显示装置。
【背景技术】
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED) 等平板显示器已经逐步取代CRT 显示器，广泛的应用于液晶电视、手机、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等。显示面板是LCD、OLED 的重要组成部分。
不论是LCD 的显示面板，还是OLED 的显示面板，通常具有一薄膜晶体管(Thin Film Transistor，TFT) 阵列基板。此TFT 阵列基板上形成有多个呈阵列式排布的R、G、B 子像素、多条扫描线、及多条数据线。每一子像素分别通过对应的扫描线来接收扫描信号、通过对应的数据线来接收数据信号，以显示影像。
如图1所示，图1为现有技术的阵列基板的结构示意图。阵列基板包括多条相互平行并依次竖直排列的数据线，如D1、D2、D3、D4、D5 等，多条相互平行并依次排列的水平的扫描线，如G1、G2、G3、G4 等，及呈阵列式排布的子像素。位于同一行的每个子像素均通过一薄膜晶体管TFT 电性连接于位于该行子像素上方的扫描线，例如第一行的每个子像素通过一TFT 电性连接于扫描线G1，第二行的每个子像素通过一TFT 电性连接于扫描线G2，依次类推；位于同一列的每个子像素均通过一TFT 电性连接于位于该列子像素左侧的数据线，例如第一列的每个子像素通过一TFT 电性连接于数据线D1，第二列的每个子像素通过一TFT电性连接于数据线D2，依次类推。
然而上述常规连接方式需要占用阵列基板很多的排布空间，占用了遮光面积，降低了显示面板的开口率，且数据线和扫描线的利用率小，造成了资源的浪费，也增加了液晶显示装置的制作成本。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板以及液晶显示装置，不仅能够减少数据线的数量，减小制作成本；而且能够节省排布空间，进一步减小遮光面积，提高像素的开口率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，其中，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同；其中，相邻两个所述子像素的极性相反；沿所述扫描线水平方向排列的所述子像素的颜色相同。
其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。
其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
其中，相邻两个所述子像素的极性相反。
其中，沿所述扫描线水平方向排列的所述子像素的颜色相同。
其中，所述TFT的漏极电连接所述子像素，栅极电连接所述扫描线，源级电连接所述数据线。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种液晶显示装置，包括相对设置的阵列基板、彩膜基板以及夹置在所述阵列基板以及彩膜基板之间的液晶分子，所述阵列基板包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。
其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
其中，相邻两个所述子像素的极性相反。
其中，沿所述扫描线水平方向排列的所述子像素的颜色相同。
其中，所述TFT的漏极电连接所述子像素，栅极电连接所述扫描线，源级电连接所述数据线。
本发明的有益效果是：区别于现有技术的情况，本实施方式的阵列基板的多条述数据线和扫描线两两交叉但不相交以形成像素区域，还包括多个沿着与数据线平行的方向依次排列的R、G、B子像素，相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，能很大程度上节省阵列基板的成本。每个子像素通过一薄膜晶体管TFT电连接至对应的扫描线与数据线且，每个像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。即沿数据线排布的相邻两个像素区域之间排布有至少两根扫描线。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。
【附图说明】
图1是现有技术阵列基板一实施方式的结构示意图；
图2是本发明阵列基板一实施方式的结构示意图；
图3是本发明阵列基板另一实施方式的结构示意图；
[根据细则91更正 29.01.2016]　
图4是本发明液晶显示装置一实施方式的结构示意图。
【具体实施方式】
本实施方式的阵列基板包括多条数据线和多条扫描线，其中，扫描线和数据线两两交叉却不相交并形成多个像素区域。在优选的实施方式中，多条数据线相互之间互相平行，多条扫描线之间相互平行，数据线与扫描线相互垂直，在此不做限定。进一步地，阵列基板还包括多个R、G、B子像素，上述R、G、B子像素沿着与数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，且形成相邻的两个所述像素区域的扫描线不同。
具体地，参阅图2，图2是本发明阵列基板一实施方式的结构示意图。本实施方式的扫描线201和数据线202两两交叉却不相交并形成多个像素区域203，多个R、G、B子像素2031沿数据线202方向依次排列，沿扫描线201水平方向排列的所述子像素2031的颜色相同，相邻两个子像素2031的极性相反。相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线202方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，虽然会相对增加扫描线201的数量，但是由于扫描线201侧的覆晶薄膜COF相对于数据线202侧的覆晶薄膜COF便宜的多，且在其他实施方式中，扫描线201甚至可以直接设置在基板上，无需覆晶薄膜COF，因此，R、G、B子像素2031沿数据线202方向依次排列能很大程度上节省阵列基板的成本。
如图2所示，形成两个像素区域203的扫描线201不同，即沿数据线202排列的相邻两个像素区域203不共用任意扫描线201。即沿数据线202排布的相邻两个像素区域203之间排布有至少两根扫描线201。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。
进一步参阅图2，每个像素区域203设置有两个沿数据线平行方向排列的子像素2031，每个子像素2031分别通过对应的TFT2032与对应的扫描线201和数据线202连接。其中，所述TFT 2032的漏极电连接所述子像素2031，栅极电连接所述扫描线201，源级电连接所述数据线202。在优选的实施方式中，每个子像素2031分别与其最相邻的扫描线201和数据线202连接。例如，本实施方式的两个相邻的像素区域203之间相互排布有两根扫描线201，分布在该两根扫描线201两侧的子像素2031分别与靠近自身的一根连接。另外，沿扫描线201平行平行排列的相邻的所述子像素2031所连接的数据线202也不同。例如，当数据线沿水平方向排布，扫描线沿垂直方向排布，如图2中所示时，沿数据线202方向平行排列的两个子像素2031中上侧的一个子像素2031与像素区域203右侧的数据线202连接，下侧的子像素2031与像素区域203左侧的数据线202连接，即奇数行的子像素2031与偶数行的子像素2031错位排列，在阵列排布的子像素2031中中，相邻行的同一次序的子像素2031分别连接于两个相邻的数据线202，相邻的数据线供应的电压不同，在数据线202输出列反转数据时即可实现点反转。不仅能够节省点反转所消耗的大量功率，降低阵列基板的成本，而且还能够实现点反转方式带来的良好的显示效果，提高画面显示的品质。
需要说明的是，扫描线201的水平排布和数据线202的垂直排布为相对的排布方向，当阵列基板的方向发生改变，对应地，扫描线201与数据线202的位置也会发生相对应的变化。因此，当阵列基板的位置发生90度旋转，或用户观看的角度改变90度时，水平方向和垂直方向也相对的发生交替，此时的数据线的列反转也对应的变成行反转，其实质并未改变，效果也是相同的，再此不做限定。
区别于现有技术，本实施方式的阵列基板的多条述数据线和扫描线两两交叉但不相交以形成像素区域，还包括多个沿着与数据线平行的方向依次排列的R、G、B子像素，相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，能很大程度上节省阵列基板的成本。每个子像素通过一薄膜晶体管TFT电连接至对应的扫描线与数据线且，每个像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。即沿数据线排布的相邻两个像素区域之间排布有至少两根扫描线。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。且，设置在每个像素区域的两个沿数据线平行方向排列的子像素分别通过对应的TFT与对应的扫描线和数据线连接，沿扫描线平行的方向排列的相邻两个子像素连接的数据线也不相同，相邻的数据线供应的电压不同，在数据线输出列反转数据时即可实现点反转。不仅能够节省点反转所消耗的大量功率，降低阵列基板的成本，而且还能够实现点反转方式带来的良好的显示效果，提高画面显示的品质。
参阅图3，图3是本发明阵列基板另一实施方式的结构示意图。本实施方式的阵列基板的扫描线301和数据线302两两交叉却不相交并形成多个像素区域303，多个R、G、B子像素3031沿数据线302方向依次排列，沿扫描线301水平方向排列的所述子像素3031的颜色相同，相邻两个子像素3031的极性相反。相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线302方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，虽然会相对增加扫描线301的数量，但是由于扫描线301侧的覆晶薄膜COF相对于数据线302侧的覆晶薄膜COF便宜的多，且在其他实施方式中，扫描线301甚至可以直接设置在基板上，无需覆晶薄膜COF，因此，R、G、B子像素3031沿数据线302方向依次排列能很大程度上节省阵列基板的成本。
如图3所示，形成两个像素区域303的扫描线301不同，即沿数据线302排列的相邻两个像素区域303不共用任意扫描线301。即沿数据线302排布的相邻两个像素区域303之间排布有至少两根扫描线301。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。
进一步地参阅图3，本实施方式中的扫描线301沿水平方向排布，数据线302沿垂直方向排布。该阵列基板位于奇数列的所述像素区域303中设置一个子像素3031，位于偶数列的所述像素区域303中设置两个沿扫描线301平行方向排列的所述子像素3031，每个所述子像素3031分别通过对应的FTF3032与对应的所述扫描线连接，其中，所述TFT 3032的漏极电连接所述子像素3031，栅极电连接所述扫描线301，源级电连接所述数据线302。且沿所述扫描线301平行的方向排列的相邻两个所述子像素3031所连接的扫描线301不同。例如，本实施方式中的两个沿数据线302排列的两个像素区域303之间排布着两根扫描线301，分布在该两根扫描线201两侧的奇数行子像素3031和偶数行子像素3032分别连接至最靠近自身的一根。
分隔在同一数据线302两侧相邻的两个所述子像素3031连接至所述同一数据线302。相交于现有技术中每一列子像素分别接不同数据线的连接方式，又能够节省一半的数据线，即相对于图1的现有技术，本实施方式的阵列基板所需要的数据线只有1/6，即节省了5/6的数据线，能够很大程度了节省了阵列基板的制作成本。
区别于现有技术，本实施方式的阵列基板的多条述数据线和扫描线两两交叉但不相交以形成像素区域，还包括多个沿着与数据线平行的方向依次排列的R、G、B子像素，相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，能很大程度上节省阵列基板的成本。每个子像素通过一薄膜晶体管TFT电连接至对应的扫描线与数据线且，每个像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。即沿数据线排布的相邻两个像素区域之间排布有至少两根扫描线。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。且分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线，能够将数据线的数量再节省一半，进一步节省阵列基板的成本。
参阅图4，图4是本发明液晶显示装置一实施方式的结构示意图，本实施方式的液晶显示装置包括阵列基板401、彩膜基板402以及夹置在所述阵列基板以及彩膜基板之间的液晶分子403。阵列基板包括多条数据线和多条扫描线，其中，扫描线和数据线两两交叉却不相交并形成多个像素区域。在优选的实施方式中，多条数据线相互之间互相平行，多条扫描线之间相互平行，数据线与扫描线相互垂直，在此不做限定。进一步地，阵列基板还包括多个R、G、B子像素，上述R、G、B子像素沿着与数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，且形成相邻的两个所述像素区域的扫描线不同。
在其中的一个实施方式中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。具体地，请参阅图2及其相关文字描述，再此不再限定。
区别于现有技术，本实施方式的阵列基板的多条述数据线和扫描线两两交叉但不相交以形成像素区域，还包括多个沿着与数据线平行的方向依次排列的R、G、B子像素，相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，能很大程度上节省阵列基板的成本。每个子像素通过一薄膜晶体管TFT电连接至对应的扫描线与数据线且，每个像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。即沿数据线排布的相邻两个像素区域之间排布有至少两根扫描线。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。且，设置在每个像素区域的两个沿数据线平行方向排列的子像素分别通过对应的TFT与对应的扫描线和数据线连接，沿扫描线平行的方向排列的相邻两个子像素连接的数据线也不相同，相邻的数据线供应的电压不同，在数据线输出列反转数据时即可实现点反转。不仅能够节省点反转所消耗的大量功率，降低阵列基板的成本，而且还能够实现点反转方式带来的良好的显示效果，提高画面显示的品质
在另一个实施方式中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。具体请参阅图3及其相关文字描述，再此不再赘述。
区别于现有技术，本实施方式的阵列基板的多条述数据线和扫描线两两交叉但不相交以形成像素区域，还包括多个沿着与数据线平行的方向依次排列的R、G、B子像素，相对于沿扫描线依次排列的现有技术，R、G、B子像素沿数据线方向依次排列所需要的数据线仅仅为1/3，节省了2/3的数据线，能很大程度上节省阵列基板的成本。每个子像素通过一薄膜晶体管TFT电连接至对应的扫描线与数据线且，每个像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。即沿数据线排布的相邻两个像素区域之间排布有至少两根扫描线。能够节省阵列基板的排布空间，减少非透光区域的面积，增加开口率。且分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线，能够将数据线的数量再节省一半，进一步节省阵列基板的成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种阵列基板，包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，其中，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同；其中，相邻两个所述子像素的极性相反；沿所述扫描线水平方向排列的所述子像素的颜色相同。
  2. 根据权利要求1所述的阵列基板，其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
  3. 根据权利要求2所述的阵列基板，其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
  4. 根据权利要求1所述的阵列基板，其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
  5. 一种阵列基板，包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，其中，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。
  6. 根据权利要求5所述的阵列基板，其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
  7. 根据权利要求6所述的阵列基板，其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
  8. 根据权利要求5所述的阵列基板，其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
  9. 根据权利要求5任一项所述的阵列基板，其中，相邻两个所述子像素的极性相反。
  10. 根据权利要求5任一项所述的阵列基板，其中，沿所述扫描线水平方向排列的所述子像素的颜色相同。
  11. 根据权利要求5任一项所述的阵列基板，其中，所述TFT的漏极电连接所述子像素，栅极电连接所述扫描线，源级电连接所述数据线。
  12. 一种液晶显示装置，包括相对设置的阵列基板、彩膜基板以及夹置在所述阵列基板以及彩膜基板之间的液晶分子，其中，所述阵列基板包括多条数据线和多条扫描线，所述数据线和扫描线两两交叉但不相交以形成像素区域，所述阵列基板还包括多个R、G、B子像素，所述R、G、B子像素沿着与所述数据线平行的方向依次排列，每个所述子像素通过一薄膜晶体管TFT电连接至对应的所述扫描线与所述数据线；每个所述像素区域中至少设置一所述子像素，形成相邻的两个所述像素区域的扫描线不同。
  13. 根据权利要求12所述的液晶显示装置，其中，每个所述像素区域中设置两个沿所述数据线平行的方向排列所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线和所述数据线连接，沿所述扫描线平行的方向排列的相邻两个所述子像素连接的数据线不同。
  14. 根据权利要求13所述的液晶显示装置，其中，所述数据线用于输出列反转驱动数据或行反转驱动数据。
  15. 根据权利要求12所述的液晶显示装置，其中，位于奇数列的所述像素区域中设置一个所述子像素，位于偶数列的所述像素区域中设置两个沿所述扫描线平行方向排列的所述子像素，每个所述子像素分别通过对应的FTF与对应的所述扫描线连接，且沿所述扫描线平行的方向排列的相邻两个所述子像素所连接的扫描线不同；分隔在同一数据线两侧相邻的两个所述子像素连接至所述同一数据线。
  16. 根据权利要求12所述的液晶显示装置，其中，相邻两个所述子像素的极性相反。
  17. 根据权利要求12所述的液晶显示装置，其中，沿所述扫描线水平方向排列的所述子像素的颜色相同。
  18. 根据权利要求12所述的液晶显示装置，其中，所述TFT的漏极电连接所述子像素，栅极电连接所述扫描线，源级电连接所述数据线。
PCT/CN2015/097997 2015-12-02 2015-12-21 阵列基板以及液晶显示装置 Ceased WO2017092082A1 (zh)

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