WO2016074181A1 - 阵列基板、液晶面板以及液晶显示器 - Google Patents

阵列基板、液晶面板以及液晶显示器 Download PDF

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Publication number
WO2016074181A1
WO2016074181A1 PCT/CN2014/090950 CN2014090950W WO2016074181A1 WO 2016074181 A1 WO2016074181 A1 WO 2016074181A1 CN 2014090950 W CN2014090950 W CN 2014090950W WO 2016074181 A1 WO2016074181 A1 WO 2016074181A1
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sub
row
pixels
pixel
group
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PCT/CN2014/090950
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English (en)
French (fr)
Inventor
李倩倩
许哲豪
陈彩琴
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深圳市华星光电技术有限公司
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Priority to KR1020177015801A priority Critical patent/KR101913527B1/ko
Priority to JP2017525020A priority patent/JP6369925B2/ja
Priority to DE112014007153.6T priority patent/DE112014007153B4/de
Priority to GB1707166.3A priority patent/GB2546693B/en
Priority to RU2017116639A priority patent/RU2673705C2/ru
Priority to US14/420,372 priority patent/US9341905B1/en
Publication of WO2016074181A1 publication Critical patent/WO2016074181A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a liquid crystal panel, and a liquid crystal display.
  • the liquid crystal panel includes at least an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer between the array substrate and the filter substrate, wherein the array substrate is provided with a pixel array and mutually intersecting data lines and A scan line, the data line provides a data signal to the pixel array, and the scan line provides a scan signal to the pixel unit.
  • the array substrate is provided with a pixel array and mutually intersecting data lines and A scan line, the data line provides a data signal to the pixel array, and the scan line provides a scan signal to the pixel unit.
  • pixels of the same column are connected to the same data line, and the data line is responsible for providing data signals to all pixels of the column; pixels of the same row are connected to the same scan line, and the scan line is responsible for A scan signal is provided to all pixels of the row.
  • the array substrate there are many ways to arrange the data lines and scan lines, one of which is to reduce the number of data lines to half of the original, that is, the shared data line (Data
  • FIG. 1 A schematic diagram of a partial structure of a conventional DLS array substrate as shown in FIG.
  • the array substrate is provided with pixel arrays P11, P12, P13, P22, P23 and mutually intersecting data lines D1 to D5 and scan lines G1 G G6, and the left and right adjacent sub-pixels of the pixel array share one data line (as shown in the figure).
  • P12 and P13 share the data line D2
  • P22 and P23 share the data line D2) such that the number of data lines is halved with respect to the number of data lines of the conventional liquid crystal drive pixel array.
  • Adjacent sub-pixels of the same row are connected to different scan lines (P12 and P13 are connected to scan lines G1 and G2, respectively), and sub-pixels of one sub-pixel are connected to the same scan line in the same row (P11 and P13 in the figure). Both are connected to the scanning line G2), so that the upper and lower adjacent sub-pixels are connected to different scanning lines (P12 and P22 are connected to the scanning lines G2 and G3, respectively). This doubles the number of scan lines relative to the number of scan lines of a conventional drive pixel array.
  • the liquid crystal panel usually adopts a dot inversion driving method, that is, the signals of the adjacent two data lines have opposite polarities, and the signals of the same data line have opposite polarities when adjacent rows. Due to the number The data line has a certain impedance, and the data signal will cause delay distortion of the waveform during transmission, which results in a difference in the charging rate of the sub-pixels in the adjacent columns of the data line.
  • the driving signal waveform diagram D (odd) is the signal waveform of the odd data line
  • D (even) is the signal waveform of the even data line
  • the signal polarities of D (odd) and D (even) are opposite.
  • the broken line is a theoretical signal waveform diagram
  • the implementation is partially an actual waveform diagram formed due to delay distortion.
  • the first charged sub-pixels P12 and P22 are insufficiently charged, and the brightness is low, and the post-charged sub-pixels P13 and P23 are better charged and the brightness is higher. From the whole column, there will be obvious bright and dark lines. Similarly, a plurality of vertical bright lines appearing in the entire liquid crystal panel will affect the display quality.
  • the present invention provides an array substrate, which is arranged in a vertical direction of a liquid crystal panel including the array substrate by an arrangement arrangement of sub-pixels and data lines and scan lines in the array substrate.
  • the bright and dark lines are improved.
  • An array substrate comprising:
  • each column of data lines forming a column group, each column group comprising two columns of sub-pixels; wherein, the sub-pixels of the odd column group are connected to the data lines closer to the sub-pixels on both sides of the column group a sub-pixel of an odd-numbered row of even-numbered columns connected to a data line closer to the sub-pixel on both sides of the column group; a sub-pixel of an even-numbered row of even-numbered columns connected to both sides of the column group a data line that is farther away from the pixel;
  • a plurality of scan lines, above and below each row of sub-pixels, are provided with scan lines for driving only the row of sub-pixels; dividing the sub-pixel array into a plurality of row groups, each row group comprising one or two rows a pixel; wherein, in the nth and n+6th row groups, a sub-pixel of each row of even-column groups is connected to a scan line above the row of sub-pixels, and an odd-numbered column of each of the nth and n+6th row groups a group of sub-pixels connected to the scan line below the row of sub-pixels; in the n+1th and n+5th row groups, the i-th and i-th-th sub-pixels of each row are connected above the row of sub-pixels Scan line, the nth and n+5th line groups, the jth of each line And the j+3th sub-pixel is connected to the scan line below the row of sub-pixels; in the n+
  • n 1, 5, 9, ..., n-4, n;
  • i 2, 6, 10, ..., i-4, i;
  • j 1, 5, 9, ..., j-4, j.
  • Each sub-pixel is connected to a corresponding data line and a corresponding scan line through a switching element.
  • the switching element is a thin film transistor, a gate of the thin film transistor is electrically connected to the corresponding scan line, a source thereof is electrically connected to the corresponding data line, a drain thereof and the corresponding sub-pixel Electrical connection.
  • the present invention also provides a liquid crystal panel including a display unit, the display unit includes an array substrate and a filter substrate disposed opposite to each other, and a liquid crystal layer between the array substrate and the filter substrate, wherein the array substrate comprises:
  • each column of data lines forming a column group, each column group comprising two columns of sub-pixels; wherein, the sub-pixels of the odd column group are connected to the data lines closer to the sub-pixels on both sides of the column group a sub-pixel of an odd-numbered row of even-numbered columns connected to a data line closer to the sub-pixel on both sides of the column group; a sub-pixel of an even-numbered row of even-numbered columns connected to both sides of the column group a data line that is farther away from the pixel;
  • a plurality of scan lines, above and below each row of sub-pixels, are provided with scan lines for driving only the row of sub-pixels; dividing the sub-pixel array into a plurality of row groups, each row group comprising one or two rows a pixel; wherein, in the nth and n+6th row groups, a sub-pixel of each row of even-column groups is connected to a scan line above the row of sub-pixels, and an odd-numbered column of each of the nth and n+6th row groups a group of sub-pixels connected to the scan line below the row of sub-pixels; in the n+1th and n+5th row groups, the i-th and i-th-th sub-pixels of each row are connected above the row of sub-pixels In the scan line, in the n+1th and n+5th row groups, the jth and j+3th subpixels of each row are connected to the scan line below the row of subpixels; the n+
  • n 1, 5, 9, ..., n-4, n;
  • i 2, 6, 10, ..., i-4, i;
  • j 1, 5, 9, ..., j-4, j.
  • Each sub-pixel is connected to a corresponding data line and a corresponding scan line through a switching element.
  • the switching element is a thin film transistor, a gate of the thin film transistor is electrically connected to the corresponding scan line, a source thereof is electrically connected to the corresponding data line, a drain thereof and the corresponding sub-pixel Electrical connection.
  • the liquid crystal panel further includes a gate driver and a source driver, the gate driver provides a scan signal to the sub-pixel array through a scan line, and the source driver supplies a data signal to the sub-pixel array through the data line.
  • the sub-pixel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • the liquid crystal panel is driven by a point flip.
  • a liquid crystal display including a liquid crystal panel and a backlight module.
  • the liquid crystal panel is disposed opposite to the backlight module, and the backlight module provides a display light source to the liquid crystal panel, so that The liquid crystal panel displays an image, wherein the liquid crystal panel is a liquid crystal panel as described above.
  • the array substrate provided in the embodiment of the present invention by the arrangement design of the connection manner of the sub-pixels and the data lines and the scan lines in the array substrate, each column of sub-pixels is driven when using the dot flip mode.
  • FIG. 1 is a partial schematic structural view of a conventional shared data line array substrate.
  • Fig. 2 is a signal waveform diagram of the dot flip driving method.
  • FIG. 3 is a schematic partial structural diagram of a shared data line array substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic view showing the structure of a sub-pixel and a data line and a scan line connected through a thin film transistor in the embodiment of the invention.
  • FIG. 5 is a schematic diagram of the array substrate according to Embodiment 1 of the present invention after being charged.
  • FIG. 6 is a schematic partial structural diagram of a shared data line array substrate according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic diagram of the array substrate according to Embodiment 2 of the present invention after being charged.
  • FIG. 8 is a schematic structural diagram of a liquid crystal display according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic structural diagram of a liquid crystal panel according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural diagram of a display unit according to Embodiment 3 of the present invention.
  • the object of the present invention is to improve the defect that a liquid crystal panel of a Data Line Share (DLS) type has a bright dark line in a vertical direction, and provides an array substrate including the sub-substrate.
  • the pixel array and the plurality of data lines and scan lines crossing each other are arranged by the connection manner of the sub-pixels and the data lines and the scan lines in the array substrate, and are driven by the dot flip mode when each column sub-pixel is spaced apart from each other. There are sub-pixels that are better charged and less charged.
  • connection mode of the sub-pixel and the data line among the plurality of data lines, one column group is formed between each two data lines, and each column group includes two columns of sub-pixels.
  • each sub-pixel is connected to a data line closer to the sub-pixel on both sides of the column group; and for a sub-pixel of an odd-numbered column group, each sub-pixel is connected to the sub-pixel A data line closer to the sub-pixel on both sides of the column group; for a sub-pixel of an even-numbered column group, each sub-pixel is connected to a data line farther from the sub-pixel on both sides of the column group.
  • closer and farther are relative.
  • a scan line for driving only the row of sub-pixels is disposed above and below each row of sub-pixels; and then the sub-pixel array is divided into multiple Row groups, each row group consisting of one or two rows of sub-pixels.
  • each row of even column groups of subpixels each subpixel is connected to the scan line above the row of subpixels, for each of the nth and n+6th row groups A sub-pixel of an odd column group, each sub-pixel being connected to a scan line below the row of sub-pixels.
  • each sub-pixel is connected to the scan line above the row of sub-pixels, for the n+1th and nthth In the +5 line group, the jth and j+3th sub-pixels of each line, each sub-pixel is connected to the scan line below the row of sub-pixels.
  • each row of odd column groups of subpixels each subpixel is connected to the scan line above the row of subpixels
  • each sub-pixel is connected to the scan line above the row of subpixels
  • a sub-pixel of each row of even-column groups each sub-pixel being connected to a scan line below the row of sub-pixels.
  • each sub-pixel is connected to the scan line above the row of sub-pixels, for the i-th and i-th of each row of the n+3th row group +1 sub-pixels, each sub-pixel connected to a scan line below the row of sub-pixels.
  • connection manner of the sub-pixel and the scan line when each row group includes two rows of sub-pixels, one row of sub-pixels in one row group is connected with the data line and the scan line and another row of sub-pixels and data lines and sweep
  • the upper lines are connected in the same way, that is, two rows of sub-pixels are used as one repeating unit.
  • FIG. 3 is a partial schematic structural view of the array substrate provided by the embodiment.
  • P11 is the first sub-pixel at the upper left
  • P78 is the last sub-pixel at the lower right.
  • each column group 11, 12, 13, 14 is formed between each two data lines, and each column group includes two columns of sub-pixels (as shown in the figure, the column group 11 includes the first and the 2 columns of subpixels).
  • each sub-pixel is connected to a data line closer to the sub-pixel on both sides of the column group (such as the sub-pixel of the column group 11 in the figure, the sub-pixel P1y is connected to a data line D1, the sub-pixel P2y is connected to the data line D2); for the sub-pixels of the odd-numbered rows of the even-numbered column groups 12, 14, each sub-pixel is connected to a data line closer to the sub-pixel on both sides of the column group ( As shown in the column 12 in the figure 1 row of sub-pixels P13, P14, sub-pixel P13 connected to data line D2, sub-pixel P14 connected to data line D3); for even-numbered sub-pixels of even-numbered column groups 12, 14, each sub-pixel is connected to the column Data lines on the two sides of the group that are farther from the sub-pixel (such as the sub-pixels P23, P24 of the second row in the column group 12, the sub-pixel P23 are connected to the
  • each line group includes one row of sub-pixels, that is, the line group 21 includes the first row of sub-pixels, and the row group 22 Includes the second row of subpixels...
  • the sub-pixels are connected to the scan lines as follows:
  • each sub-pixel is connected to the scan line above the row sub-pixel (such as the sub-pixel P13, P14, sub-pixel P13 of the row group 21 even column group 12 in the row group 21).
  • each sub-pixel is connected to a scan line below the row of sub-pixels (such as the sub-pixels P11, P12 of the odd-numbered column group 11 of the row group 21, the sub-pixels P11, P12 are connected to the scan line G21, the odd-numbered column of the row group 27
  • the sub-pixels P71, P72, and the sub-pixels P71, P72 of the group 11 are all connected to the scanning line G27).
  • each sub-pixel is connected to a scan line above the row of sub-pixels (as shown in the row group 22, the second and third sub-pixels P22, P23, The sub-pixels P22, P23 are connected to the scanning line G12, the second and third sub-pixels P62, P63 of the line group 26, the sub-pixels P62, P63 are connected to the scanning line G16), and the jth and the first for each line of the line groups 22 and 26 j + 3 sub-pixels, each sub-pixel is connected to a scan line below the row of sub-pixels (as shown in the row group 22, the first and fourth sub-pixels P21, P24, the sub-pixels P21, P24 are connected to the scan line G22, the row group 26 first and fourth sub-pixels P61, P64, and sub-pixels P61, P64 are connected to the scanning line G26).
  • i 2, 6; j
  • each sub-pixel is connected to the scan line above the row of sub-pixels (such as the sub-pixels P31, P32, sub-pixels of the row group 23 odd-numbered column group 11 in the row group 23 and 25)
  • the pixels P31, P32 are each connected to the scanning line G13
  • the sub-pixels P51, P52 are all connected to the scanning line G15
  • the even-numbered column group 12 for each of the row groups 23 and 25 , 14 sub-pixels, each sub-pixel is connected to the scan line below the row of sub-pixels (as shown in the row group 23 even
  • the sub-pixels P33, P34 of the column group 12, the sub-pixels P33, P34 are all connected to the scanning line G23, the sub-pixels P53, P54 of the even-group 12 of the row group 25, and the sub-pixels P
  • each sub-pixel is connected to a scan line above the row of sub-pixels (as shown in the row group 24, the first and fourth sub-pixels P41, P44, sub-pixels) P41 and P44 are connected to the scan line G14).
  • each sub-pixel is connected to the scan line below the row of sub-pixels (as shown in the second group of the row group 24).
  • the third sub-pixels P42, P43, and the sub-pixels P42, P43 are connected to the scanning line G24).
  • Each sub-pixel Pxy is connected to a corresponding data line and a corresponding scan line through a switching element 10.
  • the sub-pixel P13 is taken as an example.
  • the switching element 10 in this embodiment is a thin film transistor (TFT), and the gate 10a of the thin film transistor is electrically connected to the corresponding scan line G11.
  • the source 10b is electrically connected to the corresponding data line D2, and the drain 10c thereof is electrically connected to the sub-pixel P13.
  • the sub-pixels P12, P13, P22, P23, P32, P33, P42, P43, P52, P53, P62, P63, P72, P73 on both sides of the data line D2 are charged.
  • the sub-pixels P12, P13, P22, P32, P33, P42, P52, P53, P62, P72, P73 are charged by data line D2.
  • the sub-pixels P23, P43, and P63 are charged by the data line D3.
  • P12, P42 and P72 are sub-pixels with better charging
  • P22, P32, P52 and P62 are sub-pixels with poor charging
  • P33, P43 and P53 is a sub-pixel with better charging
  • P13, P23, P63 and P73 are sub-pixels with poor charging.
  • FIG. 5 is a diagram showing a distribution diagram of sub-pixels with better charging and poor charging in a frame of the above-structured array substrate.
  • the white portion indicates a sub-pixel with better charging
  • the shaded portion indicates a sub-pixel with poor charging. It can be seen that in the sub-pixels of the same column, there are sub-pixels with better charging and poor charging, and in the sub-pixels of the same row, there are also better charging and poor charging. Subpixel. Therefore, in the liquid crystal panel including the array substrate, the brightness of each portion as a whole is balanced, and the defect of the bright dark line in the vertical direction can be improved.
  • the array substrate provided in this embodiment can be regarded as obtained by repeating the partial structure shown in FIG. 3 multiple times in the lateral direction and the longitudinal direction.
  • FIG. 6 is a partial schematic structural view of the array substrate provided by the embodiment. Different from Embodiment 1 In this embodiment, in the direction in which the scan lines are arranged, the row groups 21a, 22a, 23a, 24a, 25a, 26a, 27a of the sub-pixel array are divided into two rows of sub-pixels, such as In FIG.
  • the row group 21a includes the first row and the second row of sub-pixels
  • the row group 22a includes the third row and the fourth row of the sub-pixel row group 23a including the fifth row and the sixth row of sub-pixels
  • the row group 24a includes the 7 rows and 8 rows of sub-pixels
  • row group 25a includes 9th row and 10th row sub-pixels
  • row group 26a includes 11th row and 12th row sub-pixels
  • row group 27a includes 13th row and 14th row of sub-pixels .
  • a row of sub-pixels in one row group is connected to the data line and the scanning line in the same manner as the other row of sub-pixels and the data line and the scanning line, that is, two rows of sub-pixels are used as one repeating unit.
  • the two sub-pixels adjacent to each other for example, P11 and P21
  • the connection manner with the data line and the scan line is the same as that of the line group 21 in the first embodiment, and details are not described herein again.
  • the row group 22a corresponds to the row group 21 in the embodiment 1
  • the row group 23a corresponds to the row group 23 in the embodiment 1
  • the row group 24a corresponds to the row group 24 in the embodiment 1
  • the row group 25a corresponds to the first embodiment.
  • the row group 25, the row group 26a corresponds to the row group 26 in the embodiment 1
  • the row group 27a corresponds to the row group 27 in the embodiment 1.
  • FIG. 7 is a diagram showing a distribution diagram of sub-pixels with better charging and poor charging in a frame of the above-structured array substrate. Among them, the white portion indicates a sub-pixel with better charging, and the shaded portion indicates a sub-pixel with poor charging.
  • the array substrate provided in this embodiment can be regarded as obtained by repeating the partial structure shown in FIG. 6 a plurality of times in the lateral direction and the longitudinal direction.
  • the embodiment provides a liquid crystal panel and a liquid crystal display including the same.
  • the liquid crystal display includes a liquid crystal panel 100 and a backlight module 200.
  • the liquid crystal panel 100 is disposed opposite to the backlight module 200.
  • the backlight module 200 provides a display light source to the liquid crystal panel 100 to display the image on the liquid crystal panel 100.
  • the liquid crystal panel 100 includes a display unit 1, a gate driver 2, and a source driver 3 provided with a sub-pixel array.
  • the gate driver 2 supplies a scan signal Gate to the sub-pixel array through a scan line
  • the source driver 3 supplies a data signal Data to the sub-pixel array through the data line.
  • the display unit 1 includes a liquid crystal layer 1c including an array substrate 1a and a color filter substrate 1b disposed between the array substrate 1a and the filter substrate 1b.
  • the array substrate 1a adopts an embodiment as 1 or the array substrate provided in Embodiment 2, wherein the sub-pixel Pxy includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • each column of sub-pixels is mutually There are sub-pixels with better charging and poor charging at intervals (here, charging is better and charging is relatively inferior), so that the brightness of each part in the liquid crystal panel including the array substrate is balanced, and the improvement is improved. There is a defect of a bright dark line in the vertical direction.

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Abstract

一种阵列基板，包含该阵列基板的液晶面板以及相应的液晶显示器，该阵列基板包括子像素阵列、多条数据线(D1-D5)和多条扫描线(G11-G17,G21-G27)；沿数据线(D1-D5)排列的方向将子像素阵列划分为多个列组(11-14)，沿扫描线(G11-G17,G21-G27)排列的方向将子像素阵列划分为多个行组(21-27)，通过对阵列基板中子像素与数据线(D1-D5)和扫描线(G11-G17,G21-G27)的连接方式的排布设计，在使用点翻转方式驱动时，每一列子像素中相互间隔存在充电较好和充电较差的子像素，使得包含该阵列基板的液晶面板中，整体上各部分亮度均衡，改善了在竖直方向上存在亮暗线的缺陷。

Description

阵列基板、液晶面板以及液晶显示器 技术领域
本发明涉及液晶显示技术领域,尤其涉及一种阵列基板、液晶面板以及液晶显示器。
背景技术
液晶显示器(Liquid Crystal Display，LCD)，为平面超薄的显示设备，液晶面板是液晶显示器的重要组成部分。液晶面板至少包括相对设置的阵列基板(array substrate)和滤光基板(color filter substrate)以及位于阵列基板和滤光基板之间的液晶层，阵列基板中设置有像素阵列以及相互交叉的数据线和扫描线，数据线向像素阵列提供数据信号，扫描线向像素单元提供扫描信号。传统的阵列基板中，同一列的像素连接到同一条数据线中，由该条数据线负责向该列的所有像素提供数据信号；同一行像素连接到同一扫描线中，由该条扫描线负责向该行的所有像素提供扫描信号。在阵列基板中，针对数据线和扫描线的排布设计还有很多种方式，其中有一种是能够将数据线的数量减少为原来的一半的排布方式，即共享数据线(Data Line Share，DLS)方式。
如图1所示的现有的DLS阵列基板的局部结构示意图。该阵列基板中设置有像素阵列P11、P12、P13、P22、P23以及相互交叉的数据线D1～D5和扫描线G1～G6，像素阵列的左右相邻的子像素共用一条数据线(如图中P12和P13共用数据线D2，P22和P23共用数据线D2)，使得数据线的数目相对于传统液晶驱动像素阵列的数据线数目减半。同一行的相邻子像素连接不同的扫描线(如图中P12和P13分别连接到扫描线G1和G2)，同一行相隔一个子像素的子像素连接相同的扫描线(如图中P11和P13都连接到扫描线G2)，从而上下相邻的子像素连接不同的扫描线(如图中P12和P22分别连接到扫描线G2和G3)。这样使得扫描线的数目相对于传统驱动像素阵列的扫描线数目加倍。
由于扫描线数目的加倍使得分配到扫描线上的扫描时间减少，从而子像素的充电时间减少。目前液晶面板通常采用点翻转(Dot inversion)驱动方式，即，相邻两数据线的信号极性相反，同一数据线相邻行时的信号极性相反。由于数 据线具有一定的阻抗，数据信号在传输过程中会造成波形的延迟失真，这样导致在数据线相邻列的子像素充电率差异。如图2所示的驱动信号波形图，D(odd)为奇数数据线的信号波形，D(even)为偶数数据线的信号波形，D(odd)和D(even)的信号极性是相反的，在该信号波形图中，虚线为理论上的信号波形图，实现部分为由于延迟失真而形成的实际波形图。以D(even)在D2时为例，并结合附图1，G1～G4依次开启时，D2依次对子像素P12、P13、P22、P23充电，D2在一个信号极性周期内，分别对两个子像素P12、P13和P22、P23充电。在一个信号极性周期内，由于信号失真，先充电的子像素P12、P22存在充电不足，亮度较低，后充电的子像素P13、P23充电较好，亮度较高。从整列上看，就会产生明显的亮暗线，同理，在整个液晶面板内就会产生相互间隔的多条竖直方向亮暗线，影响了显示品质。
基于上述情况，亟需一种改善液晶面板亮暗线显示缺陷的方案。
发明内容
鉴于现有技术存在的不足，本发明提供了一种阵列基板，通过对阵列基板中子像素与数据线和扫描线的连接方式的排布设计，使得包含该阵列基板的液晶面板中竖直方向亮暗线得到改善。
为了实现上述目的，本发明采用了如下的技术方案：
一种阵列基板，其中，包括：
子像素阵列；
多条数据线，每两条数据线之间形成一列组，每一列组包括两列子像素；其中，奇数列组的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的奇数行的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的偶数行的子像素，连接到该列组两侧的与该子像素较远的数据线；
多条扫描线，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素；其中，第n和第n+6行组中，每一行偶数列组的子像素，连接到该行子像素上方的扫描线，第n和第n+6行组中，每一行奇数列组的子像素，连接到该行子像素下方的扫描线；第n+1和第n+5行组中，每一行的第i和第i+1个子像素，连接到该行子像素上方的扫描线，第n+1和第n+5行组中，每一行的第j 和第j+3个子像素，连接到该行子像素下方的扫描线；第n+2和第n+4行组中，每一行奇数列组的子像素，连接到该行子像素上方的扫描线，第n+2和第n+4行组中，每一行偶数列组的子像素，连接到该行子像素下方的扫描线；第n+3行组每一行的第j和第j+3个子像素，连接到该行子像素上方的扫描线，第n+3行组每一行的第i和第i+1个子像素，连接到该行子像素下方的扫描线；
其中：
n＝1、5、9、…、n-4、n；
i＝2、6、10、…、i-4、i；
j＝1、5、9、…、j-4、j。
其中，每一子像素通过一开关元件连接到对应的数据线和对应的扫描线。
其中，所述开关元件为薄膜晶体管，所述薄膜晶体管的栅极与所述对应的扫描线电连接，其源极与所述对应的数据线电连接，其漏极与所述对应的子像素电连接。
本发明还提供了一种液晶面板，包括显示单元，所述显示单元包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层，其中，所述阵列基板包括：
子像素阵列；
多条数据线，每两条数据线之间形成一列组，每一列组包括两列子像素；其中，奇数列组的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的奇数行的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的偶数行的子像素，连接到该列组两侧的与该子像素较远的数据线；
多条扫描线，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素；其中，第n和第n+6行组中，每一行偶数列组的子像素，连接到该行子像素上方的扫描线，第n和第n+6行组中，每一行奇数列组的子像素，连接到该行子像素下方的扫描线；第n+1和第n+5行组中，每一行的第i和第i+1个子像素，连接到该行子像素上方的扫描线，第n+1和第n+5行组中，每一行的第j和第j+3个子像素，连接到该行子像素下方的扫描线；第n+2和第n+4行组中，每一行奇数列组的子像素，连接到该行子像素上方的扫描线，第n+2和第n+4 行组中，每一行偶数列组的子像素，连接到该行子像素下方的扫描线；第n+3行组每一行的第j和第j+3个子像素，连接到该行子像素上方的扫描线，第n+3行组每一行的第i和第i+1个子像素，连接到该行子像素下方的扫描线；
其中：
n＝1、5、9、…、n-4、n；
i＝2、6、10、…、i-4、i；
j＝1、5、9、…、j-4、j。
其中，每一子像素通过一开关元件连接到对应的数据线和对应的扫描线。
其中，所述开关元件为薄膜晶体管，所述薄膜晶体管的栅极与所述对应的扫描线电连接，其源极与所述对应的数据线电连接，其漏极与所述对应的子像素电连接。
其中，所述液晶面板还包括栅驱动器和源驱动器，所述栅驱动器通过扫描线向所述子像素阵列提供扫描信号，所述源驱动器通过数据线向所述子像素阵列提供数据信号。
其中，所述子像素包括红色子像素、绿色子像素和蓝色子像素。
其中，所述液晶面板采用点翻转的方式驱动。
本发明的另一方面是提供一种液晶显示器，包括液晶面板及背光模组，所述液晶面板与所述背光模组相对设置，所述背光模组提供显示光源给所述液晶面板，以使所述液晶面板显示影像，其中，所述液晶面板为如上所述的液晶面板。
相比于现有技术，本发明实施例中提供的阵列基板，通过对阵列基板中子像素与数据线和扫描线的连接方式的排布设计，在使用点翻转方式驱动时，每一列子像素中相互间隔存在充电较好和充电较差的子像素(在此，充电较好和充电较差是相对而言的)，使得包含该阵列基板的液晶面板中，整体上各部分亮度均衡，改善了在竖直方向上存在亮暗线的缺陷。
附图说明
图1为现有的共享数据线阵列基板的局部结构示意图。
图2为点翻转驱动方式的信号波形图。
图3为本发明实施例1提供的共享数据线阵列基板的局部结构示意图。
图4为发明实施例中子像素与数据线和扫描线通过薄膜晶体管连接的结构示意图。
图5为本发明实施例1提供的阵列基板在充电后的示意图。
图6为本发明实施例2提供的共享数据线阵列基板的局部结构示意图。
图7为本发明实施例2提供的阵列基板在充电后的示意图。
图8为本发明实施例3提供的液晶显示器的结构示意图。
图9为本发明实施例3提供的液晶面板的结构示意图。
图10为本发明实施例3提供的显示单元的结构示意图。
具体实施方式
如前所述，本发明的目的是为了改善了共享数据线(Data Line Share，DLS)方式的液晶面板在竖直方向上存在亮暗线的缺陷，提供了一种阵列基板，该阵列基板包括子像素阵列以及相互交叉的多条数据线和扫描线，通过对阵列基板中子像素与数据线和扫描线的连接方式的排布设计，在使用点翻转方式驱动时，每一列子像素中相互间隔存在充电较好和充电较差的子像素。
对于子像素与数据线的连接方式：多条数据线中，每两条数据线之间形成一列组，每一列组包括两列子像素。
其中，对于奇数列组的子像素，每一子像素连接到该列组两侧的与该子像素较近的数据线；对于偶数列组的奇数行的子像素，每一子像素连接到该列组两侧的与该子像素较近的数据线；对于偶数列组的偶数行的子像素，每一子像素连接到该列组两侧的与该子像素较远的数据线。在此，较近和较远是相对而言的。
对于子像素与扫描线的连接方式：首先多条扫描线中，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；然后将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素。
具体地：
对于第n和第n+6行组中，每一行偶数列组的子像素，每一子像素连接到该行子像素上方的扫描线，对于第n和第n+6行组中，每一行奇数列组的子像素，每一子像素连接到该行子像素下方的扫描线。
对于第n+1和第n+5行组中，每一行的第i和第i+1个子像素，每一子像素连接到该行子像素上方的扫描线，对于第n+1和第n+5行组中，每一行的第j和第j+3个子像素，每一子像素连接到该行子像素下方的扫描线。
对于第n+2和第n+4行组中，每一行奇数列组的子像素，每一子像素连接到该行子像素上方的扫描线，对于第n+2和第n+4行组中，每一行偶数列组的子像素，每一子像素连接到该行子像素下方的扫描线。
对于第n+3行组每一行的第j和第j+3个子像素，每一子像素连接到该行子像素上方的扫描线，对于第n+3行组每一行的第i和第i+1个子像素，每一子像素连接到该行子像素下方的扫描线。
其中：n＝1、5、9、…、n-4、n；i＝2、6、10、…、i-4、i；j＝1、5、9、…、j-4、j。
以上关于子像素与扫描线的连接方式，当每一行组包括两行子像素时，一个行组中的一行子像素与数据线和扫面线的连接方式与另一行子像素与数据线和扫面线的连接方式相同，即，将两行子像素时作为一个重复的单元。
为了使本发明的目的、技术方案以及优点更加清楚明白，下面将结合附图用实施例对本发明做进一步说明。
实施例1
图3示出了本实施例提供的阵列基板的局部结构示意图。下文中以Pxy表示具体的子像素，其中，x＝1～7，y＝1～8，如图3中，P11为左上方的第一个子像素，P78为右下方最后一个子像素。
如图3所示，数据线D1～D5中，每两条数据线之间形成一列组11、12、13、14，每一列组包括两列子像素(如图中列组11包括第1和第2列子像素)。
其中，对于奇数列组11、13的子像素，每一子像素连接到该列组两侧的与该子像素较近的数据线(如图中列组11的子像素，子像素P1y连接到数据线D1，子像素P2y连接到数据线D2)；对于偶数列组12、14的奇数行的子像素，每一子像素连接到该列组两侧的与该子像素较近的数据线(如图中列组12中第 1行的子像素P13、P14，子像素P13连接到数据线D2，子像素P14连接到数据线D3)；对于偶数列组12、14的偶数行的子像素，每一子像素连接到该列组两侧的与该子像素较远的数据线(如图中列组12中第2行的子像素P23、P24，子像素P23连接到数据线D3，子像素P24连接到数据线D2)。在此，较近和较远是相对而言的。
扫描线G11～G17和G21～G27中，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线(如图中第1行子像素的的上方和下方的扫描线分别为G11和G21，并且扫描线G11和G21仅用于驱动第1行子像素)。然后将子像素阵列划分为行组21、22、23、24、25、26、27，在本实施例中，每一行组包括一行子像素，即行组21包括第1行子像素，行组22包括第2行子像素……。
子像素与扫描线的连接方式如下：
对于行组21和27偶数列组12、14的子像素，每一子像素连接到该行子像素上方的扫描线(如图中行组21偶数列组12的子像素P13、P14，子像素P13、P14均连接到扫描线G11，行组27偶数列组12的子像素P73、P74，子像素P73、P74均连接到扫描线G17)，对于行组21和27奇数列组11、13的子像素，每一子像素连接到该行子像素下方的扫描线(如图中行组21奇数列组11的子像素P11、P12，子像素P11、P12均连接到扫描线G21，行组27奇数列组11的子像素P71、P72，子像素P71、P72均连接到扫描线G27)。
对于行组22和26每一行的第i和第i+1个子像素，每一子像素连接到该行子像素上方的扫描线(如图中行组22第2和第3个子像素P22、P23，子像素P22、P23连接到扫描线G12，行组26第2和第3个子像素P62、P63，子像素P62、P63连接到扫描线G16)，对于行组22和26每一行的第j和第j+3个子像素，每一子像素连接到该行子像素下方的扫描线(如图中行组22第1和第4个子像素P21、P24，子像素P21、P24连接到扫描线G22，行组26第1和第4个子像素P61、P64，子像素P61、P64连接到扫描线G26)。i＝2、6；j＝1、5。
对于行组23和25每一行奇数列组11、13的子像素，每一子像素连接到该行子像素上方的扫描线(如图中行组23奇数列组11的子像素P31、P32，子像素P31、P32均连接到扫描线G13，行组25奇数列组11的子像素P51、P52，子像素P51、P52均连接到扫描线G15)，对于行组23和25每一行偶数列组12、14的子像素，每一子像素连接到该行子像素下方的扫描线(如图中行组23偶数 列组12的子像素P33、P34，子像素P33、P34均连接到扫描线G23，行组25偶数列组12的子像素P53、P54，子像素P53、P54均连接到扫描线G25)。
对于行组24每一行的第j和第j+3个子像素，每一子像素连接到该行子像素上方的扫描线(如图中行组24第1和第4个子像素P41、P44，子像素P41、P44连接到扫描线G14)，对于行组24每一行的第i和第i+1个子像素，每一子像素连接到该行子像素下方的扫描线(如图中行组24第2和第3个子像素P42、P43，子像素P42、P43连接到扫描线G24)。i＝2、6；j＝1、5。
其中，每一子像素Pxy通过一开关元件10连接到对应的数据线和对应的扫描线。具体地，以子像素P13为例，如图4所示，本实施例中的开关元件10为薄膜晶体管(Thin Film Transistor，TFT)，薄膜晶体管的栅极10a与对应的扫描线G11电连接，其源极10b与对应的数据线D2电连接，其漏极10c与子像素P13电连接。
当采用点翻转(Dot inversion)驱动方式时，以对数据线D2两侧的子像素P12、P13、P22、P23、P32、P33、P42、P43、P52、P53、P62、P63、P72、P73充电为例，并结合附图3，G11、G21、…、G17、G27依次开启时，子像素P12、P13、P22、P32、P33、P42、P52、P53、P62、P72、P73由数据线D2充电，子像素P23、P43和P63由数据线D3充电。其中，在Px2列的子像素中，P12、P42和P72为充电较好的子像素，P22、P32、P52和P62为充电较差的子像素；在Px3列的子像素中，P33、P43和P53为充电较好的子像素，P13、P23、P63和P73为充电较差的子像素。
图5示出了以上结构的阵列基板在一帧画面内，充电较好和充电较差的子像素的分布图图示。其中，白色部分表示充电较好的子像素，阴影部分表示充电较差的子像素。由此可以看出，在同一列的子像素内，相互间隔存在着充电较好和充电较差的子像素，在同一行的子像素内，也相互间隔存在着充电较好和充电较差的子像素。因此包含该阵列基板的液晶面板中，整体上各部分亮度均衡，可以改善在竖直方向上存在亮暗线的缺陷。
本实施例提供的阵列基板，可以视为将如图3所示的局部结构沿横向和纵向多次重复后获得。
实施例2
图6示出了本实施例提供的阵列基板的局部结构示意图。与实施例1不同 的是，本实施例中，在沿扫描线排列的方向上，将子像素阵列划分的行组21a、22a、23a、24a、25a、26a、27a中，每一行组包括两行子像素，如图6中，行组21a包括第1行和第2行子像素，行组22a包括第3行和第4行子像素行组23a包括第5行和第6行子像素，行组24a包括第7行和第8行子像素，行组25a包括第9行和第10行子像素，行组26a包括第11行和第12行子像素，行组27a包括第13行和第14行子像素。
一个行组中的一行子像素与数据线和扫面线的连接方式与另一行子像素与数据线和扫面线的连接方式相同，即，将两行子像素时作为一个重复的单元。例如，行组21a中，第1行和第2行的所有子像素中，上下相邻的两个子像素(例如P11和P21)的连接方式相同，其中第1行和第2行的所有子像素与数据线和扫描线的连接方式与实施例1中行组21的连接方式相同，在此不再赘述。同理，行组22a对应实施例1中的行组21，行组23a对应实施例1中的行组23，行组24a对应实施例1中的行组24，行组25a对应实施例1中的行组25，行组26a对应实施例1中的行组26，行组27a对应实施例1中的行组27。
图7示出了以上结构的阵列基板在一帧画面内，充电较好和充电较差的子像素的分布图图示。其中，白色部分表示充电较好的子像素，阴影部分表示充电较差的子像素。
本实施例提供的阵列基板，可以视为将如图6所示的局部结构沿横向和纵向多次重复后获得。
实施例3
参阅如8和图9，本实施例提供了一种液晶面板以及包含该液晶面板的液晶显示器。如图8所示，该液晶显示器包括液晶面板100及背光模组200，液晶面板100与背光模组200相对设置，背光模组200提供显示光源给液晶面板100，以使液晶面板100显示影像。
其中，如图9所示，液晶面板100包括设置有子像素阵列的显示单元1、栅驱动器2以及源驱动器3。栅驱动器2通过扫描线向子像素阵列提供扫描信号Gate，源驱动器3通过数据线向子像素阵列提供数据信号Data。
其中，图10为显示单元1的结构示意图。该显示单元1包括包括相对设置阵列基板(array substrate)1a和滤光基板(color filter substrate)1b以及位于阵列基板1a和滤光基板1b之间的液晶层1c。其中，阵列基板1a采用了如实施例 1或实施例2提供的阵列基板，其中，子像素Pxy包括红色子像素、绿色子像素和蓝色子像素。
综上所述，本发明实施例中提供的阵列基板，通过对阵列基板中子像素与数据线和扫描线的连接方式的排布设计，在使用点翻转方式驱动时，每一列子像素中相互间隔存在充电较好和充电较差的子像素(在此，充电较好和充电较差是相对而言的)，使得包含该阵列基板的液晶面板中，整体上各部分亮度均衡，改善了在竖直方向上存在亮暗线的缺陷。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种阵列基板，其中，包括：
    子像素阵列；
    多条数据线，每两条数据线之间形成一列组，每一列组包括两列子像素；其中，奇数列组的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的奇数行的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的偶数行的子像素，连接到该列组两侧的与该子像素较远的数据线；
    多条扫描线，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素；其中，第n和第n+6行组中，每一行偶数列组的子像素，连接到该行子像素上方的扫描线，第n和第n+6行组中，每一行奇数列组的子像素，连接到该行子像素下方的扫描线；第n+1和第n+5行组中，每一行的第i和第i+1个子像素，连接到该行子像素上方的扫描线，第n+1和第n+5行组中，每一行的第j和第j+3个子像素，连接到该行子像素下方的扫描线；第n+2和第n+4行组中，每一行奇数列组的子像素，连接到该行子像素上方的扫描线，第n+2和第n+4行组中，每一行偶数列组的子像素，连接到该行子像素下方的扫描线；第n+3行组每一行的第j和第j+3个子像素，连接到该行子像素上方的扫描线，第n+3行组每一行的第i和第i+1个子像素，连接到该行子像素下方的扫描线；
    其中：
    n＝1、5、9、…、n-4、n；
    i＝2、6、10、…、i-4、i；
    j＝1、5、9、…、j-4、j。
  2. 根据权利要求1所述的阵列基板，其中，每一子像素通过一开关元件连接到对应的数据线和对应的扫描线。
  3. 根据权利要求2所述的阵列基板，其中，所述开关元件为薄膜晶体管，所述薄膜晶体管的栅极与所述对应的扫描线电连接，其源极与所述对应的数据线电连接，其漏极与所述对应的子像素电连接。
  4. 一种液晶面板，包括显示单元，所述显示单元包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层，其中，所述阵列基板包括：
    子像素阵列；
    多条数据线，每两条数据线之间形成一列组，每一列组包括两列子像素；其中，奇数列组的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的奇数行的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的偶数行的子像素，连接到该列组两侧的与该子像素较远的数据线；
    多条扫描线，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素；其中，第n和第n+6行组中，每一行偶数列组的子像素，连接到该行子像素上方的扫描线，第n和第n+6行组中，每一行奇数列组的子像素，连接到该行子像素下方的扫描线；第n+1和第n+5行组中，每一行的第i和第i+1个子像素，连接到该行子像素上方的扫描线，第n+1和第n+5行组中，每一行的第j和第j+3个子像素，连接到该行子像素下方的扫描线；第n+2和第n+4行组中，每一行奇数列组的子像素，连接到该行子像素上方的扫描线，第n+2和第n+4行组中，每一行偶数列组的子像素，连接到该行子像素下方的扫描线；第n+3行组每一行的第j和第j+3个子像素，连接到该行子像素上方的扫描线，第n+3行组每一行的第i和第i+1个子像素，连接到该行子像素下方的扫描线；
    其中：
    n＝1、5、9、…、n-4、n；
    i＝2、6、10、…、i-4、i；
    j＝1、5、9、…、j-4、j。
  5. 根据权利要求4所述的液晶面板，其中，每一子像素通过一开关元件连接到对应的数据线和对应的扫描线。
  6. 根据权利要求5所述的液晶面板，其中，所述开关元件为薄膜晶体管，所述薄膜晶体管的栅极与所述对应的扫描线电连接，其源极与所述对应的数据线电连接，其漏极与所述对应的子像素电连接。
  7. 根据权利要求4所述的液晶面板，其中，所述液晶面板还包括栅驱动器 和源驱动器，所述栅驱动器通过扫描线向所述子像素阵列提供扫描信号，所述源驱动器通过数据线向所述子像素阵列提供数据信号。
  8. 根据权利要求4所述的液晶面板，其中，所述子像素包括红色子像素、绿色子像素和蓝色子像素。
  9. 根据权利要求4所述的液晶面板，其中，所述液晶面板采用点翻转的方式驱动。
  10. 一种液晶显示器，包括液晶面板及背光模组，所述液晶面板与所述背光模组相对设置，所述背光模组提供显示光源给所述液晶面板，以使所述液晶面板显示影像，其中，所述液晶面板包括显示单元，所述显示单元包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层，其中，所述阵列基板包括：
    子像素阵列；
    多条数据线，每两条数据线之间形成一列组，每一列组包括两列子像素；其中，奇数列组的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的奇数行的子像素，连接到该列组两侧的与该子像素较近的数据线；偶数列组的偶数行的子像素，连接到该列组两侧的与该子像素较远的数据线；
    多条扫描线，每一行子像素的上方和下方均设置有仅用于驱动该行子像素的扫描线；将所述子像素阵列划分为多个行组，每一行组包括一行或两行子像素；其中，第n和第n+6行组中，每一行偶数列组的子像素，连接到该行子像素上方的扫描线，第n和第n+6行组中，每一行奇数列组的子像素，连接到该行子像素下方的扫描线；第n+1和第n+5行组中，每一行的第i和第i+1个子像素，连接到该行子像素上方的扫描线，第n+1和第n+5行组中，每一行的第j和第j+3个子像素，连接到该行子像素下方的扫描线；第n+2和第n+4行组中，每一行奇数列组的子像素，连接到该行子像素上方的扫描线，第n+2和第n+4行组中，每一行偶数列组的子像素，连接到该行子像素下方的扫描线；第n+3行组每一行的第j和第j+3个子像素，连接到该行子像素上方的扫描线，第n+3行组每一行的第i和第i+1个子像素，连接到该行子像素下方的扫描线；
    其中：
    n＝1、5、9、…、n-4、n；
    i＝2、6、10、…、i-4、i；
    j＝1、5、9、…、j-4、j。
  11. 根据权利要求10所述的液晶显示器，其中，每一子像素通过一开关元件连接到对应的数据线和对应的扫描线。
  12. 根据权利要求11所述的液晶显示器，其中，所述开关元件为薄膜晶体管，所述薄膜晶体管的栅极与所述对应的扫描线电连接，其源极与所述对应的数据线电连接，其漏极与所述对应的子像素电连接。
  13. 根据权利要求10所述的液晶显示器，其中，所述液晶面板还包括栅驱动器和源驱动器，所述栅驱动器通过扫描线向所述子像素阵列提供扫描信号，所述源驱动器通过数据线向所述子像素阵列提供数据信号。
  14. 根据权利要求10所述的液晶显示器，其中，所述子像素包括红色子像素、绿色子像素和蓝色子像素。
  15. 根据权利要求10所述的液晶显示器，其中，所述液晶面板采用点翻转的方式驱动。
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