WO2017096705A1 - 点反转模式的液晶显示面板 - Google Patents

点反转模式的液晶显示面板 Download PDF

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Publication number
WO2017096705A1
WO2017096705A1 PCT/CN2016/072649 CN2016072649W WO2017096705A1 WO 2017096705 A1 WO2017096705 A1 WO 2017096705A1 CN 2016072649 W CN2016072649 W CN 2016072649W WO 2017096705 A1 WO2017096705 A1 WO 2017096705A1
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Prior art keywords
thin film
film transistor
gate scan
line
drain
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PCT/CN2016/072649
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English (en)
French (fr)
Inventor
王聪
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武汉华星光电技术有限公司
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Priority to US14/913,373 priority Critical patent/US9715859B2/en
Publication of WO2017096705A1 publication Critical patent/WO2017096705A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel in a dot inversion mode.
  • LCD Liquid Crystal Display
  • advantages such as thin body, power saving, no radiation, etc., such as: LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or Laptop screens, etc., dominate the field of flat panel display.
  • PDA personal digital assistant
  • liquid crystal displays which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to fill liquid crystal molecules between a Thin Film Transistor Array Substrate (TFT Array Substrate) and a Color Filter (CF) substrate, and apply driving on the two substrates.
  • TFT Array Substrate Thin Film Transistor Array Substrate
  • CF Color Filter
  • the liquid crystal display panel includes a plurality of pixels arranged in an array.
  • each pixel has evolved from three sub-pixels including red (Red, R), green (Green), and blue (Blue) to include red, green, blue, and white (White, W).
  • Red, R red
  • Green green
  • Blue blue
  • W white
  • WRGB pixel structures Each sub-pixel is electrically connected to a thin film transistor (TFT), a gate of the TFT is connected to the horizontal scan line, a drain is connected to the data line in the vertical direction, and a source is connected to the pixel electrode.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs electrically connected to the scanning line to be turned on, so that the signal voltage on the data line can be written into the sub-pixels, and the transmittance of the liquid crystal is controlled to achieve a display effect.
  • the driving methods of the conventional liquid crystal display panel generally include a frame inversion method, a line inversion method, and a dot inversion method.
  • the dot inversion method means that the voltage polarities of the four sub-pixels adjacent to each of the sub-pixels are opposite in one frame. In the dot inversion mode, the liquid crystal display panel has the least problem of flicker and crosstalk, and the display effect is optimal.
  • a demultiplexer In the traditional WRGB pixel structure process, in order to reduce the number of pins (Pin) at the source driver (Source IC) and the number of source-driven fanout (Fanout) lines, a demultiplexer (Demux) is often designed.
  • a Fanout line is assigned to a plurality of data lines, and the data lines in the effective display area are controlled by controlling the timing of the splitters. But this will lead to any one The polarity of the multiple data lines under the Fanout line control is exactly the same.
  • the liquid crystal reverses the frame inversion mode, which causes the internal flicker to be severe, especially for the WRGB pixel structure, a Fanout line. Assigned to four data lines, there is often a significant crosstalk phenomenon that affects the display of the panel.
  • a common improvement is to perform jumper processing on the end of the splitter, and then change the scanning mode of the gate scan line from progressive scan to the odd-numbered gate scan lines, and then even
  • the strip gate scan lines are turned on in turn, which can change the polarity inversion mode of the panel, but it is not a point inversion mode in a strict sense.
  • a conventional liquid crystal display panel generally arranges horizontal gate scan lines one by one, and the spacing of each adjacent two gate scan lines is equal, and n is a positive integer, and the nth row of TFTs are located corresponding to the first Below the n gate scan lines G(n).
  • the splitter 1 for controlling each data line shown in FIG. 1 includes four branch traces 11, 12, 13, 14 and a plurality of sets of control switches, each group of control switches including T100 from left to right.
  • T200, T300, T400, a total of four TFTs the gates of the four TFTs of the same group of control switches are electrically connected to a shunt line, the source is electrically connected to a source drive fan-out line 2, and the drains are respectively connected.
  • the end of the splitter 1 is jumpered.
  • the drain of the second TFT T200 of the left set of control switches is hopped to the sixth data line D6, and the left set of control switches
  • the drain of the third TFT T300 is hopped to the seventh data line D7
  • the drain of the second TFT T200 of the right set of control switches is hopped to the second data line D2
  • the third TFT of the right set of control switches The drain of the T300 is hopped to the third data line D3.
  • the gate scan lines are scanned one by one. Since the voltages of the four data lines controlled by the same source drive fan-out line 2 have the same polarity, the display effect of the above conventional display panel is as shown in FIG.
  • the sub-pixels of the first, fourth, sixth, and seventh columns are positive polarity, and the sub-pixels of the second, third, fifth, and eighth columns are negative polarity.
  • the mth frame first turns on the odd-numbered gate scan lines, and the m+1th frame turns on the even-numbered gate scan lines in turn, and as shown in FIG.
  • the voltage polarity of the same source-driven fan-out line is opposite, and the superimposed display effect of the two adjacent frames of the conventional display panel is as shown in FIG. 7, although the dots are implemented in each column of pixels. Inversion, but dot inversion is not implemented for each row of pixels, and the dot inversion mode in a strict sense is not implemented.
  • An object of the present invention is to provide a liquid crystal display panel with a dot inversion mode, which can change the polarity inversion mode of the liquid crystal display panel by adjusting the wiring inside the liquid crystal display panel without changing the power consumption of the source driving. Reverse mode to improve the display quality of the LCD panel Good display effect.
  • the present invention provides a liquid crystal display panel of a dot inversion mode.
  • the liquid crystal display panel of the dot inversion mode of the present invention comprises a plurality of gate scan lines which are parallel to each other and distributed in the lateral direction, a plurality of data lines which are parallel to each other and distributed in the longitudinal direction, and a plurality of arrays arranged in an array. a plurality of thin film transistors for driving corresponding sub-pixels, and a splitter;
  • s be a positive integer, and the source of the s column thin film transistor is connected to the sth data line;
  • n be an even number, the adjacent n-1th gate scan line and the nth gate scan line are disposed close to each other, and the n-1th line thin film transistor is located above the n-1th gate scan line, The nth row of thin film transistors are all located under the nth gate scan line; each of the eight columns of the same row of thin film transistors is grouped in a left-to-right direction, the first and second of the n-1th row
  • the gates of the seventh and eighth thin film transistors are electrically connected to the n-1th gate scan line, and the gates of the third, fourth, fifth, and sixth thin film transistors are electrically connected to the nth a gate scan line; the gates of the first, second, seventh, and eighth thin film transistors in the nth row are electrically connected to the nth gate scan line, and the third, fourth, fifth, a gate of the sixth thin film transistor is electrically connected to the n-1th gate scan line;
  • the splitter includes first, second, third, and fourth branch traces, and a plurality of sets of control switches; each set of control switches includes first, second, third, and fourth switches from left to right
  • the thin film transistor the gates of the four switching thin film transistors of the same group of control switches are electrically connected to one shunting line, the source is electrically connected to one source driving fan-out line, and the drain is respectively connected to one data line; adjacent two The polarity of the voltage of the fan-driven fan-out line is opposite;
  • Each adjacent two sets of control switches of the splitter correspond to eight data lines arranged in order from left to right; the end of the splitter is subjected to jumper processing, and for the adjacent two sets of control switches, the left set of controls
  • the drain of the first switching thin film transistor of the switch is correspondingly connected to the first data line, the drain of the second switching thin film transistor is hopped to the seventh data line, and the drain of the third switching thin film transistor is hopped to the sixth data
  • the drain of the fourth switching thin film transistor is connected to the fourth data line; the drain of the first switching thin film transistor of the right group of control switches is connected to the fifth data line, and the drain of the second switching thin film transistor is hopped To the third data line, the drain of the third switching thin film transistor is jumped to the second data line, and the drain of the fourth switching thin film transistor is connected to the eighth data line.
  • m be a positive integer.
  • the m-th frame first opens the odd-numbered gate scan lines one by one, and the next m+1-th frame then turns on even-numbered gate scan lines one by one; in the two adjacent frames before and after, the same One source drives the fanout line to have opposite voltage polarities.
  • the sub-pixels include red, green, blue, and white four-color sub-pixels.
  • the liquid crystal display panel of the dot inversion mode of the present invention includes a plurality of parallel and along a laterally distributed gate scan line, a plurality of mutually parallel and longitudinally distributed data lines, a plurality of arrayed thin film transistors for driving corresponding sub-pixels, and a splitter;
  • s be a positive integer, and the source of the s column thin film transistor is connected to the sth data line;
  • n be an even number, the adjacent n-1th gate scan line and the nth gate scan line are disposed close to each other, and the n-1th line thin film transistor is located above the n-1th gate scan line, The nth row of thin film transistors are all located under the nth gate scan line; each of the eight columns of the same row of thin film transistors is grouped in a left-to-right direction, the first and second of the n-1th row
  • the gates of the third and fourth thin film transistors are electrically connected to the n-1th gate scan line, and the gates of the fifth, sixth, seventh, and eighth thin film transistors are electrically connected to the nth a gate scan line; the gates of the first, second, third, and fourth thin film transistors in the nth row are electrically connected to the nth gate scan line, and the fifth, sixth, seventh, The gates of the eighth thin film transistor are electrically connected to the n-1th gate scan line;
  • the splitter includes first, second, third, and fourth branch traces, and a plurality of sets of control switches; each set of control switches includes first, second, third, and fourth switches from left to right
  • the thin film transistor the gates of the four switching thin film transistors of the same group of control switches are electrically connected to one shunting line, the source is electrically connected to one source driving fan-out line, and the drain is respectively connected to one data line; adjacent two The polarity of the voltage of the fan-driven fan-out line is opposite;
  • Each adjacent two sets of control switches of the splitter correspond to eight data lines arranged in order from left to right; the end of the splitter is subjected to jumper processing, and for the adjacent two sets of control switches, the left set of controls
  • the drain of the first switching thin film transistor of the switch is correspondingly connected to the first data line, the drain of the second switching thin film transistor is jumped to the sixth data line, and the drain of the third switching thin film transistor is connected to the third data line
  • the drain of the fourth switching thin film transistor is spliced to the eighth data line; the drain of the first switching thin film transistor of the right group of control switches is connected to the fifth data line, and the drain of the second switching thin film transistor is hopped To the second data line, the drain of the third switching thin film transistor is connected to the seventh data line, and the drain of the fourth switching thin film transistor is connected to the fourth data line.
  • m be a positive integer.
  • the m-th frame first opens the odd-numbered gate scan lines one by one, and the next m+1-th frame then turns on even-numbered gate scan lines one by one; in the two adjacent frames before and after, the same One source drives the fanout line to have opposite voltage polarities.
  • the sub-pixels include red, green, blue, and white four-color sub-pixels.
  • the liquid crystal display panel of the dot inversion mode of the present invention comprises a plurality of gate scan lines which are parallel to each other and distributed in the lateral direction, a plurality of data lines which are parallel to each other and distributed in the longitudinal direction, and a plurality of arrays arranged in an array. a plurality of thin film transistors for driving corresponding sub-pixels, and a splitter;
  • s be a positive integer, and the source of the s column thin film transistor is connected to the sth data line;
  • n be an even number, the adjacent n-1th gate scan line and the nth gate scan line are disposed close to each other, and the n-1th line thin film transistor is located above the n-1th gate scan line, The nth row of thin film transistors are all located under the nth gate scan line; each of the eight columns of the same row of thin film transistors is grouped in a left-to-right direction, the first and third of the n-1th row
  • the gates of the sixth and eighth thin film transistors are electrically connected to the n-1th gate scan line, and the gates of the second, fourth, fifth, and seventh thin film transistors are electrically connected to the nth a gate scan line; the gates of the first, third, sixth, and eighth thin film transistors in the nth row are electrically connected to the nth gate scan line, and the second, fourth, fifth, a gate of the seventh thin film transistor is electrically connected to the n-1th gate scan line;
  • the splitter includes first, second, third, and fourth branch traces, and a plurality of sets of control switches; each set of control switches includes first, second, third, and fourth switches from left to right
  • the thin film transistor the gates of the four switching thin film transistors of the same group of control switches are electrically connected to one shunting line, the source is electrically connected to one source driving fan-out line, and the drain is respectively connected to one data line; adjacent two The polarity of the voltage of the fan-driven fan-out line is opposite;
  • Each adjacent two sets of control switches of the splitter correspond to eight data lines arranged in order from left to right; the end of the splitter is not subjected to jumper processing, and for the adjacent two sets of control switches, the left set
  • the drain of the first switching thin film transistor of the control switch is connected to the first data line
  • the drain of the second switching thin film transistor is connected to the second data line
  • the drain of the third switching thin film transistor is connected to the third data line.
  • the drain of the fourth switching thin film transistor is connected to the fourth data line
  • the drain of the first switching thin film transistor of the right group of control switches is connected to the fifth data line
  • the drain of the second switching thin film transistor is correspondingly connected.
  • the six data lines, the drain of the third switching thin film transistor is correspondingly connected to the seventh data line
  • the drain of the fourth switching thin film transistor is correspondingly connected to the eighth data line.
  • m be a positive integer.
  • the m-th frame first opens the odd-numbered gate scan lines one by one, and the next m+1-th frame then turns on even-numbered gate scan lines one by one; in the two adjacent frames before and after, the same One source drives the fanout line to have opposite voltage polarities.
  • the sub-pixels include red, green, blue, and white four-color sub-pixels.
  • the liquid crystal display panel of the dot inversion mode adjusts the wiring inside the liquid crystal display panel without changing the power consumption of the source driving: setting n to an even number to be adjacent
  • the n-1th gate scan line is disposed adjacent to the nth gate scan line, the n-1th thin film transistor is located above the n-1th gate scan line, and the nth row of thin film transistors are located
  • the nth gate scan line is below; the gates of some of the thin film transistors in the n-1th row and the nth row are electrically connected to the n-1th gate scan line, and the gates of some thin film transistors are Electrically connected to the nth gate scan line; and matched with the processing of the end of the splitter to change the liquid crystal display panel
  • the polarity inversion mode realizes the dot inversion mode, which can solve the problem of flicker and crosstalk of the liquid crystal display panel, improve the display quality of the liquid crystal display panel, and improve the display effect.
  • 1 is a schematic view showing the wiring of a conventional liquid crystal display panel
  • FIG. 2 is a schematic view showing the wiring of a splitter corresponding to the liquid crystal display panel of FIG. 1;
  • FIG. 3 is a timing chart corresponding to one-by-one scanning of gate scan lines in the liquid crystal display panel shown in FIG. 1;
  • FIG. 4 is a schematic diagram showing voltage polarity distribution of a conventional liquid crystal display panel at the timing shown in FIG. 3;
  • FIG. 5 is a timing chart corresponding to a timing chart of gate scan line spacer scanning in the liquid crystal display panel shown in FIG. 1 and a liquid crystal display panel of the dot inversion mode of the present invention
  • FIG. 6 is a schematic diagram showing voltage polarities of adjacent two source-driven fan-out lines of a liquid crystal display panel corresponding to the liquid crystal display panel shown in FIG. 1 and the dot inversion mode of the present invention
  • FIG. 7 is a superimposed display effect diagram of two adjacent frames of the conventional liquid crystal display panel shown in FIG. 1;
  • FIG. 8 is a schematic diagram of wiring of a first embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • FIG. 9 is a schematic diagram showing the wiring of a splitter of a first embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • FIG. 10 is a schematic diagram showing voltage polarities of an mth frame of the liquid crystal display panel shown in FIG. 8;
  • FIG. 11 is a schematic diagram showing voltage polarities of an m+1th frame of the liquid crystal display panel shown in FIG. 8;
  • FIG. 12 is a schematic diagram showing voltage polarities after superimposing adjacent two frames of pictures shown in FIG. 10 and FIG. 11;
  • FIG. 13 is a schematic diagram of wiring of a second embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • FIG. 14 is a schematic diagram showing the wiring of a splitter of a second embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • FIG. 15 is a schematic diagram showing voltage polarities of an mth frame of the liquid crystal display panel shown in FIG. 13;
  • 16 is a schematic diagram showing voltage polarities of an m+1th frame of the liquid crystal display panel shown in FIG. 13;
  • FIG. 17 is a schematic diagram showing voltage polarities after superimposing adjacent two frames of pictures shown in FIG. 15 and FIG. 16;
  • FIG. 18 is a schematic view showing the wiring of a third embodiment of the liquid crystal display panel of the dot inversion mode of the present invention.
  • FIG. 19 is a layout of a splitter of a third embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • Line diagram
  • FIG. 20 is a schematic diagram showing voltage polarities of an m-th frame of the liquid crystal display panel shown in FIG. 18;
  • 21 is a schematic diagram showing voltage polarities of an m+1th frame of the liquid crystal display panel shown in FIG. 18;
  • FIG. 22 is a schematic diagram showing voltage polarities after superimposing adjacent two frames of pictures shown in FIG. 20 and FIG. 21.
  • FIG. 22 is a schematic diagram showing voltage polarities after superimposing adjacent two frames of pictures shown in FIG. 20 and FIG. 21.
  • the present invention provides a liquid crystal display panel in a dot inversion mode.
  • FIG. 8 and FIG. 9 is a first embodiment of a liquid crystal display panel of a dot inversion mode according to the present invention.
  • the first embodiment includes a plurality of gate scan lines and a plurality of mutually parallel and laterally distributed gate lines. Parallel and longitudinally distributed data lines, a plurality of arrayed thin film transistors for driving corresponding sub-pixels, and a splitter 1.
  • s is a positive integer
  • the source of the s-th column thin film transistor is connected to the sth data line D(s).
  • the source of the first column of thin film transistors is connected to the first data line.
  • D (1) the source of the second column thin film transistor is connected to the second data line D (2), and so on.
  • n be an even number
  • the adjacent n-1th gate scan line G(n-1) is disposed close to the nth gate scan line G(n)
  • the n-1th thin film transistor is located at the Above n-1 gate scan lines G(n-1)
  • the nth row of thin film transistors are located under the nth gate scan line G(n), for example: the first gate scan line G(1) Provided close to the second gate scan line G(2), the first row of thin film transistors are located above the first gate scan line G(1), and the second row of thin film transistors are located at the second strip Below the gate scan line G(2);
  • the third gate scan line G(3) is disposed adjacent to the fourth gate scan line G(4), and the third row of thin film transistors are located at the third gate Above the scan line G(3), the fourth row of thin film transistors are located below the fourth gate scan line G(4), and so on.
  • the gates of the first, second, seventh, and eighth thin film transistors T1, T2, T7, and T8 in the n-1th row are grouped by eight columns of the same row of thin film transistors in a left-to-right direction.
  • the gates are electrically connected to the n-1th gate scan line G(n-1), and the gates of the third, fourth, fifth, and sixth thin film transistors T3, T4, T5, and T6 are electrically connected to The nth gate scan line G(n);
  • the gates of the first, second, seventh, and eighth thin film transistors T1, T2, T7, and T8 in the nth row are electrically connected to the nth gate Scanning line G(n), and the gates of the third, fourth, fifth, and sixth thin film transistors T3, T4, T5, and T6 are electrically connected to the n-1th gate scanning line G(n-1)
  • the gates of the first, second, seventh, and eighth thin film transistors T1, T2, T7, and T8 in the first row are electrically connected
  • the splitter 1 includes first, second, third, and fourth branch traces 11, 12, 13, 14 and a plurality of sets of control switches.
  • Each group of control switches includes first, second, third, and fourth switching thin film transistors T100, T200, T300, and T400 from left to right, and gates of four switching thin film transistors T100, T200, T300, and T400 of the same group of control switches
  • the poles are electrically connected to a shunt line
  • the source is electrically connected to a source driving fan-out line 2
  • the drain is respectively connected to a data line, that is, the gate of the first switching thin film transistor T100 is electrically connected to the first strip.
  • the gate of the second switching thin film transistor T200 is electrically connected to the second shunt trace 12, and the gate of the third switching thin film transistor T300 is electrically connected to the third shunt trace 13 and the fourth switch.
  • the gate of the thin film transistor T400 is electrically connected to the fourth shunt trace 14.
  • the voltages of the adjacent two source-driven fan-out lines 2 are opposite in polarity.
  • Each adjacent two sets of control switches of the splitter 1 correspond to eight data lines arranged in order from left to right; the end of the splitter 1 is subjected to jumper processing, and for the adjacent two sets of control switches, the left side is
  • the drain of the first switching thin film transistor T100 of the group control switch is connected to the first data line D(1), and the drain of the second switching thin film transistor T200 is connected to the seventh data line D(7), the third switch
  • the drain of the thin film transistor T300 is jumped to the sixth data line D(6), and the drain of the fourth switching thin film transistor T400 is connected to the fourth data line D(4); the first switch film of the right set of control switches
  • the drain of the transistor T100 is connected to the fifth data line D(5), the drain of the second switching thin film transistor T200 is hopped to the third data line D(3), and the drain of the third switching thin film transistor T300 is hopped.
  • the drain of the fourth switching thin film transistor T400 is connected to the eighth data line D(8).
  • the sub-pixels include red, green, blue, and white four-color sub-pixels.
  • the first embodiment operates under the condition shown in FIG. 5 and the voltage polarity conversion condition of the source driving fan-out line shown in FIG. 6, and m is a positive integer, and the mth frame first has an odd number (G(1) The gate scan lines of G(3) and up to G(n-1) are turned on one by one, and the next m+1th frame is followed by an even number of gate scan lines (G(2), G(4), up to G(n)) is turned on one by one. In the two frames adjacent to each other, the voltage of the same source driving fan-out line 2 is opposite. Then, since the voltages of the four data lines controlled by the same source-driven fan-out line 2 have the same polarity, as shown in FIG.
  • the n-1th line is the first of the odd-numbered thin film transistors.
  • the second, seventh, and eighth thin film transistors T1, T2, T7, and T8 are turned on, so that the first and seventh sub-pixels in the n-1th row of sub-pixels are positive, and the second and eighth sub-pixels are negative.
  • the nth row is the third of the even-line thin film transistors.
  • the fourth, fifth, and sixth thin film transistors T3, T4, T5, and T6 are turned on, so that the fourth and sixth sub-pixels in the n-th row of sub-pixels are positive, and the third and fifth sub-pixels are negative; As shown in FIG.
  • the first, second, seventh, and eighth thin film transistors T1, T2, T7, and T8 in the nth row of thin film transistors are turned on, so that the nth row of sub-pixels is The second and eighth sub-pixels are positive, and the first and seventh sub-pixels are negative; and the third, fourth, fifth, and sixth thin film transistors T3 and T4 of the n-1th thin film transistor are T5 and T6 are turned on, so that the third and fifth sub-pixels in the n-1th row of sub-pixels are positive, and the fourth and sixth sub-pixels are negative; as shown in FIG. 12, adjacent m-th frames The voltage polarity after superimposing the two frames of the m+1th frame completely realizes the dot inversion mode.
  • FIG. 13 and FIG. 14 is a second embodiment of the dot-reverse mode liquid crystal display panel of the present invention.
  • the second embodiment differs from the first embodiment in that:
  • the gates of the first, second, third, and fourth thin film transistors T1, T2, T3, and T4 in the n-1th row are electrically connected to the n-1th gate scan line G(n-1)
  • the gates of the fifth, sixth, seventh, and eighth thin film transistors T5, T6, T7, and T8 are all electrically connected to the nth gate scan line G(n); the first of the nth rows,
  • the gates of the second, third, and fourth thin film transistors T1, T2, T3, and T4 are electrically connected to the nth gate scan line G(n), and the fifth, sixth, seventh, and eighth films are electrically connected.
  • the gates of the transistors T5, T6, T7, T8 are electrically connected to the n-1th gate scan line G(n-1);
  • the drain of the first switch thin film transistor T100 of the left set of control switches is connected to the first data line D (1).
  • the drain of the second switching thin film transistor T200 is jumped to the sixth data line D(6), the drain of the third switching thin film transistor T300 is connected to the third data line D(3), and the fourth switching thin film transistor
  • the drain of the T400 is connected to the eighth data line D(8);
  • the drain of the first switching thin film transistor T100 of the right group of control switches is connected to the fifth data line D(5), and the second switching thin film transistor T200
  • the drain of the third switching thin film transistor T300 is connected to the seventh data line D(7), and the drain of the fourth switching thin film transistor T400 is connected to the first Four data lines D (4);
  • the second embodiment operates under the condition shown in FIG. 5 and the voltage polarity conversion condition of the source driving fan-out line shown in FIG. 6, and m is a positive integer, and the mth frame first has an odd number (G(1) The gate scan lines of G(3) and up to G(n-1) are turned on one by one, and the next m+1th frame is followed by an even number of gate scan lines (G(2), G(4), up to G(n)) is turned on one by one. In the two frames adjacent to each other, the voltage of the same source driving fan-out line 2 is opposite. Then, since the voltages of the four data lines controlled by the same source driving fan-out line 2 have the same polarity, as shown in FIG.
  • the n-1th line is the first of the odd-numbered thin film transistors.
  • Second, third, fourth thin film transistor T1 T2, T3, and T4 are turned on, so that the first and third sub-pixels in the n-1th row of sub-pixels are positive, and the second and fourth sub-pixels are negative; and the nth row is even-numbered in the thin film transistor.
  • the fifth, sixth, seventh, and eighth thin film transistors T5, T6, T7, and T8 are turned on, so that the sixth and eighth sub-pixels in the n-th row of sub-pixels are positive, and the fifth and seventh sub-pixels are negative. As shown in FIG.
  • the first, second, third, and fourth thin film transistors T1, T2, T3, and T4 in the nth line thin film transistor are turned on, so that the nth line
  • the second and fourth sub-pixels of the sub-pixel are positive, the first and third sub-pixels are negative; and the fifth, sixth, seventh, and eighth thin film transistors T5 of the n-1th thin film transistor , T6, T7, T8 are turned on, so that the fifth and seventh sub-pixels in the n-1th row of sub-pixels are positive, and the sixth and eighth sub-pixels are negative; as shown in FIG.
  • the polarity of the voltage after the m-frame and the m+1th frame are superimposed to achieve the dot inversion mode.
  • FIG. 18 and FIG. 19 is a third embodiment of the liquid crystal display panel of the dot inversion mode of the present invention.
  • the third embodiment differs from the first embodiment in that:
  • the gates of the first, third, sixth, and eighth thin film transistors T1, T3, T6, and T8 in the n-1th row are electrically connected to the n-1th gate scan line G(n-1)
  • the gates of the second, fourth, fifth, and seventh thin film transistors T2, T4, T5, and T7 are electrically connected to the nth gate scan line G(n); the first row in the nth row,
  • the gates of the third, sixth, and eighth thin film transistors T1, T3, T6, and T8 are electrically connected to the nth gate scan line G(n), and the second, fourth, fifth, and seventh films are electrically connected.
  • the gates of the transistors T2, T4, T5, T7 are electrically connected to the n-1th gate scan line G(n-1);
  • the drain of the first switch thin film transistor T100 of the left set of control switches is connected to the first data line D(1).
  • the drain of the second switching thin film transistor T200 is connected to the second data line D(2), the drain of the third switching thin film transistor T300 is connected to the third data line D(3), and the fourth switching thin film transistor T400 is The drain is correspondingly connected to the fourth data line D(4); the drain of the first switching thin film transistor T100 of the right group of control switches is connected to the fifth data line D(5), and the drain of the second switching thin film transistor T200
  • the drain of the third switching thin film transistor T300 is correspondingly connected to the seventh data line D(7), and the drain of the fourth switching thin film transistor T400 is correspondingly connected to the eighth data line D.
  • the third embodiment operates under the condition shown in FIG. 5 and the voltage polarity conversion condition of the source drive fan-out line shown in FIG. 6, and m is a positive integer, and the mth frame first has an odd number (G(1) The gate scan lines of G(3) and up to G(n-1) are turned on one by one, and the next m+1th frame is followed by an even number of gate scan lines (G(2), G(4), up to G(n)) is turned on one by one. In the two frames adjacent to each other, the voltage of the same source driving fan-out line 2 is opposite. Then, since the voltages of the four data lines controlled by the same source-driven fan-out line 2 have the same polarity, as shown in FIG.
  • the first, third, sixth, and eighth thin film transistors T1, T3, T6, and T8 in the n-1th row, that is, the odd-numbered thin film transistors are turned on, so that the first and third sub-pixels of the n-1th row of sub-pixels
  • the pixels are positive polarity, and the sixth and eighth sub-pixels are negative polarity
  • the second, fourth, fifth, and seventh thin film transistors T2, T4, T5, and T7 of the n-th row that is, the even-numbered thin film transistors are turned on, so that The second and fourth sub-pixels of the nth row of sub-pixels are positive polarity, and the fifth and seventh sub-pixels are negative polarity; as shown in FIG.
  • the nth row of thin film transistors The first, third, sixth, and eighth thin film transistors T1, T3, T6, and T8 are turned on, so that the sixth and eighth sub-pixels in the n-th row of sub-pixels are positive, and the first and third sub-pixels are Negative polarity; at the same time, the second, fourth, fifth, and seventh thin film transistors T2, T4, T5, and T7 of the n-1th thin film transistor are turned on, so that the fifth and seventh of the n-1th row of sub-pixels
  • the sub-pixels are positive polarity, and the second and fourth sub-pixels are negative polarity; as shown in FIG. 22, the adjacent m-th frame and the m+1th frame are superimposed. Polar fully achieves the dot inversion mode.
  • the liquid crystal display panel of the dot inversion mode of the present invention adjusts the wiring inside the liquid crystal display panel without changing the power consumption of the source driving: setting n to an even number, and adjacent n-th One gate scan line is disposed adjacent to the nth gate scan line, the n-1th thin film transistor is located above the n-1th gate scan line, and the nth row of thin film transistors are located at the nth Below the gate scan line; the gates of some of the thin film transistors in the n-1th row and the nth row are electrically connected to the n-1th gate scan line, and the gates of some of the thin film transistors are electrically connected to The nth gate scan line; and the processing of the end of the splitter to change the polarity inversion mode of the liquid crystal display panel, realize the dot inversion mode, can solve the problem of flicker and crosstalk of the liquid crystal display panel, and improve the liquid crystal display panel Display quality and improve display.

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Abstract

一种点反转模式的液晶显示面板，在不改变源极驱动功耗的情况下，调整液晶显示面板内部的布线：设n为偶数，将相邻的第n-1条栅极扫描线(G(n-1))与第n条栅极扫描线(G(n))靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线(G(n-1))上方，第n行薄膜晶体管均位于所述第n条栅极扫描线(G(n))下方；第n-1行与第n行中的部分薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线(G(n-1))，部分薄膜晶体管的栅极均电性连接于第n条栅极扫描线(G(n))；并配合分路器(1)末端的处理来改变液晶显示面板的极性反转模式，实现点反转模式，能够解决液晶显示面板闪烁及串扰的问题，提升液晶显示面板的显示质量，改善显示效果。

Description

点反转模式的液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种点反转模式的液晶显示面板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片(Color Filter，CF)基板之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
液晶显示面板包括多个呈阵列式排布的像素。随着显示技术的发展，每一像素从包括红(Red，R)、绿(Green，G)、蓝(Blue，B)三个子像素发展到包括红、绿、蓝、白(White，W)四个子像素，俗称WRGB像素结构。每个子像素电性连接一个薄膜晶体管(TFT)，TFT的栅极(Gate)连接至水平扫描线，漏极(Drain)连接至竖直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条扫描线上的所有TFT打开，从而数据线上的信号电压能够写入子像素，控制液晶的透光度，实现显示效果。
现有的液晶显示面板的驱动方式通常包括：帧反转(Frame Inversion)方式、线反转(Line Inversion)方式和点反转(Dot Inversion)方式。其中，点反转方式是指在一帧画面中，每一子像素与周边相邻的四个子像素的电压极性均相反。点反转方式下，液晶显示面板的闪烁(Flicker)及串扰(Crosstalk)问题最少，显示效果最优。
传统的WRGB像素结构的制程中，为了减小源极驱动器(Source IC)处的引脚(Pin)数以及源极驱动扇出(Fanout)线的数目，往往会设计分路器(Demux)，将一条Fanout线分配给多条数据线(Data line)，通过控制分路器的时序来控制有效显示区内的数据线。但是这样会导致任何一条 Fanout线控制下的多条数据线的极性完全相同，液晶在极性反转的过程中实现的是帧反转模式，这样会导致面板内部的闪烁严重，尤其针对WRGB像素结构，一条Fanout线分配给四条数据线，往往会有串扰明显的现象，影响面板的显示效果。常用的改善做法是将分路器末端进行跳线处理，再将栅极扫描线(Gate Line)的扫描方式由逐行扫描变为先将奇数条的栅极扫描线依次开启，然后再将偶数条栅极扫描线依次开启，这样能改变面板的极性反转模式，但，并非严格意义上的点反转模式。
请参阅图1，传统的液晶显示面板通常将水平的栅极扫描线逐条间隔排列，每相邻两条栅极扫描线的间距相等，设n为正整数，第n行TFT均位于对应的第n条栅极扫描线G(n)的下方。请参阅图2，控制图1所示的各条数据线的分路器1包括四条分路走线11、12、13、14、以及多组控制开关，每组控制开关从左至右包括T100、T200、T300、T400共四个TFT，同一组控制开关的四个TFT的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线2，漏极分别连接一条数据线；相邻两条源极驱动扇出线2的电压极性相反。所述分路器1的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第二TFT T200的漏极跳连至第六条数据线D6，左边一组控制开关的第三TFT T300的漏极跳连至第七条数据线D7，右边一组控制开关的第二TFT T200的漏极跳连至第二条数据线D2，右边一组控制开关的第三TFT T300的漏极跳连至第三条数据线D3。
在图3所示的时序控制下，栅极扫描线逐条扫描，由于受同一条源极驱动扇出线2控制的四条数据线的电压极性相同，上述传统显示面板的显示效果如图4所示，第一、第四、第六、第七列的子像素为正极性，第二、第三、第五、第八列的子像素为负极性。
在图5所示的时序控制下，第m帧先将奇数条的栅极扫描线依次开启，第m+1帧再将偶数条栅极扫描线依次开启，且如图6所示在前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反，则传统显示面板前后相邻两帧画面的叠加显示效果如图7所示，虽然对于在各列像素中实现了点反转，但是对于各行像素并没有实现点反转，并没有实现严格意义上的点反转模式。
发明内容
本发明的目的在于提供一种点反转模式的液晶显示面板，在不改变源极驱动功耗的情况下，通过调整液晶显示面板内部的布线改变液晶显示面板的极性反转模式，实现点反转模式，提升液晶显示面板的显示质量，改 善显示效果。
为实现上述目的，本发明提供一种点反转模式的液晶显示面板。可选的，本发明的点反转模式的液晶显示面板包括多条相互平行且沿横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第二、第七、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第三、第四、第五、第六薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第二、第七、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第三、第四、第五、第六薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极跳连至第七条数据线，第三开关薄膜晶体管的漏极跳连至第六条数据线，第四开关薄膜晶体管的漏极对应连接第四条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极跳连至第三条数据线，第三开关薄膜晶体管的漏极跳连至第二条数据线，第四开关薄膜晶体管的漏极对应连接第八条数据线。
设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
所述子像素包括红、绿、蓝、白四色子像素。
可选的，本发明的点反转模式的液晶显示面板包括多条相互平行且沿 横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第二、第三、第四薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第五、第六、第七、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第二、第三、第四薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第五、第六、第七、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极跳连至第六条数据线，第三开关薄膜晶体管的漏极对应连接第三条数据线，第四开关薄膜晶体管的漏极跳连至第八条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极跳连至第二条数据线，第三开关薄膜晶体管的漏极对应连接第七条数据线，第四开关薄膜晶体管的漏极跳连至第四条数据线。
设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
所述子像素包括红、绿、蓝、白四色子像素。
可选的，本发明的点反转模式的液晶显示面板包括多条相互平行且沿横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第三、第六、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第二、第四、第五、第七薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第三、第六、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第二、第四、第五、第七薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端不做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极对应连接第二条数据线，第三开关薄膜晶体管的漏极对应连接第三条数据线，第四开关薄膜晶体管的漏极对应连接第四条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极对应连接第六条数据线，第三开关薄膜晶体管的漏极对应连接第七条数据线，第四开关薄膜晶体管的漏极对应连接第八条数据线。
设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
所述子像素包括红、绿、蓝、白四色子像素。
本发明的有益效果：本发明提供的一种点反转模式的液晶显示面板，在不改变源极驱动功耗的情况下，通过调整液晶显示面板内部的布线：设n为偶数，将相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；第n-1行与第n行中的部分薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，部分薄膜晶体管的栅极均电性连接于第n条栅极扫描线；并配合分路器末端的处理来改变液晶显示面板的 极性反转模式，实现点反转模式，能够解决液晶显示面板闪烁及串扰的问题，提升液晶显示面板的显示质量，改善显示效果。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种传统的液晶显示面板的布线示意图；
图2为对应于图1的液晶显示面板的分路器的布线示意图；
图3为对应于图1所示液晶显示面板中栅极扫描线逐条扫描的时序图；
图4为传统的液晶显示面板在图3所示时序下的电压极性分布示意图；
图5为对应于图1所示液晶显示面板中栅极扫描线隔条扫描的时序图暨本发明的点反转模式的液晶显示面板的时序图；
图6为对应于图1所示所示液晶显示面板暨本发明的点反转模式的液晶显示面板的相邻两条源极驱动扇出线的电压极性示意图；
图7为图1所示传统液晶显示面板前后相邻两帧画面的叠加显示效果图；
图8为本发明的点反转模式的液晶显示面板第一实施例的布线示意图；
图9为本发明的点反转模式的液晶显示面板第一实施例的分路器的布线示意图；
图10为图8所示液晶显示面板的第m帧画面的电压极性示意图；
图11为图8所示的液晶显示面板的第m+1帧画面的电压极性示意图；
图12为图10与图11所示的相邻两帧画面叠加后的电压极性示意图；
图13为本发明的点反转模式的液晶显示面板第二实施例的布线示意图；
图14为本发明的点反转模式的液晶显示面板第二实施例的分路器的布线示意图；
图15为图13所示的液晶显示面板的第m帧画面的电压极性示意图；
图16为图13所示的液晶显示面板的第m+1帧画面的电压极性示意图；
图17为图15与图16所示的相邻两帧画面叠加后的电压极性示意图；
图18为本发明的点反转模式的液晶显示面板第三实施例的布线示意图；
图19为本发明的点反转模式的液晶显示面板第三实施例的分路器的布 线示意图；
图20为图18所示的液晶显示面板的第m帧画面的电压极性示意图；
图21为图18所示的液晶显示面板的第m+1帧画面的电压极性示意图；
图22为图20与图21所示的相邻两帧画面叠加后的电压极性示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种点反转模式的液晶显示面板。请同时参阅图8与图9，为本发明的点反转模式的液晶显示面板的第一实施例，该第一实施例包括多条相互平行且沿横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器1。
如图8所示，设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线D(s)，例如：第一列薄膜晶体管的源极对应连接第一条数据线D(1)、第二列薄膜晶体管的源极对应连接第二条数据线D(2)，依次类推。
设n为偶数，相邻的第n-1条栅极扫描线G(n-1)与第n条栅极扫描线G(n)靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线G(n-1)上方，第n行薄膜晶体管均位于所述第n条栅极扫描线G(n)下方，例如：第一条栅极扫描线G(1)与第二条栅极扫描线G(2)靠近设置，第一行薄膜晶体管均位于所述第一条栅极扫描线G(1)上方，第二行薄膜晶体管均位于所述第二条栅极扫描线G(2)下方；第三条栅极扫描线G(3)与第四条栅极扫描线G(4)靠近设置，第三行薄膜晶体管均位于所述第三条栅极扫描线G(3)上方，第四行薄膜晶体管均位于所述第四条栅极扫描线G(4)下方，依次类推。
按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8的栅极均电性连接于第n-1条栅极扫描线G(n-1)，而第三、第四、第五、第六薄膜晶体管T3、T4、T5、T6的栅极均电性连接于第n条栅极扫描线G(n)；第n行中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8的栅极均电性连接于第n条栅极扫描线G(n)，而第三、第四、第五、第六薄膜晶体管T3、T4、T5、T6的栅极均电性连接于第n-1条栅极扫描线G(n-1)，例如：第一行中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8的栅极均电性连接于第一条栅极扫描线G(1)，而第三、第四、第五、第六薄膜晶体管 T3、T4、T5、T6的栅极均电性连接于第二条栅极扫描线G(2)；第二行中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8的栅极均电性连接于第二条栅极扫描线G(2)，而第三、第四、第五、第六薄膜晶体管T3、T4、T5、T6的栅极均电性连接于第一条栅极扫描线G(1)，依次类推。
如图9所示，所述分路器1包括第一、第二、第三、第四条分路走线11、12、13、14、以及多组控制开关。每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管T100、T200、T300、T400，同一组控制开关的四个开关薄膜晶体管T100、T200、T300、T400的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线2，漏极分别连接一条数据线，即第一开关薄膜晶体管T100的栅极电性连接第一条分路走线11、第二开关薄膜晶体管T200的栅极电性连接第二条分路走线12、第三开关薄膜晶体管T300的栅极电性连接第三条分路走线13、第四开关薄膜晶体管T400的栅极电性连接第四条分路走线14。相邻两条源极驱动扇出线2的电压极性相反。
所述分路器1的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器1的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第一条数据线D(1)，第二开关薄膜晶体管T200的漏极跳连至第七条数据线D(7)，第三开关薄膜晶体管T300的漏极跳连至第六条数据线D(6)，第四开关薄膜晶体管T400的漏极对应连接第四条数据线D(4)；右边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第五条数据线D(5)，第二开关薄膜晶体管T200的漏极跳连至第三条数据线D(3)，第三开关薄膜晶体管T300的漏极跳连至第二条数据线D(2)，第四开关薄膜晶体管T400的漏极对应连接第八条数据线D(8)。
具体地，所述子像素包括红、绿、蓝、白四色子像素。
该第一实施例在图5所示的时序及图6所示的源极驱动扇出线的电压极性变换条件下工作，设m为正整数，第m帧先将奇数条(G(1)、G(3)、直至G(n-1))的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线(G(2)、G(4)、直至G(n))逐条开启。前后相邻的两帧画面中，同一条源极驱动扇出线2的电压极性相反。那么，由于受同一条源极驱动扇出线2控制的四条数据线的电压极性相同，如图10所示，在第m帧画面中：第n-1行即奇数行薄膜晶体管中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8打开，使得第n-1行子像素中的第一与第七子像素呈正极性，第二与第八子像素呈负极性；同时第n行即偶数行薄膜晶体管中的第三、 第四、第五、第六薄膜晶体管T3、T4、T5、T6打开，使得第n行子像素中的第四与第六子像素呈正极性，第三与第五子像素呈负极性；如图11所示，在第m+1帧画面中：第n行薄膜晶体管中的第一、第二、第七、第八薄膜晶体管T1、T2、T7、T8打开，使得第n行子像素中的第二与第八子像素呈正极性，第一与第七子像素呈负极性；同时第n-1行薄膜晶体管中的第三、第四、第五、第六薄膜晶体管T3、T4、T5、T6打开，使得第n-1行子像素中的第三与第五子像素呈正极性，第四与第六子像素呈负极性；如图12所示，将相邻的第m帧、与第m+1帧这两帧画面叠加后的电压极性完全实现了点反转模式。
请同时参阅图13与图14，为本发明的点反转模式的液晶显示面板的第二实施例，该第二实施例与第一实施例的区别在于：
第n-1行中的第一、第二、第三、第四薄膜晶体管T1、T2、T3、T4的栅极均电性连接于第n-1条栅极扫描线G(n-1)，而第五、第六、第七、第八薄膜晶体管T5、T6、T7、T8的栅极均电性连接于第n条栅极扫描线G(n)；第n行中的第一、第二、第三、第四薄膜晶体管T1、T2、T3、T4的栅极均电性连接于第n条栅极扫描线G(n)，而第五、第六、第七、第八薄膜晶体管T5、T6、T7、T8的栅极均电性连接于第n-1条栅极扫描线G(n-1)；
以及所述分路器1的末端做不同的跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第一条数据线D(1)，第二开关薄膜晶体管T200的漏极跳连至第六条数据线D(6)，第三开关薄膜晶体管T300的漏极对应连接第三条数据线D(3)，第四开关薄膜晶体管T400的漏极跳连至第八条数据线D(8)；右边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第五条数据线D(5)，第二开关薄膜晶体管T200的漏极跳连至第二条数据线D(2)，第三开关薄膜晶体管T300的漏极对应连接第七条数据线D(7)，第四开关薄膜晶体管T400的漏极跳连至第四条数据线D(4)；
其他结构均与第一实施例相同，此处不再进行重复描述。
该第二实施例在图5所示的时序及图6所示的源极驱动扇出线的电压极性变换条件下工作，设m为正整数，第m帧先将奇数条(G(1)、G(3)、直至G(n-1))的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线(G(2)、G(4)、直至G(n))逐条开启。前后相邻的两帧画面中，同一条源极驱动扇出线2的电压极性相反。那么，由于受同一条源极驱动扇出线2控制的四条数据线的电压极性相同，如图15所示，在第m帧画面中：第n-1行即奇数行薄膜晶体管中的第一、第二、第三、第四薄膜晶体管T1、 T2、T3、T4打开，使得第n-1行子像素中的第一与第三子像素呈正极性，第二与第四子像素呈负极性；同时第n行即偶数行薄膜晶体管中的第五、第六、第七、第八薄膜晶体管T5、T6、T7、T8打开，使得第n行子像素中的第六与第八子像素呈正极性，第五与第七子像素呈负极性；如图16所示，在第m+1帧画面中：第n行薄膜晶体管中的第一、第二、第三、第四薄膜晶体管T1、T2、T3、T4打开，使得第n行子像素中的第二与第四子像素呈正极性，第一与第三子像素呈负极性；同时第n-1行薄膜晶体管中的第五、第六、第七、第八薄膜晶体管T5、T6、T7、T8打开，使得第n-1行子像素中的第五与第七子像素呈正极性，第六与第八子像素呈负极性；如图17所示，将相邻的第m帧、与第m+1帧这两帧画面叠加后的电压极性完全实现了点反转模式。
请同时参阅图18与图19，为本发明的点反转模式的液晶显示面板的第三实施例，该第三实施例与第一实施例的区别在于：
第n-1行中的第一、第三、第六、第八薄膜晶体管T1、T3、T6、T8的栅极均电性连接于第n-1条栅极扫描线G(n-1)，而第二、第四、第五、第七薄膜晶体管T2、T4、T5、T7的栅极均电性连接于第n条栅极扫描线G(n)；第n行中的第一、第三、第六、第八薄膜晶体管T1、T3、T6、T8的栅极均电性连接于第n条栅极扫描线G(n)，而第二、第四、第五、第七薄膜晶体管T2、T4、T5、T7的栅极均电性连接于第n-1条栅极扫描线G(n-1)；
以及所述分路器1的末端不做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第一条数据线D(1)，第二开关薄膜晶体管T200的漏极对应连接第二条数据线D(2)，第三开关薄膜晶体管T300的漏极对应连接第三条数据线D(3)，第四开关薄膜晶体管T400的漏极对应连接第四条数据线D(4)；右边一组控制开关的第一开关薄膜晶体管T100的漏极对应连接第五条数据线D(5)，第二开关薄膜晶体管T200的漏极对应连接第六条数据线D(6)，第三开关薄膜晶体管T300的漏极对应连接第七条数据线D(7)，第四开关薄膜晶体管T400的漏极对应连接第八条数据线D(8)。
该第三实施例在图5所示的时序及图6所示的源极驱动扇出线的电压极性变换条件下工作，设m为正整数，第m帧先将奇数条(G(1)、G(3)、直至G(n-1))的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线(G(2)、G(4)、直至G(n))逐条开启。前后相邻的两帧画面中，同一条源极驱动扇出线2的电压极性相反。那么，由于受同一条源极驱动扇出线2控制的四条数据线的电压极性相同，如图20所示，在第m帧画面中： 第n-1行即奇数行薄膜晶体管中的第一、第三、第六、第八薄膜晶体管T1、T3、T6、T8打开，使得第n-1行子像素中的第一与第三子像素呈正极性，第六与第八子像素呈负极性；同时第n行即偶数行薄膜晶体管中的第二、第四、第五、第七薄膜晶体管T2、T4、T5、T7打开，使得第n行子像素中的第二与第四子像素呈正极性，第五与第七子像素呈负极性；如图21所示，在第m+1帧画面中：第n行薄膜晶体管中的第一、第三、第六、第八薄膜晶体管T1、T3、T6、T8打开，使得第n行子像素中的第六与第八子像素呈正极性，第一与第三子像素呈负极性；同时第n-1行薄膜晶体管中的第二、第四、第五、第七薄膜晶体管T2、T4、T5、T7打开，使得第n-1行子像素中的第五与第七子像素呈正极性，第二与第四子像素呈负极性；如图22所示，将相邻的第m帧、与第m+1帧这两帧画面叠加后的电压极性完全实现了点反转模式。
综上所述，本发明的点反转模式的液晶显示面板，在不改变源极驱动功耗的情况下，通过调整液晶显示面板内部的布线：设n为偶数，将相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；第n-1行与第n行中的部分薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，部分薄膜晶体管的栅极均电性连接于第n条栅极扫描线；并配合分路器末端的处理来改变液晶显示面板的极性反转模式，实现点反转模式，能够解决液晶显示面板闪烁及串扰的问题，提升液晶显示面板的显示质量，改善显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

  1. 一种点反转模式的液晶显示面板，包括多条相互平行且沿横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
    设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
    设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第二、第七、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第三、第四、第五、第六薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第二、第七、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第三、第四、第五、第六薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
    所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
    所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极跳连至第七条数据线，第三开关薄膜晶体管的漏极跳连至第六条数据线，第四开关薄膜晶体管的漏极对应连接第四条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极跳连至第三条数据线，第三开关薄膜晶体管的漏极跳连至第二条数据线，第四开关薄膜晶体管的漏极对应连接第八条数据线。
  2. 如权利要求1所述的点反转模式的液晶显示面板，其中，设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
  3. 如权利要求1所述的点反转模式的液晶显示面板，其中，所述子像 素包括红、绿、蓝、白四色子像素。
  4. 一种点反转模式的液晶显示面板，包括多条相互平行且沿横向分布的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
    设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
    设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第二、第三、第四薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第五、第六、第七、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第二、第三、第四薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第五、第六、第七、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
    所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
    所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极跳连至第六条数据线，第三开关薄膜晶体管的漏极对应连接第三条数据线，第四开关薄膜晶体管的漏极跳连至第八条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极跳连至第二条数据线，第三开关薄膜晶体管的漏极对应连接第七条数据线，第四开关薄膜晶体管的漏极跳连至第四条数据线。
  5. 如权利要求4所述的点反转模式的液晶显示面板，其中，设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
  6. 如权利要求4所述的点反转模式的液晶显示面板，其中，所述子像素包括红、绿、蓝、白四色子像素。
  7. 一种点反转模式的液晶显示面板，包括多条相互平行且沿横向分布 的栅极扫描线、多条相互平行且沿纵向分布的数据线、多个呈阵列式排布的用于驱动对应子像素的多个薄膜晶体管、以及分路器；
    设s为正整数，第s列薄膜晶体管的源极均对应连接第s条数据线；
    设n为偶数，相邻的第n-1条栅极扫描线与第n条栅极扫描线靠近设置，第n-1行薄膜晶体管均位于所述第n-1条栅极扫描线上方，第n行薄膜晶体管均位于所述第n条栅极扫描线下方；按照从左至右的方向将同一行薄膜晶体管的每八列作为一组，第n-1行中的第一、第三、第六、第八薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线，而第二、第四、第五、第七薄膜晶体管的栅极均电性连接于第n条栅极扫描线；第n行中的第一、第三、第六、第八薄膜晶体管的栅极均电性连接于第n条栅极扫描线，而第二、第四、第五、第七薄膜晶体管的栅极均电性连接于第n-1条栅极扫描线；
    所述分路器包括第一、第二、第三、第四条分路走线、以及多组控制开关；每组控制开关从左至右包括第一、第二、第三、第四开关薄膜晶体管，同一组控制开关的四个开关薄膜晶体管的栅极分别电性连接一条分路走线，源极共同电性连接一条源极驱动扇出线，漏极分别连接一条数据线；相邻两条源极驱动扇出线的电压极性相反；
    所述分路器的每相邻两组控制开关对应从左至右依次排列的八条数据线；所述分路器的末端不做跳线处理，对于相邻的两组控制开关，左边一组控制开关的第一开关薄膜晶体管的漏极对应连接第一条数据线，第二开关薄膜晶体管的漏极对应连接第二条数据线，第三开关薄膜晶体管的漏极对应连接第三条数据线，第四开关薄膜晶体管的漏极对应连接第四条数据线；右边一组控制开关的第一开关薄膜晶体管的漏极对应连接第五条数据线，第二开关薄膜晶体管的漏极对应连接第六条数据线，第三开关薄膜晶体管的漏极对应连接第七条数据线，第四开关薄膜晶体管的漏极对应连接第八条数据线。
  8. 如权利要求7所述的点反转模式的液晶显示面板，其中，设m为正整数，第m帧先将奇数条的栅极扫描线逐条开启，接下来的第m+1帧再将偶数条栅极扫描线逐条开启；前后相邻的两帧画面中，同一条源极驱动扇出线的电压极性相反。
  9. 如权利要求7所述的点反转模式的液晶显示面板，其中，所述子像素包括红、绿、蓝、白四色子像素。
PCT/CN2016/072649 2015-12-11 2016-01-29 点反转模式的液晶显示面板 WO2017096705A1 (zh)

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