WO2016061856A1 - Tft阵列基板 - Google Patents

Tft阵列基板 Download PDF

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WO2016061856A1
WO2016061856A1 PCT/CN2014/090461 CN2014090461W WO2016061856A1 WO 2016061856 A1 WO2016061856 A1 WO 2016061856A1 CN 2014090461 W CN2014090461 W CN 2014090461W WO 2016061856 A1 WO2016061856 A1 WO 2016061856A1
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sub
pixels
row
numbered
tft
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PCT/CN2014/090461
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English (en)
French (fr)
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陈彩琴
许哲豪
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深圳市华星光电技术有限公司
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Priority to US14/423,974 priority Critical patent/US20160275888A1/en
Publication of WO2016061856A1 publication Critical patent/WO2016061856A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the display panel is an important part of LCD and OLED. Whether it is a display panel of an LCD or a display panel of an OLED, it usually has a thin film transistor (TFT) array substrate.
  • TFT thin film transistor
  • a plurality of R, G, and B sub-pixels arranged in an array, a plurality of scanning lines, and a plurality of data lines are formed on the TFT array substrate.
  • Each sub-pixel receives a scan signal through a corresponding scan line and receives a data signal through a corresponding data line to display an image.
  • FIG. 1 is a schematic view showing the structure of a conventional TFT array substrate.
  • the conventional TFT array substrate includes a plurality of vertical data lines which are parallel to each other and arranged in sequence, such as D1, D2, D3, D4, D5, etc., and a plurality of horizontal scanning lines which are parallel to each other and sequentially arranged, such as G1, G2. , G3, G4, etc., and sub-pixels arranged in an array. Each sub-pixel located in the same row is electrically connected to a scan line located above the sub-pixel of the row through a TFT.
  • each sub-pixel of the first row is electrically connected to the scan line G1 through a TFT
  • each sub-pixel of the second row The pixels are electrically connected to the scan line G2 through a TFT, and so on; each sub-pixel located in the same column is electrically connected to the data line located on the left side of the column sub-pixel through a TFT, for example, each sub-pixel of the first column passes through a The TFT is electrically connected to the data line D1, and each sub-pixel of the second column is electrically connected to the data line D2 through a TFT, and so on.
  • FIG. 2 is a schematic structural view of a conventional TFT array substrate of a Data Line Share (DLS) type.
  • the TFT array substrate of the DLS type has one data line corresponding to every two columns of sub-pixels, and two scanning lines respectively located on the upper and lower sides thereof for each row of sub-pixels.
  • an even-numbered column sub-pixel and an odd-numbered column sub-pixel located on the left and right sides of each data line are electrically connected to the data line by a TFT, that is, the data line is shared.
  • each of the even-numbered sub-pixels is electrically connected to the scan line on the upper side of the row of sub-pixels through a TFT
  • each of the odd-numbered sub-pixels is electrically connected to the row of sub-pixels through a TFT.
  • Side scan line is electrically connected to the scan line on the upper side of the row of sub-pixels through a TFT.
  • each even-numbered column sub-pixel in the first row of sub-pixels is electrically connected to the scan line located on the upper side of the first row of sub-pixels through a TFT G1
  • each odd-numbered column sub-pixel of the first row of sub-pixels is electrically connected to the scan line G2 on the lower side of the first row of sub-pixels through a TFT
  • each of the even-numbered columns of the second row of sub-pixels passes through a TFT electrical
  • Each of the odd-line sub-pixels connected to the scan line G3 and the second row of sub-pixels on the upper side of the second-row sub-pixel is electrically connected to the scan line G4 on the lower side of the second-row sub-pixel by a TFT, and so on.
  • the number of data lines of the DLS type TFT array substrate is halved, which can reduce the cost, but at the same time, the number of scanning lines is doubled, and the charging time of each sub-pixel is reduced because the scanning line is doubled.
  • the signal delay effect of the corresponding data line and scan line tends to have a greater impact.
  • the delay of the data line (scan line) causes the odd column sub-pixel and even column sub-pixel charge rate. The difference results in a display defect of a vertical bright dark line.
  • the driving mode of the data line is two points (2dot) polarity inversion once, due to the influence of the RC delay, the data
  • the signal is not an ideal square wave, and the waveform of the actual data signal should be the arc waveform in Figure 3.
  • Let a sub-pixel be Pxy, x for the xth row, y for the yth column, and P12 subpixels as shown in FIG. 2 for the first row and second column of subpixels.
  • the even-numbered column sub-pixels connected to both sides of each data line are sequentially driven row by row before the odd-numbered column sub-pixels, for example, the sub-pixel P12 connected to the data line D2, P13, P22, P23 are driven in turn.
  • the post-driving sub-pixels are better charged than the first-driven sub-pixels, so P13 is better than P12, P23 is better than P22, and the data signal is very high.
  • the driving order is not changed, and the even-numbered column sub-pixels are driven first, and then the odd-numbered column sub-pixels are driven; that is, for the same row of sub-pixels, the even-numbered column sub-pixels are always driven first, and then the odd-numbered columns of pixels are driven;
  • the even-numbered sub-pixels may have insufficient charging, so that the position corresponding to the even-numbered sub-pixels is insufficient in brightness, and the defects of the vertical bright and dark lines are formed from the overall display effect.
  • An object of the present invention is to provide a TFT array substrate capable of staggering spatially uneven sub-pixels in a display period of the same frame, thereby improving display defects of vertical bright and dark lines; The resistance is reduced, so that the RC delay is reduced, and the mis-filling of the scanning line or the end of the data line is avoided.
  • the present invention provides a TFT array substrate, including: a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels in an array;
  • a pair of sub-pixels located between adjacent two data lines in each row of sub-pixels are flush, each sub-image
  • the adjacent odd-numbered sub-pixels and the even-numbered pair of sub-pixels in the prime are laterally staggered in a plane;
  • Each of the data lines is electrically connected to two sub-pixels on the left and right sides of the data line of each row of sub-pixels, and provides data signals for the two sub-pixels;
  • each row of sub-pixels two scanning lines respectively disposed on the upper and lower sides thereof; the n-th scanning line and the n-th scanning line are respectively located on the upper and lower sides of the n-th row of sub-pixels; the n+1th scanning The line and the n'+1th scan line are respectively located on the upper and lower sides of the n+1th row sub-pixel, n is a positive integer, and the n-th row sub-pixel and the n+1th-row sub-pixel form a repeatable Circuit component unit;
  • the nth scan line is electrically connected through the TFT and drives the even-numbered sub-pixels of the n-th row of sub-pixels, and the n-th scan line is electrically connected through the TFT and drives the odd-numbered sub-pixels of the n-th row of sub-pixels;
  • n+ One scan line is electrically connected through the TFT and drives an odd pair of sub-pixels of the n+1th row of sub-pixels, and the n'+1th scan line is electrically connected through the TFT and drives an even pair of the n+1th row of sub-pixels
  • the pixel thus, the even-numbered sub-pixels in the n-th row of sub-pixels are driven prior to the odd-numbered sub-pixels, and the even-numbered-sub-pixels in the n+1th-row sub-pixels are driven in the odd-numbered sub-pixels.
  • the data line is driven in such a way that the polarity of the two points is reversed once.
  • the n-th row sub-pixel and the n+1th-row sub-pixel are bright and dark interlaced.
  • a TFT array substrate includes: a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels in an array;
  • a pair of sub-pixels between adjacent two data lines in each row of sub-pixels are flush, and adjacent odd-numbered sub-pixels and even-numbered sub-pixels in each row of sub-pixels are laterally staggered in a plane;
  • Each of the data lines is electrically connected to two sub-pixels on the left and right sides of the data line of each row of sub-pixels, and provides data signals for the two sub-pixels;
  • the nth scan line is electrically connected through the TFT and drives the even-numbered sub-pixels of the n-th row of sub-pixels, and the n-th scan line is electrically connected through the TFT and drives the odd-numbered sub-pixels of the n-th row of sub-pixels;
  • n+ One scan line is electrically connected through the TFT and drives an even pair of sub-pixels of the n+1th row of sub-pixels, and the n'+1th scan line is electrically connected through the TFT and drives an odd pair of the n+1th row of sub-pixels a pixel;
  • the n+2th scan line is electrically connected through the TFT and drives an odd pair of the n+2th row of sub-pixels a sub-pixel, the n'+2 scan lines are electrically connected through the TFT and drive the even-numbered sub-pixels of the n+2-row sub-pixel;
  • the n+3th scan line is electrically connected through the TFT and drives the
  • the data line is driven in such a way that the polarity of the two points is reversed once.
  • the nth row, the n+1th row subpixel, and the n+2th row and the n+3th row subpixel are bright. Dark staggered.
  • the invention provides a TFT array substrate.
  • the sub-pixels with uneven spatial and dark brightness are staggered in the display period of the same frame picture, and the vertical direction is improved.
  • the display of the bright and dark lines is defective; and the overall resistance of the data line can be made smaller, the resistance delay is reduced, and the mischarge of the scanning line or the end of the data line is avoided.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic structural view of a conventional DLS type TFT array substrate
  • FIG. 3 is a waveform diagram corresponding to the data signal in FIG. 2;
  • FIG. 4 is a schematic diagram showing a data line driving manner of a TFT array substrate of a DLS type with a polarity reversal of two points;
  • FIG. 5 is a schematic view of a first embodiment of a TFT array substrate of the present invention.
  • FIG. 6 is a schematic view showing a second embodiment of a TFT array substrate of the present invention.
  • FIG. 7 is a diagram showing a light and dark distribution of sub-pixels of a first embodiment of a TFT array substrate of the present invention.
  • Fig. 8 is a view showing a sub-pixel light and dark distribution of a second embodiment of the TFT array substrate of the present invention.
  • FIG. 5 is a schematic diagram of a first embodiment of a TFT array substrate of the present invention.
  • the TFT array substrate includes a plurality of data lines, such as D1, D2, D3, D4, D5, D6, D7, etc., a plurality of scan lines, and a plurality of sub-pixels in an array.
  • a pair of sub-pixels between adjacent two data lines in each row of sub-pixels are flush, and adjacent odd-numbered sub-pixels and even-numbered sub-pixels in each row of sub-pixels are laterally staggered in a plane.
  • Each of the data lines is electrically connected to two sub-pixels on the left and right sides of the data line of each of the sub-pixels through the TFT, and provides data signals for the two sub-pixels.
  • n-th scanning line G(n) and the n-th scanning line G(n') are respectively located in the n-th row of sub-pixels P ( The upper and lower sides of n); the n+1th scanning line G(n+1) and the n'+1th scanning line G(n'+1) are respectively located in the n+1th row sub-pixel P(n) +1) on the upper and lower sides, n is a positive integer, and the nth row of subpixels P(n) and the n+1th row of subpixels P(n+1) form a repeatable circuit component, That is, the entire circuit can be formed by repeatedly setting the circuit constituent unit.
  • the first row of sub-pixels and the second row of sub-pixels form a circuit constituent unit
  • the third row and the fourth row of sub-pixels form a repeated circuit constituent unit, and so on.
  • the nth scanning line G(n) is electrically connected through the TFT and drives the even pair of sub-pixels of the nth row of sub-pixels P(n), and the nthth scanning line G(n') is electrically connected and driven by the TFT.
  • An odd-numbered pair of sub-pixels of the n-th sub-pixel P(n); the n+1th scan line G(n+1) is electrically connected through the TFT and drives an odd pair of the n+1th row of sub-pixels P(n+1)
  • the sub-pixel, the n'thth scan line G(n'+1) is electrically connected through the TFT and drives the even-numbered sub-pixels of the n+1th row of sub-pixels.
  • the even-numbered sub-pixels in the n-th row sub-pixel P(n) are driven before the odd-numbered sub-pixels, thereby charging the odd-numbered sub-pixels in the n-th row of sub-pixels
  • the effect is better than the even-numbered sub-pixel charging effect, such that the odd-numbered sub-pixels in the n-th row of sub-pixels are brighter and the even-numbered sub-pixels are darker; and the n+1th-row sub-pixels P(n+1)
  • the even-numbered sub-pixels are driven by the odd-numbered sub-pixels, so that the even-numbered sub-pixels in the n+1th-row sub-pixel are better charged than the odd-numbered sub-pixels, so that the n+1th row of sub-pixels
  • the odd number in the sub-pixel is darker and the even-numbered sub-pixel is brighter.
  • the driving method of the data line is that the polarity of the two points is reversed once. After the polarity of the data signal is inverted, the driving sequence is not changed, and finally, each of the adjacent two data lines can be made in the same frame picture display period.
  • the n-th row sub-pixel P(n) and the n+1-th row sub-pixel P(n+1) are bright and dark interlaced as shown in FIG. From the overall display effect, the sub-pixels with uneven spatial and darkness can be staggered, which improves the display defects of the vertical bright and dark lines; and can reduce the overall resistance of the data line, reduce the resistance delay, and avoid The mis-filling at the end of the scan line or data line appears.
  • FIG. 6 is a schematic diagram of a second embodiment of a TFT array substrate of the present invention.
  • the TFT array substrate includes a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels in an array.
  • a pair of sub-pixels between adjacent two data lines in each row of sub-pixels are flush, and adjacent odd-numbered sub-pixels and even-numbered sub-pixels in each row of sub-pixels are laterally staggered in a plane.
  • Each of the data lines is electrically connected to two sub-pixels on the left and right sides of the data line of each of the sub-pixels through the TFT, and provides data signals for the two sub-pixels.
  • n is a positive integer
  • n is a positive integer
  • P(n+2) and the n+3th row of sub-pixels P(n+3) form a repeatable circuit constituent unit, that is, the entire circuit can be formed by repeatedly setting circuit constituent units, for example, the first row and the second row.
  • the third row and the fourth row of sub-pixels form a circuit component unit, and the fifth row, the sixth row, the seventh row, and the eighth row of sub-pixels form a repeated circuit constituent unit, and so on.
  • the nth scanning line G(n) is electrically connected through the TFT and drives the even pair of sub-pixels of the nth row of sub-pixels P(n), and the nthth scanning line G(n') is electrically connected and driven by the TFT.
  • the n+1th scan line G(n+1) is electrically connected through the TFT and drives an even pair of the n+1th-row sub-pixel P(n+1)
  • the n'th scan line G(n'+1) is electrically connected through the TFT and drives the odd-numbered sub-pixels of the n+1th row sub-pixel P(n+1);
  • the even-numbered sub-pixels in the n-th row and the n-th-th row sub-pixels P(n), P(n+1) are driven before the odd-numbered sub-pixels, thereby
  • the charging effect of the odd-numbered sub-pixels in the n-th row and the n-th-th row sub-pixels P(n), P(n+1) is better than that of the even-numbered sub-pixels, so that the nth row and the n+th
  • the odd-numbered sub-pixels of the 1-row sub-pixels P(n) and P(n+1) are brighter, and the even-numbered sub-pixels are darker; and the n+2th row and the n+3th row of sub-pixels P(n+2) ,
  • the even-numbered sub-pixels in P(n+3) are driven by the odd-numbered sub-pixels, so that the n+2th row, the n+3th row of sub-pixels P(n+3)
  • the driving method of the data line is that the polarity of the two points is reversed once. After the polarity of the data signal is inverted, the driving sequence is not changed, and finally, each of the adjacent two data lines can be made in the same frame picture display period.
  • the nth row, the n+1th row sub-pixel P(n), P(n+1) and the n+2th row, the n+3th row sub-pixel P(n+2), P (n+3) is bright and dark, as shown in Figure 8.
  • the sub-pixels with uneven spatial and darkness can be staggered, which improves the display defects of the vertical bright and dark lines; and can reduce the overall resistance of the data line, reduce the resistance delay, and avoid The mis-filling at the end of the scan line or data line appears.
  • the TFT array substrate of the present invention improves the display of vertical bright and dark lines by changing the arrangement of sub-pixels so that sub-pixels with uneven spatial and darkness are interleaved in the display period of the same frame. Defects; and can make the overall resistance of the data line smaller, reduce the RC delay, and avoid the mischarge of the scan line or the end of the data line.

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Abstract

提供一种TFT阵列基板，该TFT阵列基板通过改变子像素的排列方式，使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且可以使数据线整体电阻变小，减小阻容延迟，避免了扫描线或者数据线末端的错充显现。

Description

TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示器已经逐步取代CRT显示器，广泛的应用于液晶电视、手机、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等。
显示面板是LCD、OLED的重要组成部分。不论是LCD的显示面板，还是OLED的显示面板，通常具有一薄膜晶体管(Thin Film Transistor，TFT)阵列基板。此TFT阵列基板上形成有多个呈阵列式排布的R、G、B子像素、多条扫描线、及多条数据线。每一子像素分别通过对应的扫描线来接收扫描信号、通过对应的数据线来接收数据信号，以显示影像。
图1所示为传统的TFT阵列基板的结构示意图。该传统的TFT阵列基板包括多条相互平行并依次排列的竖直的数据线，如D1、D2、D3、D4、D5等，多条相互平行并依次排列的水平的扫描线，如G1、G2、G3、G4等，及呈阵列式排布的子像素。位于同一行的每个子像素均通过一TFT电性连接于位于该行子像素上方的扫描线，例如第一行的每个子像素通过一TFT电性连接于扫描线G1，第二行的每个子像素通过一TFT电性连接于扫描线G2，依次类推；位于同一列的每个子像素均通过一TFT电性连接于位于该列子像素左侧的数据线，例如第一列的每个子像素通过一TFT电性连接于数据线D1，第二列的每个子像素通过一TFT电性连接于数据线D2，依次类推。
图2所示为现有的共用数据线(Data Line Share，DLS)类型的TFT阵列基板的结构示意图。该DLS类型的TFT阵列基板，对应每两列子像素设置一条数据线，对应每一行子像素设置分别位于其上、下两侧的两条扫描线。在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于该条数据线，即共用该条数据线。同时，在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线。例如，第二列与第三列子像素共用数 据线D2、第四列与第五列子像素共用数据线D3，依次类推；第一行子像素中的每一偶数列子像素通过一TFT电性连接于位于第一行子像素上侧的扫描线G1、第一行子像素中的每一奇数列子像素通过一TFT电性连接于第一行子像素下侧的扫描线G2；第二行子像素中的每一偶数列子像素通过一TFT电性连接于位于第二行子像素上侧的扫描线G3、第二行子像素中的每一奇数列子像素通过一TFT电性连接于第二行子像素下侧的扫描线G4，依次类推。相比于图1中传统的TFT阵列基板，该DLS类型的TFT阵列基板的数据线数目减半，能够减少成本，但同时扫描线数目加倍，每一子像素的充电时间因为扫描线加倍而减少了一半，因此相应数据线和扫描线的信号延迟效应往往会影响更大，例如，在数据线(扫描线)尾端，数据线(扫描线)延迟会造成奇数列子像素与偶数列子像素充电率差异，导致产生竖直亮暗线的显示缺陷。
具体的，请同时参阅图2、图3、图4，如图4所示，数据线的驱动方式为两点(2dot)极性反转一次，由于阻容延迟(RC Delay)的影响，数据信号并非理想方波，实际数据信号的波形应该为图3中的弧线波形。设一子像素为Pxy，x代表第x行，y代表第y列，如图2中的P12子像素代表第一行第二列子像素。当扫描线G1、G2、G3、G4等依次打开时，连接于每一数据线两侧的偶数列子像素先于奇数列子像素被逐行依次驱动，例如连接于数据线D2上的子像素P12、P13、P22、P23依次被驱动，在数据信号同一极性周期内，后驱动的子像素总比先驱动的子像素充电更好，这样P13比P12充电好，P23比P22充电好，数据信号极性反转后，驱动顺序未改变，依然是先驱动偶数列子像素，后驱动奇数列子像素；也就是对于同一行子像素，总是先驱动偶数列子像素，后驱动奇数列像素；那么先驱动的偶数列子像素可能有充电不足现象，使偶数列子像素对应的位置亮度不足，从整体的显示效果来看便形成了竖直亮暗线的缺陷。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且由于数据线整体电阻变小，使得阻容延迟减小，避免了扫描线或者数据线末端的错充显现。
为实现上述目的，本发明提供一种TFT阵列基板，包括：多条数据线、多条扫描线、及呈阵列式的多个子像素；
每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像 素中相邻的奇数对子像素与偶数对子像素在平面上横向错开；
每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号；
对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线和第n’条扫描线分别位于第n行子像素的上下两侧；第n+1条扫描线和第n’+1条扫描线分别位于第n+1行子像素的上、下两侧，n为正整数，且使第n行子像素与第n+1行子像素形成一个可重复的电路组成单元；
第n条扫描线通过TFT电性连接并驱动第n行子像素的偶数对子像素，第n’条扫描线通过TFT电性连接并驱动第n行子像素的奇数对子像素；第n+1条扫描线通过TFT电性连接并驱动第n+1行子像素的奇数对子像素，第n’+1条扫描线通过TFT电性连接并驱动第n+1行子像素的偶数对子像素；从而第n行子像素中的偶数对子像素先于奇数对子像素被驱动，第n+1行子像素中的偶数对子像素后于奇数对子像素被驱动。
数据线的驱动方式为两点极性反转一次。
同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行子像素与第n+1行子像素亮、暗交错。
一种TFT阵列基板，包括：多条数据线、多条扫描线、及呈阵列式的多个子像素；
每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开；
每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号；
对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线和第n’条扫描线分别位于第n行子像素的上、下两侧；第n+1条扫描线和第n’+1条扫描线分别位于第n+1行子像素的上、下两侧；第n+2条扫描线和第n’+2条扫描线分别位于第n+2行子像素的上、下两侧；第n+3条扫描线和第n’+3条扫描线分别位于第n+3行子像素的上、下两侧，n为正整数，且使第n行子像素、第n+1行子像素、第n+2行子像素及第n+3行子像素形成一个可重复的电路组成单元；
第n条扫描线通过TFT电性连接并驱动第n行子像素的偶数对子像素，第n’条扫描线通过TFT电性连接并驱动第n行子像素的奇数对子像素；第n+1条扫描线通过TFT电性连接并驱动第n+1行子像素的偶数对子像素，第n’+1条扫描线通过TFT电性连接并驱动第n+1行子像素的奇数对子像素；第n+2条扫描线通过TFT电性连接并驱动第n+2行子像素的奇数对 子像素，第n’+2条扫描线通过TFT电性连接并驱动第n+2行子像素的偶数对子像素；第n+3条扫描线通过TFT电性连接并驱动第n+3行子像素的奇数对子像素，第n’+3条扫描线通过TFT电性连接并驱动第n+3行子像素的偶数对子像素；从而第n行、第n+1行子像素中的偶数对子像素先于奇数对子像素被驱动；第n+2行、第n+3行子像素中的偶数对子像素后于奇数对子像素被驱动。
数据线的驱动方式为两点极性反转一次。
同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行、第n+1行子像素与第n+2行、第n+3行子像素亮、暗交错。
本发明的有益效果：本发明提供的一种TFT阵列基板，通过改变子像素的排列方式，使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且可以使数据线整体电阻变小，减小阻容延迟，避免了扫描线或者数据线末端的错充显现。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为传统的TFT阵列基板的结构示意图；
图2为现有的DLS类型的TFT阵列基板的结构示意图；
图3为对应图2中数据信号的波形示意图；
图4为反映DLS类型的TFT阵列基板的数据线驱动方式为两点极性反转一次的示意图；
图5为本发明的TFT阵列基板的第一种实施方式的示意图；
图6为本发明的TFT阵列基板的第二种实施方式的示意图；
图7为本发明的TFT阵列基板的第一种实施方式的子像素亮、暗分布图；
图8为本发明的TFT阵列基板的第二种实施方式的子像素亮、暗分布图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5，为本发明的TFT阵列基板的第一种实施方式的示意图。 该TFT阵列基板包括：多条数据线、如D1、D2、D3、D4、D5、D6、D7等，多条扫描线，及呈阵列式的多个子像素。
每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开。
每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号。
对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线G(n)和第n’条扫描线G(n’)分别位于第n行子像素P(n)的上、下两侧；第n+1条扫描线G(n+1)和第n’+1条扫描线G(n’+1)分别位于第n+1行子像素P(n+1)的上、下两侧，n为正整数，且使第n行子像素P(n)与第n+1行子像素P(n+1)形成一个可重复的电路组成单元，也就是通过重复设置电路组成单元可以形成整个电路，例如第1行子像素与第2行子像素形成一电路组成单元，第3行与第4行子像素形成一重复的电路组成单元，依次类推。
第n条扫描线G(n)通过TFT电性连接并驱动第n行子像素P(n)的偶数对子像素，第n’条扫描线G(n’)通过TFT电性连接并驱动第n行子像素P(n)的奇数对子像素；第n+1条扫描线G(n+1)通过TFT电性连接并驱动第n+1行子像素P(n+1)的奇数对子像素，第n’+1条扫描线G(n’+1)通过TFT电性连接并驱动第n+1行子像素的偶数对子像素。
当扫描线自上而下依次打开时，第n行子像素P(n)中的偶数对子像素先于奇数对子像素被驱动，从而该第n行子像素中的奇数对子像素的充电效果要好于偶数对子像素的充电效果，使得该第n行子像素中的奇数对子像素较亮、偶数对子像素较暗；而第n+1行子像素P(n+1)中的偶数对子像素后于奇数对子像素被驱动，从而该第n+1行子像素中的偶数对子像素的充电效果要好于奇数对子像素的充电效果，使得该第n+1行子像素中的奇数对子像素较暗、偶数对子像素较亮。
数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变，最终能够使得在同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行子像素P(n)与第n+1行子像素P(n+1)亮、暗交错，如图7所示。从整体的显示效果来看，能够将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且可以使数据线整体电阻变小，减小阻容延迟，避免了扫描线或者数据线末端的错充显现。
请参阅图6，为本发明的TFT阵列基板的第二种实施方式的示意图。 该TFT阵列基板包括：多条数据线、多条扫描线、及呈阵列式的多个子像素。
每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开。
每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号。
对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线G(n)和第n’条扫描线G(n’)分别位于第n行子像素P(n)的上、下两侧；第n+1条扫描线G(n+1)和第n’+1条扫描线G(n’+1)分别位于第n+1行子像素P(n+1)的上、下两侧；第n+2条扫描线G(n+2)和第n’+2条扫描线G(n’+2)分别位于第n+2行子像素P(n+2)的上、下两侧；第n+3条扫描线G(n+3)和第n’+3条扫描线G(n’+3)分别位于第n+3行子像素P(n+3)的上、下两侧，n为正整数，且使第n行子像素P(n)、第n+1行子像素P(n+1)、第n+2行子像素P(n+2)及第n+3行子像素P(n+3)形成一个可重复的电路组成单元，也就是通过重复设置电路组成单元可以形成整个电路，例如第1行、第2行、第3行及第4行子像素形成一电路组成单元，第5行、第6行、第7行及第8行子像素形成一重复的电路组成单元，依次类推。
第n条扫描线G(n)通过TFT电性连接并驱动第n行子像素P(n)的偶数对子像素，第n’条扫描线G(n’)通过TFT电性连接并驱动第n行子像素P(n)的奇数对子像素；第n+1条扫描线G(n+1)通过TFT电性连接并驱动第n+1行子像素P(n+1)的偶数对子像素，第n’+1条扫描线G(n’+1)通过TFT电性连接并驱动第n+1行子像素P(n+1)的奇数对子像素；第n+2条扫描线G(n+2)通过TFT电性连接并驱动第n+2行子像素P(n+2)的奇数对子像素，第n’+2条扫描线G(n’+2)通过TFT电性连接并驱动第n+2行子像素P(n+2)的偶数对子像素；第n+3条扫描线G(n+3)通过TFT电性连接并驱动第n+3行子像素P(n+3)的奇数对子像素，第n’+3条扫描线G(n’+3)通过TFT电性连接并驱动第n+3行子像素P(n+3)的偶数对子像素。
当扫描线自上而下依次打开时，第n行、第n+1行子像素P(n)、P(n+1)中的偶数对子像素先于奇数对子像素被驱动，从而该第n行、第n+1行子像素P(n)、P(n+1)中的奇数对子像素的充电效果要好于偶数对子像素的充电效果，使得该第n行、第n+1行子像素P(n)、P(n+1)的奇数对子像素较亮、偶数对子像素较暗；而第n+2行、第n+3行子像素P(n+2)、 P(n+3)中的偶数对子像素后于奇数对子像素被驱动，从而该第n+2行、第n+3行子像素P(n+2)、P(n+3)中的偶数对子像素的充电效果要好于奇数对子像素的充电效果，使得该第n+2行、第n+3子像素P(n+2)、P(n+3)中的奇数对子像素较暗、偶数对子像素较亮。
数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变，最终能够使得在同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行、第n+1行子像素P(n)、P(n+1)与第n+2行、第n+3行子像素P(n+2)、P(n+3)亮、暗交错，如图8所示。从整体的显示效果来看，能够将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且可以使数据线整体电阻变小，减小阻容延迟，避免了扫描线或者数据线末端的错充显现。
综上所述，本发明的TFT阵列基板，通过改变子像素的排列方式，使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷；且可以使数据线整体电阻变小，减小阻容延迟，避免了扫描线或者数据线末端的错充显现。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (7)

  1. 一种TFT阵列基板，包括：多条数据线、多条扫描线、及呈阵列式的多个子像素；
    每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开；
    每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号；
    对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线和第n’条扫描线分别位于第n行子像素的上下两侧；第n+1条扫描线和第n’+1条扫描线分别位于第n+1行子像素的上、下两侧，n为正整数，且使第n行子像素与第n+1行子像素形成一个可重复的电路组成单元；
    第n条扫描线通过TFT电性连接并驱动第n行子像素的偶数对子像素，第n’条扫描线通过TFT电性连接并驱动第n行子像素的奇数对子像素；第n+1条扫描线通过TFT电性连接并驱动第n+1行子像素的奇数对子像素，第n’+1条扫描线通过TFT电性连接并驱动第n+1行子像素的偶数对子像素；从而第n行子像素中的偶数对子像素先于奇数对子像素被驱动，第n+1行子像素中的偶数对子像素后于奇数对子像素被驱动。
  2. 如权利要求1所述的TFT阵列基板，其中，数据线的驱动方式为两点极性反转一次。
  3. 如权利要求1所述的TFT阵列基板，其中，同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行子像素与第n+1行子像素亮、暗交错。
  4. 一种TFT阵列基板，包括：多条数据线、多条扫描线、及呈阵列式的多个子像素；
    每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开；
    每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号；
    对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线和第n’条扫描线分别位于第n行子像素的上、下两侧；第n+1条扫描线和第n’+1条扫描线分别位于第n+1行子像素的上、下两侧；第n+2条扫描线和第n’+2条扫描线分别位于第n+2行子像素的上、下两侧；第n+3 条扫描线和第n’+3条扫描线分别位于第n+3行子像素的上、下两侧，n为正整数，且使第n行子像素、第n+1行子像素、第n+2行子像素及第n+3行子像素形成一个可重复的电路组成单元；
    第n条扫描线通过TFT电性连接并驱动第n行子像素的偶数对子像素，第n’条扫描线通过TFT电性连接并驱动第n行子像素的奇数对子像素；第n+1条扫描线通过TFT电性连接并驱动第n+1行子像素的偶数对子像素，第n’+1条扫描线通过TFT电性连接并驱动第n+1行子像素的奇数对子像素；第n+2条扫描线通过TFT电性连接并驱动第n+2行子像素的奇数对子像素，第n’+2条扫描线通过TFT电性连接并驱动第n+2行子像素的偶数对子像素；第n+3条扫描线通过TFT电性连接并驱动第n+3行子像素的奇数对子像素，第n’+3条扫描线通过TFT电性连接并驱动第n+3行子像素的偶数对子像素；从而第n行、第n+1行子像素中的偶数对子像素先于奇数对子像素被驱动；第n+2行、第n+3行子像素中的偶数对子像素后于奇数对子像素被驱动。
  5. 如权利要求4所述的TFT阵列基板，其中，数据线的驱动方式为两点极性反转一次。
  6. 如权利要求4所述的TFT阵列基板，其中，同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行、第n+1行子像素与第n+2行、第n+3行子像素亮、暗交错。
  7. 一种TFT阵列基板，包括：多条数据线、多条扫描线、及呈阵列式的多个子像素；
    每行子像素中位于相邻两条数据线之间的一对子像素平齐，每行子像素中相邻的奇数对子像素与偶数对子像素在平面上横向错开；
    每条数据线分别通过TFT与每行子像素中位于该条数据线左、右两侧的两个子像素形成电性连接，并为该两个子像素提供数据信号；
    对应每一行子像素设置分别位于其上、下两侧的两条扫描线；第n条扫描线和第n’条扫描线分别位于第n行子像素的上下两侧；第n+1条扫描线和第n’+1条扫描线分别位于第n+1行子像素的上、下两侧，n为正整数，且使第n行子像素与第n+1行子像素形成一个可重复的电路组成单元；
    第n条扫描线通过TFT电性连接并驱动第n行子像素的偶数对子像素，第n’条扫描线通过TFT电性连接并驱动第n行子像素的奇数对子像素；第n+1条扫描线通过TFT电性连接并驱动第n+1行子像素的奇数对子像素，第n’+1条扫描线通过TFT电性连接并驱动第n+1行子像素的偶数对子像素；从而第n行子像素中的偶数对子像素先于奇数对子像素被驱动，第n+1 行子像素中的偶数对子像素后于奇数对子像素被驱动；
    其中，数据线的驱动方式为两点极性反转一次；
    其中，同一帧画面显示周期内，位于相邻两条数据线之间的每一对列子像素中，第n行、第n+1行子像素与第n+2行、第n+3行子像素亮、暗交错。
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