WO2017073097A1 - 薄膜トランジスタ基板およびその製造方法 - Google Patents
薄膜トランジスタ基板およびその製造方法 Download PDFInfo
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- WO2017073097A1 WO2017073097A1 PCT/JP2016/062298 JP2016062298W WO2017073097A1 WO 2017073097 A1 WO2017073097 A1 WO 2017073097A1 JP 2016062298 W JP2016062298 W JP 2016062298W WO 2017073097 A1 WO2017073097 A1 WO 2017073097A1
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Images
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Definitions
- the present invention relates to a thin film transistor substrate used for a liquid crystal display device or the like.
- An electro-optical device such as a liquid crystal display (Liquid Crystal Display: hereinafter referred to as “LCD”) is a thin film transistor substrate (hereinafter referred to as “TFT substrate”) using a thin film transistor (hereinafter referred to as “TFT”) as a switching device. Name).
- LCD Liquid Crystal Display
- TFT substrate thin film transistor substrate
- TFT thin film transistor
- TFTs Semiconductor devices such as TFTs are characterized by low power consumption and thinness. Therefore, taking advantage of the characteristics of such semiconductor devices, it has been replaced with CRT (Cathode Ray Tube) and applied to flat panel displays.
- CRT Cathode Ray Tube
- a liquid crystal layer is generally provided between a TFT substrate and a counter substrate.
- TFTs are arranged in a matrix on the TFT substrate.
- Polarizing plates are provided outside the TFT substrate and the counter substrate, respectively.
- a backlight unit is provided outside the TFT substrate or the counter electrode.
- a color display LCD for example, a color filter of one color or two or more colors is provided on a counter substrate.
- FIG. 1 A typical structure of a TFT TFT substrate is disclosed in FIG.
- the TFT substrate has a bottom-gate back channel TFT, and a pixel electrode electrically connected to the TFT is formed in the uppermost layer.
- This structure can be manufactured using five photolithography processes (a photolithography process).
- amorphous silicon Si
- channel layer a semiconductor active layer
- a zinc oxide (ZnO) -based material a material obtained by adding gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), or the like to zinc oxide is mainly used. It has been. This technique is disclosed in Patent Documents 2 and 3, for example.
- hydrogen in the channel layer causes structural disorder when it exists between lattices, and degrades TFT characteristics such as mobility. Further, hydrogen in the channel layer is supposed to work as an electron donor, and in that case, the carrier density contributing to the characteristics increases. On the other hand, when hydrogen terminates the dangling bonds of the channel layer, the carrier density decreases. Also, when hydrogen diffuses from other layers to the channel layer during TFT operation, one of the above phenomena occurs and the characteristics fluctuate. Thus, hydrogen in the channel layer affects the initial characteristics and reliability of the TFT.
- Patent Document 4 discloses a technique for improving TFT characteristics by controlling the release and diffusion of hydrogen and oxygen by a total of three heat treatments during the manufacturing process. This is because excess hydrogen in the channel layer is removed by the first heat treatment after forming the channel layer, and oxygen is then removed by the second heat treatment after forming an insulating film containing oxygen above the channel layer. Oxygen is supplied from the insulating film containing hydrogen to the channel layer to reduce oxygen vacancies, and then the insulating film containing hydrogen is formed over the insulating film containing oxygen, and then the third heat treatment is performed on the channel layer from the insulating layer containing hydrogen. Hydrogen is supplied to the substrate to terminate defects or dangling bonds, thereby increasing on-current and mobility.
- Patent Document 4 an insulating film containing hydrogen is formed on an insulating film containing oxygen, and the insulating film is used as a hydrogen supply source.
- the amount of hydrogen in the insulating film is large, Hydrogen is excessively supplied to the channel layer.
- the threshold voltage defined as the voltage when the drain current becomes 1 ⁇ 10 ⁇ 10 A is from ⁇ 10V It is known that it cannot be turned off with a practical voltage. For this reason, in the configuration of the cited document 4, when hydrogen is excessively supplied from the insulating film as a hydrogen supply source to the channel layer and works as an electron donor, the carrier density becomes high and normal TFT operation cannot be performed.
- the present invention has been made to solve the above-described problems, and suppresses hydrogen diffusion to the channel layer during manufacture of the TFT array substrate and during TFT operation, thereby limiting the hydrogen concentration in the channel layer.
- An object of the present invention is to provide a thin film transistor substrate having a thin film transistor excellent in initial characteristics and reliability.
- An aspect of a thin film transistor substrate according to the present invention is a thin film transistor substrate in which a plurality of pixels are arranged in a matrix, and the pixel includes a gate electrode made of metal disposed on the substrate, and at least the gate electrode.
- a thin film transistor having at least the semiconductor layer, an interlayer insulating film provided on the source electrode and the drain electrode, and a pixel electrode electrically connected to the drain electrode; .5 ⁇ 10 20 atoms / cm 3 ⁇ 2 ⁇ has 10 22 atoms / cm 3 of hydrogen absorbing ability, the semiconductor layer ,
- the hydrogen concentration is 1 ⁇ 10 16 atoms / cm 3 ⁇ 3 ⁇ 10 20 atoms / cm 3.
- the gate electrode since the gate electrode has a hydrogen storage capability, the hydrogen diffused from the other layer to the gate electrode during the heat treatment during the manufacturing process is taken in and held on the surface or inside, and the hydrogen concentration in the semiconductor layer is reduced. From 1 ⁇ 10 16 atoms / cm 3 to 3 ⁇ 10 20 atoms / cm 3 , the carrier density is 1 ⁇ 10 11 atoms / cm 3 to 1 ⁇ 10 16 atoms / cm 3 , and the threshold voltage of the thin film transistor is practical Thus, a thin film transistor having excellent off characteristics is obtained.
- the TFT substrate according to the first embodiment will be described as an active matrix substrate in which a thin film transistor is used as a switching device.
- FIG. 1 is a plan view schematically illustrating the entire configuration of the TFT substrate of Embodiment 1 according to the present invention.
- a TFT TFT substrate is taken as an example.
- a TFT substrate 200 shown in FIG. 1 is a TFT array substrate in which pixel TFTs 201 are arranged in a matrix, and is roughly divided into a display region 202 and a frame region 203 provided so as to surround the display region 202.
- a plurality of gate lines (scanning signal lines) 103, a plurality of auxiliary capacitance lines 105, and a plurality of source lines (display signal lines) 101 are arranged, and the plurality of gate lines 103 are arranged in parallel to each other.
- the plurality of source lines 101 are arranged in parallel to each other so as to intersect with the plurality of gate lines 103 at right angles.
- the gate wiring 103 is disposed so as to extend in the horizontal direction (X direction), and the source wiring 101 is disposed so as to extend in the vertical direction (Y direction).
- the TFT substrate 200 Since the region surrounded by the two adjacent gate wirings 103 and the two adjacent source wirings 101 becomes the pixel 204, the TFT substrate 200 has a configuration in which the pixels 204 are arranged in a matrix.
- FIG. 1 the configuration of some of the pixels 204 is shown enlarged, and at least one pixel TFT 201 is disposed in the pixel 204.
- the pixel TFT 201 is disposed near the intersection of the source wiring 101 and the gate wiring 103, the gate electrode of the pixel TFT 201 is connected to the gate wiring 103, the source electrode of the pixel TFT 201 is connected to the source wiring 101, and the drain electrode of the pixel TFT 201 is transmissive. It is connected to the pixel electrode 17. Further, an auxiliary capacitor 209 is connected to the transmissive pixel electrode 17, and the auxiliary capacitor line 105 provided in parallel with each of the plurality of gate lines 103 also serves as the auxiliary capacitor electrode.
- the gate wiring 103 and the auxiliary capacitance wiring 105 are alternately arranged, and the auxiliary capacitance wiring 105 and the source wiring 101 are arranged so as to cross at right angles to each other.
- a scanning signal driving circuit 205 and a display signal driving circuit 206 are provided in the frame region 203 of the TFT substrate 200.
- the gate wiring 103 extends from the display area 202 to the frame area 203 on the side where the scanning signal driving circuit 205 is provided.
- the gate wiring 103 is connected to the scanning signal driving circuit 205 at the end of the TFT substrate 200. Has been.
- the source wiring 101 extends from the display area 202 to the frame area 203 on the side where the display signal driving circuit 206 is provided.
- the source wiring 101 is connected to the display signal driving circuit 206 at the end of the TFT substrate 200. It is connected.
- connection board 207 is disposed in the vicinity of the scanning signal drive circuit 205
- an external connection board 208 is disposed in the vicinity of the display signal drive circuit 206.
- the connection boards 207 and 208 are wiring boards such as FPC (Flexible Printed Circuit).
- the scanning signal driving circuit 205 supplies a gate signal (scanning signal) to the gate wiring 103 based on an external control signal.
- the gate wiring 103 is sequentially selected by this gate signal.
- the display signal driving circuit 206 supplies a display signal to the source wiring 101 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 204.
- the scanning signal driving circuit 205 and the display signal driving circuit 206 are not limited to the configuration arranged on the TFT substrate 200.
- a driving circuit is configured by TCP (Tape Carrier Carrier) and the TFT substrate 200 May be arranged in another part.
- auxiliary capacitance wiring 105 is configured to partially overlap (superimpose) in plan view with the transmissive pixel electrode 17 as will be described later with reference to a plan view.
- a storage capacitor 209 is formed using a part of the storage capacitor wiring 105 as the other electrode. Note that a portion of the auxiliary capacitance wiring 105 that overlaps the transmissive pixel electrode 17 is referred to as an auxiliary capacitance electrode. All the auxiliary capacitance lines 105 are electrically bundled outside the display area, and a common potential is supplied from the display signal driving circuit 206, for example.
- the pixel TFT 201 functions as a switching device for supplying a display voltage to the transmissive pixel electrode 17, and ON / OFF of the pixel TFT 201 is controlled by a gate signal input from the gate wiring 103. Then, when a predetermined voltage is applied to the gate wiring 103 and the pixel TFT 201 is turned on, a current flows from the source wiring 101. As a result, a display voltage is applied from the source line 101 to the transmissive pixel electrode 17 connected to the drain electrode of the pixel TFT 201, and the display voltage corresponds to the display voltage between the transmissive pixel electrode 17 and the counter electrode (not shown). An electric field is generated.
- a liquid crystal capacitor (not shown) is formed in parallel with the auxiliary capacitor 209 by liquid crystal between the transmissive pixel electrode 17 and the counter electrode.
- the counter electrode is disposed on the TFT substrate 200 side.
- the display voltage applied to the transmissive pixel electrode 17 is held for a certain period by the liquid crystal capacitor and the auxiliary capacitor 209. Note that an alignment film (not shown) may be formed on the surface of the TFT substrate 200.
- a counter substrate (not shown) is disposed on the TFT substrate 200.
- the counter substrate is, for example, a color filter substrate, and is disposed on the viewing side.
- a color filter On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed.
- BM black matrix
- the TFT substrate 200 and the counter substrate are bonded to each other through a certain gap (cell gap). Then, liquid crystal is injected into this gap and sealed. That is, a liquid crystal layer is disposed between the TFT substrate 200 and the counter substrate. Furthermore, a polarizing plate, a phase difference plate, and the like are provided on the outer surfaces of the TFT substrate 200 and the counter substrate. Further, a backlight unit or the like is disposed on the side opposite to the viewing side of the liquid crystal display panel configured as described above. Since the TFT substrate 200 is disposed on the opposite side to the viewing side and the counter substrate is disposed on the viewing side, the backlight unit is disposed outside the TFT substrate 200.
- FIG. 2 is a plan view showing a planar configuration of the pixel 204 shown in FIG. 1
- FIG. 3 is a sectional configuration taken along line AA in FIG. 2 (a sectional configuration of a TFT portion, a pixel portion, and an auxiliary capacitance portion).
- FIG. 6 is a cross-sectional view showing a cross-sectional configuration along the line BB (cross-sectional configuration of the gate terminal portion) and a cross-sectional configuration along the line CC (cross-sectional configuration of the source terminal portion).
- the TFT substrate 200 is used for a transmissive liquid crystal display device.
- a part of the gate wiring 103 constituting the gate electrode 3 is arranged so as to extend in the X direction, and similarly extends in the X direction, and a part thereof is an auxiliary capacitor.
- the auxiliary capacitance line 105 constituting the electrode is arranged so as to extend in the X direction in parallel with the gate line 103.
- a branch wiring 11 extending in the X direction branches off from the source wiring 101 extending in the Y direction, and a tip portion thereof serves as the source electrode 8.
- a transmissive pixel electrode 17 is provided in a pixel region surrounded by two adjacent gate lines 103 and two adjacent source lines 101, and the transmissive pixel electrode 17 is connected to the drain electrode 9.
- the source electrode 8 and the drain electrode 9 are connected to the channel layer 7 with a gap therebetween. These constitute the pixel TFT 201.
- the channel region 10 is formed in the channel layer 7 between the source electrode 8 and the drain electrode 9.
- the storage capacitor line 105 has two branch lines 115 extending in the Y direction.
- the branch wiring 115 is provided at a portion corresponding to two edge portions on the source wiring 101 side of the pixel region, and the auxiliary capacitor wiring 105 and the branch wiring 115 have a U-shape in a plan view. It arrange
- Each end portion of the gate wiring 103 extending to the frame region is a gate terminal 4, and a gate terminal pad 18 is connected through the gate terminal contact hole 15, and the gate terminal pad 18 is connected to the gate terminal pad 18. In this configuration, an external video scanning signal is applied to the gate terminal 4.
- each end portion of the source wiring 101 extending to the frame region is a source terminal 12, and the source terminal pad 19 is connected via the source terminal portion contact hole 16, and the source terminal pad 19 is connected to the source wiring 101.
- an external video signal is applied to the source terminal 12.
- auxiliary capacitance wirings 105 are electrically bound in the frame region and are configured to be given a common potential.
- the TFT substrate is formed on a substrate 1 which is a transparent insulating substrate such as glass or plastic, and the same conductive film is selectively provided on the substrate 1 to provide wiring and electrodes. It is composed.
- the gate electrode 3, the gate terminal 4, the gate wiring 103, and the auxiliary capacitance wiring 105 are composed of a single layer film or a multilayer film of an alloy film such as an aluminum (Al) alloy or a titanium (Ti) alloy, for example.
- the insulating film 6 is disposed so as to cover these.
- the insulating film 6 functions as a gate insulating film in the portion of the pixel TFT 201 and may be referred to as the gate insulating film 6.
- the gate insulating film 6 is composed of a laminated film of a silicon nitride film and a silicon oxide film formed thereon.
- a channel layer 7 is provided in the formation region of the pixel TFT 201 so as to face the gate electrode 3 through the gate insulating film 6.
- the channel layer 7 is formed on the gate insulating film 6 so as to overlap with the gate electrode 3 in plan view, and is configured to fit as much as possible above the gate electrode 3.
- the channel layer 7 is formed of an oxide semiconductor, and is an oxide semiconductor containing at least indium (In), gallium (Ga), and zinc (Zn), for example, zinc oxide (ZnO) and gallium oxide (Ga 2 O). 3 ) and an In—Ga—Zn—O-based oxide semiconductor to which indium oxide (In 2 O 3 ) is added. Since an oxide semiconductor has higher mobility than amorphous silicon, a small and high-performance TFT can be realized. Note that in addition to the In—Ga—Zn—O system, the oxide semiconductor includes an In—Sn—Ga—Zn—O system, which is a quaternary metal oxide, and an In—, which is a ternary metal oxide.
- an In—Ga—Zn—O-based oxide semiconductor means a metal oxide containing indium (In), gallium (Ga), and zinc (Zn), and The stoichiometric composition ratio is not particularly limited.
- the oxide semiconductor may contain silicon.
- a source electrode 8 and a drain electrode 9 made of a conductive film are disposed so as to be in contact with each other with a gap therebetween.
- a gap between the source electrode 8 and the drain electrode 9 is provided.
- a channel region 10 is formed in the channel layer 7.
- the source electrode 8, the drain electrode 9, the branch wiring 11 and the source wiring 101 in the TFT portion, and the source terminal 12 in the source terminal portion are covered with an interlayer insulating film 13.
- the interlayer insulating film 13 covers the gate insulating film 6 in the gate terminal portion and also covers the gate insulating film 6 in the pixel portion and the auxiliary capacitance portion.
- a transmissive pixel electrode 17 made of a transparent conductive film is formed on the interlayer insulating film 13, and the transmissive pixel electrode 17 has a pixel drain contact hole 14 that reaches the drain electrode 9 through the interlayer insulating film 13. In this way, the drain electrode 9 is connected.
- the source terminal pad 19 is connected to the source terminal 12 through the source terminal portion contact hole 16 that reaches the source terminal 12 through the interlayer insulating film 13.
- the gate terminal pad 18 is connected to the gate terminal 4 through the gate terminal portion contact hole 15 that reaches the gate terminal 4 through the interlayer insulating film 13 and the gate insulating film 6. It has become.
- FIGS. 4 to 8 are cross-sectional views sequentially showing manufacturing steps.
- 4 to 8 are sectional views corresponding to the sectional view shown in FIG. 3, and
- FIG. 3 corresponds to the sectional view showing the final process.
- FIG. 9 is a flowchart showing a procedure of the manufacturing method of the TFT substrate according to the first embodiment of the present invention.
- FIGS. 4 to 8 the flowcharts shown in steps S1001 to S1010 in FIG. It explains along.
- a substrate 1 which is a transparent insulating substrate such as glass is cleaned using a cleaning liquid or pure water, and a metal film (first metal film) that occludes hydrogen such as an Al alloy or a Ti alloy is formed on the substrate 1.
- the metal film is patterned by the first photolithography process to form the gate electrode 3, the gate terminal 4, the gate wiring 103, and the auxiliary capacitance wiring 105 on the substrate 1 as shown in FIG. Step S1001).
- the metal film for storing hydrogen it is desirable to use a metal having a low electrical specific resistance and an alloy such as an Al alloy or a Ti alloy. Furthermore, from the viewpoint of reducing electrical specific resistance, an AlN alloy in which nitrogen (N) is further added to the same alloy is laminated on an Al alloy containing Al as a main component and nickel (Ni) and neodymium (Nd) added. Such a laminated structure is more desirable.
- the thickness of the metal film that stores hydrogen is preferably 50 to 300 nm from the viewpoint of uniformity and coverage.
- a laminated film in which an AlNiNdN film was laminated on an AlNiNd film was formed by a sputtering method using a known argon (Ar) gas or krypton (Kr) gas.
- the sputtering conditions were a DC magnetron sputtering method, an AlNiNd alloy target was used, and an AlNiNd film having a thickness of about 200 nm was formed as a lower layer film under the conditions of a power density of 3 W / cm 2 and an Ar gas flow rate of 40 sccm.
- an AlNiNdN film having a thickness of about 50 nm is formed as an upper film under the conditions of a power density of 3 W / cm 2 , an Ar gas flow rate of 40 sccm, and an N 2 gas flow rate of 20 sccm.
- a laminated film was obtained.
- a resist material is applied onto the laminated film, and the applied resist material is exposed using a photomask to expose the resist material.
- the exposed resist material is developed and patterned to obtain a photoresist pattern.
- a series of steps for forming these photoresist patterns is referred to as a photolithography process.
- a known chemical solution containing phosphoric acid for example, a mixed acid of phosphoric acid (Phosphoric acid), nitric acid (Acetic acid) and acetic acid (Nitric acid) (hereinafter referred to as “PAN”) is used.
- Phosphoric acid phosphoric acid
- Acetic acid nitric acid
- Nitric acid acetic acid
- the laminated film of the AlNiNdN film and the AlNiNd film is collectively etched and the photoresist pattern is removed, whereby the gate electrode 3, the gate terminal 4, the gate wiring 103 and the auxiliary wiring are formed on the substrate 1 as shown in FIG.
- a capacitor wiring 105 was formed.
- the AlNiNdN film formed here receives oxygen (O) from the atmosphere during formation or the upper layer film to be formed later and has Al, N, and O, and thus has a hydrogen storage capability. It becomes.
- the upper AlNiNdN film can take in hydrogen diffused from the upper film, and the hydrogen storage capacity is 2.5 ⁇ 10 20 atoms / cm 3 to 2 ⁇ 10 22 atoms / cm 3. It is the film
- the gate insulating film 6 is formed on the substrate 1, and the gate electrode 3, the gate terminal 4, the gate wiring 103, and the auxiliary capacitance wiring 105 are covered with the gate insulating film 6 (step S1002).
- the gate insulating film 6 is composed of a laminated film in which a silicon oxide (SiO) film is laminated on a silicon nitride (SiN) film.
- the total thickness of the gate insulating film 6 varies depending on the dielectric constant of the material constituting the laminated film and the operating voltage (ON voltage) of the thin film transistor, but is preferably 150 to 500 nm.
- CVD chemical vapor deposition
- an example of using the CVD method is shown as a method for forming the SiO film and the SiN film, but a sputtering method or an ion plating method may be used.
- an oxide semiconductor film as a material of the channel layer 7 is formed on the gate insulating film 6, and the oxide semiconductor film is patterned by a second photolithography process, so that the TFT portion is formed as shown in FIG.
- the channel layer 7 is formed above the gate electrode 3 (step S1003).
- the film thickness of the channel layer 7 is preferably 10 to 100 nm from the viewpoint of film uniformity and carrier density.
- a first heat treatment (annealing process) is performed (step S1004).
- This heat treatment is performed in an atmosphere containing oxygen having an oxygen concentration in the atmosphere (20%) or higher in order to reduce excess hydrogen in the oxide semiconductor film and supply oxygen to reduce defects.
- the heat treatment temperature is desirably 300 to 450 ° C.
- the reason why the heat treatment temperature is 300 ° C. or higher is that when the heat treatment temperature is lower than 300 ° C., hydrogen is not sufficiently released from the oxide semiconductor film and oxygen is not sufficiently supplied to the oxide semiconductor film.
- the reason why the temperature is 450 ° C. or lower is that when the temperature is higher than 450 ° C., the desorption rate of the element in the oxide semiconductor film varies depending on the type of element (Zn has a particularly large desorption amount). This is because it occurs.
- the In: Ga: Zn: O atomic composition ratio is 1: 1: by sputtering using an InGaZnO target having an In: Ga: Zn: O atomic composition ratio of 1: 1: 1: 4.
- a 1: 1: 4 InGaZnO film was formed to a thickness of 40 nm.
- an oxide film in an oxygen ion deficient state (the composition ratio of O is less than 4 in the above example) in which the atomic composition ratio of oxygen is smaller than the stoichiometric composition is easily formed. Therefore, it is desirable to mix Ar gas with oxygen (O 2 ) gas and perform sputtering.
- an InGaZnO film having an amorphous structure generally has a crystallization temperature of 500 ° C. or higher, and most of the film is stable with an amorphous structure at room temperature.
- a resist material is applied on the InGaZnO film having an amorphous structure, and a photoresist pattern is formed by a second photolithography process. Then, the InGaZnO film is patterned by etching using the photoresist pattern as a mask.
- wet etching using a solution containing oxalic acid can be used.
- the solution containing oxalic acid is preferably one containing oxalic acid in the range of 1 to 10 wt%. In the first embodiment, an aqueous solution containing 5 wt% oxalic acid is used.
- the photoresist pattern is removed to obtain the channel layer 7 shown in FIG. Thereafter, heat treatment was performed for 60 minutes in an oxygen-containing atmosphere at a substrate temperature of 350 ° C.
- any composition other than the above-described composition ratio can be used as long as it has a homologous structure (InGaO 3 (ZnO) m : (m> 0)).
- a metal film (second metal film) is formed on the gate insulating film 6 including the channel layer 7, and the metal film is patterned through a third photolithography process, as shown in FIG. Then, the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 are formed (step S1005).
- the metal film formed in this step has a low electrical specific resistance, good contact characteristics with the channel layer 7, and good contact characteristics with the conductive film used for the transmissive pixel electrode 17 (especially electrical characteristics). It is desirable to use an alloy film having characteristics such as low contact resistance.
- the thickness of the metal film is preferably 50 to 300 nm from the viewpoint of film uniformity and coverage.
- a second heat treatment is performed (step S1006). Similar to the heat treatment after the channel layer is formed, this heat treatment is performed in an atmosphere containing oxygen having an oxygen concentration higher than the atmospheric concentration for the purpose of reducing excess hydrogen in the oxide semiconductor and supplying oxygen to each layer. desirable.
- the heat treatment temperature is preferably 300 to 350 ° C. The reason why the temperature is 300 ° C. or higher is that when the temperature is lower than 300 ° C., hydrogen is not sufficiently released from the oxide semiconductor film, and oxygen is not sufficiently supplied into the oxide semiconductor film. The reason why the temperature is set to 350 ° C. or lower is that when the temperature is higher than 350 ° C., the amount of metal diffusion from the source electrode 8 and the drain electrode 9 to the channel layer 7 becomes significant, affecting the characteristics.
- a laminated film in which an AlNiNd film was laminated on an AlNiNdN film was formed by a sputtering method using a known Ar gas or Kr gas.
- the sputtering condition was a DC magnetron sputtering method, using an AlNiNd alloy target, and an AlNiNdN film having a thickness of about 50 nm was formed as a lower layer film under the conditions of a power density of 3 W / cm 2 , an Ar gas flow rate of 40 sccm, and an N 2 gas flow rate of 20 sccm.
- an AlNiNd film having a thickness of about 200 nm was formed as an upper film under the conditions of a power density of 3 W / cm 2 and an Ar gas flow rate of 40 sccm to obtain a laminated film having a thickness of 250 nm.
- a resist material is applied on the laminated film, and a photoresist pattern is formed by a third photolithography process. Then, using the photoresist pattern as a mask, a known chemical solution containing phosphoric acid, for example, PAN is used to collectively etch the laminated film of the AlNiNd film and the AlNiNdN film, thereby removing the photoresist pattern. As shown in FIG. 6, the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 were formed.
- the gas added at the time of sputtering is not limited to N 2 gas.
- N is a gas such as NH 3
- N may be added to the Al film. Is possible.
- N may be added to the Al film by Ar gas or Kr gas alone. Is possible.
- an interlayer insulating film 13 as a passivation film is formed so as to cover the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 (step S1007).
- the interlayer insulating film 13 is composed of a laminated film of a lower layer film and an upper layer film, and a third heat treatment is performed after the lower layer film is formed (step S1008).
- This heat treatment is performed for the purpose of reducing excess hydrogen in the oxide semiconductor and supplying oxygen to each layer from the atmosphere and the lower layer film.
- the heat treatment is preferably performed in an atmosphere containing oxygen having an oxygen concentration in the atmosphere or higher, and the temperature of the heat treatment is preferably 200 to 350 ° C.
- the reason why the temperature is 200 ° C. or higher is that when the temperature is lower than 200 ° C., oxygen is not sufficiently supplied to the channel layer 7.
- the reason why the temperature is set to 350 ° C. or lower is that if the temperature is higher than 350 ° C., the amount of metal diffusion from the source electrode 8 and the drain electrode 9 to the channel layer 7 becomes significant, affecting the characteristics.
- the total thickness of the interlayer insulating film 13 varies depending on the dielectric constant of the material constituting the laminated film and the operating voltage (ON voltage) of the thin film transistor, but is preferably 150 to 500 nm.
- a CVD method is used.
- heat treatment was performed by holding for 60 minutes in a temperature condition of 280 ° C. in an air atmosphere.
- a resist material is applied on the interlayer insulating film 13, and a photoresist pattern is formed by a fourth photolithography process.
- the source terminal contact hole 16 reaching the surface of the source terminal 12 is formed at the same time.
- a pixel drain contact hole 14 by removing the photoresist pattern, a pixel drain contact hole 14, a gate terminal contact hole 15 and a source terminal contact hole 16 are obtained as shown in FIG.
- an example of using the CVD method is shown as a method for forming the SiO film and the SiN film, but a sputtering method or an ion plating method may be used.
- a transparent conductive film is formed on the interlayer insulating film 13, and the transparent conductive film is embedded in the pixel drain contact hole 14, the gate terminal contact hole 15, and the source terminal contact hole 16, and a fifth photolithography process is performed. Then, by patterning the transparent conductive film, as shown in FIG. 3, the transmissive pixel electrode 17 connected to the lower drain electrode 9 through the pixel drain contact hole 14, the gate terminal contact hole 15 and the source terminal contact
- the TFT substrate 200 is completed by forming the gate terminal pad 18 and the source terminal pad 19 connected to the gate terminal 4 and the source terminal 12 through the holes 16 (step S1009).
- the completed TFT substrate 200 is subjected to a fourth heat treatment in an atmosphere containing oxygen having an oxygen concentration higher than the atmospheric concentration at a temperature of 200 to 350 ° C. (step S1010).
- the hydrogen concentration of the entire TFT substrate can be reduced by diffusing the hydrogen of the entire TFT substrate to be occluded in the gate electrode 3 or released to the outside of the substrate, improving the TFT characteristics and being stable. It can be made.
- oxygen is sufficiently supplied to each layer by the first to third heat treatments, the dangling bonds of each layer are terminated with oxygen. As a result, the amount of diffusion hydrogen trapped in the dangling bonds of each layer is small during the fourth heat treatment. Therefore, the hydrogen concentration of the entire TFT substrate can be effectively reduced.
- the reason why the heat treatment temperature is set to 200 ° C. or higher is that when the temperature is lower than 200 ° C., the amount of hydrogen diffusion in the TFT substrate decreases, and the hydrogen concentration of the TFT substrate cannot be sufficiently reduced.
- the reason why the temperature is set to 350 ° C. or lower is that if the temperature is higher than 350 ° C., the amount of metal diffusion from the source electrode 8 and the drain electrode 9 to the channel layer 7 becomes significant, affecting the characteristics.
- the TFT substrate 200 was completed by holding the TFT substrate 200 in the atmosphere at about 230 ° C. for 60 minutes for heat treatment.
- FIGS. 10 to 12 show the drain current (Id) characteristics (Id-Vg characteristics) with respect to the gate voltage (Vg) of the thin film transistor when the heat treatment temperature is changed in the range of 200 to 350 ° C., and the drain-source voltage ( When Vds) is 0.1V, it is a diagram illustrating each case of 1V, 10V.
- FIG. 10 shows Id-Vg when Vds is 0.1 V before annealing and when annealing is performed at 200 ° C., 230 ° C., 250 ° C., 280 ° C., 300 ° C. and 350 ° C. The characteristics are shown.
- FIG. 11 shows the Id-Vg characteristics when Vds is 1 V, before annealing, and when annealed at 200 ° C., 230 ° C., 250 ° C., 280 ° C., 300 ° C. and 350 ° C. Show.
- FIG. 10 shows Id-Vg when Vds is 0.1 V before annealing and when annealing is performed at 200 ° C., 230 ° C., 250 ° C., 280 ° C., 300 ° C. and 350 ° C. Show.
- FIG. 11 shows the Id-Vg characteristics when Vds is 1 V, before annealing, and when annealed at 200
- Vds is 10 V
- 280 ° C. 300 ° C. and 350 ° C. Show.
- the threshold voltage is lower than ⁇ 10 V when the annealing process is not performed, and the thin film transistor cannot be turned off with a practical voltage. It can also be seen that the higher the annealing temperature, the more the threshold voltage shifts to the positive side. When the annealing temperature is 350 ° C., the threshold voltage becomes a value from several V to less than 10V. Therefore, it can be said that when the annealing temperature is in the range of 200 to 350 ° C., a thin film transistor having good off characteristics can be obtained. Note that by setting the annealing temperature to 230 to 300 ° C., a thin film transistor having more excellent off characteristics can be obtained.
- FIG. 13 is an overall view showing a hydrogen profile in the central portion of the gate electrode 3 in the TFT portion, that is, the portion indicated by the arrow D in FIG. 3, and FIG. 14 shows the hydrogen in the channel layer 7 and its nearby layers. It is a figure of a profile.
- the hydrogen profile shown in FIG. 13 shows the depth direction distribution of hydrogen in the interlayer insulating film 13, the channel layer 7 and the gate insulating film 6.
- the interlayer insulating film 13 and the gate insulating film 6 are both two layers. Therefore, the individual films are also shown separately for convenience.
- the interlayer insulating film 13 is divided into an upper SiN film as an upper interlayer insulating film 132 and a lower SiO film as a lower interlayer insulating film 131, and the gate insulating film 6 has an upper SiO film as an upper gate insulating film 62.
- the lower SiN film is shown as a lower gate insulating film 61 separately.
- FIGS. 13 and 14 shows hydrogen profiles of a part of the lower interlayer insulating film 131, the entire channel layer 7, and a part of the upper gate insulating film 62.
- hydrogen before the fourth heat treatment is shown.
- the profile is indicated by a broken line, and the hydrogen profile after the fourth heat treatment is indicated by a solid line.
- the lowest hydrogen concentration in the channel layer 7 (oxide semiconductor) after the fourth heat treatment is 2.0 ⁇ 10 20 atoms / cm 3 , which is the lowest in the lower gate insulating film 61.
- the low hydrogen concentration was 2.3 ⁇ 10 21 atoms / cm 3 .
- FIG. 15 shows the relationship between the carrier density (number / cm 3 ) in the channel layer 7 and the threshold voltage (V) of the TFT.
- V threshold voltage
- the carrier density needs to be 1 ⁇ 10 16 pieces / cm 3 or less.
- the carrier density is 1 ⁇ 10 16 atoms / cm 3 . Note that if the carrier density is too low, it cannot be turned on even when a gate voltage is applied, so the carrier density needs to be higher than 1 ⁇ 10 11 atoms / cm 3 .
- the carrier density can be measured by Hall effect measurement.
- the carrier density is measured by Hall effect measurement for TEG (test element group) created under the same conditions as the actual TFT substrate, while the actual TFT substrate is measured.
- TEG test element group
- the threshold voltage of the TFT By measuring the threshold voltage of the TFT, the correlation characteristic between the carrier density and the threshold voltage as shown in FIG. 15 is obtained.
- the hydrogen concentration in the channel layer 7 (oxide semiconductor) satisfies this condition, so the carrier density is 1 ⁇ 10 16 atoms / cm 3 or less.
- the hydrogen concentration in the oxide semiconductor needs to be 1 ⁇ 10 16 atoms / cm 3 or more.
- FIG. 16 shows the drain current (Id) characteristics (Id-Vg characteristics) with respect to the gate voltage (Vg) of the thin film transistor.
- Id drain current
- Vg gate voltage
- FIG. 17 shows Id-Vg characteristics of a thin film transistor manufactured by omitting the third heat treatment.
- the hydrogen concentration in the channel layer of this thin film transistor is higher than 3 ⁇ 10 20 atoms / cm 3 (that is, the carrier density is higher than 1 ⁇ 10 16 atoms / cm 3 ).
- the threshold voltage is lower than ⁇ 10 V, and the thin film transistor cannot be turned off at a practical voltage, which causes a problem in off characteristics.
- the characteristics of FIGS. 16 and 17 are measured with a drain-source voltage of 1V.
- the threshold voltage of the TFT can be set to a practical voltage. it can.
- the TFT substrate 200 of the present embodiment has a hydrogen concentration in the lower gate insulating film 61 of 3 ⁇ 10 21 atoms / cm 3 or less, hydrogen diffusion is suppressed when the TFT substrate 200 is used, Good reliability for the operation of the TFT can be obtained. The reason for this will be described with reference to FIGS. 18 to 21 showing the results of TFT reliability evaluation.
- FIG. 18 shows PBTS (continuous voltage gate voltage of +30 V) applied to a TFT substrate in which the hydrogen concentration in the lower gate insulating film 61 detected by SIMS satisfies 3 ⁇ 10 21 atoms / cm 3 or less for a predetermined time at room temperature. It shows the Id-Vg characteristics after performing a Positive Bias Temperature Stress) test.
- the test time is 0 seconds (s) when +30 V is not applied, when applied for 30 seconds, when applied for 100 seconds, when applied for 300 seconds, when applied for 1000 seconds, and when applied for 3000 seconds
- the threshold voltage shift was 1 V or less between the case of 0 seconds and the case of 3000 seconds.
- FIG. 19 shows that the hydrogen concentration in the lower gate insulating film 61 detected by SIMS is ⁇ 30 V at room temperature (the source-drain voltage is 0 V) with respect to a TFT substrate satisfying 3 ⁇ 10 21 atoms / cm 3 or less.
- 2 shows an Id-Vg characteristic after performing an LNBTS (Light Negative Bias Temperature Stress) test in which the gate voltage is continuously applied for a predetermined time. The test time is the same as in FIG. As shown in FIG. 19, the threshold voltage shift was 1 V or less between the case of 0 seconds and the case of 3000 seconds.
- LNBTS Light Negative Bias Temperature Stress
- FIG. 20 a PBTS test was performed on the TFT substrate in which the hydrogen concentration in the lower gate insulating film 61 detected by SIMS was 5 ⁇ 10 21 atoms / cm 3 under the same conditions as in FIG. The later Id-Vg characteristics are shown. As shown in FIG. 20, the threshold voltage shift was about 3.5 V between the case of 0 seconds and the case of 3000 seconds.
- the LNBTS test was performed on the TFT substrate in which the hydrogen concentration in the lower gate insulating film 61 detected by SIMS is 5 ⁇ 10 21 atoms / cm 3 under the same conditions as in FIG. The later Id-Vg characteristics are shown. As shown in FIG. 21, the threshold voltage shift was about 1.5 V between 0 seconds and 3000 seconds.
- the threshold voltage shift is small in both the PBTS test and the LNBTS test, and the TFT operation is favorable. It can be seen that reliability can be obtained.
- the threshold voltage of the TFT becomes a practical voltage.
- the hydrogen concentration in the lower gate insulating film 61 is 3 ⁇ 10 21 atoms / cm 3 or less, good reliability for the operation of the TFT can be obtained.
- the gate electrode 3 is formed of an AlNiNd film.
- the AlNiNdN film is a laminated film in which an AlNiNdN film is laminated thereon, and the AlNiNdN film as the upper layer film contains hydrogen in the range of 2.5 ⁇ 10 20 atoms / cm 3 to 2 ⁇ 10 22 atoms / cm 3.
- the hydrogen diffused during the TFT operation is also occluded by the gate electrode 3, it is possible to suppress an increase in the hydrogen concentration of the channel layer 7 during the TFT operation, and the characteristic variation is suppressed and the reliability is excellent. A TFT is obtained.
- the TFT substrate 200 of the first embodiment described above has the back channel etch type pixel TFT 201, but an etching stopper in which an etching stopper layer of a silicon oxide film is provided between the channel layer and the interlayer insulating film. It is good also as a structure which has a type TFT.
- FIG. 22 shows a cross-sectional configuration of a TFT substrate 200 having an etching stopper type pixel TFT 201A.
- the same components as those of the pixel TFT 201 described with reference to FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.
- a protective insulating film 21 made of a silicon oxide film having a thickness of 10 to 300 nm is disposed on the gate insulating film 6, and the protective insulating film 21 is also disposed on the channel layer 7.
- the protective insulating film 21 on the channel layer 7 functions as an etching stopper and protects the channel layer 7 from etching.
- the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101 and the source terminal 12 are disposed on the protective insulating film 21.
- the source electrode 8 and the drain electrode 9 are connected to the channel layer 7 via contact holes 31 and 32 that penetrate the protective insulating film 21 and reach the channel layer 7, respectively.
- An interlayer insulating film 13 is provided so as to cover the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 including the protective insulating film 21.
- a transmissive pixel electrode 17 made of a transparent conductive film is formed on the interlayer insulating film 13, and the transmissive pixel electrode 17 has a pixel drain contact hole 14 that reaches the drain electrode 9 through the interlayer insulating film 13. In this way, the drain electrode 9 is connected.
- the channel region 10 is formed in the channel layer 7 between the source electrode 8 and the drain electrode 9, and the channel region 10 is covered with the protective insulating film 21.
- the source terminal pad 19 is connected to the source terminal 12 through the source terminal portion contact hole 16 that reaches the source terminal 12 through the interlayer insulating film 13.
- the gate terminal pad 18 is connected to the gate terminal 4 through the gate terminal contact hole 15 that reaches the gate terminal 4 through the interlayer insulating film 13, the protective insulating film 21, and the gate insulating film 6. It is configured to be connected.
- the channel region 10 since the channel region 10 is covered with the protective insulating film 21, the channel region 10 can be protected from etching when the source electrode 8 and the drain electrode 9 are formed.
- the protective insulating film 21 is shown as covering the entire surface of the substrate 1.
- the protective insulating film 21 may be formed on the channel layer 7 in a range that fits in the region of the channel layer 7 in plan view. In that case as well, it is the same that the photolithography process is increased once.
- FIG. 23 is a plan view schematically illustrating the entire configuration of the TFT substrate according to the second embodiment of the present invention. Note that the same reference numerals are used for the same configurations as those described with reference to FIG. A duplicate description will be omitted.
- a TFT substrate 300 shown in FIG. 23 is a TFT array substrate in which pixel TFTs 301 are arranged in a matrix.
- FIG. 23 the configuration of some of the pixels 304 is shown enlarged, and at least one pixel TFT 301 is disposed in the pixel 304.
- the pixel TFT 301 is disposed near the intersection of the source wiring 101 and the gate wiring 103, the gate electrode of the pixel TFT 301 is connected to the gate wiring 103, the source electrode of the pixel TFT 401 is connected to the source wiring 101, and the drain electrode of the pixel TFT 301 is transmissive. It is connected to the pixel electrode 17.
- an auxiliary capacitor 209 is connected to the transmissive pixel electrode 17, and an auxiliary capacitor line 105 provided in parallel with each of the plurality of gate lines 103 also serves as an auxiliary capacitor electrode.
- the gate wiring 103 and the auxiliary capacitance wiring 105 are alternately arranged, and the auxiliary capacitance wiring 105 and the source wiring 101 are arranged so as to cross at right angles to each other.
- the pixel TFT 301 is a so-called dual gate type thin film transistor, and has a control electrode in addition to the gate electrode, and the control electrode is connected to the auxiliary capacitance wiring 105.
- FIG. 24 is a plan view showing a planar configuration of the pixel 304 shown in FIG. 23, and FIG. 25 is a sectional configuration taken along line AA in FIG. 24 (a sectional configuration of the TFT portion, the pixel portion, and the auxiliary capacitance portion).
- FIG. 24 is a plan view showing a planar configuration of the pixel 304 shown in FIG. 23, and FIG. 25 is a sectional configuration taken along line AA in FIG. 24 (a sectional configuration of the TFT portion, the pixel portion, and the auxiliary capacitance portion).
- FIG. 6 is a cross-sectional view showing a cross-sectional configuration along the line BB (cross-sectional configuration of the gate terminal portion) and a cross-sectional configuration along the line CC (cross-sectional configuration of the source terminal portion). Note that the same components as those of the pixel 204 described with reference to FIGS. 2 and 3 are denoted by the same reference numerals, and redundant description is omitted.
- a channel layer 7 made of an oxide semiconductor is provided on the gate electrode 3, and a source electrode 8 and a drain electrode 9 are connected to the channel layer 7 with a gap therebetween.
- a control electrode 25 having a size that does not protrude from above the channel layer 7 in a plan view is provided above the channel layer 7.
- the control electrode 25 is covered with a transparent wiring 26 made of a transparent conductive film, and the transparent wiring 26 is connected to the auxiliary capacitance wiring 105 of another pixel adjacent to the pixel 304 in the Y direction via the auxiliary capacitance electrode contact hole 27. Electrically connected.
- the storage capacitor line 105 has two branch lines 115 extending in the Y direction.
- the branch wiring 115 is provided at a portion corresponding to two edge portions on the source wiring 101 side of the pixel region, and the auxiliary capacitor wiring 105 and the branch wiring 115 have a U-shape in a plan view. It arrange
- the auxiliary capacitance line 105 is provided with a connection pad 125 extending in the direction opposite to the extending direction of the two branch lines 115.
- the connection pad 125 is provided so as to be positioned in the vicinity of the gate electrode 3 of another pixel adjacent to the pixel 304 in the Y direction.
- the transparent wiring 26 that covers the control electrode 25 of another pixel adjacent to the connection pad 125. However, they are connected via the storage capacitor electrode contact hole 27.
- the control electrode 25 is one gate electrode of a dual gate and is referred to as a control electrode for convenience in the present application.
- the dual gate has a structure in which gate electrodes are provided above and below the channel layer in order to control the threshold voltage to a desired value.
- the gate electrode (first gate electrode) provided below the channel layer has the same potential as the gate wiring.
- the gate electrode (second gate electrode) provided above the channel layer is set to a low potential that is lower than the source potential.
- the electrical characteristics of the TFT such as a threshold voltage
- the electrostatic shielding effect can be obtained by setting the potential of the second gate electrode to the GND potential (ground potential).
- the first gate electrode and the second gate electrode are electrically connected to have a common potential so that the channel layer disposed between the first gate electrode and the second gate electrode is gated from above and below. A voltage can be applied.
- control electrode 25 is a metal that occludes hydrogen, such as an Al alloy or a Ti alloy, like the gate electrode 3.
- a film that can contain hydrogen in the range of 2.5 ⁇ 10 20 atoms / cm 3 to 2 ⁇ 10 22 atoms / cm 3 contributes to further reduction in the hydrogen concentration of the entire TFT substrate. .
- a cross-sectional configuration of the pixel 304 will be described with reference to FIG.
- a channel layer 7 is provided so as to face the gate electrode 3 through the gate insulating film 6, and a conductive film is formed on the channel layer 7.
- the source electrode 8 and the drain electrode 9 are disposed so as to be in contact with each other with a gap therebetween, and when the pixel TFT 301 is operated, the channel region 10 is formed in the channel layer 7 between the source electrode 8 and the drain electrode 9. .
- the source electrode 8, the drain electrode 9, the branch wiring 11 and the source wiring 101 in the TFT portion, and the source terminal 12 in the source terminal portion are covered with an interlayer insulating film 13, and a transparent conductive film is formed on the interlayer insulating film 13 in the pixel portion.
- a control electrode 25 having a size that does not protrude from the channel layer 7 is formed on the interlayer insulating film 13.
- a transparent wiring 26 made of the same transparent conductive film as the transmissive pixel electrode 17 is provided so as to cover the control electrode 25.
- the transparent wiring 26 is connected to the connection pad 125 through the auxiliary capacitance electrode contact hole 27 that penetrates the interlayer insulating film 13 and the gate insulating film 6 and reaches the connection pad 125. ing.
- FIGS. 26 to 30 are sectional views sequentially showing manufacturing steps.
- 26 to 30 are sectional views corresponding to the sectional view shown in FIG. 25, and
- FIG. 25 corresponds to a sectional view showing the final process.
- FIG. 31 is a flowchart showing the procedure of the manufacturing method of the TFT substrate according to the first embodiment of the present invention.
- FIGS. 26 to 30 the flowcharts shown in steps S2001 to S2011 in FIG. It explains along. Note that the description overlapping the manufacturing method of the TFT substrate of Embodiment 1 described with reference to FIGS. 4 to 8 is omitted.
- the substrate 1 which is a transparent insulating substrate such as glass is cleaned using a cleaning liquid or pure water, and a metal film that occludes hydrogen such as Al alloy or Ti alloy is formed on the substrate 1.
- a metal film that occludes hydrogen such as Al alloy or Ti alloy is formed on the substrate 1.
- the metal film for storing hydrogen it is desirable to use a metal having a low electrical specific resistance and an alloy such as an Al alloy or a Ti alloy. Furthermore, from the viewpoint of reducing electrical specific resistance, an AlN alloy in which nitrogen (N) is further added to the same alloy is laminated on an Al alloy containing Al as a main component and nickel (Ni) and neodymium (Nd) added. Such a laminated structure is more desirable.
- the thickness of the metal film that stores hydrogen is preferably 50 to 300 nm from the viewpoint of uniformity and coverage.
- a 250 nm thick laminated film was formed by laminating an AlNiNdN film on an AlNiNd film by a sputtering method using a known Ar gas or Kr gas.
- a specific example of conditions for forming the AlNiNd film and the AlNiNdN film is the same as in the first embodiment.
- a resist material was applied on the laminated film, and a photoresist pattern was formed by a photolithography process.
- the laminated film of the AlNiNdN film and the AlNiNd film is collectively etched using a known PAN, and the photoresist pattern is removed, as shown in FIG.
- a gate electrode 3, a gate terminal 4, a gate wiring 103, and an auxiliary capacitance wiring 105 (including a connection pad 125) were formed on 1.
- the AlNiNdN film formed here has a hydrogen storage capacity, and can take in hydrogen diffused from the upper film, and the hydrogen storage capacity is 2.5 ⁇ 10 20 atoms / cm 3 to The film can be included in the range of 2 ⁇ 10 22 atoms / cm 3 .
- the gate insulating film 6 is formed on the substrate 1, and the gate electrode 3, the gate terminal 4, the gate wiring 103, and the auxiliary capacitance wiring 105 are covered with the gate insulating film 6 (step S2002).
- the gate insulating film 6 is composed of a laminated film in which a SiO film is laminated on a SiN film.
- the total thickness of the gate insulating film 6 varies depending on the dielectric constant of the material constituting the laminated film and the operating voltage (ON voltage) of the thin film transistor, but is preferably 150 to 500 nm. Specific conditions for forming the gate insulating film 6 are the same as those in the first embodiment.
- an oxide semiconductor film as a material of the channel layer 7 is formed on the gate insulating film 6, and the oxide semiconductor film is patterned through a second photolithography process, so that the TFT as shown in FIG.
- the channel layer 7 is formed above the part of the gate electrode 3 (step S2003).
- the film thickness of the channel layer 7 is preferably 10 to 100 nm from the viewpoint of film uniformity and carrier density. Specific conditions for forming the channel layer 7 are the same as those in the first embodiment.
- the first heat treatment is performed in an atmosphere containing oxygen at or above the atmospheric oxygen concentration (step S2004).
- the conditions for the first heat treatment are the same as those in the first embodiment.
- step S2005 by forming a metal film on the gate insulating film 6 including the channel layer 7 and patterning the metal film through a third photolithography process, as shown in FIG.
- the electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 are formed (step S2005).
- the metal film formed in this step has a low electrical specific resistance, good contact characteristics with the channel layer 7, and good contact characteristics with the conductive film used for the transmissive pixel electrode 17 (especially electrical characteristics). It is desirable to use an alloy film having characteristics such as low contact resistance.
- the thickness of the metal film is preferably 50 to 300 nm from the viewpoint of film uniformity and coverage.
- a 250 nm thick laminated film was formed by laminating an AlNiNd film on an AlNiNdN film by a sputtering method using a known Ar gas or Kr gas.
- a specific example of conditions for forming the AlNiNd film and the AlNiNdN film is the same as in the first embodiment. Note that this AlNiNdN film may also have a hydrogen storage capability.
- a second heat treatment is performed in an atmosphere containing oxygen at or above the atmospheric oxygen concentration (step S2006).
- the conditions for the second heat treatment are the same as those in the first embodiment.
- an interlayer insulating film 13 as a passivation film is formed so as to cover the source electrode 8, the drain electrode 9, the branch wiring 11, the source wiring 101, and the source terminal 12 (step S2007).
- the interlayer insulating film 13 is composed of a laminated film of a lower layer film and an upper layer film, and after the lower layer film is formed, a third heat treatment is performed (step S2008). This heat treatment is performed for the purpose of reducing excess hydrogen in the oxide semiconductor and supplying oxygen to each layer from the atmosphere and the lower layer film.
- the conditions for the third heat treatment are the same as those in the first embodiment.
- the total thickness of the interlayer insulating film 13 varies depending on the dielectric constant of the material constituting the laminated film and the operating voltage (ON voltage) of the thin film transistor, but is preferably 150 to 500 nm. Specific examples of conditions for forming the lower layer film and the upper layer film are the same as those in the first embodiment.
- step S2009 After forming a metal film that absorbs hydrogen such as an Al alloy or Ti alloy on the interlayer insulating film 13, by patterning the metal film through a fourth photolithography process, as shown in FIG. A control electrode 25 having a size that does not protrude from the channel layer 7 is formed on the interlayer insulating film 13 (step S2009).
- the metal film for storing hydrogen it is desirable to use a metal having a low electrical specific resistance and an alloy such as an Al alloy or a Ti alloy. Furthermore, from the viewpoint of reducing electrical specific resistance, a laminated structure in which an alloy containing Al as a main component and adding Ni, Nd and N on an alloy containing Al as a main component and adding Ni and Nd is more laminated. desirable.
- the thickness of the metal film that stores hydrogen is preferably 50 to 300 nm from the viewpoint of uniformity and coverage.
- a laminated film in which an AlNiNd film was laminated on an AlNiNdN film was formed by a sputtering method using a known Ar gas or Kr gas.
- the sputtering condition is a DC magnetron sputtering method, an AlNiNd alloy target is used, and an AlNiNdN film having a thickness of about 50 nm is formed as an upper film under the conditions of a power density of 3 W / cm 2 , an Ar gas flow rate of 40 sccm, and an N 2 gas flow rate of 20 sccm, Next, using the same target material, an AlNiNd film having a thickness of about 200 nm was formed as an upper film under the conditions of a power density of 3 W / cm 2 and an Ar gas flow rate of 40 sccm to obtain a laminated film having a thickness of 250 nm.
- the AlNiNdN film formed here has a hydrogen storage capacity and can take in hydrogen diffused from the lower layer film.
- the hydrogen storage capacity is 2.5 ⁇ 10 20 atoms / cm 3 to 2
- the film can be included in the range of ⁇ 10 22 atoms / cm 3 .
- a resist material is applied on the laminated film, and a photoresist pattern is obtained by a fourth photolithography process. Then, using this photoresist pattern as a mask, a known chemical solution containing phosphoric acid, for example, PAN, is used to collectively etch the laminated film of the AlNiNdN film and the AlNiNd film, thereby removing the photoresist pattern.
- the control electrode 25 shown in 29 was obtained.
- a resist material is applied on the interlayer insulating film 13, and a photoresist pattern is formed by a fifth photolithography process.
- the source terminal contact hole 16 reaching the surface of the source terminal 12 and the storage capacitor electrode contact hole 27 reaching the surface of the connection pad 125 are formed simultaneously.
- the pixel drain contact hole 14, the gate terminal portion contact hole 15, the source terminal portion contact hole 16 and the auxiliary capacitance electrode contact hole 27 are obtained as shown in FIG.
- a transparent conductive film is formed on the interlayer insulating film 13 including the control electrode 25, and the pixel drain contact hole 14, the gate terminal contact hole 15, the source terminal contact hole 16, and the auxiliary capacitance electrode contact hole 27.
- the transparent conductive film is embedded in the transparent conductive film and patterned through the sixth photolithography process, thereby connecting the transparent pixel connected to the lower drain electrode 9 through the pixel drain contact hole 14 as shown in FIG.
- a gate terminal pad 18 and a source terminal pad 19 connected to the gate terminal 4 and the source terminal 12 via the electrode 17, the gate terminal portion contact hole 15 and the source terminal contact hole 16, respectively, and an auxiliary capacitance electrode contact hole 27 Via the lower connection pad 125 TFT substrate 300 by forming a transparent wiring 26 connected is completed (step S2010).
- the specific formation conditions of the transparent conductive film are the same as those in the first embodiment.
- the fourth heat treatment is performed on the completed TFT substrate 300 at a temperature of 200 to 350 ° C. in an atmosphere containing oxygen at or above the atmospheric oxygen concentration as in the first embodiment (step S2011).
- the hydrogen concentration of the entire TFT substrate can be reduced by diffusing the hydrogen of the entire TFT substrate and allowing the gate electrode 3 and the control electrode 25 to occlude or release it outside the substrate, thereby improving the TFT characteristics. And can be stabilized.
- control electrode 25 with the ability to occlude hydrogen, the occlusion amount of hydrogen can be increased, and further reduction of the hydrogen concentration of the entire TFT substrate can be expected.
- the hydrogen depth direction distribution analysis using the secondary ion mass spectrometry (SIMS) method is performed on the channel portion of the pixel TFT 301 as in the first embodiment. went.
- the hydrogen in the interlayer insulating film, the channel layer, and the gate oxide film was reduced by the fourth heat treatment.
- the hydrogen concentration in the channel layer 7 was 3 ⁇ 10 20 atoms / cm 3 or less
- the hydrogen concentration in the lower gate insulating film 61 was 2.3 ⁇ 10 21 atoms / cm 3 . .
- the threshold voltage of the TFT is actually in the range of ⁇ 10 to 0V, and the threshold voltage of the TFT is a practical voltage. It turns out that it becomes.
- the hydrogen concentration in the lower gate insulating film 61 is 3 ⁇ 10 21 atoms / cm 3 or less, and the threshold fluctuations in the PBTS test and the LNBTS test are both 1 V or less. Therefore, it can be seen that good reliability for the operation of the TFT can be obtained.
- the TFT substrate 200 of the second embodiment described above has the back channel etch type pixel TFT 301, an etching stopper in which an etching stopper layer of a silicon oxide film is provided between the channel layer and the interlayer insulating film. It is good also as a structure which has a type TFT.
- a protective insulating film made of a silicon oxide film having a thickness of 10 to 300 nm is disposed on the channel layer 7 and used as an etching stopper layer. Also good. Note that the conditions for forming the protective insulating film are the same as those in Embodiment Mode 1.
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Abstract
Description
実施の形態1に係るTFT基板は、スイッチングデバイスとして薄膜トランジスタ(Thin Film Transistor)が用いられたアクティブマトリックス基板であるものとして説明する。
図1は、本発明に係る実施の形態1のTFT基板の全体構成を模式的に説明する平面図であり、ここでは、LCD用のTFT基板を例に採っている。
次に、図2および図3を参照して、実施の形態1のTFT基板、より具体的にはボトムゲート型の薄膜トランジスタ基板の構成について説明する。なお、本発明はTFT基板に関するものであるが、特に画素の構成に特徴を有するので、以下においては画素の構成について説明する。図2は、図1に示した画素204の平面構成を示す平面図であり、図3は、図2におけるA-A線での断面構成(TFT部、画素部、補助容量部の断面構成)、B-B線での断面構成(ゲート端子部の断面構成)およびC-C線での断面構成(ソース端子部の断面構成)を示す断面図である。なお、以下においてTFT基板200は透過型の液晶表示装置に用いるものとして説明する。
次に、本発明に係る実施の形態1のTFT基板の製造方法について、製造工程を順に示す断面図である図4~図8を用いて説明する。なお、図4~図8は、図3に示す断面図に対応する断面図であり、図3は最終工程を示す断面図に相当する。また、図9は本発明の実施の形態1のTFT基板の製造方法の手順を示すフローチャートであり、以下、図4~図8を参照しつつ、図9にステップS1001~ステップS1010で示されるフローチャートに沿って説明する。
以上説明した実施の形態1のTFT基板200においては、バックチャネルエッチ型の画素TFT201を有していたが、チャネル層と層間絶縁膜の間に酸化シリコン膜のエッチングストッパ層を設けた、エッチングストッパ型のTFTを有する構成としても良い。
<TFT基板の全体構成>
図23は、本発明に係る実施の形態2のTFT基板の全体構成を模式的に説明する平面図である、なお、図1を用いて説明したTFT基板と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図24および図25を参照して本発明に係る実施の形態2のTFT基板、より具体的にはデュアルゲート型の薄膜トランジスタ基板の構成について説明する。なお、本発明はTFT基板に関するものであるが、特に画素の構成に特徴を有するので、以下においては画素の構成について説明する。図24は、図23に示した画素304の平面構成を示す平面図であり、図25は、図24におけるA-A線での断面構成(TFT部、画素部、補助容量部の断面構成)、B-B線での断面構成(ゲート端子部の断面構成)およびC-C線での断面構成(ソース端子部の断面構成)を示す断面図である。なお、図2および図3を用いて説明した画素204と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、本発明に係る実施の形態2のTFT基板の製造方法について、製造工程を順に示す断面図である図26~図30を用いて説明する。なお、図26~図30は、図25に示す断面図に対応する断面図であり、図25は最終工程を示す断面図に相当する。また、図31は本発明の実施の形態1のTFT基板の製造方法の手順を示すフローチャートであり、以下、図26~図30を参照しつつ、図31にステップS2001~ステップS2011で示されるフローチャートに沿って説明する。なお、図4~図8を用いて説明した実施の形態1のTFT基板の製造方法と重複する説明は省略する。
以上説明した実施の形態2のTFT基板200においては、バックチャネルエッチ型の画素TFT301を有していたが、チャネル層と層間絶縁膜の間に酸化シリコン膜のエッチングストッパ層を設けた、エッチングストッパ型のTFTを有する構成としても良い。
Claims (13)
- 画素がマトリックス状に複数配列された薄膜トランジスタ基板であって、
前記画素は、
基板上に配設された金属で構成されるゲート電極と、
少なくとも前記ゲート電極を覆うゲート絶縁膜と、
前記ゲート絶縁膜を間に介して、前記ゲート電極に対向する位置に設けられた酸化物半導体で構成される半導体層と、
前記半導体層に接するソース電極およびドレイン電極と、
少なくとも前記半導体層、前記ソース電極および前記ドレイン電極の上に設けられた層間絶縁膜と、を有する薄膜トランジスタと、
前記ドレイン電極に電気的に接続される画素電極と、を備え、
前記ゲート電極は、
2.5×1020~2×1022atoms/cm3の水素吸蔵能力を有し、
前記半導体層は、
水素濃度が1×1016~3×1020atoms/cm3であることを特徴とする薄膜トランジスタ基板。 - 前記酸化物半導体が、少なくともインジウム、ガリウム、亜鉛を含む金属酸化物であることを特徴とする請求項1に記載の薄膜トランジスタ基板。
- 前記薄膜トランジスタは、
前記層間絶縁膜を間に介して前記半導体層の上方に設けられ、前記ゲート電極と異なる電位、または前記ゲート電極と共通の電位が与えられる、金属で構成された制御電極、を有し、
前記制御電極は、
2.5×1020~2×1022atoms/cm3の水素吸蔵能力を有する、請求項1記載の薄膜トランジスタ基板。 - 前記ゲート絶縁膜は、
SiN膜上にSiO膜を積層した積層膜で構成され、
前記SiN膜中の水素濃度は3×1021atoms/cm3以下である、請求項1または請求項3記載の薄膜トランジスタ基板。 - 前記ゲート電極は、Al合金およびNを含む、請求項1記載の薄膜トランジスタ基板。
- 前記ゲート電極は、
AlNiNd膜上にAlNiNdN膜を積層した積層膜で構成される、請求項5記載の薄膜トランジスタ基板。 - 前記ゲート電極および前記制御電極は、Al合金およびNを含む、請求項3記載の薄膜トランジスタ基板。
- 前記ゲート電極は、
AlNiNd膜上にAlNiNdN膜を積層した積層膜で構成され、
前記制御電極は、
AlNiNdN膜上にAlNiNd膜を積層した積層膜で構成される、請求項7記載の薄膜トランジスタ基板。 - 前記薄膜トランジスタは、
前記半導体層上を覆う保護絶縁膜をさらに有し、
前記ソース電極および前記ドレイン電極は、前記保護絶縁膜を貫通するコンタクトホールを介して前記半導体層に接する、請求項1記載の薄膜トランジスタ基板。 - 画素がマトリックス状に複数配列された薄膜トランジスタ基板の製造方法であって、
(a)前記基板上に第1の金属膜を形成し、パターニングしてゲート電極を形成する工程と、
(b)前記ゲート電極を覆うように前記基板上にゲート絶縁膜を形成する工程と、
(c)前記ゲート絶縁膜上に酸化物半導体膜を形成し、パターニングして前記ゲート電極に対向する位置に半導体層を形成する工程と、
(d)前記半導体層上を含めて前記ゲート絶縁膜上に第2の金属膜を形成し、パターニングして前記半導体層に接するソース電極およびドレイン電極を形成する工程と、
(e)少なくとも前記半導体層、前記ソース電極および前記ドレイン電極の上に層間絶縁膜13を形成する工程と、
(f)前記層間絶縁膜上に透明導電膜を形成し、パターニングして前記ドレイン電極に電気的に接続される画素電極を形成する工程と、を備え、
前記工程(c)は、
前記半導体層の形成後に、大気以上の酸素濃度の酸素を含む雰囲気下で1回目の熱処理を行う工程を含み、
前記工程(d)は、
前記第2の金属膜の形成後に、大気以上の酸素濃度の酸素を含む雰囲気下で2回目の熱処理を行う工程を含み、
前記工程(e)は、
前記層間絶縁膜として、下層膜と上層膜との積層膜を形成する工程と、
前記下層膜の形成後に、大気以上の酸素濃度の酸素を含む雰囲気下で3回目の熱処理を行う工程とを含み、
前記工程(f)は、
前記画素電極の形成後に、大気以上の酸素濃度の酸素を含む雰囲気下で4回目の熱処理を行う工程を含む、ことを特徴とする薄膜トランジスタ基板の製造方法。 - 前記酸素濃度は、20%以上である請求項10記載の薄膜トランジスタ基板の製造方法。
- 前記工程(a)は、
前記第1の金属膜を、AlNiNd膜上にAlNiNdN膜を積層した積層膜で形成する工程を含む、請求項10記載の薄膜トランジスタ基板の製造方法。 - 前記工程(e)の後、
前記層間絶縁膜上に、AlNiNdN膜上にAlNiNd膜を積層した積層膜の第2の金属膜を形成し、パターニングして前記半導体層の上方に対応する位置に前記ゲート電極と異なる電位、または前記ゲート電極と共通の電位が与えられる制御電極を形成する工程を備える、請求項12記載の薄膜トランジスタ基板の製造方法。
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