WO2017049840A1 - 一种具有高电源抑制比的带隙基准电压源 - Google Patents

一种具有高电源抑制比的带隙基准电压源 Download PDF

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WO2017049840A1
WO2017049840A1 PCT/CN2016/073580 CN2016073580W WO2017049840A1 WO 2017049840 A1 WO2017049840 A1 WO 2017049840A1 CN 2016073580 W CN2016073580 W CN 2016073580W WO 2017049840 A1 WO2017049840 A1 WO 2017049840A1
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voltage
circuit
drain
gate
source
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PCT/CN2016/073580
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English (en)
French (fr)
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吴建辉
吴爱东
林志伦
杜媛
姚芹
李红
陈超
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东南大学
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices

Definitions

  • the present invention relates to a reference voltage source for a radio frequency, digital to analog hybrid circuit, and more particularly to a bandgap reference voltage source having a high power supply rejection ratio.
  • the reference voltage source has become an indispensable basic circuit module in digital analog circuits, and is widely used in communication circuits, memories, sensors and other fields.
  • the role of the reference voltage source is mainly to provide a stable reference voltage to other modules in the circuit.
  • the stability of the reference voltage source is directly related to the operating state of the circuit and the performance of the circuit.
  • the reference voltage source should have the advantages of stable output, strong anti-interference ability, small temperature coefficient, etc.
  • the commonly used reference voltage source mainly has Zener diode voltage source and band. There are two kinds of gap reference voltage sources. Because of the non-surface band gap mechanism, the bandgap reference voltage source has better stability and wider application range.
  • the bandgap reference is usually implemented in a bipolar device.
  • the base-emitter voltage VBE of the bipolar transistor is a negative temperature coefficient and is biased at two different current densities. Set, the difference between the two base-emitter voltages ⁇ VBE is the amount of positive temperature coefficient. Combining VBE and ⁇ VBE in a certain ratio will produce a voltage with a near zero temperature coefficient, which is the bandgap reference voltage.
  • the design requires that the bandgap reference voltage be approximately 1.25V to 10V.
  • the bandgap reference voltage is inevitably affected by the noise of the op amp, power supply, and resistor, which limits the application of the bandgap reference voltage supply in the high-precision field.
  • the power supply rejection ratio of the reference power supply is the ratio of the input power supply variation to the output voltage variation. This parameter reflects how much the noise signal produces correspondingly in the output signal. The higher the power supply rejection ratio, the stronger the circuit's suppression of noise. In high-speed, high-accuracy applications, the power supply rejection ratio of the bandgap reference is required to suppress the effects of noise signals on the output signal.
  • the traditional single bandgap reference voltage source is mainly suppressed by the error amplifier in the circuit for the low frequency noise signal, and is mainly suppressed by the RC filter for the high frequency noise signal, and the loop width and the output are reduced for the suppression of the noise of the intermediate frequency.
  • the RC bandwidth which causes the power consumption of the bandgap reference to increase, the structure is more complicated, and the manufacturing process is more demanding.
  • a reference voltage source having low power consumption, high power supply rejection ratio, stable performance, and simple structure is provided.
  • the present invention provides a bandgap reference voltage source having a high power supply rejection ratio, which is adopted.
  • the voltage self-regulating circuit suppresses the power supply noise for the first time, and inputs the suppressed voltage signal as a power signal into the first-order temperature-compensated reference voltage generating circuit, and the first-order temperature-compensated reference voltage generating circuit suppresses the power supply noise for the second time.
  • the invention combines the voltage self-adjusting technology and the bandgap reference voltage source temperature compensation technology to effectively improve the power supply rejection ratio of the bandgap reference voltage source, so that the bandgap reference voltage source can be adapted to high precision application requirements.
  • the present invention provides a bandgap reference voltage source having a high power supply rejection ratio, including a DC voltage source Vdd, a first-order temperature compensation reference voltage generating circuit 3, and an error amplifier 4
  • the bias voltage generating circuit 5 and the reference starting circuit 6 further include a voltage self-regulating circuit 1 and a starting circuit 2; the DC voltage source Vdd supplies a power supply voltage to the bandgap reference voltage source; and the voltage self-regulating circuit 1 uses a DC voltage source
  • the voltage Vdd is used as the initial voltage signal, receives the bias voltage signal outputted by the bias voltage generating circuit 5, and first suppresses the noise in the initial voltage according to the bias voltage signal to generate a first suppression signal, and the first suppression is performed.
  • the signals are input to the first-order temperature compensation reference voltage generating circuit 3, the error amplifier 4, the bias voltage generating circuit 5, and the power supply voltage signal input terminal of the reference starting circuit 6, respectively; the starting circuit 2 uses the DC voltage source voltage Vdd as the starting voltage.
  • the signal is simultaneously connected to the voltage self-regulating circuit 1 and the bias voltage generating circuit 5, respectively, when the voltage self-regulating circuit 1 operates When the voltage self-regulating circuit 1 stops working, the starting circuit 2 is turned on, and the control voltage starts to operate from the adjusting circuit 1; the first-order temperature compensating reference voltage generating circuit 3 is connected to the error amplifier 4 to the error amplifier.
  • the first-order temperature-compensated reference voltage generating circuit 3 is simultaneously connected to the reference starting circuit 6, receives the reference starting current signal output from the reference starting circuit 6, and inputs a starting bias signal to the reference starting circuit 6; the error amplifier 4 and the bias voltage are generated.
  • the circuit 5 is connected to input a voltage adjustment signal to the bias voltage generating circuit 5.
  • the voltage self-regulating circuit 1 includes: PMOS transistors MP1a, MP2, MP3 and NMOS transistors MN1a, MN1b, MN2; wherein the sources of MP1a and MP2 are connected, and the connection point thereof is connected to the DC power source Vdd; the gate of the MP1a Connected to the gate of MP2, while the gate of MP1a is connected to the drain, the drain of MP1a is connected to the drain of MN1a; the drain of MP2 is connected to the source of MP3, and the connection point is used as the voltage self-regulating circuit 1.
  • the connection point is simultaneously connected to the drain of the MN2; the gate of the MP3 is used as a second bias signal input end of the voltage self-regulating circuit 1, and the drain of the MP3 is connected to the gate of the MN2 and simultaneously The drains of MN1b are connected; the sources of MN2, MN1a, MN1b are grounded; the gates of MN1a and MN1b are connected, and the connection point is used as the first bias signal input terminal of voltage self-regulating circuit 1; a bias signal input and a second The bias signal input terminal is connected to the bias voltage generating circuit 5, and receives the first bias voltage signal and the second bias voltage signal output from the bias voltage generating circuit 5.
  • the voltage self-regulating circuit 1 further includes a feedback loop including: PMOS transistors MP1b, MP12 and NMOS transistors MN3a and MN3b; the sources of MP1b and MP12 are both connected to the DC power supply Vdd, and the gate of the MP1b
  • the gate of MP1a is connected, the drain of MP1b is connected to the drain of MN3a and connected to the gate of MN3a; the gate of MN3a is connected to the gate of MN3b, the source of MN3a is connected to the source of MN3b, and the connection point is connected with MP2 and MN2.
  • the drain is connected; the drain of MN3b is connected to the gate of MP2 and is connected to the gate and drain of MP12; MP12 and MP3b form a feedback amplifier, MP1b and MN3a provide bias current for MN3b; feedback loop regulates voltage
  • the change of the output current of the circuit 1 is controlled within a certain range, and the rear stage circuit is prevented from malfunctioning due to a sudden change of the input current.
  • the starting circuit 2 comprises NMOS transistors MN4, MN5 and a resistor R1; one end of R1 is connected to a DC power source Vdd, the other end is connected to the gate of MN5, and the gate of MN5 is simultaneously connected to the drain of MN4, MN5
  • the drain is connected to the drain connection point of MP1a and MN1a in the voltage self-regulating circuit (1), the source of MN5 is grounded, and the gate of MN4 is connected to the first bias signal input end of the voltage self-regulating circuit (1), MN4 The source is grounded.
  • the first-order temperature-compensated reference voltage generating circuit 3 includes: PMOS transistors MP4a, MP4b, MP6, MP7, resistors R2, R3a, R3b, R4 and NPN tubes Q1, Q2, Q3; MP4a, MP4b, MP6, MP7
  • the source is connected, and the connection point is the first input end of the first-order temperature compensation reference voltage generating circuit 3 receives the first suppression signal output from the voltage self-regulating circuit 1; the gates of the MP4a, MP4b, and MP6 are connected, and the connection point thereof
  • the third input end of the first-order temperature compensation reference voltage generating circuit 3 receives the voltage adjustment signal output by the error amplifier 4, and the voltage adjustment signal is converted into a current of zero temperature coefficient by MP4a, MP4b, MP6, and then generated by the resistor R4.
  • a drain of the MP4a is connected to the non-inverting input terminal of the error amplifier 4, and a connection point is a third output end of the first-order temperature-compensated reference voltage generating circuit 3 connected to the non-inverting input terminal of the error amplifier 4, MP4a
  • the drain is connected to the resistors R3a and R2 at the same time, the other end of the R3a is grounded, the other end of the R2 is connected to the collector of the NPN tube Q1; the collector of Q1 is connected to the base, the emitter is grounded; the drain of the MP4b is The inverting input terminal of the error amplifier 4 is connected, and the connection point is the fourth output end of the first-order temperature compensation reference voltage generating circuit 3 is connected to the inverting input terminal of the error amplifier 4, the drain of the MP4b and the NPN tube Q2 The collector is connected, the collector of Q2 is connected to the base, the emitter is grounded, the drain of MP4b is connected to one end of the resistor R3b,
  • the reference start current signal outputted by the start circuit 6 is connected to the other end of the R3b, the drain of the MP4b is connected to the base of the NPN transistor Q3; the drain of the MP6 is passed The resistor R4 is grounded, and the connection point of MP6 and R4 is the fifth output end of the first-order temperature-compensated reference voltage generating circuit 3 as the reference voltage output end of the bandgap reference voltage source; the base of the MP7 is connected to the drain a connection point is a first output end of the first-order temperature-compensated reference voltage generating circuit 3, and a start bias signal is outputted to the start-up circuit 6.
  • the drain of the MP7 is connected to the collector of the NPN transistor Q3, and the connection point is the one.
  • the second output of the step temperature compensation reference voltage generating circuit 3 supplies power to the error amplifier 4, and the emitter of Q3 is grounded.
  • the error amplifier 4 comprises PMOS transistors MP10a, MP10b, MP11a, MP11b, NPN transistors Q4, Q5, NMOS transistors MN7a, MN7b, MN8a, MN8b and capacitor C1; the sources of MP10a, MP10b, MP11a, MP11b are connected, and connected
  • the first input terminal of the error amplifier 4 receives the first suppression signal outputted by the voltage self-regulating circuit 1 as a power supply voltage;
  • the gates of the MP10a, MP10b are connected, and the connection point thereof receives the first-order temperature as the second input terminal of the error amplifier 4 Compensating the supply voltage outputted by the reference voltage generating circuit 3;
  • the drain of the MP10a is connected to the collector of the NPN transistor Q4 and is connected to the drain of the NMOS transistor MN8b;
  • the drain of the MP10b is connected to the collector of the NPN transistor Q5, and simultaneously with the NMOS
  • the drains of the tubes MN7a are
  • MP11a and MP11b The poles are connected, the gate and drain of MP11a are connected, and the drain of MP11a is connected to the drain of MN8b; the drain of MP11b is connected to the drain of MN7b, and the connection point is used as the output of error amplifier 4; MN8b and MN7b The source is grounded; one end of the capacitor C1 is connected to the drain of the MN7b, and the other end is grounded.
  • the bias voltage generating circuit 5 comprises: PMOS transistors MP5, MP13, NMOS transistor MN6 and resistor R6; the source of the MP5 is connected to the source of the MP13, and the connection point thereof serves as the first input terminal of the voltage generating circuit 5.
  • the gate of the MP5 is connected to the gate of the MP13, and the connection point thereof is connected as the second input terminal of the bias voltage generating circuit 5 to the output terminal of the error amplifier 4;
  • the drain is connected to the drain of the MN6, and the connection point serves as a first output end of the voltage generating circuit 5 to output a first bias voltage signal to the voltage self-regulating circuit 1;
  • the drain of the MN6 is connected to the gate, and the source of the MN6 is grounded;
  • the drain of MP13 is grounded through R6, and the junction of MP13 and R6 serves as a second output of voltage generating circuit 5 to output a second bias voltage signal to voltage self-regulating circuit 1.
  • the reference starting circuit 6 includes PMOS transistors MP8, MP9 and a resistor R5; the sources of MP8 and MP9 are connected, and the connection point serves as a first input of the reference starting circuit 6 to receive the first suppression of the voltage self-regulating circuit 1 output. a signal; the gate of the MP8 serves as a second input of the reference enable circuit 6 to receive a first-order temperature compensated reference voltage
  • the start bias signal outputted by the circuit 3 is generated; the drain of the MP8 is grounded through R5; the gate of the MP9 is connected to the contacts of the MP8 and R5, and the drain of the MP9 is used as the output of the reference start circuit 6 to the first-order temperature compensated reference voltage generating circuit.
  • 3 Input the reference start current signal.
  • the present invention has the following advantages over a conventional reference voltage source:
  • the invention adopts a design mode combining a voltage self-regulating circuit and a first-order temperature-compensated reference voltage generating circuit, and can suppress the power supply noise twice, so that the power supply rejection ratio of the bandgap reference power supply voltage is greatly improved;
  • the voltage self-regulating circuit has a feedback loop, which can automatically adjust the magnitude of the output current, and solves the problem that the sudden increase of the current required by the latter circuit causes instability of the entire circuit and increases the stability of the circuit;
  • the voltage self-regulating circuit can be applied not only to the first-order temperature-compensated bandgap reference generating circuit used in the present invention, but also to other bandgap reference generating circuits, and has strong compatibility;
  • the first-order temperature-compensated bandgap reference voltage source of the present invention adopts a parasitic NPN tube and can be realized in a CMOS process; the current mode structure is adopted, which is suitable for operation under a low power supply voltage, and has the advantages of low power consumption.
  • Figure 1 is a structural view of the present invention
  • FIG. 2 is a schematic diagram of an overall circuit topology according to an embodiment of the present invention.
  • FIG. 3 is a circuit topology diagram of a startup circuit and a voltage self-regulating circuit that does not include a feedback loop;
  • FIG. 4 is a circuit topology diagram including a feedback loop in a startup circuit and a voltage self-regulating circuit
  • Figure 5 is a circuit topology diagram of the error amplifier
  • FIG. 6 is a simulation diagram of a suppression effect of power supply noise by a conventional bandgap reference voltage source and a bandgap reference voltage source having a high power supply rejection ratio provided by the present invention.
  • the bandgap reference voltage source having a high power supply rejection ratio includes a DC voltage source Vdd, a first-order temperature compensation reference voltage generating circuit 3, an error amplifier 4, and a bias voltage generating circuit. 5 and the reference starting circuit 6, further comprising a voltage self-regulating circuit 1 and a starting circuit 2;
  • the DC voltage source Vdd provides a power supply voltage for the bandgap reference voltage source;
  • the voltage self-regulating circuit 1 uses the DC voltage source voltage Vdd as a starting voltage a signal, receiving the bias voltage signal output by the bias voltage generating circuit 5, first suppressing the noise in the initial voltage according to the bias voltage signal to generate a first suppression signal, and inputting the first suppression signal into the first-order temperature Compensation reference voltage a generating circuit 3, an error amplifier 4, a bias voltage generating circuit 5, and a power supply voltage signal input terminal of the reference starting circuit 6;
  • the starting circuit 2 uses a DC voltage source voltage Vdd as a starting voltage signal, and a voltage self-regulating circuit 1 is
  • Embodiment 1 The circuit structure of the voltage self-regulating circuit 1 and the starting circuit 2 is as shown in FIG. 3:
  • the voltage self-regulating circuit 1 includes PMOS transistors MP1a, MP2, MP3 and NMOS transistors MN1a, MN1b, MN2; wherein the sources of MP1a and MP2 are connected, and the connection point thereof is connected to the DC power source Vdd; the gate of MP1a and the gate of MP2 Connected, while the gate of MP1a is connected to the drain, the drain of MP1a is connected to the drain of MN1a; the drain of MP2 is connected to the source of MP3, and the connection point is used as the first suppression signal output of the voltage self-regulating circuit 1.
  • connection point is simultaneously connected to the drain of the MN2; the gate of the MP3 acts as the second bias signal input terminal of the voltage self-regulating circuit 1, and the drain of the MP3 is connected to the gate of the MN2 and is simultaneously connected to the drain of the MN1b.
  • the sources of MN2, MN1a, and MN1b are both grounded; the gates of MN1a and MN1b are connected, and the connection point thereof serves as the first bias signal input terminal of the voltage self-regulating circuit 1; the voltage self-regulating circuit 1 is input through the first bias signal.
  • the terminal and the second bias signal input terminal are connected to the bias voltage generating circuit 5, and receive the first bias voltage signal and the second bias voltage signal output from the bias voltage generating circuit 5.
  • the starting circuit 2 includes: NMOS transistors MN4, MN5 and a resistor R1; one end of R1 is connected to a DC power supply Vdd, the other end is connected to the gate of MN5, the gate of MN5 is simultaneously connected to the drain of MN4, and the drain and voltage of MN5 are connected.
  • the drain connection point of MP1a and MN1a in the self-regulating circuit 1 is connected, the source of MN5 is grounded, the gate of MN4 is connected to the first bias signal input terminal of the voltage self-regulating circuit 1, and the source of MN4 is grounded.
  • the preferred design of the first-order temperature-compensated reference voltage generating circuit 3, the error amplifier 4, the bias voltage generating circuit 5, and the reference starting circuit 6 is as shown in FIG. 2:
  • the first-order temperature-compensated reference voltage generating circuit 3 includes PMOS transistors MP4a, MP4b, MP6, and MP7, resistors R2, R3a, R3b, and R4 and NPN tubes Q1, Q2, and Q3; and sources of MP4a, MP4b, MP6, and MP7 are connected and connected.
  • the first input terminal of the first-order temperature compensation reference voltage generating circuit 3 receives the voltage from the regulating circuit 1
  • the first suppression signal is output; the gates of MP4a, MP4b, and MP6 are connected, and the connection point is a voltage adjustment signal output by the third amplifier receiving the error amplifier 4 of the first-order temperature compensation reference voltage generating circuit 3, and the voltage adjustment is performed.
  • the signal is converted into a current of zero temperature coefficient by MP4a, MP4b, MP6, and then a reference voltage is generated through the resistor R4; the drain of the MP4a is connected to the non-inverting input terminal of the error amplifier 4, and the connection point is the first-order temperature compensation reference
  • the third output terminal of the voltage generating circuit 3 is connected to the non-inverting input terminal of the error amplifier 4, the drain of the MP4a is simultaneously connected to the resistors R3a and R2, the other end of the R3a is grounded, and the other end of the R2 is connected to the collector of the NPN transistor Q1; Q1
  • the collector is connected to the base and the emitter is grounded; the drain of the MP4b is connected to the inverting input of the error amplifier 4, and the connection point is the fourth output of the first-order temperature-compensated reference voltage generating circuit 3 and
  • the inverting input terminal of the error amplifier 4 is connected, the drain of the MP4b is connected to the collector of the NPN transistor Q2, the
  • connection point is the second input end of the first-order temperature compensation reference voltage generating circuit 3 receives the reference starting current signal output by the reference starting circuit 6, the other end of R3b is grounded, the drain of MP4b and the base of the NPN tube Q3 Connected; the drain of MP6 is grounded through a resistor R4, and the connection point of MP6 and R4 is the fifth output end of the first-order temperature-compensated reference voltage generating circuit 3 as a reference voltage output terminal of the bandgap reference voltage source; MP7
  • the base is connected to the drain, and the connection point is that the first output end of the first-order temperature compensation reference voltage generating circuit 3 outputs a start bias signal to the start circuit 6, and the drain of the MP7 is connected to the collector of the NPN tube Q3.
  • the connection point is that the second output end of the first-order temperature compensation reference voltage generating circuit 3 supplies power to the error amplifier 4, and the emitter of Q3 is grounded.
  • the error amplifier 4 includes PMOS transistors MP10a, MP10b, MP11a, MP11b, NPN transistors Q4, Q5, NMOS transistors MN7a, MN7b, MN8a, MN8b and capacitor C1; the sources of MP10a, MP10b, MP11a, MP11b are connected, and the connection point is used as an error.
  • the first input terminal of the amplifier 4 receives the first suppression signal outputted by the voltage self-regulating circuit 1 as a power supply voltage; the gates of the MP10a and MP10b are connected, and the connection point thereof receives the first-order temperature compensation reference voltage as the second input terminal of the error amplifier 4
  • the output voltage of the output of the circuit 3 is generated; the drain of the MP10a is connected to the collector of the NPN transistor Q4 and is connected to the drain of the NMOS transistor MN8b; the drain of the MP10b is connected to the collector of the NPN transistor Q5, and simultaneously with the NMOS transistor MN7a
  • the drain is connected; the NPN transistors Q4 and Q5 are connected to the common emitter, and the connection point is grounded, the base of Q4 is used as the inverting input terminal of the error amplifier 4, the base of Q5 is used as the non-inverting input terminal of the error amplifier 4; the drain of the MN7a
  • the pole is connected to the gate, the source of MN7a is grounded, the
  • the bias voltage generating circuit 5 includes: a PMOS transistor MP5, an MP13, an NMOS transistor MN6 and a resistor R6; a source of the MP5 is connected to a source of the MP13, and a connection point thereof is used as a first input terminal of the voltage generating circuit 5 to receive a voltage self-regulating circuit.
  • the gate of MP5 is connected to the gate of MP13, and the connection point thereof is connected as the second input terminal of the bias voltage generating circuit 5 to the output terminal of the error amplifier 4;
  • the drain of the MP5 is connected to the MN6 The drain is connected, and the connection point serves as a first output end of the voltage generating circuit 5 to output a first bias voltage signal to the voltage self-regulating circuit 1;
  • a drain of the MN6 is connected to the gate, a source of the MN6 is grounded; and a drain of the MP13 passes R6 is grounded, and the contact of MP13 and R6 serves as a second output terminal of the voltage generating circuit 5 to output a second bias voltage signal to the voltage self-regulating circuit 1.
  • the reference starting circuit 6 includes PMOS transistors MP8, MP9 and a resistor R5; the sources of MP8 and MP9 are connected, and the connection point serves as a first input terminal of the reference starting circuit 6 to receive a first suppression signal output by the voltage self-regulating circuit 1; a gate of the MP8
  • the second input terminal of the reference start circuit 6 receives the start bias signal output by the first-order temperature compensation reference voltage generating circuit 3; the drain of the MP8 is grounded through R5; the gate of the MP9 is connected to the contacts of the MP8 and R5, and the MP9 is drained.
  • the pole serves as an output terminal of the reference start circuit 6 to input a reference start current signal to the first-order temperature compensation reference voltage generating circuit 3.
  • the first-order temperature-compensated reference voltage generating circuit is directly powered by the DC power source Vdd, and the power supply noise is assumed to be an AC small signal, which is expressed as VaVdd.
  • the output noise signal generated at the output of the bandgap reference is Vavf, and the power supply rejection ratio PSRR can be obtained.
  • Vf is the output signal of the error amplifier 4, representing the voltage change of the PMOS transistors MP4a and MP4b due to the power supply noise VaVdd
  • Va is the magnitude of the voltage change of the non-inverting input terminal of the error amplifier
  • Vb is the error The magnitude of the voltage change at the inverting input of the amplifier
  • Add indicates the power supply rejection capability of the error amplifier (small signal gain from the power supply to the output of the amplifier)
  • gm6 indicates the transconductance of the PMOS transistor MP6, and gm4 indicates the overall PMOS transistor MP4a and MP4b. Transconductance, where gm6 and gm4 are equal;
  • RQ1 and RQ2 are the equivalent resistances of NPN transistors Q1 and Q2, respectively. make
  • Equation 2 the power supply rejection ratio PSRR of the bandgap reference voltage source excluding the voltage self-regulating circuit 1 can be obtained, and the expression is:
  • the voltage self-regulating circuit 1 suppresses the power supply noise Vavdn for the first time, and according to FIG. 3, the following formula can be obtained:
  • Vregn is the noise signal outputted by the voltage self-regulating circuit 1
  • Vn is the voltage change value of the gate of the PMOS transistor MP2 due to the power supply noise
  • Ax represents the gain of the power supply noise Vavdn to the gate voltage change of the MP2, and Ax is close.
  • a constant of 1 gm2 is the transconductance of the PMOS transistor MP2
  • Vreg is the output voltage of the input DC voltage Vdd at the voltage self-regulating circuit
  • Rregn is the equivalent output resistance seen from the output terminal of the voltage self-regulating circuit 1.
  • Rregn is approximately Where gnm2 is the transconductance of the NMOS transistor MN2, and the value of Rregn is brought into the equation 5
  • Equation 6 Bringing Equation 6 into Equation 1 can result in a bandgap reference with a voltage self-regulating circuit 1.
  • the power supply rejection ratio PSRR_H is expressed as:
  • the power supply rejection of the bandgap reference voltage source with the voltage self-regulating circuit 1 is much larger than the PSRR_H than the previously derived first-order temperature-compensated reference voltage generating circuit without the voltage self-regulating circuit 1.
  • the power supply rejection ratio that is, the bandgap reference voltage source including the voltage self-regulating circuit 1 is more resistant to power supply noise.
  • Embodiment 2 According to the bandgap reference voltage source of Embodiment 1, the voltage self-regulating circuit 1 further includes a feedback circuit, as shown in FIG. 4, comprising: PMOS transistors MP1b, MP12 and NMOS transistors MN3a and MN3b; MP1b and The source of MP12 is connected to DC power supply Vdd, the gate of MP1b is connected to the gate of MP1a, the drain of MP1b is connected to the drain of MN3a and connected to the gate of MN3a; the gate of MN3a is connected to the gate of MN3b.
  • a feedback circuit as shown in FIG. 4, comprising: PMOS transistors MP1b, MP12 and NMOS transistors MN3a and MN3b; MP1b and The source of MP12 is connected to DC power supply Vdd, the gate of MP1b is connected to the gate of MP1a, the drain of MP1b is connected to the drain of MN3a and connected to the gate of MN3a; the
  • MN3a is connected to the source of MN3b and the connection point is connected to the drains of MP2 and MN2; the drain of MN3b is connected to the gate of MP2 and is connected to the gate and drain of MP12; wherein MP12 and MP3b form a feedback amplifier, MP1b and MN3a provide bias current for MN3b; the feedback loop controls the change of the output current of the voltage self-regulating circuit 1 within a certain range, so as to prevent the latter circuit from malfunctioning due to sudden changes of the input current.
  • the current output from the output of the voltage self-regulating circuit 1 becomes large due to the particularly large noise interference of the subsequent stage circuit, particularly the first-order temperature-compensated reference voltage generating circuit.
  • the circuit does not include the above feedback loop, the circuit is as shown in FIG. 3.
  • the drain of the PMOS transistor MP2 outputs a fixed current, and the voltage Vreg at the output of the voltage self-regulating circuit 1 becomes smaller.
  • the smaller Vreg causes the branch current of the NMOS transistor MN2 to become smaller, causing the tube to enter the linear region.
  • the circuit of the latter stage, especially the first-order temperature-compensated reference voltage generating circuit may not work properly due to the voltage at the Vreg output becoming smaller.
  • the circuit when the circuit includes a feedback loop, the circuit is as shown in FIG. 4.
  • the feedback loop can further reduce the output impedance of the Vreg output and improve the power supply rejection ratio.
  • Figure 6 shows a comparison of the two power supply rejection ratios.
  • the former is a waveform diagram of the noise suppression effect of the bandgap reference voltage source without a voltage self-regulating circuit
  • the latter is a waveform diagram of the noise suppression effect of the present invention. It can be seen that the bandgap reference with a voltage self-regulating circuit has a higher power supply rejection ratio.
  • a typical bandgap reference power supply rejection ratio is about 72.29 dB at low frequencies and about 62.34 dB at 1 kHz.
  • the bandgap reference voltage source power supply rejection ratio proposed by the present invention is about 139.5 dB at a low frequency, which is 67.21 dB higher than the former; and about 120.4 dB at 1 kHz, which is 58.06 dB higher than the former.

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Abstract

一种具有高电源抑制比的带隙基准电压源，包括电压自调节电路（1），启动电路（2），一阶温度补偿基准电压产生电路（3），误差放大器（4），偏置电压产生电路（5）和基准启动电路（6）。该带隙基准电压源利用电压自调节电路（1）对电源噪声先进行一定程度的抑制，再给后级的带隙基准电路提供电源，带隙基准电路对噪声进行进一步抑制，从而使整个电源具有很高的电源抑制比。此外，该自调节电路（1）还具有一个反馈回路，能自动调节输出电流的大小，解决了由于后级电路所需的电流突然增大给整个电路造成不稳定的问题，同时可进一步提高带隙基准电压源的电源抑制比，相比于传统带隙基准电压源稳定性更好，电源抑制比更高，可适应高精度的工作要求。

Description

一种具有高电源抑制比的带隙基准电压源 技术领域
本发明涉及用于射频、数模混合电路的基准电压源，尤其是一种具有高电源抑制比的带隙基准电压源。
背景技术
随着系统集成技术的快速发展，基准电压源已成为数字模拟电路中不可缺少的基本电路模块，广泛应用于通信电路、存储器、传感器等领域。基准电压源的作用主要在于向电路中的其他模块提供稳定的基准电压，基准电压源的稳定性直接关系到电路的工作状态及电路的性能。为了满足电路在不同外界环境下的正常工作要求，基准电压源应具有输出稳定、抗干扰能力强、温度系数小等优点，在现有技术中常用基准电压源主要有齐纳二极管电压源和带隙基准电压源两种，带隙基准电压源由于建立在非表面的带隙机理上，因此具有更好的稳定性，应用范围也更加广泛。
在一般的电路设计中，带隙基准电压源通常采用双极型器件来实现，双极型晶体管的基区-发射区电压VBE是一个负温度系数的电压量，在两个不同的电流密度偏置下，两个基区-发射区电压之差ΔVBE是正温度系数的量，将VBE与ΔVBE以一定的比例组合，会产生一个近零温度系数的电压，该电压就是带隙基准电压，根据不同的设计要求，带隙基准电压约为1.25V到10V。但是，带隙基准电压中不可避免的会受到运放、电源、电阻的噪声影响，限制了带隙基准电压电源在高精度领域的应用，为了解决这一问题，通常采用的方法为提高带隙基准电压电源的电源抑制比。电源抑制比是输入电源变化量与输出电压变化量的比值，这个参数反应了噪声信号在输出信号中相应产生多大变化量，电源抑制比越高，表示电路对噪声的抑制越强。在高速高精度的应用场合，需要带隙基准电压源的电源抑制比非常高，以抑制噪声信号对输出信号的影响。
传统的单独带隙基准电压源对于低频噪声信号主要通过电路中误差放大器来抑制，对于高频噪声信号主要通过RC滤波来抑制，而对于中频的噪声的抑制，则需要提高环路宽度和降低输出RC带宽，这样会导致带隙基准电压源的功耗增加，结构更加复杂，对其制作工艺的要求更高。
发明内容
发明目的：为解决上述技术问题，提供一种具有低功耗、高电源抑制比、性能稳定且结构简单的基准电压源，本发明提出一种具有高电源抑制比的带隙基准电压源，采用 电压自调节电路对电源噪声进行第一次抑制，并将抑制后的电压信号作为电源信号输入一阶温度补偿基准电压产生电路，一阶温度补偿基准电压产生电路对电源噪声进行第二次抑制，本发明通过将电压自调节技术与带隙基准电压源温度补偿技术相结合的方式，可有效提高带隙基准电压源的电源抑制比，使带隙基准电压源可以适应高精度的应用需求。
技术方案：为解决上述技术问题，实现上述技术效果，本发明提出一种具有高电源抑制比的带隙基准电压源，包括直流电压源Vdd、一阶温度补偿基准电压产生电路3、误差放大器4、偏置电压产生电路5和基准启动电路6，还包括电压自调节电路1和启动电路2；直流电压源Vdd为所述带隙基准电压源提供电源电压；电压自调节电路1以直流电压源电压Vdd作为起始电压信号，接收偏置电压产生电路5输出的偏置电压信号，根据偏置电压信号对起始电压中的噪声进行第一次抑制产生第一抑制信号，并将第一抑制信号分别输入一阶温度补偿基准电压产生电路3、误差放大器4、偏置电压产生电路5和基准启动电路6的电源电压信号输入端；所述启动电路2以直流电压源电压Vdd作为起始电压信号，同时分别与电压自调节电路1和偏置电压产生电路5相连，当电压自调节电路1工作时，启动电路2截止，当电压自调节电路1停止工作时，启动电路2导通，控制电压自调节电路1开始工作；一阶温度补偿基准电压产生电路3与误差放大器4相连，向误差放大器4提供放大器偏置电压信号，同时接收误差放大器4输出的电压调节信号，并将调节电压信号转化为零温度系数的电流，进而产生基准电压，基准电压作为所述带隙基准电压源的输出信号；一阶温度补偿基准电压产生电路3同时与基准启动电路6相连，接收基准启动电路6输出的基准启动电流信号，并向基准启动电路6输入启动偏置信号；误差放大器4与偏置电压产生电路5相连，向偏置电压产生电路5输入电压调节信号。
作为优选设计，电压自调节电路1包括：PMOS管MP1a、MP2、MP3和NMOS管MN1a、MN1b、MN2；其中，MP1a和MP2的源极相连，其连接点与直流电源Vdd相连；MP1a的栅极与MP2的栅极相连，同时MP1a的栅极与漏极相连，MP1a的漏极与MN1a的漏极相连；MP2的漏极与MP3的源极相连，连接点作为所述电压自调节电路1的第一抑制信号输出端，该连接点同时与MN2的漏极相连；MP3的栅极作为电压自调节电路1的第二偏置信号输入端，MP3的漏极与MN2的栅极相连并同时与MN1b的漏极相连；MN2、MN1a、MN1b的源极均接地；MN1a和MN1b的栅极相连，其连接点作为电压自调节电路1的第一偏置信号输入端；电压自调节电路1通过第一偏置信号输入端和第二 偏置信号输入端与偏置电压产生电路5相连，接收偏置电压产生电路5输出的第一偏置电压信号和第二偏置电压信号。
进一步的，所述电压自调节电路1还包括一个反馈回路，反馈回路包括：PMOS管MP1b、MP12和NMOS管MN3a和MN3b；MP1b和MP12的源极均与直流电源Vdd相连，MP1b的栅极与MP1a的栅极相连，MP1b的漏极与MN3a的漏极相连同时与MN3a的栅极相连；MN3a的栅极与MN3b的栅极相连，MN3a与MN3b的源极相连且连接点与MP2和MN2的漏极相连；MN3b的漏极与MP2的栅极相连同时与MP12的栅极和漏极相连；其中MP12和MP3b构成一个反馈放大器，MP1b和MN3a为MN3b提供偏置电流；反馈回路将电压自调节电路1输出电流的变化控制在一定范围内，避免后级电路因为输入的电流突然变化导致不能正常工作。
作为优选，所述启动电路2包括NMOS管MN4、MN5和电阻R1；R1的一端与直流电源Vdd相连，另一端与MN5的栅极相连，MN5的栅极同时与MN4的漏极相连，MN5的漏极与电压自调节电路(1)中MP1a和MN1a的漏极连接点相连，MN5的源极接地，MN4的栅极与电压自调节电路(1)的第一偏置信号输入端相连，MN4的源极接地。
作为优选，所述一阶温度补偿基准电压产生电路3包括：PMOS管MP4a、MP4b、MP6、MP7，电阻R2、R3a、R3b、R4和NPN管Q1、Q2、Q3；MP4a、MP4b、MP6、MP7的源极相连，连接点为所述一阶温度补偿基准电压产生电路3的第一输入端接收电压自调节电路1输出的第一抑制信号；MP4a、MP4b、MP6的栅极相连，其连接点为所述一阶温度补偿基准电压产生电路3的第三输入端接收误差放大器4输出的电压调节信号，该电压调节信号通过MP4a、MP4b、MP6转换为零温度系数的电流，进而通过电阻R4产生基准电压；MP4a的漏极与所述误差放大器4的同相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第三输出端与误差放大器4同相输入端相连，MP4a的漏极同时与电阻R3a和R2相连，R3a的另一端接地，R2的另一端与NPN管Q1的集电极相连；Q1的集电极与基极相连，发射极接地；MP4b的漏极与所述误差放大器4的反相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第四输出端与误差放大器4的反相输入端相连，MP4b的漏极与NPN管Q2的集电极相连，Q2的集电极与基极相连，发射极接地，MP4b的漏极与电阻R3b的一端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第二输入端接收基准启动电路6输出的基准启动电流信号，R3b的另一端接地，MP4b的漏极与NPN管Q3的基极相连；MP6的漏极通过 电阻R4接地，MP6与R4的连接点为所述一阶温度补偿基准电压产生电路3的第五输出端，作为所述带隙基准电压源的基准电压输出端；MP7的基极与漏极相连，其连接点为所述一阶温度补偿基准电压产生电路3的第一输出端向启动电路6输出启动偏置信号，MP7的漏极与NPN管Q3的集电极相连，连接点为所述一阶温度补偿基准电压产生电路3的第二输出端为误差放大器4供电，Q3的发射极接地。
作为优选，误差放大器4包括PMOS管MP10a、MP10b、MP11a、MP11b，NPN管Q4、Q5，NMOS管MN7a、MN7b、MN8a、MN8b和电容C1；MP10a、MP10b、MP11a、MP11b的源极相连，其连接点作为误差放大器4的第一输入端接收电压自调节电路1输出的第一抑制信号作为供电电压；MP10a、MP10b的栅极相连，其连接点作为误差放大器4的第二输入端接收一阶温度补偿基准电压产生电路3输出的供电电压；MP10a的漏极与NPN管Q4的集电极相连，同时与NMOS管MN8b的漏极相连；MP10b的漏极与NPN管Q5的集电极相连，同时与NMOS管MN7a的漏极相连；NPN管Q4和Q5为共射极连接，且连接点接地，Q4的基极作为误差放大器4的反相输入端，Q5的基极作为误差放大器4的同相输入端；MN7a的漏极与栅极相连，MN7a的源极接地，MN7a的栅极与MN7b的栅极相连；MN8a的漏极与栅极相连，MN8a的源极接地，MN8a的栅极与MN8b的栅极相连；MP11a与MP11b的栅极相连，MP11a的栅极和漏极相连，同时MP11a的漏极与MN8b的漏极相连；MP11b的漏极与MN7b的漏极相连，其连接点作为误差放大器4的输出端；MN8b和MN7b的源极接地；电容C1的一端与MN7b漏极相连，另一端接地。
作为优选，所述偏置电压产生电路5包括：PMOS管MP5、MP13，NMOS管MN6和电阻R6；MP5的源极与MP13的源极相连，其连接点作为电压产生电路5的第一输入端接收电压自调节电路1输出的第一抑制信号；MP5的栅极和MP13的栅极相连，其连接点作为偏置电压产生电路5的第二输入端与误差放大器4的输出端相连；MP5的漏极与MN6的漏极相连，连接点作为电压产生电路5的第一输出端向电压自调节电路1输出第一偏置电压信号；MN6的漏极与栅极相连，MN6的源极接地；MP13的漏极通过R6接地，MP13与R6的接点作为电压产生电路5的第二输出端向电压自调节电路1输出第二偏置电压信号。
作为优选，所述基准启动电路6包括PMOS管MP8、MP9和电阻R5；MP8和MP9的源极相连，连接点作为基准启动电路6的第一输入端接收电压自调节电路1输出的第一抑制信号；MP8的栅极作为基准启动电路6的第二输入端接收一阶温度补偿基准电压 产生电路3输出的启动偏置信号；MP8的漏极通过R5接地；MP9的栅极与MP8和R5的接点相连，MP9漏极作为基准启动电路6的输出端向一阶温度补偿基准电压产生电路3输入基准启动电流信号。
有益效果：相比于传统基准电压源，本发明具有以下优点：
1、本发明采用电压自调节电路与一阶温度补偿基准电压产生电路相结合的设计方式，对于电源噪声可以进行两次抑制，使带隙基准电源电压的电源抑制比大大提高；
2、该电压自调节电路具有一个反馈回路，能自动调节输出电流的大小，解决了由于后级电路所需的电流突然增大给整个电路造成不稳定的问题，增加了电路的稳定性；
3、该电压自调节电路不仅仅可以应用于本发明中所使用的一阶温度补偿带隙基准产生电路，还可以适用于其他的带隙基准产生电路，兼容性强；
4、本发明中的一阶温度补偿带隙基准电压源采用寄生NPN管，可以在CMOS工艺下实现；采用电流模结构，适合低电源电压下工作，具有低功耗的优点。
附图说明
图1为本发明的结构图；
图2为本发明实施例的整体电路拓扑图；
图3为启动电路和电压自调节电路中不包含反馈回路的电路拓扑图；
图4为启动电路和电压自调节电路中包含反馈回路的电路拓扑图；
图5为误差放大器的电路拓扑图；
图6为传统带隙基准电压源和本发明提供的具有高电源抑制比的带隙基准电压源对于电源噪声的抑制效果仿真图。
图中，1、电压自调节电路，2、启动电路，3、一阶温度补偿基准电压产生电路，4、误差放大器，5、偏置电压产生电路，6、基准启动电路。
具体实施方式
下面结合附图与实施例对本发明作更进一步的说明。
如图1所示为本发明的结构图，所述具有高电源抑制比的带隙基准电压源包括直流电压源Vdd、一阶温度补偿基准电压产生电路3、误差放大器4、偏置电压产生电路5和基准启动电路6，还包括电压自调节电路1和启动电路2；直流电压源Vdd为所述带隙基准电压源提供电源电压；电压自调节电路1以直流电压源电压Vdd作为起始电压信号，接收偏置电压产生电路5输出的偏置电压信号，根据偏置电压信号对起始电压中的噪声进行第一次抑制产生第一抑制信号，并将第一抑制信号分别输入一阶温度补偿基准电压 产生电路3、误差放大器4、偏置电压产生电路5和基准启动电路6的电源电压信号输入端；所述启动电路2以直流电压源电压Vdd作为起始电压信号，同时分别与电压自调节电路1和偏置电压产生电路5相连，当电压自调节电路1工作时，启动电路2截止，当电压自调节电路1停止工作时，启动电路2导通，控制电压自调节电路1开始工作；一阶温度补偿基准电压产生电路3与误差放大器4相连，向误差放大器4提供放大器偏置电压信号，同时接收误差放大器4输出的电压调节信号，并将电压调节信号转化为零温度系数的电流，进而产生基准电压，基准电压作为所述带隙基准电压源的输出信号；一阶温度补偿基准电压产生电路3同时与基准启动电路6相连，接收基准启动电路6输出的基准启动电流信号，并向基准启动电路6输入启动偏置信号；误差放大器4与偏置电压产生电路5相连，向偏置电压产生电路5输入电压调节信号。
实施例1：所述电压自调节电路1和启动电路2的电路结构为如图3所示：
电压自调节电路1包括PMOS管MP1a、MP2、MP3和NMOS管MN1a、MN1b、MN2；其中，MP1a和MP2的源极相连，其连接点与直流电源Vdd相连；MP1a的栅极与MP2的栅极相连，同时MP1a的栅极与漏极相连，MP1a的漏极与MN1a的漏极相连；MP2的漏极与MP3的源极相连，连接点作为所述电压自调节电路1的第一抑制信号输出端，该连接点同时与MN2的漏极相连；MP3的栅极作为电压自调节电路1的第二偏置信号输入端，MP3的漏极与MN2的栅极相连并同时与MN1b的漏极相连；MN2、MN1a、MN1b的源极均接地；MN1a和MN1b的栅极相连，其连接点作为电压自调节电路1的第一偏置信号输入端；电压自调节电路1通过第一偏置信号输入端和第二偏置信号输入端与偏置电压产生电路5相连，接收偏置电压产生电路5输出的第一偏置电压信号和第二偏置电压信号。
启动电路2包括：NMOS管MN4、MN5和电阻R1；R1的一端与直流电源Vdd相连，另一端与MN5的栅极相连，MN5的栅极同时与MN4的漏极相连，MN5的漏极与电压自调节电路1中MP1a和MN1a的漏极连接点相连，MN5的源极接地，MN4的栅极与电压自调节电路1的第一偏置信号输入端相连，MN4的源极接地。
所述一阶温度补偿基准电压产生电路3、误差放大器4、偏置电压产生电路5和基准启动电路6的优选设计如图2所示：
一阶温度补偿基准电压产生电路3包括PMOS管MP4a、MP4b、MP6、MP7，电阻R2、R3a、R3b、R4和NPN管Q1、Q2、Q3；MP4a、MP4b、MP6、MP7的源极相连，连接点为所述一阶温度补偿基准电压产生电路3的第一输入端接收电压自调节电路1输 出的第一抑制信号；MP4a、MP4b、MP6的栅极相连，其连接点为所述一阶温度补偿基准电压产生电路3的第三输入端接收误差放大器4输出的电压调节信号，该电压调节信号通过MP4a、MP4b、MP6转换为零温度系数的电流，进而通过电阻R4产生基准电压；MP4a的漏极与所述误差放大器4的同相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第三输出端与误差放大器4同相输入端相连，MP4a的漏极同时与电阻R3a和R2相连，R3a的另一端接地，R2的另一端与NPN管Q1的集电极相连；Q1的集电极与基极相连，发射极接地；MP4b的漏极与所述误差放大器4的反相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第四输出端与误差放大器4的反相输入端相连，MP4b的漏极与NPN管Q2的集电极相连，Q2的集电极与基极相连，发射极接地，MP4b的漏极与电阻R3b的一端相连，其连接点为所述一阶温度补偿基准电压产生电路3的第二输入端接收基准启动电路6输出的基准启动电流信号，R3b的另一端接地，MP4b的漏极与NPN管Q3的基极相连；MP6的漏极通过电阻R4接地，MP6与R4的连接点为所述一阶温度补偿基准电压产生电路3的第五输出端，作为所述带隙基准电压源的基准电压输出端；MP7的基极与漏极相连，其连接点为所述一阶温度补偿基准电压产生电路3的第一输出端向启动电路6输出启动偏置信号，MP7的漏极与NPN管Q3的集电极相连，连接点为所述一阶温度补偿基准电压产生电路3的第二输出端为误差放大器4供电，Q3的发射极接地。
误差放大器4包括PMOS管MP10a、MP10b、MP11a、MP11b，NPN管Q4、Q5，NMOS管MN7a、MN7b、MN8a、MN8b和电容C1；MP10a、MP10b、MP11a、MP11b的源极相连，其连接点作为误差放大器4的第一输入端接收电压自调节电路1输出的第一抑制信号作为供电电压；MP10a、MP10b的栅极相连，其连接点作为误差放大器4的第二输入端接收一阶温度补偿基准电压产生电路3输出的供电电压；MP10a的漏极与NPN管Q4的集电极相连，同时与NMOS管MN8b的漏极相连；MP10b的漏极与NPN管Q5的集电极相连，同时与NMOS管MN7a的漏极相连；NPN管Q4和Q5为共射极连接，且连接点接地，Q4的基极作为误差放大器4的反相输入端，Q5的基极作为误差放大器4的同相输入端；MN7a的漏极与栅极相连，MN7a的源极接地，MN7a的栅极与MN7b的栅极相连；MN8a的漏极与栅极相连，MN8a的源极接地，MN8a的栅极与MN8b的栅极相连；MP11a与MP11b的栅极相连，MP11a的栅极和漏极相连，同时MP11a的漏极与MN8b的漏极相连；MP11b的漏极与MN7b的漏极相连，其连接点作为误差放大器4的输出端；MN8b和MN7b的源极接地；电容C1的一端与MN7b漏极相连，另一 端接地。
偏置电压产生电路5包括：PMOS管MP5、MP13，NMOS管MN6和电阻R6；MP5的源极与MP13的源极相连，其连接点作为电压产生电路5的第一输入端接收电压自调节电路1输出的第一抑制信号；MP5的栅极和MP13的栅极相连，其连接点作为偏置电压产生电路5的第二输入端与误差放大器4的输出端相连；MP5的漏极与MN6的漏极相连，连接点作为电压产生电路5的第一输出端向电压自调节电路1输出第一偏置电压信号；MN6的漏极与栅极相连，MN6的源极接地；MP13的漏极通过R6接地，MP13与R6的接点作为电压产生电路5的第二输出端向电压自调节电路1输出第二偏置电压信号。
基准启动电路6包括PMOS管MP8、MP9和电阻R5；MP8和MP9的源极相连，连接点作为基准启动电路6的第一输入端接收电压自调节电路1输出的第一抑制信号；MP8的栅极作为基准启动电路6的第二输入端接收一阶温度补偿基准电压产生电路3输出的启动偏置信号；MP8的漏极通过R5接地；MP9的栅极与MP8和R5的接点相连，MP9漏极作为基准启动电路6的输出端向一阶温度补偿基准电压产生电路3输入基准启动电流信号。
下面通过具体原理阐述电压自调节电路1对提高电源抑制比的作用。
当上述带隙基准电压源不包括电压自调节电路1时，即一阶温度补偿基准电压产生电路直接由直流电源Vdd供电，假设电源噪声为一个交流小信号，表示为VaVdd，设经过电路作用在带隙基准的输出端的产生的输出噪声信号为Vavf，则可以得到电源抑制比PSRR，表达式为：
Figure PCTCN2016073580-appb-000001
   (式1)
电源抑制比PSRR的值越大表示对电源噪声的抑制越强。
根据图2所示的电路连接关系，还可以得到以下公式：
Figure PCTCN2016073580-appb-000002
  (式2)
式中，Vf为误差放大器4的输出端信号，代表PMOS管MP4a和MP4b由于电源噪声VaVdd所产生的电压变化，Va为误差放大器的同相输入端电压变化大小，Vb为误差 放大器的反相输入端电压变化大小，Add表示误差放大器的电源抑制能力(电源噪声从电源到放大器输出端的小信号增益)；gm6表示PMOS管MP6的跨导，gm4表示PMOS管MP4a和MP4b整体的跨导，其中gm6与gm4的值相等；RQ1和RQ2分别为NPN晶体管Q1和Q2的等效电阻。令，
Rx＝R3b□RQ2
Ry＝R3a□(R2+RQ1)
将式2带入式1，可得到不包括电压自调节电路1的带隙基准电压源的电源抑制比PSRR，表达式为：
Figure PCTCN2016073580-appb-000003
  (式3)
当上述带隙基准电压源包括电压自调节电路1时，如图3所示，电压自调节电路1对电源噪声Vavdn进行第一次抑制，根据图3可以得到以下公式：
Figure PCTCN2016073580-appb-000004
  (式4)
式中,Vregn为电压自调节电路1输出的噪声信号，Vn为由于电源噪声的作用，PMOS管MP2栅极的电压变化值，Ax表示电源噪声Vavdn到MP2栅极电压变化的增益，Ax为接近于1的一个常数，gm2为PMOS管MP2的跨导，Vreg为输入的直流电压Vdd在电压自调节电路1的输出信号，Rregn为从电压自调节电路1输出端看进去的等效输出电阻。将式4带入式1，可得到电压自调节电路1的电源抑制比的表达式为：
Figure PCTCN2016073580-appb-000005
  (式5)
Rregn的值约为
Figure PCTCN2016073580-appb-000006
其中gnm2为NMOS管MN2的跨导，将Rregn的值带入式5可得
Figure PCTCN2016073580-appb-000007
  (式6)
将式6带入式1可得包括电压自调节电路1的带隙基准电压源电源抑制比PSRR_H表达式为：
Figure PCTCN2016073580-appb-000008
  (式7)
式中，Rx＝R3b□RQ2，Ry＝R3a□(R2+RQ1)
将式3与式7比较可知，带有电压自调节电路1的带隙基准电压源的电源抑制比PSRR_H要远大于前面推导的没有电压自调节电路1作用的一阶温度补偿基准电压产生电路的电源抑制比，即包括电压自调节电路1的带隙基准电压源对于电源噪声的抑制能力更强。
实施例2：根据实施例1的带隙基准电压源，电压自调节电路1还包括一个反馈电路，反馈回路如图4所示，包括：PMOS管MP1b、MP12和NMOS管MN3a和MN3b；MP1b和MP12的源极均与直流电源Vdd相连，MP1b的栅极与MP1a的栅极相连，MP1b的漏极与MN3a的漏极相连同时与MN3a的栅极相连；MN3a的栅极与MN3b的栅极相连，MN3a与MN3b的源极相连且连接点与MP2和MN2的漏极相连；MN3b的漏极与MP2的栅极相连同时与MP12的栅极和漏极相连；其中MP12和MP3b构成一个反馈放大器，MP1b和MN3a为MN3b提供偏置电流；反馈回路将电压自调节电路1输出电流的变化控制在一定范围内，避免后级电路因为输入的电流突然变化导致不能正常工作。
下面通过具体原理阐述反馈电路对提高电路稳定性的作用。
假设由于后级电路特别是一阶温度补偿基准电压产生电路由于特别大的噪声干扰，后级电路在电压自调节电路1的输出端输出的电流变大。当电路不包括上述反馈回路时，电路如图3所示，PMOS管MP2漏极输出固定的电流，电压自调节电路1输出端电压Vreg变小。Vreg变小一方面会导致NMOS管MN2所在支路电流变小，使管子进入线性区。另一方面，后级的电路特别是一阶温度补偿基准电压产生电路会由于Vreg输出端电压变小而不能正常工作。
但是，当电路包括反馈回路时，电路如图4所示，当Vreg输出端电压变小，PMOS管MP2栅极电压会相应减小，从而使MP2的漏极输出电流增大，大大降低了由于后级噪声干扰电压自调节电路1输出端电压Vreg变小使得电路不正常工作的可能性，增加了电路的稳定性。还有值得一提的是，反馈环路能进一步减小Vreg输出端的输出阻抗，提高了电源抑制比。
图6展示了两幅电源抑制比的对比图，前者为不加电压自调节电路的带隙基准电压源对噪声抑制效果的波形图，后者本发明对噪声抑制效果的波形图。比较可见，带有电压自调节电路的带隙基准电压源电源抑制比更高。普通的带隙基准电压源电源抑制比在低频约为72.29dB，在1kHz处约为62.34dB。本发明提出的带隙基准电压源电源抑制比在低频约为139.5dB，相比前者提高67.21dB；在1kHz处约为120.4dB，相比前者提高58.06dB。
以上所述仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (8)

  1. 一种具有高电源抑制比的带隙基准电压源，包括直流电压源Vdd、一阶温度补偿基准电压产生电路(3)、误差放大器(4)、偏置电压产生电路(5)和基准启动电路(6)，其特征在于，还包括电压自调节电路(1)和启动电路(2)；直流电压源Vdd为所述带隙基准电压源提供电源电压；电压自调节电路(1)以直流电压源电压Vdd作为起始电压信号，接收偏置电压产生电路(5)输出的偏置电压信号，根据偏置电压信号对起始电压中的噪声进行第一次抑制产生第一抑制信号，并将第一抑制信号分别输入一阶温度补偿基准电压产生电路(3)、误差放大器(4)、偏置电压产生电路(5)和基准启动电路(6)的电源电压信号输入端；所述启动电路(2)以直流电压源电压Vdd作为起始电压信号，同时分别与电压自调节电路(1)和偏置电压产生电路(5)相连，当电压自调节电路(1)工作时，启动电路(2)截止，当电压自调节电路(1)停止工作时，启动电路(2)导通，控制电压自调节电路(1)开始工作；一阶温度补偿基准电压产生电路(3)与误差放大器(4)相连，向误差放大器(4)提供放大器偏置电压信号，同时接收误差放大器(4)输出的电压调节信号，并将调节电压信号转化为零温度系数的电流，进而产生基准电压，基准电压作为所述带隙基准电压源的输出信号；一阶温度补偿基准电压产生电路(3)同时与基准启动电路(6)相连，接收基准启动电路(6)输出的基准启动电流信号，并向基准启动电路(6)输入启动偏置信号；误差放大器(4)与偏置电压产生电路(5)相连，向偏置电压产生电路(5)输入电压调节信号。
  2. 根据权利要求1所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，所述电压自调节电路(1)包括：PMOS管MP1a、MP2、MP3和NMOS管MN1a、MN1b、MN2；其中，MP1a和MP2的源极相连，其连接点与直流电源Vdd相连；MP1a的栅极与MP2的栅极相连，同时MP1a的栅极与漏极相连，MP1a的漏极与MN1a的漏极相连；MP2的漏极与MP3的源极相连，连接点作为所述电压自调节电路(1)的第一抑制信号输出端，该连接点同时与MN2的漏极相连；MP3的栅极作为电压自调节电路(1)的第二偏置信号输入端，MP3的漏极与MN2的栅极相连并同时与MN1b的漏极相连；MN2、MN1a、MN1b的源极均接地；MN1a和MN1b的栅极相连，其连接点作为电压自调节电路(1)的第一偏置信号输入端；电压自调节电路(1)通过第一偏置信号输入端和第二偏置信号输入端与偏置电压产生电路(5)相连，接收偏置电压产生电路(5)输出的第一偏置电压信号和第二偏置电压信号。
  3. 根据权利要求2所述的一种具有高电源抑制比的带隙基准电压源，其特征在于， 所述电压自调节电路(1)还包括一个反馈回路，所述反馈回路包括：PMOS管MP1b、MP12和NMOS管MN3a和MN3b；MP1b和MP12的源极均与直流电源Vdd相连，MP1b的栅极与MP1a的栅极相连，MP1b的漏极与MN3a的漏极相连同时与MN3a的栅极相连；MN3a的栅极与MN3b的栅极相连，MN3a与MN3b的源极相连且连接点与MP2和MN2的漏极相连；MN3b的漏极与MP2的栅极相连同时与MP12的栅极和漏极相连；其中MP12和MP3b构成一个反馈放大器，MP1b和MN3a为MN3b提供偏置电流；反馈回路将电压自调节电路(1)输出电流的变化控制在一定范围内，避免后级电路因为输入的电流突然变化导致不能正常工作。
  4. 根据权利要求2所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，所述启动电路(2)包括NMOS管MN4、MN5和电阻R1；R1的一端与直流电源Vdd相连，另一端与MN5的栅极相连，MN5的栅极同时与MN4的漏极相连，MN5的漏极与电压自调节电路(1)中MP1a和MN1a的漏极连接点相连，MN5的源极接地，MN4的栅极与电压自调节电路(1)的第一偏置信号输入端相连，MN4的源极接地。
  5. 根据权利要求2所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，所述一阶温度补偿基准电压产生电路(3)包括PMOS管MP4a、MP4b、MP6、MP7，电阻R2、R3a、R3b、R4和NPN管Q1、Q2、Q3；MP4a、MP4b、MP6、MP7的源极相连，连接点为所述一阶温度补偿基准电压产生电路(3)的第一输入端接收电压自调节电路(1)输出的第一抑制信号；MP4a、MP4b、MP6的栅极相连，其连接点为所述一阶温度补偿基准电压产生电路(3)的第三输入端接收误差放大器(4)输出的电压调节信号，该电压调节信号通过MP4a、MP4b、MP6转换为零温度系数的电流，进而通过电阻R4产生基准电压；MP4a的漏极与所述误差放大器(4)的同相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路(3)的第三输出端与误差放大器(4)同相输入端相连，MP4a的漏极同时与电阻R3a和R2相连，R3a的另一端接地，R2的另一端与NPN管Q1的集电极相连；Q1的集电极与基极相连，发射极接地；MP4b的漏极与所述误差放大器(4)的反相输入端相连，其连接点为所述一阶温度补偿基准电压产生电路(3)的第四输出端与误差放大器(4)的反相输入端相连，MP4b的漏极与NPN管Q2的集电极相连，Q2的集电极与基极相连，发射极接地，MP4b的漏极与电阻R3b的一端相连，其连接点为所述一阶温度补偿基准电压产生电路(3)的第二输入端接收基准启动电路(6)输出的基准启动电流信号，R3b的另一端接地，MP4b的漏极与NPN管Q3的基极相连；MP6的漏极通过电阻R4接地，MP6与R4的连接点为所述一阶温度补偿基准电压产生电路(3)的第五输出端，作为所述带隙基准电压源的基准电压输出端；MP7的基极与漏极相连，其连接点为所述一 阶温度补偿基准电压产生电路(3)的第一输出端向启动电路(6)输出启动偏置信号，MP7的漏极与NPN管Q3的集电极相连，连接点为所述一阶温度补偿基准电压产生电路(3)的第二输出端为误差放大器(4)供电，Q3的发射极接地。
  6. 根据权利要求1所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，误差放大器(4)包括PMOS管MP10a、MP10b、MP11a、MP11b，NPN管Q4、Q5，NMOS管MN7a、MN7b、MN8a、MN8b和电容C1；MP10a、MP10b、MP11a、MP11b的源极相连，其连接点作为误差放大器(4)的第一输入端接收电压自调节电路(1)输出的第一抑制信号作为供电电压；MP10a、MP10b的栅极相连，其连接点作为误差放大器(4)的第二输入端接收一阶温度补偿基准电压产生电路(3)输出的供电电压；MP10a的漏极与NPN管Q4的集电极相连，同时与NMOS管MN8b的漏极相连；MP10b的漏极与NPN管Q5的集电极相连，同时与NMOS管MN7a的漏极相连；NPN管Q4和Q5为共射极连接，且连接点接地，Q4的基极作为误差放大器(4)的反相输入端，Q5的基极作为误差放大器(4)的同相输入端；MN7a的漏极与栅极相连，MN7a的源极接地，MN7a的栅极与MN7b的栅极相连；MN8a的漏极与栅极相连，MN8a的源极接地，MN8a的栅极与MN8b的栅极相连；MP11a与MP11b的栅极相连，MP11a的栅极和漏极相连，同时MP11a的漏极与MN8b的漏极相连；MP11b的漏极与MN7b的漏极相连，其连接点作为误差放大器(4)的输出端；MN8b和MN7b的源极接地；电容C1的一端与MN7b漏极相连，另一端接地。
  7. 根据权利要求1所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，所述偏置电压产生电路(5)包括：PMOS管MP5、MP13，NMOS管MN6和电阻R6；MP5的源极与MP13的源极相连，其连接点作为电压产生电路(5)的第一输入端接收电压自调节电路(1)输出的第一抑制信号；MP5的栅极和MP13的栅极相连，其连接点作为偏置电压产生电路(5)的第二输入端与误差放大器(4)的输出端相连；MP5的漏极与MN6的漏极相连，连接点作为电压产生电路(5)的第一输出端向电压自调节电路(1)输出第一偏置电压信号；MN6的漏极与栅极相连，MN6的源极接地；MP13的漏极通过R6接地，MP13与R6的接点作为电压产生电路(5)的第二输出端向电压自调节电路(1)输出第二偏置电压信号。
  8. 根据权利要求1所述的一种具有高电源抑制比的带隙基准电压源，其特征在于，所述基准启动电路(6)包括PMOS管MP8、MP9和电阻R5；MP8和MP9的源极相连，连接点作为基准启动电路(6)的第一输入端接收电压自调节电路(1)输出的第一抑制信号；MP8的栅极作为基准启动电路(6)的第二输入端接收一阶温度补偿基准电压产生电 路(3)输出的启动偏置信号；MP8的漏极通过R5接地；MP9的栅极与MP8和R5的接点相连，MP9漏极作为基准启动电路(6)的输出端向一阶温度补偿基准电压产生电路(3)输入基准启动电流信号。
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