WO2016015523A1 - 一种具有低失调电压高psrr的带隙基准源 - Google Patents

一种具有低失调电压高psrr的带隙基准源 Download PDF

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Publication number
WO2016015523A1
WO2016015523A1 PCT/CN2015/081096 CN2015081096W WO2016015523A1 WO 2016015523 A1 WO2016015523 A1 WO 2016015523A1 CN 2015081096 W CN2015081096 W CN 2015081096W WO 2016015523 A1 WO2016015523 A1 WO 2016015523A1
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Prior art keywords
channel
channel fet
field effect
effect transistor
drain
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PCT/CN2015/081096
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English (en)
French (fr)
Inventor
苏胜新
杜新纲
杨小坤
原义栋
胡毅
何洋
李振国
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国家电网公司
北京南瑞智芯微电子科技有限公司
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Publication of WO2016015523A1 publication Critical patent/WO2016015523A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Definitions

  • the present invention relates to the field of bandgap reference sources, and in particular to a bandgap reference source having a low offset voltage and a high PSRR.
  • the integrated circuit is mainly divided into two parts: an analog circuit and a digital circuit.
  • the on-chip bandgap voltage reference source is the core module of the analog circuit, and its performance determines the performance and function of the entire analog circuit and even the entire chip.
  • the bandgap voltage reference which is the most widely used and has the best performance index, is realized by a bipolar device. The principle is to superimpose the voltage of the positive temperature coefficient and the voltage of the negative temperature coefficient with a certain coefficient to obtain an approximate zero temperature. The bandgap voltage of the coefficient.
  • the requirements for the bandgap voltage reference source are also increasing, especially in the voltage input range, circuit offset, power supply voltage rejection ratio and power consumption.
  • Some system power supply voltages vary widely (eg, 2.5V to 5.5V) and require low power consumption to extend system operating time (eg, battery-powered systems, dual-interface IC card systems, etc.); some systems require higher The power supply rejection ratio reduces the output reference voltage from system power supply noise (eg, power management systems); some systems require small offsets in the output reference voltage (eg, ADC and DAC circuits, etc.).
  • the existing technical solutions are difficult to meet the requirements of the above different circuit systems for the bandgap voltage reference source.
  • the existing circuit of the high power supply voltage rejection ratio PSRR Power Supply Rejection Ratio
  • the core bandgap reference circuit is composed of current mirrors MP1, MP2, MP3, resistors R3, R4 and transistors Q1, Q2. composition.
  • the loop amplifier controls the VREG point by detecting the voltage at point B, allowing it to operate at the correct voltage.
  • the structure uses a voltage negative feedback method to achieve stability of the core node voltage VREG over a wide frequency range, thereby increasing the power supply rejection ratio of the output voltage.
  • the output voltage of the circuit is:
  • V be2 is the base-emitter voltage of Q2
  • V T is the thermal voltage
  • R 3 is the resistance of resistor R3
  • R 4 is the resistance of resistor R4.
  • the reference voltage is affected by the system power supply, and voltage cascading (for example, cascode structure, power regulator, etc.) and Large on-chip filter capacitors are implemented.
  • the voltage cascading limits the input voltage range, and the on-chip filter capacitors take up a large chip area, thereby increasing the production cost of the chip.
  • the accuracy of the output voltage is affected by the current multiplication factor N, and the change of N causes the output voltage to change, thereby affecting the accuracy of the output voltage. Due to the large difference between the voltages of the two points (Vbe) and the point E (VBG) of A and B, it is difficult to achieve an accurate multiplication factor N by the ratio of the current mirror, which affects the output voltage VBG. Precision.
  • the invention is to overcome the defects that the band gap reference source in the prior art is affected by the channel length modulation effect and the output voltage accuracy is not high. According to an aspect of the invention, a low low offset voltage high PSRR bandgap reference source is proposed. .
  • a low-low offset voltage high PSRR bandgap reference source includes: a first P-channel FET, a second P-channel FET, a third P-channel FET, and a fourth P-channel field a effect transistor, a first resistor, a second resistor, a third resistor, a first bipolar transistor, a second bipolar transistor, and a voltage feedback circuit;
  • the aspect ratio of the channel field effect transistor is 1:N, and the ratio of the resistance of the first resistor to the resistance of the second resistor is N:1;
  • the gate of the first P-channel FET is connected to the gate of the second P-channel FET and is connected to the drain of the third P-channel FET; the gate and the fourth of the third P-channel FET a gate of the P-channel FET is connected to the connection node of the first resistor and the third resistor;
  • a drain of the first P-channel FET is connected to a source of the third P-channel FET, and a drain of the second P-channel FET is connected to a source of the fourth P-channel FET;
  • the drain of the third P-channel FET is sequentially connected to the emitter of the first bipolar transistor through the first resistor and the third resistor;
  • a drain of the fourth P-channel FET is connected to an emitter of the second bipolar transistor through a second resistor, and The drain of the fourth P-channel FET is also connected to the voltage output terminal;
  • a base of the first bipolar transistor is connected to the base of the second bipolar transistor and grounded, and a collector of the first bipolar transistor is connected to the collector of the second bipolar transistor and grounded;
  • the voltage feedback input end of the voltage feedback circuit is connected to the drain of the fourth P-channel FET, and the voltage feedback output end is respectively connected to the source of the first P-channel FET and the source of the second P-channel FET;
  • the voltage feedback circuit is configured to determine an output feedback voltage according to a drain voltage of the fourth P-channel FET, and control a drain voltage of the third P-channel FET to be equal to a drain voltage of the fourth P-channel FET.
  • the ratio of the emitter area of the first bipolar transistor to the second bipolar transistor is M:1;
  • the output voltage at the voltage output is:
  • V be2 is the base-emitter voltage of the second bipolar transistor
  • V T is the thermal voltage
  • R 2 is the resistance of the second resistor
  • R 3 is the resistance of the third resistor.
  • the voltage feedback circuit comprises: a fifth P-channel FET, a sixth P-channel FET, a seventh P-channel FET, an eighth P-channel FET, and a ninth P-channel FET.
  • a tenth P channel field effect transistor a first N channel field effect transistor, a second N channel field effect transistor, a third N channel field effect transistor, a fourth N channel field effect transistor, a fifth N channel field effect transistor, a six-N-channel field effect transistor, a seventh N-channel field effect transistor, a fourth resistor, and a compensation capacitor;
  • the source of the ninth P-channel FET is connected to the source of the tenth P-channel FET and is connected to an external power supply, and the gate of the ninth P-channel FET is connected to the gate of the tenth P-channel FET and Connected to the drain of the tenth P-channel FET, the drain of the tenth P-channel FET is also connected to the drain of the third N-channel FET; the ninth P-channel FET and the tenth P-channel field
  • the effect tube constitutes a current mirror;
  • the drain of the ninth P-channel FET is a voltage feedback output, and is respectively connected to the source of the fifth P-channel FET and the source of the sixth P-channel FET;
  • a gate of the fifth P-channel FET is connected to a gate of the second P-channel FET;
  • the gate of the sixth P-channel FET is a voltage feedback input terminal connected to the drain of the fourth P-channel FET;
  • a gate of the seventh P channel field effect transistor and a gate of the eighth P channel field effect transistor are respectively connected to a gate of the fourth P channel field effect transistor;
  • the drain of the fifth P-channel FET is connected to the source of the seventh P-channel FET, and the sixth P-channel field effect The drain of the transistor is connected to the source of the eighth P-channel FET;
  • a drain of the seventh P-channel FET is connected to a gate of the first N-channel FET, a gate of the second N-channel FET, and a gate of the third N-channel FET; a seventh P-channel field
  • the drain of the effect transistor is also connected to the drain of the first N-channel FET through a fourth resistor;
  • the drain of the eighth P-channel FET is respectively connected to the drain of the second N-channel FET and the gate of the seventh N-channel FET; the drain of the seventh N-channel FET and the ninth P-channel The drain of the MOSFET is connected, and the source of the seventh N-channel FET is grounded;
  • the source of the first N-channel FET is connected to the drain of the fourth N-channel FET, the source of the second N-channel FET is connected to the drain of the fifth N-channel FET, and the third N-channel The source of the MOSFET is connected to the drain of the sixth N-channel FET;
  • a gate of the fourth N-channel FET, a gate of the fifth N-channel FET, and a gate of the sixth N-channel FET are respectively connected to the drain of the first N-channel field effect transistor;
  • a source of the fourth N-channel FET, a source of the fifth N-channel FET, and a source of the sixth N-channel FET are respectively connected and grounded;
  • One end of the compensation capacitor is connected to the drain of the eighth P-channel FET, and the other end is connected to the drain of the ninth P-channel FET.
  • the first N-channel FET, the second N-channel FET, the third N-channel FET, the fourth N-channel FET, the fifth N-channel FET, and the sixth N-channel are transistors capable of withstanding a high power supply voltage;
  • the P-channel FET, the eighth P-channel FET, and the seventh N-channel FET are transistors with low supply voltage and low threshold voltage.
  • the compensation capacitor is an on-chip capacitor, and the lower plate of the compensation capacitor is connected to the drain of the eighth P-channel field effect transistor, and the upper plate is connected to the drain of the ninth P-channel field effect transistor.
  • the voltage feedback circuit comprises: a fifth P-channel FET, a sixth P-channel FET, a seventh P-channel FET, an eighth P-channel FET, and a ninth P-channel FET. a tenth P channel field effect transistor, an eleventh P channel field effect transistor, a twelfth P channel field effect transistor, a first N channel field effect transistor, a second N channel field effect transistor, and a third N channel field effect transistor a fourth N-channel field effect transistor, a fifth N-channel field effect transistor, a sixth N-channel field effect transistor, and a compensation capacitor;
  • the source of the eleventh P-channel FET is connected to the source of the twelfth P-channel FET and is connected to the external power a source, a gate of the eleventh P-channel FET is connected to a gate of the twelfth P-channel FET and connected to a drain of the twelfth P-channel FET, and a twelfth P-channel FET
  • the drain is also connected to the drain of the sixth N-channel FET; the eleventh P-channel FET and the twelfth P-channel FET form a current mirror;
  • the drain of the eleventh P-channel FET is a voltage feedback output, and is respectively connected to the source of the fifth P-channel FET, the source of the sixth P-channel FET, and the source of the seventh P-channel FET. Extremely connected
  • the gate of the fifth P-channel FET is connected to the gate of the sixth P-channel FET and is connected to the gate of the second P-channel FET;
  • the gate of the seventh P-channel FET is a voltage feedback input a terminal connected to a drain of the fourth P-channel FET;
  • the drain of the fifth P-channel FET is connected to the source of the eighth P-channel FET, the drain of the sixth P-channel FET is connected to the source of the ninth P-channel FET, and the seventh P-channel
  • the drain of the MOSFET is connected to the source of the tenth P-channel FET;
  • a gate of the eighth P-channel FET, a gate of the ninth P-channel FET, and a gate of the tenth P-channel FET are respectively connected to the gate of the fourth P-channel field effect transistor;
  • the drains of the eighth P-channel FET are respectively connected to the drain and the gate of the fourth N-channel FET; the drains of the ninth P-channel FET are respectively connected to the drains of the first N-channel FET, a gate of the second N-channel FET is connected; a drain of the tenth P-channel FET is respectively connected to a drain of the second N-channel FET and a gate of the third N-channel FET; The source of the channel FET is grounded;
  • a gate of the first N-channel FET is connected to a source of the second N-channel FET, and a source of the first N-channel FET is grounded; a source of the second N-channel FET and a fifth N a drain of the channel field effect transistor is connected; the first N-channel field effect transistor and the second N-channel field effect transistor form a Gainboost structure;
  • a gate of the fourth N-channel FET, a gate of the fifth N-channel FET, and a gate of the sixth N-channel FET are respectively connected; a source of the fourth N-channel FET and a fifth N-channel The source of the MOSFET and the source of the sixth N-channel FET are respectively connected and grounded;
  • One end of the compensation capacitor is connected to the drain of the tenth P-channel FET, and the other end is connected to the drain of the eleventh P-channel FET.
  • the fourth N-channel FET, the fifth N-channel FET, the sixth N-channel FET, the eleventh P-channel FET, and the twelfth P-channel FET are affordable a transistor with a high supply voltage
  • First P-channel FET, second P-channel FET, third P-channel FET, fourth P-channel FET, fifth P-channel FET, sixth P-channel FET, seventh P-channel field effect transistor, eighth P-channel FET, ninth P-channel FET, tenth P-channel FET, first N-channel FET, second N-channel FET, and third N-channel FET are low supply voltage, A transistor with a low threshold voltage.
  • the compensation capacitor is an on-chip capacitor, and the lower plate of the compensation capacitor is connected to the drain of the tenth P-channel field effect transistor, and the upper plate is connected to the drain of the eleventh P-channel field effect transistor.
  • a third P-channel FET MP3, a fourth P-channel FET MP4 and a first resistor R1 are added, and the single-layer circuit mirror is replaced with Double-layer current mirror structure with self-biasing resistor (ie, first resistor R1), which reduces the influence of channel length modulation effect between each current mirror field effect transistor, and ensures accurate current multiplication coefficient (N) Sex, which in turn reduces the offset of the output voltage.
  • the structure features low power consumption, low offset voltage, high power supply rejection ratio PSRR, and wide supply voltage input range.
  • FIG. 1 is a circuit diagram of a high power supply voltage rejection ratio circuit in the prior art
  • FIG. 2 is a circuit structural diagram of a low offset voltage high PSRR bandgap reference source according to an embodiment of the present invention
  • FIG. 3 is a circuit structural diagram of a low offset voltage high PSRR bandgap reference source in the first embodiment
  • FIG. 4 is a circuit structural diagram of a low offset voltage high PSRR bandgap reference source in the second embodiment.
  • FIG. 2 is a circuit diagram of the low offset voltage high PSRR bandgap reference source, specifically including:
  • the first P-channel FET MP1, the second P-channel FET MP2, the third P-channel FET MP3, and the fourth P-channel FET MP4 constitute a current mirror; wherein, the first P-channel field effect transistor MP1 aspect ratio of width to length ratio than the second P-channel field effect transistor MP2 is 1:N, the first resistor R1 and the resistance R 1 and the resistance ratio of the second resistor R2 is N R 2 : 1.
  • the gate of the first P-channel FET MP1 is connected to the gate of the second P-channel FET MP2 and to the drain of the third P-channel FET MP3 (ie, in FIG. 2). Node C) is connected; the gate of the third P-channel FET MP3 is connected to the gate of the fourth P-channel FET MP4, and is connected to the first resistor R1 and the third resistor R3 (ie, in FIG. 2) Node A) is connected.
  • the drain of the first P-channel FET MP1 is connected to the source of the third P-channel FET MP3, and the drain of the second P-channel FET MP2 is connected to the source of the fourth P-channel FET MP4;
  • the drain of the third P-channel FET MP3 is sequentially connected to the emitter of the first bipolar transistor Q1 through the first resistor R1 and the third resistor R3.
  • the drain of the fourth P-channel FET MP4 (ie, node D in FIG. 2) is connected to the emitter of the second bipolar transistor Q2 (ie, node B in FIG. 2) through the second resistor R2, and is fourth.
  • the drain of the P-channel FET MP4 is also connected to the voltage output terminal VBG.
  • the base of the first bipolar transistor Q1 is connected to the base of the second bipolar transistor Q2 and grounded, and the collector of the first bipolar transistor Q1 is connected to the collector of the second bipolar transistor Q2 and grounded;
  • the voltage feedback input terminal Vf of the voltage feedback circuit 10 is connected to the drain of the fourth P-channel FET MP4, and the voltage feedback output terminal VREG is respectively connected to the source of the first P-channel FET MP1 and the second P-channel FET.
  • the source of the MP2 is connected; the voltage feedback circuit 10 is configured to determine an output feedback voltage according to the drain voltage of the fourth P-channel FET MP4, and control the drain voltage of the third P-channel FET MP3 (ie, the voltage at the node C). ) is equal to the drain voltage of the fourth P-channel FET MP4 (ie, the voltage at node D).
  • the ratio of the aspect ratio of the first P-channel FET MP1 to the aspect ratio of the second P-channel FET MP2 is 1:N
  • the resistance R 1 of the first resistor R1 is
  • the ratio of the resistance R 2 of the two resistors R2 is N:1
  • the ratio of the emitter areas of the first bipolar transistor Q1 to the second bipolar transistor Q2 is M:1.
  • the voltage feedback circuit 10 determines the output feedback voltage VREG according to the drain voltage of the fourth P-channel FET MP4 (ie, the voltage at the node D) to maintain the voltage of the VREG at the correct voltage; and controls the third P-channel FET
  • the drain voltage of the MP3 is equal to the drain voltage of the fourth P-channel FET MP4, thereby ensuring that the voltages at the two points of the node C and the node D are equal.
  • the ratio of the aspect ratio of the first P-channel FET MP1 to the aspect ratio of the second P-channel FET MP2 is 1:N
  • the first P-channel FET MP1 and the second P-channel field flow is also 1:N.
  • R 1 : R 2 N: 1
  • the current flowing through the two branches of MP1 and MP2 is equal to the voltage drop generated across the resistors R1 and R2, respectively. Since the voltages at the two points C and D are equal, the voltages at points A and B are also equal. Therefore, the current flowing through resistors R1, R3, MP3, and MP1 is:
  • V be2 is the base-emitter voltage of the second bipolar transistor Q2 (ie, the voltage between the Q2 emitter and the base of Q2)
  • V be1 is the base-emitter of the first bipolar transistor Q1.
  • the voltage, R 3 is the resistance of the third resistor R3.
  • V be2 -V be1 V T ⁇ ln(M ⁇ N) (4)
  • V T is the thermal voltage
  • V T KT/q
  • K is the Boltzmann constant
  • T is the absolute temperature
  • q is the electron charge.
  • V be2 is a negative temperature coefficient
  • V R2 is a positive temperature coefficient
  • the third P-channel FET MP3 and the fourth P-channel FET are added.
  • the MP4 and the first resistor R1 replace the single-layer circuit mirror with a double-layer current mirror structure with a self-biasing resistor (ie, the first resistor R1), thereby reducing the channel length modulation effect between the respective current mirror field effect transistors. Influence, guaranteed current The accuracy of the multiplication factor (N), which in turn reduces the offset of the output voltage.
  • the structure features low power consumption, low offset voltage, high power supply rejection ratio PSRR, and wide supply voltage input range.
  • the first resistor R1 is used to bias the first P-channel FET MP1 and the third P-channel FET MP3 to operate in the saturation region.
  • the second resistor R2 is added to balance the current mirror state of the two branches of the first P-channel field effect transistor MP1 and the second P-channel field effect transistor MP2, and the positive temperature coefficient voltage can also be adjusted so that the bandgap reference voltage can be directly Output from point D.
  • the voltages at point C and point D are equal, the voltages at points A and B are also equal. This not only allows the bandgap reference voltage to be adjusted in real time by the negative feedback loop, but also increases its PSRR to the power supply, and reduces the current offset relative to the bandgap reference source in Figure 1, reducing circuit power consumption.
  • the structure of the low offset voltage high PSRR bandgap reference source is described in detail below by two embodiments.
  • the voltage feedback circuit 10 includes: a fifth P-channel FET MP5, a sixth P-channel FET MP6, a seventh P-channel FET MP7, and an eighth P-channel field.
  • Effect transistor MP8 ninth P-channel FET MP9, tenth P-channel FET MP10, first N-channel FET 1, second N-channel FET 2, third N-channel FET MN3, Four N-channel FETs MN4, fifth N-channel FETs MN5, sixth N-channel FETs MN6, seventh N-channel FETs MN7, fourth resistors R4, and compensation capacitors Cc.
  • the source of the ninth P-channel FET MP9 is connected to the source of the tenth P-channel FET MP10 and connected to the external power supply, and the gate of the ninth P-channel FET MP9 is The gate of the tenth P-channel FET MP10 is connected and connected to the drain of the tenth P-channel FET MP10 (ie, node F), and the drain of the tenth P-channel FET MP10 is also connected to the third N-channel field.
  • the drain of the effect transistor MN3 is connected; the ninth P-channel field effect transistor MP9 and the tenth P-channel field effect transistor MP10 form a current mirror.
  • the drain of the ninth P-channel FET MP9 is a voltage feedback output terminal, and is respectively connected to the source of the fifth P-channel FET MP5 and the source of the sixth P-channel FET MP6.
  • the gate of the fifth P-channel FET MP5 is connected to the gate of the second P-channel FET MP2.
  • the gate of the sixth P-channel FET MP6 is a voltage feedback input terminal connected to the drain of the fourth P-channel FET MP4 (ie, node D in FIG. 3).
  • the gate of the seventh P-channel FET MP7 and the gate of the eighth P-channel FET MP8 are respectively connected to the gate of the fourth P-channel FET.
  • the drain of the fifth P-channel FET MP5 is connected to the source of the seventh P-channel FET MP7, sixth The drain of the P-channel FET MP6 is connected to the source of the eighth P-channel FET MP8.
  • the drain of the seventh P-channel FET MP7 (ie, node H in FIG. 3) and the gate of the first N-channel FET MN1, the gate of the second N-channel FET MN2, and the third N-channel field
  • the gate of the effect transistor MN3 is connected;
  • the drain of the seventh P-channel FET MP7 is also connected to the drain of the first N-channel FET MN1 (ie, the node G in FIG. 3) through the fourth resistor R4.
  • the drain of the eighth P-channel FET MP8 (ie, node E in FIG. 3) is respectively connected to the drain of the second N-channel FET MN2 and the gate of the seventh N-channel FET MN7;
  • the drain of the channel field effect transistor MN7 is connected to the drain of the ninth P-channel field effect transistor MP9, and the source of the seventh N-channel field effect transistor MN7 is grounded.
  • the source of the first N-channel FET MN1 is connected to the drain of the fourth N-channel FET MN4, and the source of the second N-channel FET MN2 is connected to the drain of the fifth N-channel FET MN5.
  • the source of the third N-channel field effect transistor MN3 is connected to the drain of the sixth N-channel field effect transistor MN6.
  • the gate of the fourth N-channel FET MN4, the gate of the fifth N-channel FET MN5, and the gate of the sixth N-channel FET MN6 are respectively connected to the drain of the first N-channel FET MN1. Extremely connected.
  • the source of the fourth N-channel FET MN4, the source of the fifth N-channel FET MN5, and the source of the sixth N-channel FET MN6 are respectively connected and grounded.
  • One end of the compensation capacitor Cc is connected to the drain of the eighth P-channel field effect transistor MP8, and the other end is connected to the drain of the ninth P-channel field effect transistor MP9.
  • the compensation capacitor Cc is specifically an on-chip capacitor, and the lower plate of the compensation capacitor Cc is connected to the drain of the eighth P-channel field effect transistor MP8, and the upper plate and the ninth P-channel field effect transistor MP9 are connected. The drains are connected.
  • the working principle of the voltage feedback circuit 10 is as follows:
  • the drain of the seventh P-channel FET MP7 detects the voltage change at the D point, and forms a Cascode with the eighth P-channel FET MP8, the second N-channel FET 2, and the fifth N-channel FET MN5.
  • the common-gate voltage amplifier amplifies the voltage change at point D.
  • the amplified voltage is fed back to the VREG terminal through the seventh N-channel FET MN7, so that the VREG is maintained at the correct voltage and the voltages at the two points C and D are equal.
  • the structure uses the voltage negative feedback method to realize the core node VREG is stable in a wide frequency range; at the same time, the current mirror MP9, MP10 and the FET MN3, MN6 form an internal regulator to isolate the power supply voltage from the VREG, thereby improving the VREG pair.
  • the power supply VDD has a power supply rejection ratio PSRR.
  • the MN1, MN2, MN4, MN5 and the resistor R4 adopt a resistance self-biasing cascode structure, and the current bias branch of the loop amplifier is reduced while ensuring the high impedance of the E point. number.
  • the cascode amplifier composed of MN3 and MN6 can be directly biased by a resistor self-biasing branch.
  • the cascode amplifier composed of MN3 and MN6 increases the output impedance of point F to ground, so that point F (ie, MP9)
  • point F ie, MP9
  • the gate has better follow-up characteristics to the power supply, optimizes the power supply rejection ratio of VREG to VDD, and optimizes the PSRR of the VBG to the power supply VDD.
  • the first N-channel FET 1, the second N-channel FET 2, the third N-channel FET MN3, the fourth N-channel FET MN4, the fifth N-channel FET MN5, and the sixth N-channel FET MN6, ninth P-channel FET MP9, and tenth P-channel FET MP10 are transistors capable of withstanding high power supply voltage; first P-channel FET, second P-channel FET, and Three P channel field effect transistor, fourth P channel field effect transistor, fifth P channel field effect transistor MP5, sixth P channel field effect transistor MP6, seventh P channel field effect transistor MP7, eighth P channel field effect transistor MP8
  • the seventh N-channel FET MN7 is a transistor with a low power supply voltage and a low threshold voltage.
  • the voltage of the VREG can be adjusted to a low level to ensure that all tubes operate in a saturated region.
  • the reduction in VREG allows the circuit to operate at a lower VDD voltage.
  • Only the high-voltage tubes MP9 and MP10 can “see” the high power supply voltage input, ensuring that the low-voltage tube will not be broken down with high power supply voltage input.
  • MN1, MN2, MN3, MN4, MN5 and MN6 all use the same type of transistor.
  • the voltage feedback circuit 10 includes: a fifth P-channel FET MP5, a sixth P-channel FET MP6, a seventh P-channel FET MP7, and an eighth P-channel field.
  • Effect transistor MP8 ninth P-channel FET MP9, tenth P-channel FET MP10, eleventh P-channel FET MP11, twelfth P-channel FET MP12, first N-channel FET MN1 a second N-channel FET, a third N-channel FET MN3, a fourth N-channel FET MN4, a fifth N-channel FET MN5, a sixth N-channel FET MN6, and a compensation capacitor Cc.
  • the source of the eleventh P-channel FET MP11 is connected to the source of the twelfth P-channel FET MP12 and connected to the external power source, and the gate of the eleventh P-channel FET MP11 and the twelfth P-channel field
  • the gate of the effect transistor MP12 is connected to and connected to the drain of the twelfth P-channel FET MP12, and the drain of the twelfth P-channel FET MP12 is also connected to the drain of the sixth N-channel FET MN6;
  • the eleventh P-channel field effect transistor MP11 and the twelfth P-channel field effect transistor MP12 form a current mirror.
  • the drain of the eleventh P-channel FET MP11 is a voltage feedback output, and is respectively connected to the source of the fifth P-channel FET MP5, the source of the sixth P-channel FET MP6, and the seventh P-channel field effect.
  • Tube MP7 The source is connected.
  • the gate of the fifth P-channel FET MP5 is connected to the gate of the sixth P-channel FET MP6 and is connected to the gate of the second P-channel FET MP2; the gate of the seventh P-channel FET MP7 The extreme voltage feedback input is coupled to the drain of the fourth P-channel FET MP4.
  • the drain of the fifth P-channel FET MP5 is connected to the source of the eighth P-channel FET MP8, and the drain of the sixth P-channel FET MP6 is connected to the source of the ninth P-channel FET MP9.
  • the drain of the seventh P-channel FET MP7 is connected to the source of the tenth P-channel FET MP10.
  • the gate of the eighth P-channel FET MP8, the gate of the ninth P-channel FET MP9, and the gate of the tenth P-channel FET MP10 are respectively connected to the gate of the fourth P-channel FET MP4. Extremely connected.
  • the drain of the eighth P-channel FET MP8 is respectively connected to the drain and the gate of the fourth N-channel FET MN4; the drain of the ninth P-channel FET MP9 is respectively connected to the first N-channel FET MN1 a drain connected to the gate of the second N-channel FET MN2; a drain of the tenth P-channel FET MP10 and a drain of the second N-channel FET MN2, and a third N-channel FET MN3 The gate is connected; the source of the third N-channel FET MN3 is grounded.
  • the gate of the first N-channel FET MN1 is connected to the source of the second N-channel FET MN2, and the source of the first N-channel FET MN1 is grounded; the source of the second N-channel FET MN2 Connected to the drain of the fifth N-channel FET MN5; the first N-channel FET MN1 and the second N-channel FET MN2 form a Gainboost structure.
  • the gate of the fourth N-channel FET MN4, the gate of the fifth N-channel FET MN5, and the gate of the sixth N-channel FET MN6 are respectively connected; the source of the fourth N-channel FET MN4, The source of the fifth N-channel FET MN5 and the source of the sixth N-channel FET MN6 are respectively connected and grounded.
  • the compensation capacitor Cc is connected to the drain of the tenth P-channel field effect transistor MP10, and the other end is connected to the drain of the eleventh P-channel field effect transistor MP11.
  • the compensation capacitor Cc may be an on-chip capacitor, and the lower plate of the compensation capacitor Cc is connected to the drain of the tenth P-channel FET MP10, and the drain of the upper plate and the eleventh P-channel FET MP11 Connected.
  • the current mirror composed of the eleventh P-channel field effect transistor MP11, the twelfth P-channel field effect transistor MP12, and the sixth N-channel field effect transistor MN6 form an internal regulator, which generates a stable voltage VREG, and isolates the power supply voltage VDD from the VREG.
  • the working principle of the voltage feedback circuit 10 is as follows:
  • the seventh P-channel FET MP7 collects the node D voltage change, and is connected with the tenth P-channel FET MP10,
  • the second N-channel FET 2, the fifth N-channel FET MN5 constitutes a Cascode (co-source common-gate) voltage amplifier, which amplifies the voltage change at point D.
  • the amplified voltage is fed back to the VREG terminal through the third N-channel FET MN3, so that the VREG is maintained at the correct voltage and the voltages at the two points C and D are equal.
  • the structure uses the voltage negative feedback method to realize that the core node VREG is stable over a wide frequency range, thereby improving the power supply rejection ratio PSRR of the output voltage VBG.
  • the fifth P-channel FET MP5 and the eighth P-channel FET MP8 provide bias to the fifth N-channel FET MN5 and the sixth N-channel FET MN6 through the fourth N-channel FET MN4.
  • the sixth P-channel FET MP6 and the ninth P-channel FET MP9 provide bias to the second N-channel FET MN2.
  • the single-layer current mirror is also replaced with a double-layer current mirror structure with a self-bias resistor by adding the eighth P-channel field effect transistor MP8 and the ninth P-channel field effect transistor MP9.
  • the voltage feedback circuit 10 adopts a voltage negative feedback method to realize that the core node VREG is stable in a wide frequency range, so that the VREG is maintained at the correct voltage, and the voltages at the two points C and D are equal, and the output voltage can be increased.
  • VBG's power supply rejection ratio is PSRR.
  • the gate of the first N-channel field effect transistor MN1 is connected to the source of the second N-channel field effect transistor MN2.
  • the first N-channel field effect transistor MN1 and the second N-channel field effect transistor MN2 constitute a Gainboost structure.
  • MN1 and MN2 adopt Gainboost structure to improve the output impedance of point F.
  • MP2 and MP5 form Cascode current mirror also improve the output impedance of point D; the output impedance is increased, the loop gain is increased, and C and D are reduced.
  • the gain error of the two points further reduces the effect of the gain error on the output voltage offset.
  • the fourth N-channel field effect transistor MN4, the fifth N-channel field effect transistor MN5, the sixth N-channel field effect transistor MN6, the eleventh P-channel field effect transistor MP11, and the twelfth P-channel field effect transistor MP12 are Transistor capable of withstanding high supply voltage; first P-channel FET, second P-channel FET, third P-channel FET, fourth P-channel FET, fifth P-channel FET MP5, Six P-channel FET MP6, seventh P-channel FET MP7, eighth P-channel FET MP8, ninth P-channel FET MP9, tenth P-channel FET MP10, first N-channel field effect
  • the tube MN1, the second N-channel field effect transistor MN2, and the third N-channel field effect transistor MN3 are transistors with a low power supply voltage and a low threshold voltage.
  • the voltage of the VREG can be adjusted to a low level to ensure that all tubes operate in a saturated region.
  • the reduction in VREG allows the circuit to operate at a lower VDD voltage. Only the high voltage tubes MP11 and MP12 can “see” the high power supply voltage input, which ensures low input under high power supply voltage. The voltage tube will not be broken down.
  • MN4, MN5 and MN6 all use the same type of transistor.
  • the present invention can be embodied in a variety of different forms.
  • the technical solutions of the present invention are exemplified above with reference to FIG. 2 to FIG. 4, which does not mean that the specific examples applied to the present invention can be limited to In a particular process or embodiment structure, one of ordinary skill in the art will appreciate that the specific embodiments provided above are only a few examples of various preferred uses, and any embodiment embodying the claims of the present invention should be in the present invention. Within the scope of the technical solution.

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Abstract

一种具有低失调电压高PSRR的带隙基准源，包括：第一P沟道场效应管（MP1）、第二P沟道场效应管（MP2）、第三P沟道场效应管（MP3）、第四P沟道场效应管（MP4）、第一电阻（R1）、第二电阻（R2）、第三电阻（R3）、第一双极型晶体管（Q1）、第二双极型晶体管（Q2）和电压反馈电路（10）。该具有低失调电压高PSRR的带隙基准源通过采用双层电流镜结构以及增加偏置电阻，降低了各个电流镜之间的沟道长度调制效应的影响，保证了电流倍乘系数的准确性，进而降低了输出电压的失调。

Description

一种具有低失调电压高PSRR的带隙基准源 技术领域
本发明涉及带隙基准源技术领域，具体地，涉及一种具有低失调电压高PSRR的带隙基准源。
背景技术
集成电路主要分成模拟电路和数字电路两部分。片上带隙电压基准源作为模拟电路的核心模块，它的性能好坏决定着整个模拟电路乃至整个芯片的性能好坏与功能实现。目前应用最广泛、性能指标最好的带隙电压基准都是采用双极型器件实现，它的原理是将正温度系数的电压和负温度系数的电压以一定的系数相叠加来得到近似零温度系数的带隙电压。
随着技术的进步和人们对系统要求指标的提高，系统对带隙电压基准源指标要求也不断提高，特别是在电压输入范围、电路失调、电源电压抑制比和功耗等方面。有些系统电源电压的变化范围很宽(如2.5V～5.5V)，并且要求功耗很低以延长系统工作时间(例如：电池供电系统、双界面IC卡系统等)；有些系统要求较高的电源抑制比可以减小输出基准电压受到系统电源噪声的影响(例如：电源管理系统)；有些系统要求输出基准电压的失调很小(例如：ADC和DAC电路等)。现有的技术方案很难同时满足以上不同的电路系统对带隙电压基准源的要求。
现有的高电源电压抑制比PSRR(Power Supply Rejection Ratio)的电路一般采用图1所示的结构，核心的带隙基准电路由电流镜MP1、MP2、MP3，电阻R3、R4和三极管Q1、Q2组成。环路放大器通过检测B点电压来控制VREG点，使其工作在正确的电压上。该结构采用电压负反馈的方法来实现核心节点电压VREG在很宽的频率范围内的稳定，从而提高了输出电压的电源抑制比。电路的输出电压为：
Figure PCTCN2015081096-appb-000001
其中，Vbe2为Q2的基极-发射极电压，VT为热电压，R3为电阻R3的阻值，R4为电阻R4的阻值。
通过对以上现有技术的研究和实际电路系统应用环境的考虑很容易发现现有技术存在以下缺点：
(1)、在现有技术中为了实现很宽的电源电压范围，同时支持高、低电源电压输入，考虑到电路的可靠性和寿命，电路本身必须采用高压器件实现，而高压器件受到其本身高阈值电压的影响，很难支持低电压(如：2.5V)工作状态，或者在低电压条件下性能会有很大的下降。
(2)、在现有的技术中，为了实现很高的电源电压抑制比减小基准电压受到系统电源的影响，一般采用电压级联(例如：共源共栅结构、电源regulator等)和很大的片上滤波电容实现。而电压级联会限制输入电压范围，片上滤波电容会占用很大的芯片面积，从而提高芯片的生产成本。
(3)、在式子(1)中输出电压的精度受到电流倍乘因子N的影响，N的变化会导致输出电压的变化，从而影响输出电压的精度。由于A、B两点(Vbe)和E点(VBG)电压差别较大，受到沟道长度调制效应的影响，很难通过电流镜的比例实现精确的倍乘因子N，进而影响输出电压VBG的精度。
发明内容
本发明是为了克服现有技术中带隙基准源受到沟道长度调制效应的影响，输出电压精度不高的缺陷，根据本发明的一个方面，提出一种低低失调电压高PSRR带隙基准源。
根据本发明实施例的一种低低失调电压高PSRR带隙基准源，包括：第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第一电阻、第二电阻、第三电阻、第一双极型晶体管、第二双极型晶体管和电压反馈电路；
第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管和第四P沟道场效应管组成电流镜；第一P沟道场效应管的宽长比与第二P沟道场效应管的宽长比的比值为1∶N，且第一电阻的阻值与第二电阻的阻值的比值为N∶1；
第一P沟道场效应管的栅极与第二P沟道场效应管的栅极相连，并与第三P沟道场效应管的漏极相连；第三P沟道场效应管的栅极与第四P沟道场效应管的栅极相连，并与第一电阻和第三电阻的连接节点相连；
第一P沟道场效应管的漏极与第三P沟道场效应管的源极相连，第二P沟道场效应管的漏极与第四P沟道场效应管的源极相连；
第三P沟道场效应管的漏极依次通过第一电阻、第三电阻与第一双极型晶体管的发射极相连；
第四P沟道场效应管的漏极通过第二电阻与第二双极型晶体管的发射极相连，且 第四P沟道场效应管的漏极还与电压输出端相连；
第一双极型晶体管的基极与第二双极型晶体管的基极相连并接地，第一双极型晶体管的集电极与第二双极型晶体管的集电极相连并接地；
电压反馈电路的电压反馈输入端与第四P沟道场效应管的漏极相连，电压反馈输出端分别与第一P沟道场效应管的源极、第二P沟道场效应管的源极相连；电压反馈电路用于根据第四P沟道场效应管的漏极电压确定输出反馈电压，控制第三P沟道场效应管的漏极电压与第四P沟道场效应管的漏极电压相等。
在上述技术方案中，第一双极型晶体管与第二双极型晶体管的发射极面积之比为M∶1；
电压输出端的输出电压为：
Figure PCTCN2015081096-appb-000002
其中，Vbe2为第二双极型晶体管的基极-发射极电压，VT为热电压，R2为第二电阻的阻值，R3为第三电阻的阻值。
在上述技术方案中，电压反馈电路包括：第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第七N沟道场效应管、第四电阻、补偿电容；
第九P沟道场效应管的源极与第十P沟道场效应管的源极相连并接外部电源，第九P沟道场效应管的栅极与第十P沟道场效应管的栅极相连并与第十P沟道场效应管的漏极相连，第十P沟道场效应管的漏极还与第三N沟道场效应管的漏极相连；第九P沟道场效应管与第十P沟道场效应管组成电流镜；
第九P沟道场效应管的漏极为电压反馈输出端，并分别与第五P沟道场效应管的源极、第六P沟道场效应管的源极相连；
第五P沟道场效应管的栅极与第二P沟道场效应管的栅极相连；
第六P沟道场效应管的栅极为电压反馈输入端，与第四P沟道场效应管的漏极相连；
第七P沟道场效应管的栅极、第八P沟道场效应管的栅极分别与第四P沟道场效应管的栅极相连；
第五P沟道场效应管的漏极与第七P沟道场效应管的源极相连，第六P沟道场效 应管的漏极与第八P沟道场效应管的源极相连；
第七P沟道场效应管的漏极与第一N沟道场效应管的栅极、第二N沟道场效应管的栅极和第三N沟道场效应管的栅极相连；第七P沟道场效应管的漏极还通过第四电阻与第一N沟道场效应管漏极相连的；
第八P沟道场效应管的漏极分别与第二N沟道场效应管的漏极、第七N沟道场效应管的栅极相连；第七N沟道场效应管的漏极与第九P沟道场效应管的漏极相连，且第七N沟道场效应管的源极接地；
第一N沟道场效应管的源极与第四N沟道场效应管的漏极相连，第二N沟道场效应管的源极与第五N沟道场效应管的漏极相连，第三N沟道场效应管的源极与第六N沟道场效应管的漏极相连；
第四N沟道场效应管的栅极、第五N沟道场效应管的栅极、第六N沟道场效应管的栅极分别相连，并与第一N沟道场效应管的漏极相连；
第四N沟道场效应管的源极、第五N沟道场效应管的源极、第六N沟道场效应管的源极分别相连且接地；
补偿电容的一端与第八P沟道场效应管的漏极相连、另一端与第九P沟道场效应管的漏极相连。
在上述技术方案中，第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第九P沟道场效应管、第十P沟道场效应管为可承受高电源电压的晶体管；
第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第七N沟道场效应管为低电源电压、低阈值电压的晶体管。
在上述技术方案中，补偿电容为片内电容，且补偿电容的下极板与第八P沟道场效应管的漏极相连、上极板与第九P沟道场效应管的漏极相连。
在上述技术方案中，电压反馈电路包括：第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第十一P沟道场效应管、第十二P沟道场效应管、第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、补偿电容；
第十一P沟道场效应管的源极与第十二P沟道场效应管的源极相连并接外部电 源，第十一P沟道场效应管的栅极与第十二P沟道场效应管的栅极相连并与第十二P沟道场效应管的漏极相连，第十二P沟道场效应管的漏极还与第六N沟道场效应管的漏极相连；第十一P沟道场效应管与第十二P沟道场效应管组成电流镜；
第十一P沟道场效应管的漏极为电压反馈输出端，并分别与第五P沟道场效应管的源极、第六P沟道场效应管的源极、第七P沟道场效应管的源极相连；
第五P沟道场效应管的栅极与第六P沟道场效应管的栅极相连，并与第二P沟道场效应管的栅极相连；第七P沟道场效应管的栅极为电压反馈输入端，与第四P沟道场效应管的漏极相连；
第五P沟道场效应管的漏极与第八P沟道场效应管的源极相连，第六P沟道场效应管的漏极与第九P沟道场效应管的源极相连，第七P沟道场效应管的漏极与第十P沟道场效应管的源极相连；
第八P沟道场效应管的栅极、第九P沟道场效应管的栅极、第十P沟道场效应管的栅极分别相连，并与第四P沟道场效应管的栅极相连；
第八P沟道场效应管的漏极分别与第四N沟道场效应管的漏极和栅极相连；第九P沟道场效应管的漏极分别与第一N沟道场效应管的漏极、第二N沟道场效应管的栅极相连；第十P沟道场效应管的漏极分别与第二N沟道场效应管的漏极、第三N沟道场效应管的栅极相连；第三N沟道场效应管的源极接地；
第一N沟道场效应管的栅极与第二N沟道场效应管的源极相连，且第一N沟道场效应管的源极接地；第二N沟道场效应管的源极与第五N沟道场效应管的漏极相连；第一N沟道场效应管和第二N沟道场效应管组成Gainboost结构；
第四N沟道场效应管的栅极、第五N沟道场效应管的栅极、第六N沟道场效应管的栅极分别相连；第四N沟道场效应管的源极、第五N沟道场效应管的源极、第六N沟道场效应管的源极分别相连且接地；
补偿电容的一端与第十P沟道场效应管的漏极相连、另一端与第十一P沟道场效应管的漏极相连。
在上述技术方案中，第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第十一P沟道场效应管、第十二P沟道场效应管为可承受高电源电压的晶体管；
第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八 P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管为低电源电压、低阈值电压的晶体管。
在上述技术方案中，补偿电容为片内电容，且补偿电容的下极板与第十P沟道场效应管的漏极相连、上极板与第十一P沟道场效应管的漏极相连。
本发明实施例提供的一种低失调电压高PSRR带隙基准源中，加入第三P沟道场效应管MP3、第四P沟道场效应管MP4和第一电阻R1，将单层电路镜换成带自偏置电阻(即第一电阻R1)的双层电流镜结构，从而降低了各个电流镜场效应管之间的沟道长度调制效应的影响，保证了电流倍乘系数(N)的准确性，进而降低了输出电压的失调。该结构具有低功耗、低失调电压、高电源抑制比PSRR和宽的电源电压输入范围等特点。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。在附图中：
图1为现有技术中的高电源电压抑制比电路的电路图；
图2为本发明实施例中低失调电压高PSRR带隙基准源的电路结构图；
图3为实施例一中低失调电压高PSRR带隙基准源的电路结构图；
图4为实施例二中低失调电压高PSRR带隙基准源的电路结构图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。
根据本发明实施例，提供了一种具有低失调电压高PSRR的带隙基准源，图2为该低失调电压高PSRR带隙基准源的电路图，具体包括：
第一P沟道场效应管MP1、第二P沟道场效应管MP2、第三P沟道场效应管MP3、第四P沟道场效应管MP4、第一电阻R1、第二电阻R2、第三电阻R3、第一双极型晶体管Q1、第二双极型晶体管Q2和电压反馈电路10。
具体的，第一P沟道场效应管MP1、第二P沟道场效应管MP2、第三P沟道场效应管MP3和第四P沟道场效应管MP4组成电流镜；其中，第一P沟道场效应管MP1的宽长比与第二P沟道场效应管MP2的宽长比的比值为1∶N，且第一电阻R1的阻值R1与第二电阻R2的阻值R2的比值为N∶1。
如图2所示，第一P沟道场效应管MP1的栅极与第二P沟道场效应管MP2的栅极相连，并与第三P沟道场效应管MP3的漏极(即图2中的节点C)相连；第三P沟道场效应管MP3的栅极与第四P沟道场效应管MP4的栅极相连，并与第一电阻R1和第三电阻R3的连接节点(即图2中的节点A)相连。
第一P沟道场效应管MP1的漏极与第三P沟道场效应管MP3的源极相连，第二P沟道场效应管MP2的漏极与第四P沟道场效应管MP4的源极相连；第三P沟道场效应管MP3的漏极依次通过第一电阻R1、第三电阻R3与第一双极型晶体管Q1的发射极相连。
第四P沟道场效应管MP4的漏极(即图2中的节点D)通过第二电阻R2与第二双极型晶体管Q2的发射极(即图2中的节点B)相连，且第四P沟道场效应管MP4的漏极还与电压输出端VBG相连。
第一双极型晶体管Q1的基极与第二双极型晶体管Q2的基极相连并接地，第一双极型晶体管Q1的集电极与第二双极型晶体管Q2的集电极相连并接地；
电压反馈电路10的电压反馈输入端Vf与第四P沟道场效应管MP4的漏极相连，电压反馈输出端VREG分别与第一P沟道场效应管MP1的源极、第二P沟道场效应管MP2的源极相连；电压反馈电路10用于根据第四P沟道场效应管MP4的漏极电压确定输出反馈电压，控制第三P沟道场效应管MP3的漏极电压(即节点C处的电压)与第四P沟道场效应管MP4的漏极电压(即节点D处的电压)相等。
下面详细介绍该电路的工作原理。
如图2所示，第一P沟道场效应管MP1的宽长比与第二P沟道场效应管MP2的宽长比的比值为1∶N，且第一电阻R1的阻值R1与第二电阻R2的阻值R2的比值为N∶1，第一双极型晶体管Q1与第二双极型晶体管Q2的发射极面积之比为M∶1。
电压反馈电路10根据第四P沟道场效应管MP4的漏极电压(即节点D处的电压)确定输出反馈电压VREG，使VREG的电压保持在正确的电压上；控制第三P沟道场效应管MP3的漏极电压与第四P沟道场效应管MP4的漏极电压相等，从而保证节点C与节点D两点的电压相等。
由于第一P沟道场效应管MP1的宽长比与第二P沟道场效应管MP2的宽长比的比值为1∶N，则流过第一P沟道场效应管MP1和第二P沟道场效应管MP2两条支路的电流的比值也为1∶N。又由于R1∶R2＝N∶1，则流过MP1和MP2两条支路的电流分别在电阻R1和R2上产生的压降相等。由于C、D两点电压相等，所以A、B两点电压也相等。因此，流过电阻R1、R3、MP3和MP1的电流为：
Figure PCTCN2015081096-appb-000003
其中，Vbe2为第二双极型晶体管Q2的基极-发射极电压(即Q2发射极与Q2基极之间的电压)，Vbe1为第一双极型晶体管Q1的基极-发射极电压，R3为第三电阻R3的阻值。
由于流过MP2的电流是流过MP1的电流的N倍，所以电阻R2上产生的压降为：
Figure PCTCN2015081096-appb-000004
由于流过Q2的电流是流过Q1电流的N倍，又由于，第一双极型晶体管Q1与第二双极型晶体管Q2的发射极面积之比为M∶1，所以Q2的电流密度是Q1电流密度的M×N倍，所以：
Vbe2-Vbe1＝VT×ln(M×N)               (4)
其中，VT为热电压，VT＝KT/q；K为波尔兹曼常数，T为绝对温度，q为电子电荷。联立式子(2)、式子(3)和式子(4)，得到：
Figure PCTCN2015081096-appb-000005
其中，Vbe2为负温度系数，VR2为正温度系数，且：
Figure PCTCN2015081096-appb-000006
Figure PCTCN2015081096-appb-000007
因此，适当的选取式子(5)中VT的温度系数，即适当选取M、N、R2、R3的值，即可以得到近似零温度系数的VBG电压。
与传统的单层电流镜结构相比，在本发明实施例提供的一种具有低失调电压高PSRR的带隙基准源中，加入第三P沟道场效应管MP3、第四P沟道场效应管MP4和第一电阻R1，将单层电路镜换成带自偏置电阻(即第一电阻R1)的双层电流镜结构，从而降低了各个电流镜场效应管之间的沟道长度调制效应的影响，保证了电流倍 乘系数(N)的准确性，进而降低了输出电压的失调。该结构具有低功耗、低失调电压、高电源抑制比PSRR和宽的电源电压输入范围等特点。
第一电阻R1用于偏置第一P沟道场效应管MP1和第三P沟道场效应管MP3，使二者工作在饱和区。加入第二电阻R2，平衡了第一P沟道场效应管MP1和第二P沟道场效应管MP2两条支路的电流镜状态，同时也可以调节正温度系数电压，使带隙基准电压可以直接由D点输出。当保证了C点和D点电压相等的同时，A点和B点的电压也相等。这样不仅使带隙基准电压会实时受到负反馈环路的调节，提高了其对电源的PSRR，而且相对于图1中的带隙基准源还减少了一条电流偏置，降低了电路功耗。
下面通过两个实施例详细介绍该低失调电压高PSRR带隙基准源的结构。
实施例一
参见图3所示，在实施例一中，电压反馈电路10包括：第五P沟道场效应管MP5、第六P沟道场效应管MP6、第七P沟道场效应管MP7、第八P沟道场效应管MP8、第九P沟道场效应管MP9、第十P沟道场效应管MP10、第一N沟道场效应管MN1、第二N沟道场效应管MN2、第三N沟道场效应管MN3、第四N沟道场效应管MN4、第五N沟道场效应管MN5、第六N沟道场效应管MN6、第七N沟道场效应管MN7、第四电阻R4、补偿电容Cc。
具体的，参见图3所示，第九P沟道场效应管MP9的源极与第十P沟道场效应管MP10的源极相连并接外部电源，第九P沟道场效应管MP9的栅极与第十P沟道场效应管MP10的栅极相连并与第十P沟道场效应管MP10的漏极(即节点F)相连，第十P沟道场效应管MP10的漏极还与第三N沟道场效应管MN3的漏极相连；第九P沟道场效应管MP9与第十P沟道场效应管MP10组成电流镜。
第九P沟道场效应管MP9的漏极为电压反馈输出端，并分别与第五P沟道场效应管MP5的源极、第六P沟道场效应管MP6的源极相连。
第五P沟道场效应管MP5的栅极与第二P沟道场效应管MP2的栅极相连。
第六P沟道场效应管MP6的栅极为电压反馈输入端，与第四P沟道场效应管MP4的漏极(即图3中的节点D)相连。
第七P沟道场效应管MP7的栅极、第八P沟道场效应管MP8的栅极分别与第四P沟道场效应管的栅极相连。
第五P沟道场效应管MP5的漏极与第七P沟道场效应管MP7的源极相连，第六 P沟道场效应管MP6的漏极与第八P沟道场效应管MP8的源极相连。
第七P沟道场效应管MP7的漏极(即图3中的节点H)与第一N沟道场效应管MN1的栅极、第二N沟道场效应管MN2的栅极和第三N沟道场效应管MN3的栅极相连；第七P沟道场效应管MP7的漏极还通过第四电阻R4与第一N沟道场效应管MN1漏极(即图3中的节点G)相连的。
第八P沟道场效应管MP8的漏极(即图3中的节点E)分别与第二N沟道场效应管MN2的漏极、第七N沟道场效应管MN7的栅极相连；第七N沟道场效应管MN7的漏极与第九P沟道场效应管MP9的漏极相连，且第七N沟道场效应管MN7的源极接地。
第一N沟道场效应管MN1的源极与第四N沟道场效应管MN4的漏极相连，第二N沟道场效应管MN2的源极与第五N沟道场效应管MN5的漏极相连，第三N沟道场效应管MN3的源极与第六N沟道场效应管MN6的漏极相连。
第四N沟道场效应管MN4的栅极、第五N沟道场效应管MN5的栅极、第六N沟道场效应管MN6的栅极分别相连，并与第一N沟道场效应管MN1的漏极相连。
第四N沟道场效应管MN4的源极、第五N沟道场效应管MN5的源极、第六N沟道场效应管MN6的源极分别相连且接地。
补偿电容Cc的一端与第八P沟道场效应管MP8的漏极相连、另一端与第九P沟道场效应管MP9的漏极相连。
在实施例一中，补偿电容Cc具体为片内电容，且补偿电容Cc的下极板与第八P沟道场效应管MP8的漏极相连、上极板与第九P沟道场效应管MP9的漏极相连。
该电压反馈电路10的工作原理具体如下：
第七P沟道场效应管MP7的漏极检测D点电压变化，并与第八P沟道场效应管MP8、第二N沟道场效应管MN2、第五N沟道场效应管MN5组成Cascode(共源共栅)电压放大器，将D点的电压变化放大。被放大的电压通过第七N沟道场效应管MN7反馈到VREG端，使得VREG保持在正确的电压上，并保证C、D两点的电压相等。该结构采用电压负反馈的方法实现核心节点VREG在很宽的频率范围内稳定；同时，电流镜MP9、MP10和场效应管MN3、MN6组成内部regulator对电源电压与VREG进行隔离，从而提高VREG对电源VDD的电源抑制比PSRR。
此外，在实施例一中，MN1、MN2、MN4、MN5和电阻R4采用电阻自偏置共源共栅结构，在保证E点高阻抗的同时，减少了环路放大器的电流偏置支路个数。同时 MN3和MN6组成的共源共栅放大器可以直接采用电阻自偏置支路进行偏置，MN3和MN6组成的共源共栅放大器增大了F点对地的输出阻抗，使F点(即MP9的栅极)对电源的跟随特性更好，优化了VREG对VDD的电源抑制比，进而优化了VBG对电源VDD的PSRR。
优选的，第一N沟道场效应管MN1、第二N沟道场效应管MN2、第三N沟道场效应管MN3、第四N沟道场效应管MN4、第五N沟道场效应管MN5、第六N沟道场效应管MN6、第九P沟道场效应管MP9、第十P沟道场效应管MP10为可承受高电源电压的晶体管；第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管MP5、第六P沟道场效应管MP6、第七P沟道场效应管MP7、第八P沟道场效应管MP8、第七N沟道场效应管MN7为低电源电压、低阈值电压的晶体管。
采用低阈值电压的晶体管，可以将VREG的电压调到很低而保证所有管子都工作的饱和区。VREG的降低，可以使电路在更低VDD电压下正常工作。而只有高压管MP9、MP10能够“看到”高的电源电压输入，保证了在高电源电压输入的情况下低电压管子不会被击穿。为了保证镜像的准确性，MN1、MN2、MN3、MN4、MN5和MN6都采用同种类型的晶体管。
实施例二
在实施例二中，参见图4所示，电压反馈电路10包括：第五P沟道场效应管MP5、第六P沟道场效应管MP6、第七P沟道场效应管MP7、第八P沟道场效应管MP8、第九P沟道场效应管MP9、第十P沟道场效应管MP10、第十一P沟道场效应管MP11、第十二P沟道场效应管MP12、第一N沟道场效应管MN1、第二N沟道场效应管MN2、第三N沟道场效应管MN3、第四N沟道场效应管MN4、第五N沟道场效应管MN5、第六N沟道场效应管MN6、补偿电容Cc。
第十一P沟道场效应管MP11的源极与第十二P沟道场效应管MP12的源极相连并接外部电源，第十一P沟道场效应管MP11的栅极与第十二P沟道场效应管MP12的栅极相连并与第十二P沟道场效应管MP12的漏极相连，第十二P沟道场效应管MP12的漏极还与第六N沟道场效应管MN6的漏极相连；第十一P沟道场效应管MP11与第十二P沟道场效应管MP12组成电流镜。
第十一P沟道场效应管MP11的漏极为电压反馈输出端，并分别与第五P沟道场效应管MP5的源极、第六P沟道场效应管MP6的源极、第七P沟道场效应管MP7 的源极相连。
第五P沟道场效应管MP5的栅极与第六P沟道场效应管MP6的栅极相连，并与第二P沟道场效应管MP2的栅极相连；第七P沟道场效应管MP7的栅极为电压反馈输入端，与第四P沟道场效应管MP4的漏极相连。
第五P沟道场效应管MP5的漏极与第八P沟道场效应管MP8的源极相连，第六P沟道场效应管MP6的漏极与第九P沟道场效应管MP9的源极相连，第七P沟道场效应管MP7的漏极与第十P沟道场效应管MP10的源极相连。
第八P沟道场效应管MP8的栅极、第九P沟道场效应管MP9的栅极、第十P沟道场效应管MP10的栅极分别相连，并与第四P沟道场效应管MP4的栅极相连。
第八P沟道场效应管MP8的漏极分别与第四N沟道场效应管MN4的漏极和栅极相连；第九P沟道场效应管MP9的漏极分别与第一N沟道场效应管MN1的漏极、第二N沟道场效应管MN2的栅极相连；第十P沟道场效应管MP10的漏极分别与第二N沟道场效应管MN2的漏极、第三N沟道场效应管MN3的栅极相连；第三N沟道场效应管MN3的源极接地。
第一N沟道场效应管MN1的栅极与第二N沟道场效应管MN2的源极相连，且第一N沟道场效应管MN1的源极接地；第二N沟道场效应管MN2的源极与第五N沟道场效应管MN5的漏极相连；第一N沟道场效应管MN1和第二N沟道场效应管MN2组成Gainboost结构。
第四N沟道场效应管MN4的栅极、第五N沟道场效应管MN5的栅极、第六N沟道场效应管MN6的栅极分别相连；第四N沟道场效应管MN4的源极、第五N沟道场效应管MN5的源极、第六N沟道场效应管MN6的源极分别相连且接地。
补偿电容Cc的一端与第十P沟道场效应管MP10的漏极相连、另一端与第十一P沟道场效应管MP11的漏极相连。具体的，补偿电容Cc可以为片内电容，且补偿电容Cc的下极板与第十P沟道场效应管MP10的漏极相连、上极板与第十一P沟道场效应管MP11的漏极相连。
第十一P沟道场效应管MP11、第十二P沟道场效应管MP12组成的电流镜以及第六N沟道场效应管MN6组成内部regulator，产生稳定电压VREG，对电源电压VDD与VREG进行隔离。
该电压反馈电路10的工作原理具体如下：
第七P沟道场效应管MP7采集节点D电压变化，并与第十P沟道场效应管MP10、 第二N沟道场效应管MN2、第五N沟道场效应管MN5组成Cascode(共源共栅)电压放大器，将D点的电压变化放大。被放大的电压通过第三N沟道场效应管MN3反馈到VREG端，使得VREG保持在正确的电压上，并保证C、D两点的电压相等。该结构采用电压负反馈的方法实现核心节点VREG在很宽的频率范围内稳定，从而可以提高输出电压VBG的电源抑制比PSRR。
第五P沟道场效应管MP5和第八P沟道场效应管MP8通过第四N沟道场效应管MN4为第五N沟道场效应管MN5、第六N沟道场效应管MN6提供偏置。第六P沟道场效应管MP6和第九P沟道场效应管MP9为第二N沟道场效应管MN2提供偏置。
在实施例二中，通过加入第八P沟道场效应管MP8和第九P沟道场效应管MP9，也将单层电流镜换成带自偏置电阻的双层电流镜结构。从而降低了各个电流镜之间的沟道长度调制效应的影响，可以保证了电流倍乘系数(N)的准确性，并进而降低了输出电压VBG的失调。同时，该电压反馈电路10采用电压负反馈的方法实现核心节点VREG在很宽的频率范围内稳定，使得VREG保持在正确的电压上，并保证C、D两点的电压相等，可以提高输出电压VBG的电源抑制比PSRR。
此外，在实施例二中，第一N沟道场效应管MN1的栅极与第二N沟道场效应管MN2的源极相连。此时，第一N沟道场效应管MN1和第二N沟道场效应管MN2组成Gainboost结构。
MN1和MN2采用Gainboost结构，提高了F点的输出阻抗；同时MP2和MP5组成Cascode电流镜也提高了D点的输出阻抗；输出阻抗的提高，增大了环路增益，减小了C、D两点的增益误差，从而进一步降低了增益误差对输出电压失调的影响。
优选的，第四N沟道场效应管MN4、第五N沟道场效应管MN5、第六N沟道场效应管MN6、第十一P沟道场效应管MP11、第十二P沟道场效应管MP12为可承受高电源电压的晶体管；第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管MP5、第六P沟道场效应管MP6、第七P沟道场效应管MP7、第八P沟道场效应管MP8、第九P沟道场效应管MP9、第十P沟道场效应管MP10、第一N沟道场效应管MN1、第二N沟道场效应管MN2、第三N沟道场效应管MN3为低电源电压、低阈值电压的晶体管。
采用低阈值电压的晶体管，可以将VREG的电压调到很低而保证所有管子都工作的饱和区。VREG的降低，可以使电路在更低VDD电压下正常工作。而只有高压管MP11、MP12能够“看到”高的电源电压输入，保证了在高电源电压输入的情况下低 电压管子不会被击穿。为了保证镜像的准确性，MN4、MN5和MN6都采用同种类型的晶体管。
本发明能有多种不同形式的具体实施方式，上面以图2-图4为例结合附图对本发明的技术方案作举例说明，这并不意味着本发明所应用的具体实例只能局限在特定的流程或实施例结构中，本领域的普通技术人员应当了解，上文所提供的具体实施方案只是多种优选用法中的一些示例，任何体现本发明权利要求的实施方式均应在本发明技术方案所要求保护的范围之内。
最后应说明的是：以上所述仅为本发明的优选实施例而已，并不用于限制本发明，尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种具有低失调电压高PSRR的带隙基准源，其特征在于，包括：第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第一电阻、第二电阻、第三电阻、第一双极型晶体管、第二双极型晶体管和电压反馈电路；
    所述第一P沟道场效应管、所述第二P沟道场效应管、所述第三P沟道场效应管和所述第四P沟道场效应管组成电流镜；所述第一P沟道场效应管的宽长比与所述第二P沟道场效应管的宽长比的比值为1∶N，且所述第一电阻的阻值与所述第二电阻的阻值的比值为N∶1；
    所述第一P沟道场效应管的栅极与所述第二P沟道场效应管的栅极相连，并与所述第三P沟道场效应管的漏极相连；所述第三P沟道场效应管的栅极与所述第四P沟道场效应管的栅极相连，并与所述第一电阻和所述第三电阻的连接节点相连；
    所述第一P沟道场效应管的漏极与所述第三P沟道场效应管的源极相连，所述第二P沟道场效应管的漏极与所述第四P沟道场效应管的源极相连；
    所述第三P沟道场效应管的漏极依次通过所述第一电阻、所述第三电阻与所述第一双极型晶体管的发射极相连；
    所述第四P沟道场效应管的漏极通过所述第二电阻与所述第二双极型晶体管的发射极相连，且所述第四P沟道场效应管的漏极还与电压输出端相连；
    所述第一双极型晶体管的基极与所述第二双极型晶体管的基极相连并接地，所述第一双极型晶体管的集电极与所述第二双极型晶体管的集电极相连并接地；
    所述电压反馈电路的电压反馈输入端与所述第四P沟道场效应管的漏极相连，电压反馈输出端分别与所述第一P沟道场效应管的源极、所述第二P沟道场效应管的源极相连；所述电压反馈电路用于根据所述第四P沟道场效应管的漏极电压确定输出反馈电压，控制所述第三P沟道场效应管的漏极电压与所述第四P沟道场效应管的漏极电压相等。
  2. 根据权利要求1所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述第一双极型晶体管与所述第二双极型晶体管的发射极面积之比为M∶1；
    所述电压输出端的输出电压为：
    Figure PCTCN2015081096-appb-100001
    其中，Vbe2为第二双极型晶体管的基极-发射极电压，VT为热电压，R2为第二电阻的阻值，R3为第三电阻的阻值。
  3. 根据权利要求1或2所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述电压反馈电路包括：第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第七N沟道场效应管、第四电阻、补偿电容；
    所述第九P沟道场效应管的源极与所述第十P沟道场效应管的源极相连并接外部电源，所述第九P沟道场效应管的栅极与所述第十P沟道场效应管的栅极相连并与所述第十P沟道场效应管的漏极相连，所述第十P沟道场效应管的漏极还与所述第三N沟道场效应管的漏极相连；所述第九P沟道场效应管与所述第十P沟道场效应管组成电流镜；
    所述第九P沟道场效应管的漏极为电压反馈输出端，并分别与所述第五P沟道场效应管的源极、所述第六P沟道场效应管的源极相连；
    所述第五P沟道场效应管的栅极与所述第二P沟道场效应管的栅极相连；
    所述第六P沟道场效应管的栅极为电压反馈输入端，与所述第四P沟道场效应管的漏极相连；
    所述第七P沟道场效应管的栅极、所述第八P沟道场效应管的栅极分别与所述第四P沟道场效应管的栅极相连；
    所述第五P沟道场效应管的漏极与所述第七P沟道场效应管的源极相连，所述第六P沟道场效应管的漏极与所述第八P沟道场效应管的源极相连；
    所述第七P沟道场效应管的漏极与所述第一N沟道场效应管的栅极、所述第二N沟道场效应管的栅极和所述第三N沟道场效应管的栅极相连；所述第七P沟道场效应管的漏极还通过所述第四电阻与所述第一N沟道场效应管漏极相连；
    所述第八P沟道场效应管的漏极分别与所述第二N沟道场效应管的漏极、所述第七N沟道场效应管的栅极相连；所述第七N沟道场效应管的漏极与所述第九P沟道场效应管的漏极相连，且所述第七N沟道场效应管的源极接地；
    所述第一N沟道场效应管的源极与所述第四N沟道场效应管的漏极相连，所述 第二N沟道场效应管的源极与所述第五N沟道场效应管的漏极相连，所述第三N沟道场效应管的源极与所述第六N沟道场效应管的漏极相连；
    所述第四N沟道场效应管的栅极、所述第五N沟道场效应管的栅极、所述第六N沟道场效应管的栅极分别相连，并与所述第一N沟道场效应管的漏极相连；
    所述第四N沟道场效应管的源极、所述第五N沟道场效应管的源极、所述第六N沟道场效应管的源极分别相连且接地；
    所述补偿电容的一端与所述第八P沟道场效应管的漏极相连、另一端与所述第九P沟道场效应管的漏极相连。
  4. 根据权利要求3所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第九P沟道场效应管、第十P沟道场效应管为可承受高电源电压的晶体管；
    所述第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第七N沟道场效应管为低电源电压、低阈值电压的晶体管。
  5. 根据权利要求3所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述补偿电容为片内电容，且所述补偿电容的下极板与所述第八P沟道场效应管的漏极相连、上极板与所述第九P沟道场效应管的漏极相连。
  6. 根据权利要求1或2所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述电压反馈电路包括：第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第十一P沟道场效应管、第十二P沟道场效应管、第一N沟道场效应管、第二N沟道场效应管、第三N沟道场效应管、第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、补偿电容；
    所述第十一P沟道场效应管的源极与所述第十二P沟道场效应管的源极相连并接外部电源，所述第十一P沟道场效应管的栅极与所述第十二P沟道场效应管的栅极相连并与所述第十二P沟道场效应管的漏极相连，所述第十二P沟道场效应管的漏极还与所述第六N沟道场效应管的漏极相连；所述第十一P沟道场效应管与所述第十二P沟道场效应管组成电流镜；
    所述第十一P沟道场效应管的漏极为电压反馈输出端，并分别与所述第五P沟道 场效应管的源极、所述第六P沟道场效应管的源极、所述第七P沟道场效应管的源极相连；
    所述第五P沟道场效应管的栅极与所述第六P沟道场效应管的栅极相连，并与所述第二P沟道场效应管的栅极相连；所述第七P沟道场效应管的栅极为电压反馈输入端，与所述第四P沟道场效应管的漏极相连；
    所述第五P沟道场效应管的漏极与所述第八P沟道场效应管的源极相连，所述第六P沟道场效应管的漏极与所述第九P沟道场效应管的源极相连，所述第七P沟道场效应管的漏极与所述第十P沟道场效应管的源极相连；
    所述第八P沟道场效应管的栅极、所述第九P沟道场效应管的栅极、所述第十P沟道场效应管的栅极分别相连，并与所述第四P沟道场效应管的栅极相连；
    所述第八P沟道场效应管的漏极分别与所述第四N沟道场效应管的漏极和栅极相连；所述第九P沟道场效应管的漏极分别与所述第一N沟道场效应管的漏极、所述第二N沟道场效应管的栅极相连；所述第十P沟道场效应管的漏极分别与所述第二N沟道场效应管的漏极、所述第三N沟道场效应管的栅极相连；所述第三N沟道场效应管的源极接地；
    所述第一N沟道场效应管的栅极与所述第二N沟道场效应管的源极相连，且所述第一N沟道场效应管的源极接地；所述第二N沟道场效应管的源极与所述第五N沟道场效应管的漏极相连；所述第一N沟道场效应管和所述第二N沟道场效应管组成Gainboost结构；
    所述第四N沟道场效应管的栅极、所述第五N沟道场效应管的栅极、所述第六N沟道场效应管的栅极分别相连；所述第四N沟道场效应管的源极、所述第五N沟道场效应管的源极、所述第六N沟道场效应管的源极分别相连且接地；
    所述补偿电容的一端与所述第十P沟道场效应管的漏极相连、另一端与所述第十一P沟道场效应管的漏极相连。
  7. 根据权利要求6所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述第四N沟道场效应管、第五N沟道场效应管、第六N沟道场效应管、第十一P沟道场效应管、第十二P沟道场效应管为可承受高电源电压的晶体管；
    所述第一P沟道场效应管、第二P沟道场效应管、第三P沟道场效应管、第四P沟道场效应管、第五P沟道场效应管、第六P沟道场效应管、第七P沟道场效应管、第八P沟道场效应管、第九P沟道场效应管、第十P沟道场效应管、第一N沟道场效 应管、第二N沟道场效应管、第三N沟道场效应管为低电源电压、低阈值电压的晶体管。
  8. 根据权利要求6所述的具有低失调电压高PSRR的带隙基准源，其特征在于，所述补偿电容为片内电容，且所述补偿电容的下极板与所述第十P沟道场效应管的漏极相连、上极板与所述第十一P沟道场效应管的漏极相连。
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