WO2021248267A1 - 一种高电源纹波抑制的电压基准电路 - Google Patents

一种高电源纹波抑制的电压基准电路 Download PDF

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Publication number
WO2021248267A1
WO2021248267A1 PCT/CN2020/094880 CN2020094880W WO2021248267A1 WO 2021248267 A1 WO2021248267 A1 WO 2021248267A1 CN 2020094880 W CN2020094880 W CN 2020094880W WO 2021248267 A1 WO2021248267 A1 WO 2021248267A1
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circuit
tube
power supply
gate
drain
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PCT/CN2020/094880
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English (en)
French (fr)
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张金勇
梅逢城
曹建民
相韶华
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深圳技术大学
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Priority to PCT/CN2020/094880 priority Critical patent/WO2021248267A1/zh
Publication of WO2021248267A1 publication Critical patent/WO2021248267A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc

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  • the present invention relates to the technical field of integrated circuits, and more specifically, to a voltage reference circuit with high power supply ripple suppression.
  • the CMOS voltage reference is an indispensable key module in the system chip, and it has a wide range of applications in various analog chips such as operational amplifier bias circuits, ADCs, and power management. Especially in high-precision sensing circuits, a precise bias circuit plays a vital role in improving the performance of the entire system. In order to provide a stable and high-precision bias for the entire analog front-end circuit, the voltage reference circuit usually pursues two important design indicators: temperature drift suppression and power supply ripple suppression. At the same time, it is necessary to take into account the complexity, power consumption and chip area of the voltage reference circuit. As a general-purpose module, there are a large number of CMOS voltage reference circuit design schemes.
  • CMOS voltage reference circuit At present, the main implementation methods of CMOS voltage reference circuit are:
  • MOS tubes working in the sub-threshold region can work at a relatively low power supply voltage and bias current, so that a low-voltage operating voltage reference circuit can be designed, and it has a very low circuit Power consumption.
  • Switched capacitor type bandgap reference circuit Switched capacitor technology is widely used in analog integrated circuits due to its high matching accuracy and low static power consumption. Therefore, the voltage reference circuit designed by switched capacitor technology can reach a better level in area and power consumption at the same time.
  • the aforementioned (1) traditional voltage reference circuit can meet basic applications and is suitable for occasions where system accuracy is not high, and its temperature drift suppression and power supply ripple suppression capabilities are average.
  • the voltage reference circuit in the aforementioned (2) can work under the condition of a power supply voltage lower than 1V, but because its MOS tube bias current working in the sub-threshold region is very small, it is very susceptible to transistor leakage current, circuit noise or other noises. Interference.
  • the working state of the MOS transistor in the sub-threshold area is extremely sensitive, and it is easy to leave the sub-threshold area under interference and cause the circuit to fail.
  • the suppression capability of power supply voltage noise is crossed.
  • the voltage reference circuit in the aforementioned (3) has advantages in terms of chip area and power consumption, the total introduction of switching noise and the charge feedthrough effect of the MOS switch have an impact on the output of the reference voltage, and the power supply voltage ripple suppression capability Also poor.
  • the technical problem to be solved by the present invention is to provide a voltage reference circuit with high power supply ripple suppression in view of the above-mentioned defects of the prior art.
  • the technical scheme adopted by the present invention to solve its technical problems is: constructing a voltage reference circuit with high power supply ripple suppression, including: a bandgap reference circuit, a power supply ripple suppression circuit and a soft start circuit;
  • the input terminal of the power supply ripple suppression circuit is connected to an external input power supply voltage
  • the output terminal of the power supply ripple suppression circuit is connected to the input terminal of the bandgap reference circuit
  • the output terminal of the bandgap reference circuit outputs a reference Voltage
  • the soft start circuit is respectively connected to the external input power supply voltage and the bandgap reference circuit
  • the bandgap reference circuit is used to generate a reference voltage
  • the power supply ripple suppression circuit is used to suppress power supply ripple so that the bandgap reference circuit does not change with the external input power supply voltage
  • the soft-start circuit The voltage stabilizing circuit changes from the zero current operating point state to the normal operating point state.
  • the bandgap reference circuit includes: a reference voltage generating circuit and a voltage reference output circuit;
  • the input terminal of the reference voltage generating circuit is connected to the output terminal of the power supply ripple suppression circuit, the output terminal of the reference voltage generating circuit is connected to the input terminal of the voltage reference output circuit, and the output terminal of the voltage reference output circuit The output terminal outputs the reference voltage;
  • the input terminal of the reference voltage generating circuit is the input terminal of the bandgap reference circuit
  • the output terminal of the voltage reference output circuit is the output terminal of the bandgap reference circuit.
  • the reference voltage generating circuit includes: a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first triode, a second triode, and a first resistor;
  • the source of the first PMOS tube is connected to the source of the second PMOS tube and the output terminal of the voltage reference output circuit is connected to the output terminal of the power supply ripple suppression circuit, and the gate of the first PMOS tube
  • the electrode is connected to the gate of the second PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the first triode.
  • the emitter of the tube is connected, the collector of the first triode is grounded, the base of the first triode and the base of the second triode are shorted and connected to the ground, the second The collector of the triode is grounded, and the emitter of the second triode is connected to the source of the second NMOS transistor through the first resistor;
  • the gate of the second NMOS tube is short-circuited with the gate of the first NMOS tube and is connected to the soft-start circuit with the drain of the first NMOS tube; the drain of the second NMOS tube Connected to the drain of the second PMOS tube;
  • the gate of the second PMOS tube and its drain are short-circuited and respectively connected to the input terminals of the power supply ripple suppression circuit and the voltage reference output circuit.
  • the voltage reference output circuit includes: a third PMOS tube, a fourth PMOS tube, a second resistor, and a third triode;
  • the source of the third PMOS tube is connected to the output terminal of the power supply ripple suppression circuit as the input terminal of the voltage reference circuit, and the drain of the third PMOS tube is connected to the source of the fourth PMOS tube ,
  • the gate of the third PMOS tube is connected to the drain of the second PMOS tube and connected to the power supply ripple suppression circuit; the gate of the third PMOS tube is also used as the output of the voltage reference circuit Terminal connected to the soft start circuit;
  • the gate and drain of the fourth PMOS transistor are short-circuited, and the drain of the fourth PMOS transistor is connected to the emitter of the third triode through the second resistor.
  • the base and collector are grounded;
  • connection end of the drain of the fourth PMOS transistor and the second resistor serves as the output end of the bandgap reference circuit to output the reference voltage.
  • the power supply ripple suppression circuit includes: an embedded amplifier connected to the bandgap reference circuit.
  • the power supply ripple suppression circuit further includes: a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, and a ninth NMOS tube;
  • the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are connected to the external input power voltage, the gate of the seventh PMOS transistor is short-circuited with the gate of the eighth PMOS transistor, so The gate of the seventh PMOS transistor is connected to its drain, and the drain of the eighth PMOS transistor is used as the output terminal of the power supply ripple suppression circuit to connect to the input terminal of the bandgap reference circuit;
  • the drain of the seventh NMOS transistor is connected to the drain of the eighth PMOS transistor, the gate of the seventh NMOS transistor is connected to the embedded amplifier; the source of the seventh NMOS transistor is grounded;
  • the gate of the eight NMOS tube is connected to the embedded amplifier, the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, and the gate of the ninth NMOS tube is connected to the embedded amplifier, The source of the ninth NMOS transistor is grounded.
  • the embedded amplifier includes: a fifth PMOS tube, a sixth PMOS tube, a first capacitor, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube;
  • the source of the fifth PMOS tube and the source of the sixth PMOS tube are connected to the drain of the eighth PMOS tube, and the drain of the fifth PMOS tube is connected to the gate of the seventh NMOS tube. Connected to the drain of the third NMOS transistor, and the drain of the fifth PMOS transistor is also connected to the drain of the seventh NMOS transistor through the first capacitor;
  • the gate of the fifth PMOS tube is connected to the drain of the first PMOS tube, and the gate of the sixth PMOS tube is connected to the gate of the first PMOS tube and the gate of the second PMOS tube. Connection end; the drain of the sixth PMOS tube is connected to the first end of the built-in resistor, and the drain of the sixth PMOS tube is also connected to the gate of the eighth NMOS tube and the gate of the third NMOS tube The connecting end of the electrode and the gate of the fourth NMOS and;
  • the second end of the built-in resistor is connected to the drain of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the drain of the sixth NMOS tube, and the source of the sixth NMOS tube is connected to The source of the fifth NMOS tube is grounded; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are connected and connected to the gate of the ninth NMOS tube and the fourth NMOS tube.
  • the drain of the fifth NMOS tube is connected to the source of the third NMOS tube, and the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube.
  • the soft-start circuit includes: a bias circuit connected to the external input power supply voltage to provide a bias to the soft-start circuit.
  • the soft-start circuit further includes: a ninth PMOS tube, a tenth PMOS tube, and an eleventh PMOS tube;
  • the source of the ninth PMOS transistor, the source of the tenth PMOS transistor, and the source of the eleventh PMOS transistor are connected to the external input power supply voltage, and the gate of the eleventh PMOS transistor is connected to the The gate of the third PMOS tube, and the drain of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube;
  • the drain of the ninth PMOS tube is connected to the drain of the first NMOS tube and the connecting end of the gate of the first NMOS tube and the gate of the second NMOS tube.
  • the ninth PMOS tube The gate of the tenth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to its drain, and the drain of the tenth PMOS transistor is connected to the bias circuit.
  • the bias circuit includes: a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a tenth NMOS tube, and an eleventh NMOS tube;
  • the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, and the fifteenth PMOS tube are connected in series in reverse ratio, and the source of the twelfth PMOS tube is connected to the external input power supply voltage,
  • the drain of the fifteenth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the drain of the eleventh NMOS transistor is short-circuited to its gate;
  • the source of the tenth NMOS transistor and the source of the eleventh NMOS transistor are commonly grounded, and the gate of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor.
  • the voltage reference circuit with high power supply ripple suppression implementing the present invention has the following beneficial effects: including: a bandgap reference circuit, a power supply ripple suppression circuit and a soft start circuit; the input end of the power supply ripple suppression circuit is connected to the external input power supply voltage , The output end of the power supply ripple suppression circuit is connected with the input end of the bandgap reference circuit, the output end of the bandgap reference circuit outputs the reference voltage, and the soft start circuit is respectively connected to the external input power supply voltage and the bandgap reference circuit; for the bandgap reference circuit To generate the reference voltage, the power supply ripple suppression circuit is used to suppress the power supply ripple so that the bandgap reference circuit does not change with the external input power supply voltage.
  • the soft start circuit converts the bandgap reference circuit from the zero current operating point state to the normal operating point state.
  • the invention has a wide working voltage range, good power supply ripple suppression capability, low circuit complexity, low power consumption, and small occupied area.
  • FIG. 1 is a schematic structural diagram of a voltage reference circuit with high power supply ripple suppression according to an embodiment of the present invention
  • FIG. 2 is a circuit principle diagram of a voltage reference circuit with high power supply ripple suppression provided by an embodiment of the present invention.
  • FIG. 1 is a voltage reference circuit with high power supply ripple suppression provided by an embodiment of the present invention.
  • the voltage reference circuit with high power supply ripple suppression can be widely used in analog chips such as operational amplifier bias circuits, ADCs, and power management. middle.
  • the voltage reference circuit for high power supply ripple suppression includes: a bandgap reference circuit 20, a power supply ripple suppression circuit 10 and a soft start circuit 30.
  • the input terminal of the power supply ripple suppression circuit 10 is connected to the external input power supply voltage
  • the output terminal of the power supply ripple suppression circuit 10 is connected to the input terminal of the bandgap reference circuit 20, and the output terminal of the bandgap reference circuit 20 outputs the reference voltage
  • soft start The circuit 30 is respectively connected to the external input power supply voltage and the bandgap reference circuit 20; the bandgap reference circuit 20 is used to generate a reference voltage, and the power supply ripple suppression circuit 10 is used to suppress the power supply ripple so that the bandgap reference circuit 20 does not follow the external input power supply voltage Change, the soft start circuit 30 converts the voltage stabilizing circuit from the zero current operating point state to the normal operating point state.
  • the bandgap reference circuit 20 includes: a reference voltage generating circuit and a voltage reference output circuit.
  • the input terminal of the reference voltage generating circuit is connected to the output terminal of the power supply ripple suppression circuit 10, the output terminal of the reference voltage generating circuit is connected to the input terminal of the voltage reference output circuit, and the output terminal of the voltage reference output circuit outputs the reference voltage; the reference voltage is generated
  • the input terminal of the circuit is the input terminal of the bandgap reference circuit 20, and the output terminal of the voltage reference output circuit is the output terminal of the bandgap reference circuit 20.
  • FIG. 2 is a circuit diagram of a voltage reference circuit with high power supply ripple suppression according to an embodiment of the present invention.
  • VDD is the external input power supply voltage
  • GND is the ground (ie, the power reference ground).
  • the reference voltage generating circuit includes: a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first transistor Q1, a second transistor Q2, and The first resistance R1.
  • the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are connected to the output terminal of the voltage reference output circuit to the output terminal of the power supply ripple suppression circuit 10.
  • the gate of the first PMOS tube MP1 is connected to the second PMOS tube
  • the gate of MP2 is connected, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the source of the first NMOS tube MN1 is connected to the emitter of the first transistor Q1, the first transistor
  • the collector of Q1 is grounded, the base of the first transistor Q1 and the base of the second transistor Q2 are shorted and connected to ground, the collector of the second transistor Q2 is grounded, and the collector of the second transistor Q2 is grounded.
  • the emitter is connected to the source of the second NMOS tube MN2 through the first resistor R1; the gate of the second NMOS tube MN2 is shorted to the gate of the first NMOS tube MN1 and is connected to the drain of the first NMOS tube MN1 together to the soft Start-up circuit 30; the drain of the second NMOS tube MN2 is connected to the drain of the second PMOS tube MP2; the gate of the second PMOS tube MP2 is short-circuited with its drain and connected to the power supply ripple suppression circuit 10 and the voltage reference output circuit respectively ⁇ input terminal.
  • the voltage reference output circuit includes: a third PMOS tube MP3, a fourth PMOS tube MP4, a second resistor R2, and a third transistor Q3.
  • the source of the third PMOS tube MP3 is used as the input terminal of the voltage reference circuit to connect to the output terminal of the power ripple suppression circuit 10, the drain of the third PMOS tube MP3 is connected to the source of the fourth PMOS tube MP4, and the third PMOS tube MP3
  • the gate of the second PMOS tube MP2 is connected to the drain of the power supply ripple suppression circuit 10; the gate of the third PMOS tube MP3 is also connected to the soft-start circuit 30 as the output terminal of the voltage reference circuit;
  • the fourth PMOS tube The gate and drain of MP4 are short-circuited, the drain of the fourth PMOS transistor MP4 is connected to the emitter of the third transistor Q3 through the second resistor R2, and the base and collector of the third transistor Q3 are grounded; fourth The connection end of the drain of the PMOS transistor MP4 and the second resistor R2 serves as the output end of the bandgap reference circuit 20 to output a reference voltage.
  • the reference voltage generating circuit is independent of temperature.
  • the design principle of the reference voltage generating circuit is to use voltages with opposite temperature coefficients to be linearly superimposed with appropriate weights to reach a reference voltage with zero temperature coefficient at a certain temperature, thereby obtaining a reference that basically does not change with temperature.
  • Voltage the negative temperature coefficient voltage is generated by the base-emitter voltage of the first transistor Q1 and the second transistor Q2 of the PNP, and the positive temperature coefficient voltage is generated by the first transistor Q1 and the first transistor Q1 operating at different current densities.
  • the voltage difference ⁇ VBE between the base region and the emitter region generated by the second transistor Q2 is generated.
  • the current proportional to temperature is:
  • V BE1 is the base-emitter voltage of the first transistor Q1
  • V BE2 is the base-emitter voltage of the second transistor Q2
  • R1 is the resistance of the first resistor R1
  • KT/ q is a coefficient
  • n is the area ratio of the first transistor Q1 to the second transistor Q2.
  • the voltage reference output circuit is composed of a third PMOS tube MP3, a fourth PMOS tube MP4, a third transistor Q3 and a second resistor R2, and its output band gap voltage is:
  • Vref is the reference voltage output by the bandgap reference circuit 20
  • VBE3 is the base-emitter voltage of the third transistor Q3
  • R2 is the resistance value of the second resistor R2.
  • the bandgap reference circuit 20 since the entire voltage reference circuit adopts an internal feedback mechanism, the bandgap reference circuit 20 does not adopt the cascode cascode structure used in the mainstream bandgap reference circuit 20, which avoids the cascode cascode structure of the mainstream cascode.
  • the structure consumes extra MOS tube over-driving voltage, which causes the problem of higher power supply voltage during normal operation.
  • the reference voltage output by the bandgap reference circuit 20 of the present invention is lower than the power supply voltage by at least 3 overdrive voltages. Therefore, the power supply voltage can work at less than 1.8V. Of course, this embodiment can also achieve a power supply voltage as low as about 1.5V or even lower through reasonable design.
  • the power supply ripple suppression circuit 10 of this embodiment includes: an embedded amplifier connected to the bandgap reference circuit 20.
  • the power supply ripple suppression circuit 10 further includes: a seventh PMOS tube MP7, an eighth PMOS tube MP8, a seventh NMOS tube MN7, an eighth NMOS tube MN8, and a ninth NMOS tube MN9.
  • the source of the seventh PMOS tube MP7 and the source of the eighth PMOS tube MP8 are connected to the external input power voltage, the gate of the seventh PMOS tube MP7 is short-circuited with the gate of the eighth PMOS tube MP8, and the gate of the seventh PMOS tube MP7
  • the drain of the eighth PMOS tube MP8 is connected to the input terminal of the bandgap reference circuit 20 as the output terminal of the power ripple suppression circuit 10; the drain of the seventh NMOS tube MN7 is connected to the drain of the eighth PMOS tube MP8.
  • the gate of the seventh NMOS tube MN7 is connected to the embedded amplifier; the source of the seventh NMOS tube MN7 is grounded; the gate of the eighth NMOS tube MN8 is connected to the embedded amplifier, and the source of the eighth NMOS tube MN8 is connected to the ninth NMOS
  • the drain of the tube MN9 is connected, the gate of the ninth NMOS tube MN9 is connected to the embedded amplifier, and the source of the ninth NMOS tube MN9 is grounded.
  • the embedded amplifier includes: a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first capacitor C1, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, and a fourth NMOS tube MN4.
  • Six NMOS tube MN6 Six NMOS tube MN6.
  • the source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are connected to the drain of the eighth PMOS tube MP8, and the drain of the fifth PMOS tube MP5 is connected to the gate of the seventh NMOS tube MN7 and the third NMOS tube.
  • the drain of MN3 is connected, the drain of the fifth PMOS transistor MP5 is also connected to the drain of the seventh NMOS transistor MN7 through the first capacitor C1; the gate of the fifth PMOS transistor MP5 is connected to the drain of the first PMOS transistor MP1, the sixth The gate of the PMOS tube MP6 is connected to the connecting terminal of the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2; the drain of the sixth PMOS tube MP6 is connected to the first terminal of the built-in resistor, and the sixth PMOS tube MP6
  • the drain is also connected to the gate of the eighth NMOS tube MN8, the gate of the third NMOS tube MN3, and the connecting end of the gate of the fourth NMOS tube; the second end of the built-in resistor is connected to the drain of the fourth NMOS tube MN4 ,
  • the drain of the fourth NMOS transistor MN4 is connected to the drain of the sixth NMOS transistor MN6, the source of the sixth NMOS transistor MN6 and the
  • the bandgap reference circuit 20 is set to work under the internal calibration voltage Vreg (that is, the eighth PMOS tube MP8), and the high-gain feedback loop ensures the drain potential of the first PMOS tube MP1 and the second PMOS tube MP2.
  • Vreg that is, the drain voltage of the eighth PMOS tube MP8
  • the bandgap reference circuit 20 working under the internal voltage has a higher The power supply rejection ratio.
  • the suppression principle of the power supply ripple suppression circuit 10 of this embodiment is as follows: Assume that the change (set increase) of the external input power supply voltage VDD causes the drain voltage (ie Vreg) of the eighth PMOS tube MP8 to increase, causing the flow through The relative values of the current of the first transistor Q1, the second transistor Q2, the drain potential of the first PMOS transistor MP1 and the gate potential of the second PMOS transistor MP2 change. The variation of the drain potential of the first PMOS tube MP1 and the gate potential of the second PMOS tube MP2 passes through the fifth PMOS tube MP5, the sixth PMOS tube MP6, the third NMOS tube MN3, the fourth NMOS tube MN4, and the fifth NMOS tube.
  • the built-in amplifier formed by the tube MN5 and the sixth NMOS tube MN6 amplifies the gate potential of the seventh NMOS tube MN7, and finally the feedback current generated by the seventh NMOS tube MN7 reduces the drain voltage of the eighth PMOS tube MP8 , To maintain the correct voltage required.
  • the embedded amplifier is a two-pole amplifier.
  • the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5, and the sixth NMOS tube MN6 form a cascode structure of common gate cascode, which makes the gain of the embedded amplifier very high. High open loop gain.
  • the first capacitor C1 is used as a Miller compensation capacitor, so that the embedded amplifier has high stability.
  • the circuit can ensure that the gate-drain voltages of the first PMOS tube MP1 and the second PMOS tube MP2 are stable and equal, so that the Vreg voltage can remain stable without changing with the external input power supply voltage (VDD). .
  • the feedback mechanism ensures that the currents of the first transistor Q1 and the second transistor Q2 have relatively small changes, and the output Vref DC current is formed by the third PMOS tube MP3 and the second PMOS tube MP2
  • the current mirror mirrors therefore, the Vref branch current can be kept stable, and the Vref output has a high suppression ability to the change of the power supply VDD.
  • the soft start circuit 30 includes: a bias circuit connected to an external input power supply voltage to provide a bias to the soft start circuit 30.
  • the soft start circuit 30 further includes: a ninth PMOS tube MP9, a tenth PMOS tube MP10, and an eleventh PMOS tube MP11.
  • the source of the ninth PMOS tube MP9, the source of the tenth PMOS tube MP10, and the source of the eleventh PMOS tube MP11 are connected to the external input power voltage, and the gate of the eleventh PMOS tube MP11 is connected to the gate of the third PMOS tube MP3
  • the drain of the eleventh PMOS tube MP11 is connected to the drain of the tenth PMOS tube MP10; the drain of the ninth PMOS tube MP9 and the drain of the first NMOS tube MN1 and the gate of the first NMOS tube MN1 and the second
  • the connection end of the gate of the NMOS tube MN2 is connected, the gate of the ninth PMOS tube MP9 is connected to the gate of the tenth PMOS tube MP10, and the gate of the tenth PMOS tube MP10 is connected to its drain.
  • the drain is connected to the bias circuit.
  • the bias circuit includes: a twelfth PMOS tube MP12, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a fifteenth PMOS tube MP15, a tenth NMOS tube MN10, and an eleventh NMOS tube MN11 .
  • the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14, and the fifteenth PMOS tube MP15 are connected in series in reverse order, and the source of the twelfth PMOS tube MP12 is connected to the external input power supply voltage,
  • the drain of the fifteenth PMOS tube MP15 is connected to the drain of the eleventh NMOS tube MN11, and the drain of the eleventh NMOS tube MN11 is shorted to its gate; the source of the tenth NMOS tube MN10 and the eleventh NMOS tube MN11
  • the sources of the tenth NMOS transistor MN10 are connected to the gate of the eleventh NMOS transistor MN11.
  • the main function of the soft start circuit 30 of this embodiment is to switch the bandgap reference circuit 20 from the zero current operating point state to the normal operating point state of the circuit, so as to prevent the circuit from entering the zero state steady state after power-on and failing to realize the circuit startup.
  • the bias circuit provides a bias to the soft start circuit 30, wherein the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the 14th PMOS tube MP14, and the fifteenth PMOS tube MP15 consist of four inverted tubes. Connect in series to obtain a large resistance, which in turn makes the circuit have a very low quiescent current.
  • the working principle of the soft start circuit 30 is: when the voltage stabilizer circuit is powered on, if the voltage stabilizer circuit does not work normally, the entire bias circuit generates zero current. At this time, the first NMOS tube MN1 and the second NMOS tube The gate voltage of MN2 is very low, and the gate voltages of the first PMOS tube MP1 and the second PMOS tube MP2 are very high. Therefore, the eleventh PMOS tube MP11 in the soft start circuit 30 is turned off.
  • the current mirror composed of the ninth PMOS tube MP9 and the tenth PMOS tube MP10 will start to work through the self-bias circuit of the soft start circuit 30, thereby causing the first NMOS tube MN1 and the second NMOS tube MN2 to work. Therefore, the bandgap reference circuit 20 starts to work.
  • the gate voltages of the first PMOS tube MP1 and the second PMOS tube MP2 drop, causing the eleventh PMOS tube MP11 to be turned on.
  • the eleventh PMOS tube MP11 makes it possible to flow through the ninth PMOS tube MP9. And the current of the tenth PMOS tube MP10 is almost zero, so that the soft start circuit 30 is turned off.
  • the power consumption of the soft-start circuit 30 after normal startup is extremely small, and the current in the bandgap reference circuit 20 can be at the microampere level. Therefore, the power consumption of the entire voltage stabilizing circuit can reach the microwatt level.
  • the embodiment of the present invention can be implemented by using a high-voltage MOS tube, or the structure of the built-in amplifier in the internal feedback control can be modified, for example, an internal OTA amplifier can be used to implement the internal feedback control.
  • a traditional common-gate cascaded PMOS tube can be used to replace the first PMOS tube MP1 and the second PMOS tube MP2 in FIG. 2.
  • the first NMOS tube MN1 and the first NMOS tube MN1 in the bandgap reference circuit 20 can also be replaced by traditional common-gate cascaded NMOS tubes.
  • the soft start circuit 30 can be modified in other forms to realize circuit start. Based on such a design, the effect and performance of improving power supply voltage ripple suppression designed by the present invention can also be achieved.
  • the present invention is designed based on lower voltage and frequency, but its architecture and design principles are suitable for voltage reference circuit design applied in other application scenarios, such as high-voltage power supply chips and high-frequency circuit power supply chips.
  • the circuit structure of the invention is simple, can provide a reference voltage with high suppression capability for temperature drift and power supply voltage ripple, and has low circuit power consumption and a small-sized chip area at the same time.
  • the power supply ripple suppression circuit 10 based on an internal high-gain feedback mechanism can obtain a strong power supply ripple suppression capability.
  • the bandgap reference circuit 20 of the present invention can work normally at a voltage lower than 1.8V, or even 1.5V, within the working voltage range.
  • the circuit adopts a low bias current to achieve higher performance while having low static power consumption; the circuit has fewer components and small size, and is easy to realize monolithic integration under standard CMOS technology and high-voltage CMOS technology.

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Abstract

本发明涉及一种高电源纹波抑制的电压基准电路，包括：带隙基准电路、电源纹波抑制电路以及软启动电路；电源纹波抑制电路的输入端与外部输入电源电压连接，电源纹波抑制电路的输出端与带隙基准电路的输入端连接，带隙基准电路的输出端输出参考电压，软启动电路分别连接外部输入电源电压以及带隙基准电路；带隙基准电路用于产生参考电压，电源纹波抑制电路用于抑制电源纹波以使带隙基准电路不随外部输入电源电压变化，软启动电路将稳压电路从零电流工作点状态转换为正常工作点状态。本发明具有较宽的工作电压范围，温漂抑制能力和电源纹波抑制能力好，电路复杂度低，功耗低，且占用面积小。

Description

一种高电源纹波抑制的电压基准电路 技术领域
本发明涉及集成电路的技术领域，更具体地说，涉及一种高电源纹波抑制的电压基准电路。
背景技术
CMOS电压基准是系统芯片中必不可少的关键模块，在各类运放偏置电路、ADC、电源管理等模拟芯片中有着广泛的应用。特别是高精度传感电路中，精准的偏置电路对于整个系统的性能提高具有至关重要的作用。为了给整个模拟前端电路提供稳定高精度的偏置，电压基准电路通常追求两个重要的设计指标：温漂抑制能力和电源纹波抑制能力。同时要兼顾波及电压基准电路的复杂度、功耗和芯片面积。作为一个通用模块，目前已有大量的CMOS电压基准电路设计方案。
目前对CMOS电压基准电路主要实现方法有：
(1)传统的电压基准电路：作为经典的电压带隙基准电路，采用三极管与电阻作为温度补偿，同时通过运算放大器作为误差放大来控制三极管上方的MOS电流镜，用来提升带隙电压基准的输出精度。
(2)亚阈值区的电压基准电路：工作在亚阈值区的MOS管可以工作在比较低的电源电压和偏置电流，从而可以设计出低电压工作的电压基准电路，并且具有十分低的电路功耗。
(3)开关电容型带隙基准电路：开关电容技术由于其匹配精度高、静态功耗小的优点在模拟集成电路中应用非常广泛。因此，通过开关电容技术设计的电压基准电路可以同时在面积和功耗上达到一个较好的水平。
然而，前述(1)传统的电压基准电路能够满足基本的应用，适合于系统精度要求不高的场合，其温漂抑制和电源纹波抑制能力一般。前述(2)中的电压基准电路可以在低于1V的电源电压条件下工作，但是由于其工作在亚阈值区的MOS管偏置电流很小，极易受晶体管漏电流、电路噪声或其他噪声的干扰。同时亚 阈值区的MOS晶体管工作状态极其敏感，在受干扰下容易脱离亚阈值区而使电路失效。电源电压噪声的抑制能力交叉。前述(3)中的电压基准电路尽管在芯片面积和功耗方面占优势，但共引入的开关噪声，以及MOS开关的电荷馈通效应对基准电压的输出有影响，同时电源电压纹波抑制能力也较差。
发明概述
技术问题
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种高电源纹波抑制的电压基准电路。
问题的解决方案
技术解决方案
本发明解决其技术问题所采用的技术方案是：构造一种高电源纹波抑制的电压基准电路，包括：带隙基准电路、电源纹波抑制电路以及软启动电路；
所述电源纹波抑制电路的输入端与外部输入电源电压连接，所述电源纹波抑制电路的输出端与所述带隙基准电路的输入端连接，所述带隙基准电路的输出端输出参考电压，所述软启动电路分别连接所述外部输入电源电压以及所述带隙基准电路；
所述带隙基准电路用于产生参考电压，所述电源纹波抑制电路用于抑制电源纹波以使所述带隙基准电路不随所述外部输入电源电压变化，所述软启动电路将所述稳压电路从零电流工作点状态转换为正常工作点状态。
在一个实施例中，所述带隙基准电路包括：基准电压产生电路和电压基准输出电路；
所述基准电压产生电路的输入端与所述电源纹波抑制电路的输出端连接，所述基准电压产生电路的输出端与所述电压基准输出电路的输入端连接，所述电压基准输出电路的输出端输出所述参考电压；
所述基准电压产生电路的输入端为所述带隙基准电路的输入端，所述电压基准输出电路的输出端为所述带隙基准电路的输出端。
在一个实施例中，所述基准电压产生电路包括：第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管、第一三极管、第二三极管以及第一电阻；
所述第一PMOS管的源极和所述第二PMOS管的源极连接和所述电压基准输出电路的输出端连接所述电源纹波抑制电路的输出端，所述第一PMOS管的栅极与所述第二PMOS管的栅极连接，所述第一PMOS管的漏极与所述第一NMOS管的漏极连接，所述第一NMOS管的源极与所述第一三极管的发射极连接，所述第一三极管的集电极接地，所述第一三极管的基极与所述第二三极管的基极短接并接至地，所述第二三极管的集电极接地，所述第二三极管的发射极通过所述第一电阻连接所述第二NMOS管的源极；
所述第二NMOS管的栅极与所述第一NMOS管的栅极短接并与所述第一NMOS管的漏极共同连接至所述软启动电路；所述第二NMOS管的漏极与所述第二PMOS管的漏极连接；
所述第二PMOS管的栅极与其漏极短接并分别连接所述电源纹波抑制电路和所述电压基准输出电路的输入端。
在一个实施例中，所述电压基准输出电路包括：第三PMOS管、第四PMOS管、第二电阻和第三三极管；
所述第三PMOS管的源极作为所述电压基准电路的输入端连接所述电源纹波抑制电路的输出端，所述第三PMOS管的漏极与所述第四PMOS管的源极连接，所述第三PMOS管的栅极与所述第二PMOS管的漏极连接并连接至所述电源纹波抑制电路；所述第三PMOS管的栅极还作为所述电压基准电路的输出端连接至所述软启动电路；
所述第四PMOS管的栅极与漏极短接，所述第四PMOS管的漏极通过所述第二电阻连接所述第三三极管的发射极，所述第三三极管的基极和集电极接地；
所述第四PMOS管的漏极与所述第二电阻的连接端作为所述带隙基准电路的输出端输出所述参考电压。
在一个实施例中，所述电源纹波抑制电路包括：与所述带隙基准电路连接的内嵌放大器。
在一个实施例中，所述电源纹波抑制电路还包括：第七PMOS管、第八PMOS管、第七NMOS管、第八NMOS管和第九NMOS管；
所述第七PMOS管的源极和所述第八PMOS管的源极连接所述外部输入电源电 压，所述第七PMOS管的栅极与所述第八PMOS管的栅极短接，所述第七PMOS管的栅极与其漏极连接，所述第八PMOS管的漏极作为所述电源纹波抑制电路的输出端连接所述带隙基准电路的输入端；
所述第七NMOS管的漏极连接所述第八PMOS管的漏极，所述第七NMOS管的栅极连接所述内嵌放大器；所述第七NMOS管的源极接地；所述第八NMOS管的栅极连接所述内嵌放大器，所述第八NMOS管的源极与所述第九NMOS管的漏极连接，所述第九NMOS管的栅极连接所述内嵌放大器，所述第九NMOS管的源极接地。
在一个实施例中，所述内嵌放大器包括：第五PMOS管、第六PMOS管、第一电容、第三NMOS管、第四NMOS管、第五NMOS管和第六NMOS管；
所述第五PMOS管的源极和所述第六PMOS管的源极与所述第八PMOS管的漏极连接，所述第五PMOS管的漏极与所述第七NMOS管的栅极和所述第三NMOS管的漏极连接，所述第五PMOS管的漏极还通过所述第一电容连接所述第七NMOS管的漏极；
所述第五PMOS管的栅极连接所述第一PMOS管的漏极，所述第六PMOS管的栅极连接所述第一PMOS管的栅极和所述第二PMOS管的栅极的连接端；所述第六PMOS管的漏极连接内嵌电阻的第一端，所述第六PMOS管的漏极还连接所述第八NMOS管的栅极、所述第三NMOS管的栅极和所述第四NMOS和的栅极的连接端；
所述内嵌电阻的第二端连接所述第四NMOS管的漏极，所述第四NMOS管的漏极连接所述第六NMOS管的漏极，所述第六NMOS管的源极和所述第五NMOS管的源极接地；所述第五NMOS管的栅极和所述第六NMOS管的栅极连接并连接至所述第九NMOS管的栅极和所述第四NMOS管的漏极，所述第五NMOS管的漏极连接所述第三NMOS管的源极连接，所述第三NMOS管的栅极和所述第四NMOS管的栅极连接。
在一个实施例中，所述软启动电路包括：与所述外部输入电源电压连接、给所述软启动电路提供偏置的偏置电路。
在一个实施例中，所述软启动电路还包括：第九PMOS管、第十PMOS管和第 十一PMOS管；
所述第九PMOS管的源极、所述第十PMOS管的源极和所述第十一PMOS管的源极连接所述外部输入电源电压，所述第十一PMOS管的栅极连接所述第三PMOS管的栅极，所述第十一PMOS管的漏极连接所述第十PMOS管的漏极；
所述第九PMOS管的漏极与所述第一NMOS管的漏极和所述第一NMOS管的栅极与所述第二NMOS管的栅极的连接端连接，所述第九PMOS管的栅极与所述第十PMOS管的栅极连接，且所述第十PMOS管的栅极与其漏极连接，所述第十PMOS管的漏极与所述偏置电路连接。
在一个实施例中，所述偏置电路包括：第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管、第十NMOS管和第十一NMOS管；
所述第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管依次倒比串联连接，且所述第十二PMOS管的源极连接所述外部输入电源电压、所述第十五PMOS管的漏极与所述第十一NMOS管的漏极连接，所述第十一NMOS管的漏极与其栅极短接；
所述第十NMOS管的源极和所述第十一NMOS管的源极共同接地，所述第十NMOS管的栅极和所述第十一NMOS管的栅极连接。
发明的有益效果
有益效果
实施本发明的高电源纹波抑制的电压基准电路，具有以下有益效果：包括：带隙基准电路、电源纹波抑制电路以及软启动电路；电源纹波抑制电路的输入端与外部输入电源电压连接，电源纹波抑制电路的输出端与带隙基准电路的输入端连接，带隙基准电路的输出端输出参考电压，软启动电路分别连接外部输入电源电压以及带隙基准电路；带隙基准电路用于产生参考电压，电源纹波抑制电路用于抑制电源纹波以使带隙基准电路不随外部输入电源电压变化，软启动电路将带隙基准电路从零电流工作点状态转换为正常工作点状态。本发明具有较宽的工作电压范围，电源纹波抑制能力好，电路复杂度低，功耗低，且占用面积小。
对附图的简要说明
附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是本发明实施例提供的一种高电源纹波抑制的电压基准电路的结构示意图；
图2是本发明实施例提供的一种高电源纹波抑制的电压基准电路的电路原理图。
实施该发明的最佳实施例
本发明的最佳实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
参考图1，图1为本发明实施例提供的高电源纹波抑制的电压基准电路，该高电源纹波抑制的电压基准电路可广泛应用于运放偏置电路、ADC、电源管理等模拟芯片中。
具体的，如图1所示，该高电源纹波抑制的电压基准电路包括：带隙基准电路20、电源纹波抑制电路10以及软启动电路30。
电源纹波抑制电路10的输入端与外部输入电源电压连接，电源纹波抑制电路10的输出端与带隙基准电路20的输入端连接，带隙基准电路20的输出端输出参考电压，软启动电路30分别连接外部输入电源电压以及带隙基准电路20；带隙基准电路20用于产生参考电压，电源纹波抑制电路10用于抑制电源纹波以使带隙基准电路20不随外部输入电源电压变化，软启动电路30将稳压电路从零电流工作点状态转换为正常工作点状态。
本实施例中，带隙基准电路20包括：基准电压产生电路和电压基准输出电路。
基准电压产生电路的输入端与电源纹波抑制电路10的输出端连接，基准电压产生电路的输出端与电压基准输出电路的输入端连接，电压基准输出电路的输出端输出参考电压；基准电压产生电路的输入端为带隙基准电路20的输入端，电压基准输出电路的输出端为带隙基准电路20的输出端。
参考图2，图2为本发明实施例提供的一种高电源纹波抑制的电压基准电路的电路图。如图2所示，VDD为外部输入电源电压，GND为地(即电源参考地)。
如图2所示，基准电压产生电路包括：第一PMOS管MP1、第二PMOS管MP2、第一NMOS管MN1、第二NMOS管MN2、第一三极管Q1、第二三极管Q2以及第一电阻R1。
第一PMOS管MP1的源极和第二PMOS管MP2的源极连接和电压基准输出电路的输出端连接电源纹波抑制电路10的输出端，第一PMOS管MP1的栅极与第二PMOS管MP2的栅极连接，第一PMOS管MP1的漏极与第一NMOS管MN1的漏极连接，第一NMOS管MN1的源极与第一三极管Q1的发射极连接，第一三极管Q1的集电极接地，第一三极管Q1的基极与第二三极管Q2的基极短接并接至地，第二三极管Q2的集电极接地，第二三极管Q2的发射极通过第一电阻R1连接第二NMOS管MN2的源极；第二NMOS管MN2的栅极与第一NMOS管MN1的栅极短接并与第一NMOS管MN1的漏极共同连接至软启动电路30；第二NMOS管MN2的漏极与第二PMOS管MP2的漏极连接；第二PMOS管MP2的栅极与其漏极短接并分别连接电源纹波抑制电路10和电压基准输出电路的输入端。
进一步地，如图2所示，电压基准输出电路包括：第三PMOS管MP3、第四PMOS管MP4、第二电阻R2和第三三极管Q3。
第三PMOS管MP3的源极作为电压基准电路的输入端连接电源纹波抑制电路10的输出端，第三PMOS管MP3的漏极与第四PMOS管MP4的源极连接，第三PMOS管MP3的栅极与第二PMOS管MP2的漏极连接并连接至电源纹波抑制电路10；第三PMOS管MP3的栅极还作为电压基准电路的输出端连接至软启动电路30；第四PMOS管MP4的栅极与漏极短接，第四PMOS管MP4的漏极通过第二电阻R2连接第三三极管Q3的发射极，第三三极管Q3的基极和集电极接地；第四PMOS管MP4的漏极与第二电阻R2的连接端作为带隙基准电路20的输出端输出参考电压。
本实施例中，基准电压产生电路与温度无关。本实施例中，基准电压产生电路的设计原理为利用具有相反温度系数的电压以适当的权重线性叠加，在某一温度达到具有零温度系数的基准电压，从而得到一个基本上不随温度变化的基准电压。其中，负温度系数电压由PNP的第一三极管Q1和第二三极管Q2的基极-发射极电压产生，正温度系数电压由工作在不同电流密度下的第一三极管Q1和第 二三极管Q2产生的基区-发射区的电压差ΔVBE产生。其中与温度成正比的电流为：
Figure PCTCN2020094880-appb-000001
上式中，V BE1为第一三极管Q1的基区-发射区电压，V BE2为第二三极管Q2的基区-发射区电压，R1为第一电阻R1的阻值，KT/q为系数，n为第一三极管Q1与第二三极管Q2的面积比。
电压基准输出电路由第三PMOS管MP3、第四PMOS管MP4、第三三极管Q3和第二电阻R2组成，其输出带隙电压为：
Figure PCTCN2020094880-appb-000002
上式中，Vref即为带隙基准电路20输出的参考电压，VBE3为第三三极管Q3的基区-发射区电压，R2为第二电阻R2的阻值。
结合(1式)和(2式)可以得到：
Figure PCTCN2020094880-appb-000003
由(3式)可以看出，通过设置第一三极管Q1和第二三极管Q2的面积比n与第二电阻R2、第一电阻R1的阻值，可以得到温度补偿后的电压基准输出(即参考电压输出)。
本发明实施例中，由于整个电压基准电路采用了内部反馈机制，因此，带隙基准电路20未采用主流带隙基准电路20中使用的共栅cascode级联结构，避免了主流共栅cascode级联结构消耗额外MOS管过驱动电压而造成正常工作的电源电压较高的问题。
另外，本发明的带隙基准电路20输出的参考电压比电源电压低至少3个过驱动 电压，因此，电源电压可以工作在低于1.8V的情形下工作。当然，本实施例通过合理设计还可以实现低至1.5V左右甚至更低的电源电压。
进一步地，本实施例的电源纹波抑制电路10包括：与带隙基准电路20连接的内嵌放大器。
如图2所示，该电源纹波抑制电路10还包括：第七PMOS管MP7、第八PMOS管MP8、第七NMOS管MN7、第八NMOS管MN8和第九NMOS管MN9。
第七PMOS管MP7的源极和第八PMOS管MP8的源极连接外部输入电源电压，第七PMOS管MP7的栅极与第八PMOS管MP8的栅极短接，第七PMOS管MP7的栅极与其漏极连接，第八PMOS管MP8的漏极作为电源纹波抑制电路10的输出端连接带隙基准电路20的输入端；第七NMOS管MN7的漏极连接第八PMOS管MP8的漏极，第七NMOS管MN7的栅极连接内嵌放大器；第七NMOS管MN7的源极接地；第八NMOS管MN8的栅极连接内嵌放大器，第八NMOS管MN8的源极与第九NMOS管MN9的漏极连接，第九NMOS管MN9的栅极连接内嵌放大器，第九NMOS管MN9的源极接地。
进一步地，如图2所示，内嵌放大器包括：第五PMOS管MP5、第六PMOS管MP6、第一电容C1、第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5和第六NMOS管MN6。
第五PMOS管MP5的源极和第六PMOS管MP6的源极与第八PMOS管MP8的漏极连接，第五PMOS管MP5的漏极与第七NMOS管MN7的栅极和第三NMOS管MN3的漏极连接，第五PMOS管MP5的漏极还通过第一电容C1连接第七NMOS管MN7的漏极；第五PMOS管MP5的栅极连接第一PMOS管MP1的漏极，第六PMOS管MP6的栅极连接第一PMOS管MP1的栅极和第二PMOS管MP2的栅极的连接端；第六PMOS管MP6的漏极连接内嵌电阻的第一端，第六PMOS管MP6的漏极还连接第八NMOS管MN8的栅极、第三NMOS管MN3的栅极和第四NMOS和的栅极的连接端；内嵌电阻的第二端连接第四NMOS管MN4的漏极，第四NMOS管MN4的漏极连接第六NMOS管MN6的漏极，第六NMOS管MN6的源极和第五NMOS管MN5的源极接地；第五NMOS管MN5的栅极和第六NMOS管MN6的栅极连接并连接至第九NMOS管MN9的栅极和第四NMOS管MN4的漏极，第五NMOS管MN5 的漏极连接第三NMOS管MN3的源极连接，第三NMOS管MN3的栅极和第四NMOS管MN4的栅极连接。
由图2可知，带隙基准电路20置于内部校准电压Vreg(即第八PMOS管MP8)下工作，通过高增益的反馈回路保证第一PMOS管MP1的漏极电位和第二PMOS管MP2的栅极电位相同，并以此来调节Vreg(即第八PMOS管MP8的漏极电压)，使其基本不随电源电压变化而变化，最终使工作在内部电压下的带隙基准电路20具有较高的电源抑制比。
具体的，本实施例的电源纹波抑制电路10的抑制原理如下：假设外部输入电源电压VDD的变化(设升高)引起第八PMOS管MP8的漏电压(即Vreg)升高，使流经第一三极管Q1、第二三极管Q2的电流及第一PMOS管MP1的漏极电位、第二PMOS管MP2的栅极电位相对值产生变化。第一PMOS管MP1的漏极电位和第二PMOS管MP2的栅极电位的变化量经过第五PMOS管MP5、第六PMOS管MP6、第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5和第六NMOS管MN6构成的内嵌放大器放大，使第七NMOS管MN7的栅极电位升高，最终由第七NMOS管MN7产生的反馈电流使第八PMOS管MP8的漏极电压降低，保持为所需要的正确电压。其中，内嵌放大器为一个二极放大器，第三NMOS管MN3、第四NMOS管MN4、第五NMOS管MN5和第六NMOS管MN6形成共栅cascode的级联结构，使得内嵌放大器增益具有非常高的开环增益。第一电容C1作为米勒补偿电容，使得内嵌放大器具有高稳定性。通过内部高增益的反馈机制，电路能够确保第一PMOS管MP1和第二PMOS管MP2的栅漏电压稳定且相等，以使Vreg电压可以保持稳定而不随外部输入电源电压(VDD)的变化而变化。
另外，本实施例中，反馈机制保证第一三极管Q1和第二三极管Q2的电流相对变化较小，输出的Vref的直流电流为第三PMOS管MP3与第二PMOS管MP2形成的电流镜镜像，因此，Vref支路电流能够保持稳定，Vref输出对电源VDD变化的具有很高的抑制能力。
本实施例中，软启动电路30包括：与外部输入电源电压连接、给软启动电路30提供偏置的偏置电路。
进一步地，软启动电路30还包括：第九PMOS管MP9、第十PMOS管MP10和第 十一PMOS管MP11。
第九PMOS管MP9的源极、第十PMOS管MP10的源极和第十一PMOS管MP11的源极连接外部输入电源电压，第十一PMOS管MP11的栅极连接第三PMOS管MP3的栅极，第十一PMOS管MP11的漏极连接第十PMOS管MP10的漏极；第九PMOS管MP9的漏极与第一NMOS管MN1的漏极和第一NMOS管MN1的栅极与第二NMOS管MN2的栅极的连接端连接，第九PMOS管MP9的栅极与第十PMOS管MP10的栅极连接，且第十PMOS管MP10的栅极与其漏极连接，第十PMOS管MP10的漏极与偏置电路连接。
本实施例中，偏置电路包括：第十二PMOS管MP12、第十三PMOS管MP13、第十四PMOS管MP14、第十五PMOS管MP15、第十NMOS管MN10和第十一NMOS管MN11。
第十二PMOS管MP12、第十三PMOS管MP13、第十四PMOS管MP14、第十五PMOS管MP15依次倒比串联连接，且第十二PMOS管MP12的源极连接外部输入电源电压、第十五PMOS管MP15的漏极与第十一NMOS管MN11的漏极连接，第十一NMOS管MN11的漏极与其栅极短接；第十NMOS管MN10的源极和第十一NMOS管MN11的源极共同接地，第十NMOS管MN10的栅极和第十一NMOS管MN11的栅极连接。
本实施例的软启动电路30的主要作用是将带隙基准电路20从零电流工作点状态转换到电路的正常工作点状态，避免电路上电后进入零状态的稳态而无法实现电路启动。
进一步地，偏置电路给软启动电路30提供偏置，其中，第十二PMOS管MP12、第十三PMOS管MP13、第十四PMOS管MP14、第十五PMOS管MP15由四个倒比管串联以获得很大的电阻，进而使电路具有极低的静态电流。
具体的，软启动电路30的工作原理为：稳压电路上电时，若稳压电路不能正常工作，则整个偏置电路产生零电流，这时，导致第一NMOS管MN1和第二NMOS管MN2的栅极电压很低，而第一PMOS管MP1和第二PMOS管MP2的栅极电压很高，因此，软启动电路30中的第十一PMOS管MP11截止。而电路上电时，第九PMOS管MP9与第十PMOS管MP10组成的电流镜会通过软启动电路30的自身偏置 电路开始工作，从而引起第一NMOS管MN1和第二NMOS管MN2工作，因此带隙基准电路20启动工作。同时，第一PMOS管MP1和第二PMOS管MP2的栅极电压下降，致使第十一PMOS管MP11导通，通过电路的设计，第十一PMOS管MP11导致使得可以流经第九PMOS管MP9和第十PMOS管MP10的电流几乎为零，从而关断软启动电路30。软启动电路30的偏置电路中，由于串联多个二极管连接的倒比管，其自身的电流极小(为纳安级)。因此，正常启动后的软启动电路30功耗极小，而带隙基准电路20中的电流可以是微安级别，因此，整个稳压电路的功耗可以达到微瓦级别。
在其他一些实施例中，本发明实施例可以采用高压MOS管实现，也可以更改内部反馈控制中内嵌放大器的结构，比如采用内部OTA放大器实现内部反馈控制。另外带隙基准电路20中，可以采用传统的共栅级联PMOS管代替图2中的第一PMOS管MP1和第二PMOS管MP2。同样带隙基准电路20中的第一NMOS管MN1和第一NMOS管MN1，也可以采用传统的共栅级联NMOS管替代。而软启动电路30可以采用其他形式的变更，实现电路启动。基于这样的化设计同样可以实现本发明设计的提升电源电压纹波抑制的效果和性能。
需要说明的是，本发明为基于较低的电压和频率设计，但是其架构和设计原理适用于应用在其他应用场景下的电压基准电路设计，如高压电源芯片以及高频电路电源芯片。
本发明电路结构简单，能够提供对温漂和电源电压纹波的高抑制能力的基准电压，同时具有低电路功耗和小尺寸的芯片面积。基于内部高增益反馈机制的电源纹波抑制电路10，可以获得较强电源纹波抑制能力。另外，本发明的带隙基准电路20可以在低于1.8V，甚至1.5V的电压下正常工作，工作电压范围内。而且，电路采用低的偏置电流，在实现较高的性能同时具有低的静态功耗；电路元器件少、尺寸小，易于实现在标准CMOS工艺和高压CMOS工艺下的单片集成。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。

Claims (10)

  1. 一种高电源纹波抑制的电压基准电路，其特征在于，包括：带隙基准电路、电源纹波抑制电路以及软启动电路；
    所述电源纹波抑制电路的输入端与外部输入电源电压连接，所述电源纹波抑制电路的输出端与所述带隙基准电路的输入端连接，所述带隙基准电路的输出端输出参考电压，所述软启动电路分别连接所述外部输入电源电压以及所述带隙基准电路；
    所述带隙基准电路用于产生参考电压，所述电源纹波抑制电路用于抑制电源纹波以使所述带隙基准电路不随所述外部输入电源电压变化，所述软启动电路将所述稳压电路从零电流工作点状态转换为正常工作点状态。
  2. 根据权利要求1所述的高电源纹波抑制的电压基准电路，其特征在于，所述带隙基准电路包括：基准电压产生电路和电压基准输出电路；
    所述基准电压产生电路的输入端与所述电源纹波抑制电路的输出端连接，所述基准电压产生电路的输出端与所述电压基准输出电路的输入端连接，所述电压基准输出电路的输出端输出所述参考电压；
    所述基准电压产生电路的输入端为所述带隙基准电路的输入端，所述电压基准输出电路的输出端为所述带隙基准电路的输出端。
  3. 根据权利要求2所述的高电源纹波抑制的电压基准电路，其特征在于，所述基准电压产生电路包括：第一PMOS管、第二PMOS管、第一NMOS管、第二NMOS管、第一三极管、第二三极管以及第一电阻；
    所述第一PMOS管的源极和所述第二PMOS管的源极连接和所述电压基准输出电路的输出端连接所述电源纹波抑制电路的输出端，所述第一PMOS管的栅极与所述第二PMOS管的栅极连接，所述第一PMOS管的漏极与所述第一NMOS管的漏极连接，所述第一NM OS管的源极与所述第一三极管的发射极连接，所述第一三极管的集电极接地，所述第一三极管的基极与所述第二三极管的基极短接并接至地，所述第二三极管的集电极接地，所述第二三极管的发射极通过所述第一电阻连接所述第二NMOS管的源极；
    所述第二NMOS管的栅极与所述第一NMOS管的栅极短接并与所述第一NMOS管的漏极共同连接至所述软启动电路；所述第二NMOS管的漏极与所述第二PMOS管的漏极连接；
    所述第二PMOS管的栅极与其漏极短接并分别连接所述电源纹波抑制电路和所述电压基准输出电路的输入端。
  4. 根据权利要求3所述的高电源纹波抑制的电压基准电路，其特征在于，所述电压基准输出电路包括：第三PMOS管、第四PMOS管、第二电阻和第三三极管；
    所述第三PMOS管的源极作为所述电压基准电路的输入端连接所述电源纹波抑制电路的输出端，所述第三PMOS管的漏极与所述第四PMOS管的源极连接，所述第三PMOS管的栅极与所述第二PMOS管的漏极连接并连接至所述电源纹波抑制电路；所述第三PMOS管的栅极还作为所述电压基准电路的输出端连接至所述软启动电路；
    所述第四PMOS管的栅极与漏极短接，所述第四PMOS管的漏极通过所述第二电阻连接所述第三三极管的发射极，所述第三三极管的基极和集电极接地；
    所述第四PMOS管的漏极与所述第二电阻的连接端作为所述带隙基准电路的输出端输出所述参考电压。
  5. 根据权利要求4所述的高电源纹波抑制的电压基准电路，其特征在于，所述电源纹波抑制电路包括：与所述带隙基准电路连接的内嵌放大器。
  6. 根据权利要求5所述的高电源纹波抑制的电压基准电路，其特征在于，所述电源纹波抑制电路还包括：第七PMOS管、第八PMOS管 、第七NMOS管、第八NMOS管和第九NMOS管；
    所述第七PMOS管的源极和所述第八PMOS管的源极连接所述外部输入电源电压，所述第七PMOS管的栅极与所述第八PMOS管的栅极短接，所述第七PMOS管的栅极与其漏极连接，所述第八PMOS管的漏极作为所述电源纹波抑制电路的输出端连接所述带隙基准电路的输入端；
    所述第七NMOS管的漏极连接所述第八PMOS管的漏极，所述第七NMOS管的栅极连接所述内嵌放大器；所述第七NMOS管的源极接地；所述第八NMOS管的栅极连接所述内嵌放大器，所述第八NMOS管的源极与所述第九NMOS管的漏极连接，所述第九NMOS管的栅极连接所述内嵌放大器，所述第九NMOS管的源极接地。
  7. 根据权利要求6所述的高电源纹波抑制的电压基准电路，其特征在于，所述内嵌放大器包括：第五PMOS管、第六PMOS管、第一电容、第三NMOS管、第四NMOS管、第五NMOS管和第六NMOS管；
    所述第五PMOS管的源极和所述第六PMOS管的源极与所述第八PMOS管的漏极连接，所述第五PMOS管的漏极与所述第七NMOS管的栅极和所述第三NMOS管的漏极连接，所述第五PMOS管的漏极还通过所述第一电容连接所述第七NMOS管的漏极；
    所述第五PMOS管的栅极连接所述第一PMOS管的漏极，所述第六PMOS管的栅极连接所述第一PMOS管的栅极和所述第二PMOS管的栅极的连接端；所述第六PMOS管的漏极连接内嵌电阻的第一端，所述第六PMOS管的漏极还连接所述第八NMOS管的栅极、所述第三NMOS管的栅极和所述第四NMOS和的栅极的连接端；
    所述内嵌电阻的第二端连接所述第四NMOS管的漏极，所述第四NMOS管的漏极连接所述第六NMOS管的漏极，所述第六NMOS管的源极和所述第五NMOS管的源极接地；所述第五NMOS管的栅极和所述第六NMOS管的栅极连接并连接至所述第九NMOS管的栅极 和所述第四NMOS管的漏极，所述第五NMOS管的漏极连接所述第三NMOS管的源极连接，所述第三NMOS管的栅极和所述第四NMOS管的栅极连接。
  8. 根据权利要求7所述的高电源纹波抑制的电压基准电路，其特征在于，所述软启动电路包括：与所述外部输入电源电压连接、给所述软启动电路提供偏置的偏置电路。
  9. 根据权利要求8所述的高电源纹波抑制的电压基准电路，其特征在于，所述软启动电路还包括：第九PMOS管、第十PMOS管和第十一PMOS管；
    所述第九PMOS管的源极、所述第十PMOS管的源极和所述第十一PMOS管的源极连接所述外部输入电源电压，所述第十一PMOS管的栅极连接所述第三PMOS管的栅极，所述第十一PMOS管的漏极连接所述第十PMOS管的漏极；
    所述第九PMOS管的漏极与所述第一NMOS管的漏极和所述第一NMOS管的栅极与所述第二NMOS管的栅极的连接端连接，所述第九PMOS管的栅极与所述第十PMOS管的栅极连接，且所述第十PMOS管的栅极与其漏极连接，所述第十PMOS管的漏极与所述偏置电路连接。
  10. 根据权利要求9所述的高电源纹波抑制的电压基准电路，其特征在于，所述偏置电路包括：第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管、第十NMOS管和第十一NMOS管；
    所述第十二PMOS管、第十三PMOS管、第十四PMOS管、第十五PMOS管依次倒比串联连接，且所述第十二PMOS管的源极连接所述外部输入电源电压、所述第十五PMOS管的漏极与所述第十一NMOS管的漏极连接，所述第十一NMOS管的漏极与其栅极短接；
    所述第十NMOS管的源极和所述第十一NMOS管的源极共同接地，所述第十NMOS管的栅极和所述第十一NMOS管的栅极连接。
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