WO2017020549A1 - 移位寄存器、栅极驱动电路、显示面板的驱动方法、显示装置 - Google Patents

移位寄存器、栅极驱动电路、显示面板的驱动方法、显示装置 Download PDF

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Publication number
WO2017020549A1
WO2017020549A1 PCT/CN2016/070491 CN2016070491W WO2017020549A1 WO 2017020549 A1 WO2017020549 A1 WO 2017020549A1 CN 2016070491 W CN2016070491 W CN 2016070491W WO 2017020549 A1 WO2017020549 A1 WO 2017020549A1
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Prior art keywords
node
shift register
control
signal
stage shift
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PCT/CN2016/070491
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English (en)
French (fr)
Inventor
李付强
樊君
陈小川
董学
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to EP16825319.3A priority Critical patent/EP3333843B1/en
Priority to US15/125,851 priority patent/US9747854B2/en
Publication of WO2017020549A1 publication Critical patent/WO2017020549A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • the present invention relates to the field of display technologies, and more particularly to a shift register, a gate driving circuit, a display panel, a driving method thereof, and a display device.
  • liquid crystal displays have been widely used in electronic display products such as televisions, computers, mobile phones and personal digital assistants.
  • the liquid crystal display includes a data driver (Source Driver), a gate driver (Gate Driver), a liquid crystal display panel, and the like.
  • a pixel array is arranged in the liquid crystal display panel, and the gate driving device is configured to sequentially turn on each pixel row in the pixel array to transmit the pixel data output by the data driver to each pixel in the currently opened pixel row, thereby displaying Image to be displayed.
  • the gate driving device is generally formed on the array substrate of the liquid crystal display by an array process, that is, a Gate Driver on Array (GOA) process, which not only saves cost, but also can realize a liquid crystal panel ( Panel) symmetrical aesthetic design on both sides, at the same time, the bonding area of the integrated circuit of IC (Integrated Circuit) and the wiring space of the Fan-out area are omitted, so that a narrow bezel can be realized. Design; and, this integrated process also eliminates the bonding process in the direction of the gate scan line, thereby increasing throughput and yield.
  • a Gate Driver on Array GAA
  • the gate driving device is generally composed of a plurality of cascaded shift registers, such that the driving signal output ends of the shift registers of the respective stages correspond to the respective gate lines, respectively, for sequentially outputting the scanning signals to the respective gate lines in the scanning direction.
  • the structure of the specific shift register is as shown in FIG. 1 , and includes: an input unit 01, a reset unit 02, a node control unit 03, a pull-up unit 04, a pull-down unit 05, an input signal terminal Input, a reset signal end Reset, and a first clock signal.
  • the input unit 01 is for controlling the potential of the first node PU under the control of the input signal terminal Input
  • the reset unit 02 is for controlling the first node under the control of the reset signal end Reset.
  • the potential of the PU, the node control unit 03 is for controlling the potential of the first node PU and the second node PD, and pulling up
  • the unit 04 is configured to provide a signal of the first clock signal terminal ck to the driving signal output terminal Out under the control of the first node PU
  • the pull-down unit 05 is configured to signal the reference signal terminal Vref under the control of the second node PD It is supplied to the drive signal output terminal Out.
  • the shift registers of the gate driving devices in the display panel are generally as shown in FIG. 1.
  • the display panel sequentially outputs scanning signals to the respective gate lines in the scanning direction through the shift registers of the stages.
  • the power consumption of the display panel also increases with the increase of the resolution, resulting in a greatly reduced standby time. Therefore, how to reduce the power consumption of the display product to improve the standby time is a technical problem that a person skilled in the art needs to solve.
  • embodiments of the present invention provide a shift register, a gate driving circuit, a display panel, a driving method thereof, and a display device, which are used to reduce the resolution of a display panel in a special case, thereby reducing the display panel. Power consumption.
  • a shift register provided by an embodiment of the present invention includes: a first pull-up unit, a first pull-down unit, an output control unit, a second pull-up unit, and a second pull-down unit; wherein the first pull-up unit Connected to the first node, the first clock signal end and the driving signal output end, and provide a signal of the first clock signal end to the driving signal output end under the control of the first node; the first pull-down unit and the first a two-node, a reference signal end and a drive signal output end are connected, and a signal of the reference signal end is supplied to the drive signal output end under the control of the second node; the output control unit and the first node The second node is connected, the selection control signal end, the third node, and the fourth node are connected, and the first node and the third node are turned on when the selection control signal end receives the selection control signal.
  • the second pull-up unit is connected to the third node, the first clock signal end, and the selective driving output end, And providing, according to the control of the third node, the signal of the first clock signal end to the selective driving output end; the second pull-down unit and the fourth node, the reference signal end, and a selection driving output
  • the terminals are connected, and under the control of the fourth node, the signal of the reference signal terminal is supplied to the selection drive output.
  • the output control unit includes: a first switching transistor and a second switching transistor; wherein a gate of the first switching transistor is connected to the selection control signal end, and a source a pole connected to the first node, a drain connected to the third node; a gate of the second switching transistor connected to the selection control signal end, a source and the second node Connected, the drain is connected to the fourth node.
  • the second pull-up unit includes: a third switching transistor; wherein a gate of the third switching transistor is connected to the third node, a source and the The first clock signal terminal is connected, and the drain is connected to the selective driving output terminal.
  • the second pull-down unit includes: a fourth switching transistor; wherein a gate of the fourth switching transistor is connected to the fourth node, a source and the reference The signal terminals are connected, and the drain is connected to the selective drive output terminal.
  • the embodiment of the present invention further provides a gate driving circuit, including a plurality of cascaded shift registers provided by the embodiments of the present invention; wherein the shift register further includes an input unit and a reset a unit, the input unit is connected to the input signal end and the first node, the reset unit is connected to the reset signal end and the first node; except for the last stage shift register, each of the other stages is shifted
  • the driving signal output end of the register is respectively connected to the input signal end of the next-stage shift register adjacent thereto; the signal input end of the first-stage shift register is used for receiving the trigger signal; in addition to the first-stage shift register,
  • the driving signal output ends of each of the remaining shift registers are respectively connected to the reset signal terminals of the upper shift register adjacent thereto; the selected drive outputs of the shift registers of the respective stages are connected to the gate lines.
  • the method further includes: a plurality of first switching devices, a kth first switching device and a first switch control end, and a third node in the 3k-2th stage shift register And a third node in the 3kth stage shift register is connected, and the third node in the 3k-2th stage shift register and the third stage in the 3kth stage shift register are controlled under the control of the first switch control end Three nodes are turned on; a plurality of second switching devices, a kth second switching device and a first switching control terminal, a fourth node in the 3k-2th stage shift register, and a third in the 3kth stage shift register Four nodes are connected, and the fourth node in the 3k-2th stage shift register is turned on with the fourth node in the 3kth stage shift register under the control of the first switch control end; wherein k is greater than or equal to An integer of 1.
  • the method further includes: a plurality of third switching devices, an nth first switching device and a second switching control terminal, and a third node in the 4n-3th stage shift register And a third node in the 4n-1th stage shift register is connected, and the third node and the 4n-1th stage in the 4th-3th stage shift register are shifted under the control of the second switch control end.
  • a third node in the register is turned on; a plurality of fourth switching devices, an nth second switching device and a second switching control terminal, a fourth node in the 4n-3th stage shift register, and a 4n-1th
  • the fourth node in the stage shift register is connected, and the fourth of the 4n-3 stage shift registers is controlled under the control of the second switch control terminal
  • the node is turned on with the fourth node in the 4n-1th stage shift register; wherein n is an integer greater than or equal to 1.
  • the method further includes: a plurality of fifth switching devices, a third node of the nth first switching device and the third switching control terminal, and a third node of the 4th-2th stage shift register And the third node in the 4nth stage shift register is connected, and the third node in the 4th-2th stage shift register and the 4th stage shift register are controlled under the control of the third switch control end Three nodes are turned on; a plurality of sixth switching devices, an nth second switching device and a third switching control terminal, a fourth node in the 4th-2th stage shift register, and a 4nth stage shift register The fourth node is connected, and the fourth node in the 4th-2th stage shift register is turned on with the fourth node in the 4nth stage shift register under the control of the third switch control end; wherein n is greater than An integer equal to 1.
  • an embodiment of the present invention further provides a display panel including N gate lines, a first gate driving circuit and a second gate driving respectively connected to the N gate lines on both sides of the display panel
  • the first gate driving circuit and the second gate driving circuit are both the gate driving circuits; and the selected driving output terminal and the corresponding gate of the shift register in each of the gate driving circuits a line connection;
  • the display panel further includes a driving control circuit, the driving control circuit is connected to the first and second gate driving circuits, and outputting a selection control signal to the first and second gate driving circuits,
  • the first gate driving circuit outputs a first group of timing control signals and a second group of timing control signals outputted to the second gate driving circuit; wherein the first group of timing control signals includes at least a first trigger signal and a a clock signal, the second group of timing control signals includes at least a second trigger signal and a third clock signal, the first trigger signal and the second trigger signal having the same width, the first gate driving power Under the control of the first group of timing control signals, the scan
  • the method further includes: a mode switching circuit connected to each of the driving control circuits; wherein the mode switching circuit receives the first mode control signal: controlling The driving control circuit delays a timing of each signal in the first group of timing control signals by a trigger signal width from a timing of a corresponding signal in the second group of timing control signals; and controls the driving control circuit to The selection control signal terminal of the odd-numbered stage shift register in the first gate driving circuit outputs a selection control signal, and outputs a selection control signal to the selection control signal terminal of the even-numbered stage shift register in the second gate driving circuit.
  • the first gate driving is electrically
  • the circuit includes the plurality of first switching devices and the plurality of second switching devices, the mode switching circuit controlling all of the first switching devices and all of the second switching devices to be turned on when receiving the second mode control signal a state; controlling the drive control circuit to delay a timing of each of the second set of timing control signals by a trigger signal width from a timing of a corresponding one of the first set of timing control signals; and controlling the drive control circuit to a selection control signal terminal of the 3kth stage shift register in the first gate driving circuit outputs a selection control signal to a selection control signal end of a 3k-1th stage shift register in the second gate driving circuit Output selection control signal.
  • the first gate driving circuit includes the plurality of third switching devices and the plurality of fourth switching devices
  • the second gate driving The circuit includes the plurality of fifth switching devices and the plurality of sixth switching devices, the mode switching circuit, when receiving the third mode control signal: controlling all of the third switching devices, all of the fourth switching devices, all The five-switching device and all of the sixth switching devices are in an on state; controlling the driving control circuit to delay a timing of each signal in the first group of timing control signals by a timing of a corresponding signal in the second group of timing control signals a trigger signal width; and controlling the drive control circuit to output a selection control signal to the selection control signal terminal of the 4n-1th stage shift register in the first gate driving circuit, to drive the second gate
  • the selection control signal terminal of the 4nth stage shift register in the circuit outputs a selection control signal.
  • the mode switching circuit controls all the switching devices to be in a closed state when receiving the fourth mode control signal; and controls the driving control circuit to make the second
  • the timing of each signal in the group timing control signal is the same as the timing of the corresponding signal in the first group timing control signal; and the control control circuit is controlled to output a selection control signal to the selection control signal terminals of all the shift registers.
  • the embodiment of the present invention further provides a display device, which includes any of the above display panels provided by the embodiments of the present invention.
  • the embodiment of the present invention further provides a driving method for the above display panel, comprising: when the mode switching circuit receives the first mode control signal: controlling all the switching devices to be in a closed state; and controlling the driving control circuit Delaying a timing of each of the first set of timing control signals by a trigger signal width from a timing of a corresponding one of the second set of timing control signals; and controlling the drive control circuit to drive with the first gate a selection control signal terminal of the odd-numbered shift register in the circuit outputs a selection control signal, and outputs a selection control signal to a selection control signal end of the even-numbered stage shift register in the second gate driving circuit;
  • the mode switching circuit When the mode switching circuit receives the second mode control signal: controlling all of the first switching devices and all of the second switching devices to be in an on state; controlling all of the third switching devices, all of the fourth switching devices, all of the fifth switching devices And all the sixth switching devices are in a closed state; controlling the driving control circuit to delay a timing of each signal in the second group of timing control signals by a trigger signal width from a timing of a corresponding signal in the first group of timing control signals; And controlling the driving control circuit to output a selection control signal to the selection control signal end of the 3kth stage shift register in the first gate driving circuit, and shifting to the 3k-1th stage in the second gate driving circuit
  • the selection control of the bit register outputs a selection control signal;
  • the mode switching circuit When the mode switching circuit receives the third mode control signal: controlling all of the first switching devices and all of the second switching devices to be in an off state; controlling all of the third switching devices, all of the fourth switching devices, all of the fifth switching devices, and All sixth switching devices are in an on state; controlling the driving control circuit to delay a timing of each signal in the first group of timing control signals by a trigger signal width from a timing of a corresponding signal in the second group of timing control signals; And controlling the driving control circuit to output a selection control signal to the selection control signal end of the 4n-1th stage shift register in the first gate driving circuit, and shifting to the 4th level in the second gate driving circuit
  • the selection control of the bit register outputs a selection control signal;
  • the mode switching circuit receives the fourth mode control signal: controlling all the switching devices to be in an off state; controlling the driving control circuit to make a timing of each signal in the second group of timing control signals and the first group of timings The timings of the corresponding signals in the control signal are the same; and the drive control circuit is controlled to output a selection control signal to the selection control signal terminals of all the shift registers.
  • an output control unit and a second pull-up unit are added to the existing shift register.
  • a second pull-down unit and a selection control signal terminal wherein the output control unit is configured to enable the first node and the third node in the shift register to be turned on when the selection control signal end receives the selection control signal, and to make the second The node and the fourth node are turned on;
  • the second pull-up unit is configured to provide the signal of the first clock signal end to the selected driving output terminal under the control of the third node;
  • the second pull-down unit is configured to be under the control of the fourth node The signal at the reference signal terminal is supplied to the selection drive output.
  • the selection of the scan signal output can be selected by the output control unit, the second pull-up unit, the second pull-down unit, and the control of the selection control signal terminal.
  • the gate driving circuit constituted by the above shift register it is possible to selectively output a scanning signal to a part of the gate lines.
  • the above-mentioned gate driving circuit is adopted in the display panel provided by the embodiment of the present invention, and the difference is also added.
  • 1 is a schematic structural diagram of a prior art shift register
  • FIG. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 5 is a timing diagram of signals corresponding to the shift register shown in FIG. 4; FIG.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of signals corresponding to a first gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a second schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • 9b is a timing diagram of two sets of timing control signals output by the control driving control circuit when the mode switching circuit receives the first mode control signal or the third mode control signal in the display panel according to an embodiment of the present disclosure
  • 9c is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a first mode control signal in a display panel according to an embodiment of the present disclosure
  • 10a is a second schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 10b is a timing diagram of two sets of timing control signals output by the control driving control circuit when the mode switching circuit receives the second mode control signal in the display panel according to the embodiment of the present disclosure
  • 10c is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a second mode control signal in a display panel according to an embodiment of the present disclosure
  • Figure 10d is a partial enlarged view of the display panel shown in Figure 10a;
  • Figure 11a is a third schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 11b is a timing diagram of a scan signal on a corresponding gate line when a mode switching circuit receives a third mode control signal in a display panel according to an embodiment of the present disclosure
  • FIG. 12 is a timing diagram of scan signals on a corresponding gate line when a mode switching circuit receives a fourth mode control signal in a display panel according to an embodiment of the present invention.
  • a shift register provided by an embodiment of the present invention includes: an input unit 1, a reset unit 2, a node control unit 3, a first pull-up unit 4, a first pull-down unit 5, and an input signal end.
  • the control ends of the first control unit are connected to the first node PU, and the second end of the node control unit 3 and the control end of the first pull-down unit 5 are both connected to the second node PD; the output end of the first pull-up unit 4 and the first The output of the pull-down unit 5 is connected to the drive signal output Out of the shift register.
  • the input unit 1 is configured to control the potential of the first node PU under the control of the input signal terminal Input
  • the reset unit 2 is configured to control the potential of the first node PU under the control of the reset signal end Reset
  • the node control unit 3 uses For controlling the potentials of the first node PU and the second node PD
  • the first pull-up unit 4 is configured to provide the signal of the first clock signal terminal ck1 to the driving signal output terminal Out under the control of the first node PU
  • the first The pull unit 5 is for supplying a signal of the reference signal terminal Vref to the drive signal output terminal Out under the control of the second node PD.
  • the shift register further includes an output control unit 6, a second pull-up unit 7, a second pull-down unit 8, and a selection control signal terminal EN.
  • the first input end of the output control unit 6 is connected to the first node PU, the second input end is connected to the second node PD, and the third input end is connected to the selection control signal end EN, the first output end and the third node A and the
  • the first input end of the two pull-up units 7 is connected, the second output end is connected to the first input end of the fourth node B and the second pull-down unit 8; the second input end of the second pull-up unit 7 and the first clock signal
  • the terminal ck1 is connected, the output terminal of the second pull-up unit 7 is connected to the output terminal of the second pull-down unit 8 as a selective drive output terminal of the shift register; the second input terminal of the second pull-down unit 8 is connected to the reference signal terminal Vref. .
  • the output control unit 6 is configured to: when the selection control signal terminal EN receives the selection control signal, turn on the first node PU and the third node A, and turn on the second node PD and the fourth node B;
  • the second pull-up unit 7 is configured to provide a signal of the first clock signal terminal ck1 to the selective drive output terminal Output under the control of the third node A;
  • the second pull-down unit 8 is configured to use the reference signal under the control of the fourth node B
  • the signal of the terminal Vref is supplied to the selection drive output Output.
  • the above shift register provided by the embodiment of the invention is equivalent to adding an output control unit, a second pull-up unit, a second pull-down unit and a selection control signal end to the existing shift register; wherein, the output control unit And configured to: when the selection control signal end receives the selection control signal, turn on the first node and the third node, and turn on the second node and the fourth node; and use the second pull-up unit to control the third node
  • the signal of the first clock signal terminal ck1 is supplied to the selective driving output terminal Output; the second pull-down unit is configured to supply the signal of the reference signal terminal Vref to the selective driving output terminal Output under the control of the fourth node.
  • the output control unit 6 may specifically include: a first switching transistor T1 and a second switching transistor T2; wherein, the first switching transistor The gate of T1 is connected to the selection control signal terminal EN, the source is connected to the first node PU, the drain is connected to the third node A; the gate of the second switching transistor T2 is connected to the selection control signal terminal EN, the source and the The two nodes are connected to each other, and the drain is connected to the fourth node B.
  • the selection control signal terminal EN controls the first switching transistor T1 and the second switching transistor T2 to be in an on state
  • the first node PU and the third node A are turned on
  • the first node The two-node PD and the fourth node B are turned on.
  • the first switching transistor T1 and the second switching transistor T2 may both be P-type transistors or N-type transistors, which are not limited herein.
  • the above is only a specific structure of the output control unit in the shift register.
  • the specific structure of the output control unit is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. There is no limit here.
  • the second pull-up unit 7 may specifically include: a third switching transistor T3; wherein, the gate of the third switching transistor T3 Connected to the third node A, the source is connected to the first clock signal terminal ck1, and the drain is connected to the selection drive output terminal Output.
  • the third switching transistor T3 when the third switching transistor T3 is in an on state under the control of the third node A, the third switching transistor T3 will be the first clock signal terminal ck1. The signal is supplied to the select drive output Output.
  • the above is only a specific structure of the second pull-up unit in the shift register.
  • the specific structure of the second pull-up unit is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be known to those skilled in the art. Other structures are not limited here.
  • the second pull-down unit 8 may specifically include: a fourth switching transistor T4; wherein, the gate of the fourth switching transistor T4 The fourth node B is connected, the source is connected to the reference signal terminal Vref, and the drain is connected to the selection driving output terminal Output.
  • the fourth switching transistor T4 when the fourth switching transistor T4 is in an on state under the control of the fourth node B, the fourth switching transistor T4 supplies the signal of the reference signal terminal Vref to the selected driving output terminal. .
  • the above is only a specific structure of the second pull-down unit in the shift register.
  • the specific structure of the second pull-down unit is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other known to those skilled in the art. Structure, not limited here.
  • the node control unit is specifically configured to control the potential of the second node PD according to the potential of the first node PU, and control the first node PU according to the potential of the second node PD.
  • the potential thereby controlling the basic functions of the shift register by controlling the potentials of the first node PU and the second node PD.
  • the structures of the input unit 1, the reset unit 2, the node control unit 3, the first pull-up unit 4, and the first pull-down unit 5 are the same as in the prior art. It will not be described in detail here. The following is explained by a specific embodiment, but is not limited thereto.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the input unit 1 may include a fifth switching transistor T5; the reset unit 2 may include a sixth switching transistor T6; and the node control unit 3 may include a seventh switching transistor T7, an eighth switching transistor T8, and a nine-switch transistor T9, a tenth switching transistor T10 and a first capacitor C1; the first pull-up unit 4 may include an eleventh switching transistor T11 and a second capacitor C2; the first pull-down unit 5 may include a twelfth switching transistor T12 .
  • the gate of the fifth switching transistor T5 is connected to the input signal terminal Input, the source is connected to the first DC signal terminal VDD, the drain is connected to the pull-up node PU, and the gate of the sixth switching transistor T6 is connected to the reset signal terminal Reset.
  • the source is connected to the second DC signal terminal VSS, and the drain is connected to the first node PU; the gate and the source of the seventh switching transistor T7 are both connected to the second clock signal terminal ckb1, and the drain
  • the pole is connected to the second node PD; the gate of the eighth switching transistor T8 is connected to the second node PD, the source is connected to the reference signal terminal Vref, the drain is connected to the first node PU; the gate of the ninth switching transistor T9 is The first node is connected to the PU, the source is connected to the reference signal terminal Vref, and the drain is connected to the second node PD.
  • the gate of the tenth switching transistor T10 is connected to the driving signal output terminal Out, and the source is connected to the reference signal terminal Vref.
  • the pole is connected to the second node PD; the gate of the eleventh switching transistor T11 is connected to the first node PU, the source is connected to the first clock signal terminal ck1, and the drain is connected to the driving signal output terminal Out; the twelfth switching transistor The gate of T12 is connected to the second node PD, the source is connected to the reference signal terminal Vref, and the drain is connected to the driving signal output terminal Out; the first capacitor C1 is connected between the second node PD and the reference signal terminal Vref; The capacitor C2 is connected between the first node PU and the drive signal output terminal Out.
  • all of the switching transistors in FIG. 4 are N-type transistors.
  • all switching transistors may also be P-type transistors, or some of the transistors are N-type transistors, and some of the transistors are P-type transistors. Not limited.
  • the shift register repeats the fourth phase and the fifth phase until the potential of the input signal terminal Input becomes high again.
  • the switching transistor mentioned in the above embodiment of the present invention may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the source and the drain of these switching transistors are interchangeable according to the type of the transistor and the input signal, and no specific distinction is made here.
  • an embodiment of the present invention further provides a gate driving circuit, as shown in FIG. 6, including a plurality of the above-mentioned shift registers: SR(1), SR(2), ..., SR (N-1), SR(N) (A total of N shift registers).
  • the signal input terminal Input of the first stage shift register SR(1) is for receiving the trigger signal; the driving signal output of each of the shift registers SR(m) of each stage except the first stage shift register SR(1)
  • the terminal OUT_m is connected to the reset signal terminal Reset of the previous stage shift register SR(m-1) adjacent thereto.
  • the selection drive output Output_m of each stage shift register SR(m) is used to be connected to the gate line.
  • the gate driving circuit is connected to the corresponding gate line gatem through the selective driving output terminal Output_m of each stage shift register SR(m) for sequentially outputting the scanning signal to the corresponding gate line.
  • the first clock signal terminal ck1 of the odd-numbered shift register and the second clock signal terminal ckb1 of the even-numbered shift register are used.
  • Receiving the same clock signal (indicated as CK1 in the figure), the second clock signal terminal ckb1 of the odd-numbered shift register and the first clock signal terminal ck1 of the even-numbered shift register are used to receive the same clock signal (shown as CKB1 in the figure) ).
  • an embodiment of the present invention further provides a display panel, as shown in FIG. 7, including N gate lines (gate1, gate2, gate3, ...), which are respectively located on both sides of the display panel and are respectively connected with N gate lines.
  • N gate lines gate1, gate2, gate3, ...)
  • a first gate driving circuit GOA1 and a second gate driving circuit GOA2 wherein the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are the above-described gate driving circuits provided by the embodiments of the present invention
  • the selection drive output Output_m of the shift register SR(m) in each gate drive circuit is connected to the corresponding gate line.
  • the display panel further includes a drive control circuit 10 coupled to the first and second gate drive circuits (GOA1 and GOA2) for outputting at least to the first and second gate drive circuits (GOA1 and GOA2) Selecting a control signal, outputting a first group of timing control signals (including at least a first trigger signal STV1, a first clock signal CK1, and a second clock signal CKB1) to the first gate driving circuit GOA1, and outputting a second gate driving circuit Two sets of timing control signals (including at least a second trigger signal STV2, a third clock signal CK2, and a fourth clock signal CKB2); wherein each group of timing control signals includes at least a trigger signal and a clock signal, and each group of timing control signals is triggered The widths of the signals are the same, and each of the gate driving circuits (GOA1 and GOA2) is used to sequentially output the scanning signals from the driving signal output terminal Out under the control of the corresponding group timing control signals received.
  • a drive control circuit 10 coupled to the first and second gate drive circuit
  • the first gate driving circuit GOA1 is taken as an example to specifically describe the control of a gate driving circuit by a set of timing control signals.
  • the first gate driving circuit GOA1 as shown in FIG. 6, the driving control circuit inputs the first trigger signal STV1 to the first stage shift register SR(1) to the first clock signal terminal ck1 and the even number of the odd-numbered shift register, respectively.
  • the second clock signal terminal ckb1 of the stage shift register inputs the first clock signal CK1, and inputs the second clock signal CKB1 to the second clock signal terminal ckb1 of the odd-numbered shift register and the first clock signal terminal ck1 of the even-numbered shift register. .
  • the driving signal output terminal Out_1 After the first stage shift register SR(1) receives the first trigger signal STV1, when the first clock signal terminal ck1 receives the first clock signal CK1 for the first time, the driving signal output terminal Out_1 outputs a scan signal.
  • the drive output terminal Output_1 When the corresponding output control unit is in the on state, the drive output terminal Output_1 is selected to output a scan signal to the first gate line gate1, and the scan signal outputted by the drive signal output terminal Out_1 of the first stage shift register SR(1) is supplied to the first The input signal terminal Input of the second stage shift register SR(2); when the second stage shift register SR(2) receives the scan signal output by the first stage shift register SR(1), when its first clock signal When the terminal ck1 receives the second clock signal CKB1 for the first time, the driving signal output terminal Out_2 outputs a scanning signal.
  • the driving output terminal Output_2 is selected to output the scanning to the second gate line gate2.
  • the signal, the scan signal outputted by the drive signal output terminal Out_2 of the second stage shift register SR(2) is supplied to the input signal terminal Input of the third stage shift register SR(3); when the third stage shift register SR(3) Received a second level shift After the scan signal outputted by the register SR(2) is received, the drive signal output terminal Out_3 outputs a scan signal when the first clock signal terminal ck1 receives the first clock signal CK1.
  • the drive output terminal Output_3 is selected to output a scan signal to the third gate line gate3, and the scan signal outputted by the drive signal output terminal Out_3 of the third stage shift register SR(3) is supplied to the fourth stage shift register SR(4).
  • the input signal terminal Input, and so on, the shift registers of each stage sequentially output the scan signals to the corresponding gate lines.
  • the input/output timing diagram corresponding to the specific first gate driving circuit GOA1 is as shown in FIG. 8.
  • the drive control circuit 10 inputs a second trigger signal to the first stage shift register of the second gate drive circuit GOA2 to the first clock signal end of the odd-numbered shift register and the second clock of the even-numbered shift register, respectively.
  • the signal terminal inputs a third clock signal, and inputs a fourth clock signal to the second clock signal end of the odd-numbered shift register and the first clock signal end of the even-numbered shift register.
  • the specific working principle of the second gate driving circuit is the same as that of the first gate driving circuit, and details are not described herein.
  • the method further includes: A mode switching circuit 20 connected to the drive control circuit 10.
  • the mode switching circuit 20 controls the drive control circuit 10 such that each of the first group of timing control signals (including at least the first trigger signal STV1, the first clock signal CK1, and the second clock signal CKB1) The timing of the signal is delayed by one trigger signal width from the timing of the corresponding signal in the second set of timing control signals (including at least the second trigger signal STV2, the third clock signal CK2, and the fourth clock signal CKB2).
  • the timing diagrams of the specific two sets of timing control signals are as shown in FIG.
  • the driving signal output ends of the shift registers of the respective stages are sequentially outputted with the scanning signals; and when the nth stage shift register of the first driving control circuit When the drive signal output end outputs the scan signal, the drive signal output end of the n+1th stage shift register of the second drive control circuit also outputs the scan signal.
  • the mode switching circuit 20 also controls the shift register (SR(1), SR() of the drive control circuit 10 connected to the odd gate lines (gate1, gate3, gate5, ...) in the first gate drive circuit GOA1.
  • the selection control signal terminals of SR(5) may output the selection control signal to the shift register (SR() of the second gate drive circuit GOA2 connected to the even-numbered gate lines (gate2, gate4, gate6, ...) 2)
  • the selection control signal terminals of SR(4), SR(4)%) output the selection control signal.
  • the first gate driving circuit sequentially outputs the scanning signals only to the odd gate lines
  • the second gate driving circuit sequentially outputs the scanning signals only to the even number of gate lines, thereby realizing two adjacent ones along the scanning direction.
  • the gate line is a gate line group, and each gate line group sequentially receives the scan signal, that is, the display panel is scanned simultaneously by two gate lines, and the resolution of the display panel is reduced to 1/2 resolution.
  • the black line at the start of the gate line indicates that the selection control signal end of the shift register in the gate driving circuit is a selective control signal, and the corresponding selected driving output terminal is capable of outputting a scan signal.
  • the circle at the beginning of the gate line indicates that the selection control signal terminal of the shift register in the gate driving circuit has no control signal selected, and the corresponding selected driving output terminal does not output the scan signal.
  • a timing chart of scanning signals on the respective gate lines along the scanning direction on the display panel is as shown in FIG. 9c.
  • the third embodiment further includes: a third n-2th stage shift register respectively connected to the first gate driving circuit GOA1.
  • a first switching device 30 between the node A and the third node A of the 3nth stage shift register (not shown in the specific structure of FIG. 10a, see FIG. 10d), and respectively connected to the first gate driving circuit a second switching device 40 between the fourth node B of the 3n-2th stage shift register of the GOA1 and the fourth node B of the 3nth stage shift register (the specific structure is not shown in FIG. 10a, see FIG. 10d, 10d is a partial specific structural diagram of the dashed box in Fig. 10a; wherein n is an integer greater than one.
  • the mode switching circuit 20 also controls all of the first switching device 30 and all of the second switching devices 40 to be in an on state when receiving the second mode control signal; causing the third n-2 stage shift of the first gate driving circuit GOA1
  • the third node A of the register has the same potential as the third node A of the 3nth stage shift register, and shifts the fourth node B and the 3nth stage of the 3n-2th stage shift register of the first gate driving circuit GOA1.
  • the potential of the fourth node B of the bit register is the same, so that the potential of the selection drive output OUT of the 3n-2th stage shift register of the first gate drive circuit GOA1 and the select drive output of the 3nth stage shift register are output.
  • the potentials are the same, where n is an integer greater than one.
  • the mode switching circuit 20 also controls the drive control circuit 10 such that the timing ratio of each of the second group of timing control signals (including at least the second trigger signal STV2, the third clock signal CK2, and the fourth clock signal CKB2)
  • the timing of the corresponding signals in a set of timing control signals (including at least the first trigger signal STV1, the first clock signal CK1, and the second clock signal CKB1) is delayed by one trigger signal width; the timing diagrams of the specific two sets of timing control signals are as shown in FIG. 10b. Show.
  • the drive signal output ends of the shift registers of the respective stages are sequentially outputted with the scan signal; and when the drive signal output end of the j-th stage shift register of the second drive control circuit GOA2 outputs the scan signal, the first drive control circuit
  • the drive signal output of the j+1th shift register of GOA1 also outputs a scan signal, where j is an integer greater than or equal to one.
  • the mode switching circuit 20 further controls the drive control circuit 10 to output a selection control signal to the second gate of the selection control signal terminal of the shift register connected to the 3nth gate line in the first gate driving circuit GOA1.
  • the selection control signal terminals of the shift registers connected to the 3n-1th gate lines in the pole drive circuit GOA2 each output a selection control signal.
  • the first gate driving circuit GOA1 sequentially outputs the scanning signals only to the 3nth gate line
  • the second gate driving circuit GOA2 sequentially outputs the scanning signals only to the 3n-1th gate lines, thereby realizing the scanning direction.
  • the adjacent three gate lines are a gate line group, and each gate line group sequentially receives the scan signal, that is, the display panel is scanned simultaneously by three gate lines, and the resolution of the display panel is reduced to 1/3 resolution.
  • the black line at the start of the gate line indicates that the selection control signal end of the shift register in the gate driving circuit is a selective control signal, and the corresponding selected driving output terminal is capable of outputting a scan signal.
  • the starting end of the gate line is a circle indicating that the selection control signal end of the shift register in the gate driving circuit has no control signal selected, and the corresponding selected driving output terminal does not output. Scanning the signal, however, since all of the first switching device 30 and all of the second switching devices 40 in the first gate driving circuit GOA1 are in an on state, the 3n-2th shift in the first gate driving circuit GOA1 The selection drive output of the register outputs the same scan signal as the selected drive output of the 3nth stage shift register.
  • a timing chart of the scanning signals on the respective gate lines along the scanning direction on the display panel is as shown in FIG. 10c.
  • the third node A of the 4n-1th stage shift register respectively connected to the first gate driving circuit GOA1 is further included.
  • the third switching device 50 between the third node A of the 4th-3th stage shift register is respectively connected to the fourth node B and the 4th-th of the 4n-1th stage shift register of the first gate driving circuit GOA1.
  • the fourth switching device 60 between the fourth node B of the 3-level shift register is respectively connected to the third node A and the 4n-2th shift register of the 4n-th stage shift register of the second gate driving circuit GOA2
  • the mode switching circuit 20 controls all of the first switching devices 30 and all of the second switching devices 40 to be in an off state upon receiving the third mode control signal; controlling all of the third switching devices 50, all of the fourth switching devices 60, all The fifth switching device 70 and all of the sixth switching devices 80 are in an on state.
  • the potential of the selected driving output end of the 4n-1th stage shift register of the first gate driving circuit is made the same as the potential of the selected driving output end of the 4n-3th stage shift register; and the second gate driving circuit is made
  • the potential of the selection drive output of the 4nth stage shift register is the same as the potential of the selected drive output of the 4n-2 stage shift register.
  • the mode switching circuit 20 also controls the drive control circuit 10 such that the timing of each of the signals in the first group of timing control signals is delayed by one trigger signal width from the timing of the corresponding signals in the second group of timing control signals.
  • the mode switching circuit 20 also controls the drive control circuit 10 such that the timing of each of the signals in the first group of timing control signals is delayed by one trigger signal width from the timing of the corresponding signals in the second group of timing control signals.
  • the mode switching circuit 20 also controls the drive control circuit 10 to input the selection control signal of the shift register connected to the 4n-1th gate line in the first gate drive circuit GOA1.
  • the selection control signal is outputted to the selection control signal terminal of the shift register connected to the 4nth gate line in the second gate driving circuit to output a selection control signal.
  • the potential of the selected driving output terminal of the 4n-1th stage shift register of the first gate driving circuit GOA1 is the same as the potential of the selected driving output terminal of the 4n-3th stage shift register; the second gate
  • the potential of the selection drive output terminal of the 4nth stage shift register of the drive circuit GOA2 is the same as the potential of the selected drive output terminal of the 4n-2th stage shift register.
  • the first gate driving circuit GOA1 simultaneously outputs scanning signals to the 4n-1th and 4n-3th gate lines
  • the second gate driving circuit GOA2 simultaneously outputs to the 4nth and 4thth to 2ndth gate lines. Scanning the signal, so that the adjacent four gate lines are taken as a gate line group along the scanning direction, and each gate line group sequentially receives the scan signal, that is, the display panel is simultaneously scanned by four gate lines, and the resolution of the display panel is reduced to 1 /4 resolution.
  • a timing chart of scanning signals on the respective gate lines along the scanning direction on the display panel is as shown in FIG. 11b.
  • the mode switching circuit 20 is further configured to: when receiving the fourth mode control signal: control all switching devices to be in a closed state to ensure signals of each gate line Do not affect each other;
  • the mode switching circuit 20 also controls the driving control circuit 10 to make the timing of each signal in the second group of timing control signals the same as the timing of the corresponding signal in the first group of timing control signals;
  • the drive signal output terminal of the nth stage shift register of the drive control circuit GOA1 outputs the scan signal
  • the drive signal output terminal of the nth stage shift register of the second drive control circuit GOA2 also outputs the scan signal.
  • the mode switching circuit 20 also controls the drive control circuit 10 to output a selection control signal to the selection control signal terminals of all the shift registers.
  • the first gate driving circuit sequentially outputs the scanning signals to the N gate lines
  • the second gate driving circuit sequentially outputs the scanning signals to the N gate lines, thereby realizing the function of scanning line by line in the scanning direction, that is, displaying
  • the panel has a higher resolution.
  • a timing chart of scanning signals on the respective gate lines along the scanning direction on the display panel is as shown in FIG. 12 .
  • the sustain duration of each mode control signal is an integer multiple of the duration used to scan the N gate lines, and switching between any two mode control signals The point is synchronized with the starting point of the scan raster.
  • the switching device may be a switching transistor, or may be another electronic switch control module, which is not limited herein.
  • the display panel provided by the embodiment of the present invention adds a switching device between the shift registers by setting an output control unit, a second pull-up unit, and a second pull-down unit in the shift register, and controls two sets of timings.
  • the timing of the control signal achieves the purpose of reducing the resolution.
  • the embodiment of the present invention only gives four cases, the display panel which realizes 1/5 resolution, 1/6 resolution, etc. based on the above idea also belongs to the protection of the present invention. range.
  • the user can send a mode control signal to the mode switching circuit through the operation interface of the display panel according to actual requirements, which is not limited herein.
  • the display panel provided by the embodiment of the present invention may be a liquid crystal display panel or an organic electroluminescence display panel, which is not limited herein.
  • an embodiment of the present invention further provides a display device, including any of the above display panels provided by the embodiments of the present invention.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • an embodiment of the present invention further provides a driving method for the foregoing display panel, including:
  • the mode switching circuit When the mode switching circuit receives the first mode control signal: controlling all the switching devices to be in an off state; controlling the driving control circuit to make the timing of each signal in the first group of timing control signals be shorter than the timing of the corresponding signals in the second group of timing control signals Delaying a trigger signal width; and controlling the drive control circuit to output a selection control signal to the selection control signal terminal of the shift register connected to the odd gate lines in the first gate driving circuit, to the second gate driving circuit and the even number
  • the selection control signal terminal of the shift register connected to the gate line outputs a selection control signal;
  • the mode switching circuit When the mode switching circuit receives the second mode control signal: controlling all of the first switching device and all of the second switching devices to be in an on state; controlling all of the third switching devices, all of the fourth switching devices, all of the fifth switches Device and all sixth switching devices are off; control drive
  • the control circuit delays the timing of each signal in the second group of timing control signals by a trigger signal width from the timing of the corresponding signal in the first group of timing control signals; and controls the driving control circuit to the third gate driving circuit and the third n gate
  • the selection control signal terminal of the line-connected shift register outputs a selection control signal, and the selection control signal is output to the selection control signal terminal of the shift register connected to the 3n-1th gate line in the second gate driving circuit, wherein n is an integer greater than or equal to 1;
  • the mode switching circuit When the mode switching circuit receives the third mode control signal: controlling all of the first switching devices and all of the second switching devices to be in an off state; controlling all of the third switching devices, all of the fourth switching devices, all of the fifth switching devices And all the sixth switching devices are in an on state; the control driving control circuit delays the timing of each signal in the first group of timing control signals by a trigger signal width than the timing of the corresponding signals in the second group of timing control signals; and controls the driving control circuit Selecting a control signal to the selection control signal terminal of the shift register connected to the 4n-1th gate line in the first gate driving circuit to shift the connection to the 4nth gate line in the second gate driving circuit The selection control signal terminal of the register outputs a selection control signal;
  • the mode switching circuit When the mode switching circuit receives the fourth mode control signal: controlling all the switching devices to be in a closed state; and controlling the driving control circuit to make the timing of each signal in the second group of timing control signals and the corresponding signals in the first group of timing control signals The timings are the same; and the control drive control circuit outputs a selection control signal to the selection control signal terminals of all the shift registers.
  • a shift register, a driving method of a display panel, and a related device are provided in an embodiment of the present invention.
  • the shift register is equivalent to adding an output control unit, a second pull-up unit, and a second to the existing shift register.
  • a pull-down unit and a selection control signal end wherein, the output control unit is configured to: when the selection control signal end receives the selection control signal, turn on the first node and the third node, and turn on the second node and the fourth node;
  • the second pull-up unit is configured to provide the signal of the first clock signal end to the selected driving output terminal under the control of the third node; the second pull-down unit is configured to provide the signal of the reference signal end to the selection under the control of the fourth node Drive output.
  • the gate driving circuit constituted by the above shift register, it is possible to selectively output a scanning signal to a part of the gate lines.
  • the gate driving circuit is adopted, and a third node respectively connecting the two shift registers and a fourth node respectively connecting the two shift registers are added.
  • a switching device, and a mode switching circuit connected to the driving control circuit.

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  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器、栅极驱动电路、显示面板及其驱动方法和显示装置。该移位寄存器中增加输出控制单元(6)、第二上拉单元(7)、第二下拉单元(8)和选择控制信号端(EN)，可以控制在选择驱动输出端(Output)是否输出扫描信号。在栅极驱动电路中，通过控制在选择控制信号端(EN)施加的选择控制信号，可以选择性地向部分栅线输出扫描信号。在显示面板中，除了采用上述栅极驱动电路之外，还增加了连接两个移位寄存器的第三节点(A)的开关器件(30,50,70)以及连接两个移位寄存器的第四节点(B)之间的开关器件(40,60,80)、以及模式切换电路(20)。模式切换电路(20)可以根据不同的模式控制信号使显示面板按不同的分辨率进行显示，从而选择性的使显示面板降低功耗，延长待机时间。

Description

移位寄存器、栅极驱动电路、显示面板的驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤指一种移位寄存器、栅极驱动电路、显示面板及其驱动方法、以及显示装置。
背景技术
在科技发展日新月异的现今时代中，液晶显示器已经广泛地应用在电子显示产品上，如电视机、计算机、手机及个人数字助理装置等。液晶显示器包括数据驱动装置(Source Driver)、栅极驱动装置(Gate Driver)及液晶显示面板等。在液晶显示面板中布置有像素阵列，而栅极驱动装置用以依序开启像素阵列中的各像素行，以将数据驱动器输出的像素数据传输至当前开启的像素行中的各像素，进而显示待显示图像。
目前，栅极驱动装置一般通过阵列工艺形成在液晶显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺，这种集成工艺不仅节省了成本，而且可以做到液晶面板(Panel)两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，从而可以实现窄边框的设计；并且，这种集成工艺还可以省去栅极扫描线方向的绑定工艺，从而提高了产能和良率。
栅极驱动装置通常由多个级联的移位寄存器构成，这样将各级移位寄存器的驱动信号输出端分别对应于各条栅线，用于沿扫描方向依次向各条栅线输出扫描信号。具体移位寄存器的结构如图1所示，包括：输入单元01、复位单元02、节点控制单元03、上拉单元04、下拉单元05、输入信号端Input、复位信号端Reset、第一时钟信号端ck和参考信号端Vref；其中，输入单元01的输出端、复位单元02的输出端、节点控制单元03的第一端、以及上拉单元04的控制端均与第一节点PU相连，节点控制单元03的第二端和下拉单元05的控制端均与第二节点PD相连；上拉单元04的输出端和下拉单元05的输出端均与移位寄存器的驱动信号输出端Out相连。在如图1所示的移位寄存器中，输入单元01用于在输入信号端Input的控制下控制第一节点PU的电位，复位单元02用于在复位信号端Reset的控制下控制第一节点PU的电位，节点控制单元03用于控制第一节点PU和第二节点PD的电位，上拉 单元04用于在第一节点PU的控制下将第一时钟信号端ck的信号提供给驱动信号输出端Out，下拉单元05用于在第二节点PD的控制下，将参考信号端Vref的信号提供给驱动信号输出端Out。
目前，显示面板中的栅极驱动装置的各级移位寄存器一般均如图1所示，显示面板通过各级移位寄存器沿扫描方向依次向各栅线输出扫描信号。但是随着显示产品分辨率越来越高，显示面板的功耗也随着分辨率的增大而增大，导致待机时间大大减小。因此，如何降低显示产品的功耗，以提高待机时间是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本发明实施例提供一种移位寄存器、栅极驱动电路、显示面板及其驱动方法、以及显示装置，用于实现可以在特殊情况下降低显示面板的分辨率，从而降低显示面板的功耗。
本发明实施例提供的一种移位寄存器，包括：第一上拉单元、第一下拉单元、输出控制单元、第二上拉单元以及第二下拉单元；其中，所述第一上拉单元与第一节点、第一时钟信号端和驱动信号输出端相连，并且在所述第一节点的控制下将第一时钟信号端的信号提供给驱动信号输出端；所述第一下拉单元与第二节点、参考信号端和驱动信号输出端相连，并且在所述第二节点的控制下将参考信号端的信号提供给所述提供给驱动信号输出端；所述输出控制单元与所述第一节点、所述第二节点相连、选择控制信号端、第三节点和第四节点相连，并且在所述选择控制信号端接收到选择控制信号时使所述第一节点和所述第三节点导通以及使所述第二节点和所述第四节点导通；所述第二上拉单元与所述第三节点、所述第一时钟信号端以及选择驱动输出端相连，并且在所述第三节点的控制下将所述第一时钟信号端的信号提供给所述选择驱动输出端；所述第二下拉单元与所述第四节点、所述参考信号端以及选择驱动输出端相连，并且在所述第四节点的控制下，将所述参考信号端的信号提供给所述选择驱动输出端。
在本发明实施例提供的移位寄存器中，所述输出控制单元包括：第一开关晶体管和第二开关晶体管；其中，所述第一开关晶体管的栅极与所述选择控制信号端相连，源极与所述第一节点相连，漏极与所述第三节点相连；所述第二开关晶体管的栅极与所述选择控制信号端相连，源极与所述第二节点 相连，漏极与所述第四节点相连。
在本发明实施例提供的移位寄存器中，所述第二上拉单元包括：第三开关晶体管；其中，所述第三开关晶体管的栅极与所述第三节点相连，源极与所述第一时钟信号端相连，漏极与所述选择驱动输出端相连。
在本发明实施例提供的移位寄存器中，所述第二下拉单元包括：第四开关晶体管；其中，所述第四开关晶体管的栅极与所述第四节点相连，源极与所述参考信号端相连，漏极与所述选择驱动输出端相连。
相应地，本发明实施例还提供了一种栅极驱动电路，包括多个级联的本发明实施例提供的上述任一种移位寄存器；其中，所述移位寄存器还包括输入单元和复位单元，所述输入单元与输入信号端和所述第一节点相连，所述复位单元与复位信号端和所述第一节点相连；除最后一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的下一级移位寄存器的输入信号端相连；第一级移位寄存器的信号输入端用于接收触发信号；除第一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的上一级移位寄存器的复位信号端相连；各级移位寄存器的选择驱动输出端用于与栅线相连。
在本发明实施例提供的栅极驱动电路中，还包括：多个第一开关器件，第k个第一开关器件与第一开关控制端、第3k-2级移位寄存器中的第三节点、以及第3k级移位寄存器中的第三节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第三节点与第3k级移位寄存器中的第三节点导通；多个第二开关器件，第k个第二开关器件与第一开关控制端、第3k-2级移位寄存器中的第四节点、以及第3k级移位寄存器中的第四节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第四节点与第3k级移位寄存器中的第四节点导通；其中，k为大于等于1的整数。
在本发明实施例提供的栅极驱动电路中，还包括：多个第三开关器件，第n个第一开关器件与第二开关控制端、第4n-3级移位寄存器中的第三节点、以及第4n-1级移位寄存器中的第三节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第三节点与第4n-1级移位寄存器中的第三节点导通；多个第四开关器件，第n个第二开关器件与第二开关控制端、将第4n-3级移位寄存器中的第四节点、以及第4n-1级移位寄存器中的第四节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第四 节点与第4n-1级移位寄存器中的第四节点导通；其中，n为大于等于1的整数。
在本发明实施例提供的栅极驱动电路中，还包括：多个第五开关器件，第n个第一开关器件与第三开关控制端、第4n-2级移位寄存器中的第三节点、以及第4n级移位寄存器中的第三节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第三节点与第4n级移位寄存器中的第三节点导通；多个第六开关器件，第n个第二开关器件与第三开关控制端、将第4n-2级移位寄存器中的第四节点、以及第4n级移位寄存器中的第四节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第四节点与第4n级移位寄存器中的第四节点导通；其中，n为大于等于1的整数。
相应地，本发明实施例还提供了一种显示面板，包括N条栅线，分别位于显示面板两侧且均与所述N条栅线连接的第一栅极驱动电路和第二栅极驱动电路；所述第一栅极驱动电路和所述第二栅极驱动电路均为上述的栅极驱动电路；且各所述栅极驱动电路中的移位寄存器的选择驱动输出端与对应的栅线连接；所述显示面板还包括驱动控制电路，该驱动控制电路与所述第一和第二栅极驱动电路连接，向所述第一和第二栅极驱动电路输出选择控制信号，向所述第一栅极驱动电路输出第一组时序控制信号，以及向所述第二栅极驱动电路输出的第二组时序控制信号；其中，第一组时序控制信号至少包括第一触发信号和第一时钟信号，第二组时序控制信号至少包括第二触发信号和第三时钟信号，所述第一触发信号和第二触发信号的宽度相同，所述第一栅极驱动电路在第一组时序控制信号的控制下依序由各级移位寄存器的驱动信号输出端输出扫描信号，所述第二栅极驱动电路在第二组时序控制信号的控制下依序由各级移位寄存器的驱动信号输出端输出扫描信号。
较佳地，在本发明实施例提供的上述显示面板中，还包括：与各所述驱动控制电路连接的模式切换电路；其中，所述模式切换电路在接收到第一模式控制信号时：控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向与所述第一栅极驱动电路中第奇数级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中第偶数级移位寄存器的选择控制信号端输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述第一栅极驱动电 路包括所述多个第一开关器件和所述多个第二开关器件，所述模式切换电路在接收到第二模式控制信号时：控制所有第一开关器件和所有第二开关器件处于导通状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中的第3k级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第3k-1级移位寄存器的选择控制信号端输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述第一栅极驱动电路包括所述多个第三开关器件和所述多个第四开关器件，所述第二栅极驱动电路包括所述多个第五开关器件和所述多个第六开关器件，所述模式切换电路在接收到第三模式控制信号时：控制所有第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于导通状态；控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向与所述第一栅极驱动电路中的第4n-1级移位寄存器的选择控制信号端均输出选择控制信号，向所述第二栅极驱动电路中的第4n级移位寄存器的选择控制信号端均输出选择控制信号。
较佳地，在本发明实施例提供的上述显示面板中，所述模式切换电路在接收到第四模式控制信号时：控制所有开关器件处于关闭状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序与所述第一组时序控制信号中对应信号的时序相同；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
相应地，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述任一种显示面板。
相应地，本发明实施例还提供了一种上述显示面板的驱动方法，包括：当所述模式切换电路接收到第一模式控制信号时：控制所有开关器件处于关闭状态；控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向与所述第一栅极驱动电路中第奇数级移位寄存器的选择控制信号端输出选择控制信号，向与所述第二栅极驱动电路中第偶数级移位寄存器的选择控制信号端输出选择控制信号；
当所述模式切换电路接收到第二模式控制信号时：控制所有第一开关器件和所有第二开关器件处于导通状态；控制所有第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于关闭状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中第3k级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中第3k-1条级移位寄存器的选择控制信号端输出选择控制信号；
当所述模式切换电路接收到第三模式控制信号时：控制所有第一开关器件和所有第二开关器件处于关闭状态；控制所有第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于导通状态；控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向与所述第一栅极驱动电路中第4n-1级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中第4n级移位寄存器的选择控制信号端输出选择控制信号；
当所述模式切换电路接收到第四模式控制信号时：控制所有开关器件处于关闭状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序与所述第一组时序控制信号中对应信号的时序相同；并且控制所述驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
在本发明实施例提供的上述移位寄存器、栅极驱动电路、显示面板及其驱动方法、以及显示装置中，在现有的移位寄存器的基础上增加了输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端；其中，输出控制单元用于在选择控制信号端接收到选择控制信号时，使移位寄存器中的第一节点和第三节点导通，以及使第二节点和第四节点导通；第二上拉单元用于在第三节点的控制下将第一时钟信号端的信号提供给选择驱动输出端；第二下拉单元用于在第四节点的控制下将参考信号端的信号提供给选择驱动输出端。可以通过输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端的控制决定选择驱动输出端是否有扫描信号输出。在采用上述移位寄存器构成的栅极驱动电路中，可以实现有选择性地向部分栅线输出扫描信号。在本发明实施例提供的显示面板中采用上述栅极驱动电路，并且还增加了分别 连接两个移位寄存器的第三节点的开关器件以及分别连接两个移位寄存器的第四节点之间的开关器件、以及与驱动控制电路连接的模式切换电路。这样当模式切换电路接收到不同的模式控制信号时，可以使显示面板按不同的分辨率进行显示，从而可以选择性的使显示面板降低功耗，延长待机时间。
附图说明
图1为现有技术的移位寄存器的结构示意图；
图2为本发明实施例提供的移位寄存器的结构示意图之一；
图3为本发明实施例提供的移位寄存器的结构示意图之二；
图4为本发明实施例提供的移位寄存器的具体结构示意图；
图5为图4所示的移位寄存器对应的信号时序图；
图6为本发明实施例提供的栅极驱动电路的结构示意图；
图7为本发明实施例提供的显示面板的结构示意图之一；
图8为本发明实施例提供的第一栅极驱动电路对应的信号时序图；
图9a为本发明实施例提供的显示面板的结构示意图之二；
图9b为本发明实施例提供的显示面板中当模式切换电路接收到第一模式控制信号时或第三模式控制信号时控制驱动控制电路输出的两组时序控制信号的时序图；
图9c为本发明实施例提供的显示面板中当模式切换电路接收到第一模式控制信号时所对应的栅线上的扫描信号的时序图；
图10a为本发明实施例提供的显示面板的结构示意图之二；
图10b为本发明实施例提供的显示面板中当模式切换电路接收到第二模式控制信号时控制驱动控制电路输出的两组时序控制信号的时序图；
图10c为本发明实施例提供的显示面板中当模式切换电路接收到第二模式控制信号时所对应的栅线上的扫描信号的时序图；
图10d为图10a为所示显示面板的局部放大示意图；
图11a为本发明实施例提供的显示面板的结构示意图之三；
图11b为本发明实施例提供的显示面板中当模式切换电路接收到第三模式控制信号时所对应的栅线上的扫描信号的时序图；
图12为本发明实施例提供的显示面板中当模式切换电路接收到第四模式控制信号时所对应的栅线上的扫描信号的时序图。
具体实施方式
下面结合附图，对本发明实施例提供的移位寄存器、栅极驱动电路、显示面板及其驱动方法、以及显示装置的具体实施方式进行详细地说明。
下面先对本发明实施例提供的移位寄存器进行说明。
本发明实施例提供的一种移位寄存器，如图2所示，包括：输入单元1、复位单元2、节点控制单元3、第一上拉单元4、第一下拉单元5、输入信号端Input、复位信号端Reset、第一时钟信号端ck1和参考信号端Vref；其中，输入单元1的输出端、复位单元2的输出端、节点控制单元3的第一端、以及第一上拉单元4的控制端均与第一节点PU相连，节点控制单元3的第二端、第一下拉单元5的控制端均与第二节点PD相连；第一上拉单元4的输出端和第一下拉单元5的输出端均与移位寄存器的驱动信号输出端Out相连。具体地，输入单元1用于在输入信号端Input的控制下控制第一节点PU的电位，复位单元2用于在复位信号端Reset的控制下控制第一节点PU的电位，节点控制单元3用于控制第一节点PU和第二节点PD的电位，第一上拉单元4用于在第一节点PU的控制下将第一时钟信号端ck1的信号提供给驱动信号输出端Out，第一下拉单元5用于在第二节点PD的控制下将参考信号端Vref的信号提供给驱动信号输出端Out。
此外，如图2所示，移位寄存器还包括：输出控制单元6、第二上拉单元7、第二下拉单元8和选择控制信号端EN。输出控制单元6的第一输入端与第一节点PU相连，第二输入端与第二节点PD相连，第三输入端与选择控制信号端EN相连，第一输出端与第三节点A和第二上拉单元7的第一输入端相连，第二输出端与第四节点B和第二下拉单元8的第一输入端相连；第二上拉单元7的第二输入端与第一时钟信号端ck1相连，第二上拉单元7的输出端与第二下拉单元8的输出端相连作为移位寄存器的选择驱动输出端Output；第二下拉单元8的第二输入端与参考信号端Vref相连。
具体地，输出控制单元6用于在选择控制信号端EN接收到选择控制信号时，使第一节点PU和第三节点A导通，以及使第二节点PD和第四节点B导通；第二上拉单元7用于在第三节点A的控制下将第一时钟信号端ck1的信号提供给选择驱动输出端Output；第二下拉单元8用于在第四节点B的控制下将参考信号端Vref的信号提供给选择驱动输出端Output。
本发明实施例提供的上述移位寄存器，相当于在现有的移位寄存器的基础上增加了输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端；其中，输出控制单元用于在选择控制信号端接收到选择控制信号时，使第一节点和第三节点导通，以及使第二节点和第四节点导通；第二上拉单元用于在第三节点的控制下将第一时钟信号端ck1的信号提供给选择驱动输出端Output；第二下拉单元用于在第四节点的控制下将参考信号端Vref的信号提供给选择驱动输出端Output。由此，可以通过输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端的控制来决定选择驱动输出端是否有扫描信号输出。结果，在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。
下面结合具体实施例，对本发明进行详细说明。需要说明的是，本实施例中是为了更好的解释本发明，但不限制本发明。
较佳地，在本发明实施例提供的上述移位寄存器中，如图3所示，输出控制单元6，具体可以包括：第一开关晶体管T1和第二开关晶体管T2；其中，第一开关晶体管T1的栅极与选择控制信号端EN相连，源极与第一节点PU相连，漏极与第三节点A相连；第二开关晶体管T2的栅极与选择控制信号端EN相连，源极与第二节点PD相连，漏极与第四节点B相连。
本发明实施例提供的上述移位寄存器，当选择控制信号端EN控制第一开关晶体管T1和第二开关晶体管T2处于导通状态时，第一节点PU与第三节点A被导通，并且第二节点PD与第四节点B被导通。
在具体实施时，第一开关晶体管T1和第二开关晶体管T2可以均为P型晶体管，也可以均为N型晶体管，在此不作限定。
以上仅是举例说明移位寄存器中输出控制单元的具体结构，在具体实施时，输出控制单元的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器中，如图3所示，第二上拉单元7，具体可以包括：第三开关晶体管T3；其中，第三开关晶体管T3的栅极与第三节点A相连，源极与第一时钟信号端ck1相连，漏极与选择驱动输出端Output相连。
本发明实施例提供的上述移位寄存器，当第三开关晶体管T3在第三节点A的控制下处于导通状态时，第三开关晶体管T3将第一时钟信号端ck1 的信号提供给选择驱动输出端Output。
以上仅是举例说明移位寄存器中第二上拉单元的具体结构，在具体实施时，第二上拉单元的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
较佳地，在本发明实施例提供的上述移位寄存器中，如图3所示，第二下拉单元8，具体可以包括：第四开关晶体管T4；其中，第四开关晶体管T4的栅极与第四节点B相连，源极与参考信号端Vref相连，漏极与选择驱动输出端Output相连。
本发明实施例提供的上述移位寄存器，当第四开关晶体管T4在第四节点B的控制下处于导通状态时，第四开关晶体管T4将参考信号端Vref的信号提供给选择驱动输出端Output。
以上仅是举例说明移位寄存器中第二下拉单元的具体结构，在具体实施时，第二下拉单元的具体结构不限于本发明实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不做限定。
具体地，在本发明实施例提供的上述移位寄存器中，节点控制单元具体用于根据第一节点PU的电位控制第二节点PD的电位，根据第二节点PD的电位控制第一节点PU的电位，从而通过控制第一节点PU和第二节点PD的电位，实现移位寄存器的基本功能。
进一步地，在本发明实施例提供的上述移位寄存器中，输入单元1、复位单元2、节点控制单元3、第一上拉单元4和第一下拉单元5的结构均与现有技术相同，在此不作详述。下面通过一个具体实施例说明，但是不限于此。
实施例一：
具体地，如图4所示，输入单元1可以包括第五开关晶体管T5；复位单元2可以包括第六开关晶体管T6；节点控制单元3可以包括第七开关晶体管T7、第八开关晶体管T8、第九开关晶体管T9、第十开关晶体管T10和第一电容C1；第一上拉单元4可以包括第十一开关晶体管T11和第二电容C2；第一下拉单元5可以包括第十二开关晶体管T12。
第五开关晶体管T5的栅极与输入信号端Input相连，源极与第一直流信号端VDD相连，漏极与上拉节点PU相连；第六开关晶体管T6的栅极与复位信号端Reset相连，源极与第二直流信号端VSS相连，漏极与第一节点PU相连；第七开关晶体管T7的栅极与源极均与第二时钟信号端ckb1相连，漏 极与第二节点PD相连；第八开关晶体管T8的栅极与第二节点PD相连，源极与参考信号端Vref相连，漏极与第一节点PU相连；第九开关晶体管T9的栅极与第一节点PU相连，源极与参考信号端Vref相连，漏极与第二节点PD相连；第十开关晶体管T10的栅极与驱动信号输出端Out相连，源极与参考信号端Vref相连，漏极与第二节点PD相连；第十一开关晶体管T11的栅极与第一节点PU相连，源极与第一时钟信号端ck1相连，漏极与驱动信号输出端Out相连；第十二开关晶体管T12的栅极与第二节点PD相连，源极与参考信号端Vref相连，漏极与驱动信号输出端Out相连；第一电容C1连接于第二节点PD与参考信号端Vref之间；第二电容C2连接于第一节点PU与驱动信号输出端Out之间。
具体地，在图4中所有开关晶体管均为N型晶体管，当然在具体实施时，所有开关晶体管也可以均为P型晶体管，或者部分晶体管为N型晶体管，部分晶体管为P型晶体管，在此不作限定。
具体地，以图4所示的移位寄存器为例对本发明实施例提供的移位寄存器的工作原理进行说明。对应的工作时序图如图5所示，可以分为t1、t2、t3、t4和t5五个阶段。下述描述中以1表示高电位信号，0表示低电位信号。
在第一阶段t1，Input＝1，ck1＝0，ckb1＝1，Reset＝0，EN＝1。
由于Input＝1，第五开关晶体管T5导通，第一节点PU的电位为高电位，第十一开关晶体管T11导通，驱动信号输出端Out的电位为低电位。由于ckb1＝1，第七开关晶体管T7导通，同时由于第一节点PU的电位为高电位，第九开关晶体管T9导通，第二节点PD的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第三节点A的电位为高电位，第三开关晶体管T3导通，选择驱动输出端Output的电位为低电位。
在第二阶段t2，Input＝0，ck1＝1，ckb1＝0，Reset＝0，EN＝1。
由于ck1＝1，由于第二电容的自举作用，第一节点PU的电位被进一步拉高，第十一开关晶体管T11保持导通，驱动信号输出端Out的电位为高电位。由于第一节点PU的电位为高电位，第九开关晶体管T9导通，第二节点PD的电位为低电位。由于驱动信号输出端Out的电位为高电位，第十开关晶体管T10导通，第二节点PD的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第三节点A的电位为高电位，第三开关晶体管T3导通，选择驱动输出端Output的电位为高电位。
在第三阶段t3，Input＝0，ck1＝0，ckb1＝1，Reset＝1，EN＝1。
由于Reset＝1，第六开关晶体管T6导通，第一节点PU的电位为低电位。由于ckb1＝1，第七开关晶体管T7导通，第二节点PD的电位为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四节点B的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
在第四阶段t4，Input＝0，ck1＝1，ckb1＝0，Reset＝0，EN＝1。
由于第一电容C1的作用，第二节点PD的电位仍保持为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四节点B的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
在第五阶段t5，Input＝0，ck1＝0，ckb1＝1，Reset＝0，EN＝1。
由于ckb1＝1，第七开关晶体管T7导通，第二节点PD的电位为高电位，第十二开关晶体管T12导通，驱动信号输出端Out的电位为低电位。由于第二节点PD的电位为高电位，第八开关晶体管T8导通，第一节点PU的电位为低电位。由于EN＝1，第一开关晶体管T1和第二开关晶体管T2导通，第四节点B的电位为高电位，第四开关晶体管T4导通，选择驱动输出端Output的电位为低电位。
之后，移位寄存器一直重复第四阶段和第五阶段，直至输入信号端Input的电位再次变为高电位。
需要说明的是本发明上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。在具体实施中，这些开关晶体管的源极和漏极根据晶体管类型以及输入信号的不同，其功能可以互换，在此不做具体区分。
基于同一发明构思，本发明实施例还提供了一种栅极驱动电路，如图6所示，包括级联的多个上述移位寄存器：SR(1)、SR(2)、……、SR(N-1)、SR(N) (共N个移位寄存器)。
除最后一级移位寄存器SR(N)之外，其余每一级移位寄存器SR(m)的驱动信号输出端OUT_m(1≤m≤N)分别与与其相邻的下一级移位寄存器SR(m+1)的输入信号端Input相连。
第一级移位寄存器SR(1)的信号输入端Input用于接收触发信号；除第一级移位寄存器SR(1)之外，其余每一级移位寄存器SR(m)的驱动信号输出端OUT_m分别与与其相邻的上一级移位寄存器SR(m-1)的复位信号端Reset相连。
各级移位寄存器SR(m)的选择驱动输出端Output_m用于与栅线相连。
上述栅极驱动电路通过各级移位寄存器SR(m)的选择驱动输出端Output_m与对应的栅线gatem连接，用于顺序地向对应的栅线输出扫描信号。
进一步地，在本发明实施例提供的上述栅极驱动电路中，如图6所示，一般奇数级移位寄存器的第一时钟信号端ck1与偶数级移位寄存器的第二时钟信号端ckb1用于接收同一时钟信号(图中表示为CK1)，奇数级移位寄存器的第二时钟信号端ckb1与偶数级移位寄存器的第一时钟信号端ck1用于接收同一时钟信号(图中表示为CKB1)。
基于同一发明构思，本发明实施例还提供了一种显示面板，如图7所示，包括N条栅线(gate1、gate2、gate3…)，分别位于显示面板两侧且均与N条栅线连接的第一栅极驱动电路GOA1和第二栅极驱动电路GOA2，其中，第一栅极驱动电路GOA1和第二栅极驱动电路GOA2均为本发明实施例提供的上述栅极驱动电路；且各栅极驱动电路中的移位寄存器SR(m)的选择驱动输出端Output_m与对应的栅线连接。
显示面板还包括驱动控制电路10，该驱动控制电路10与第一和第二栅极驱动电路(GOA1和GOA2)连接，至少用于向第一和第二栅极驱动电路(GOA1和GOA2)输出选择控制信号，向第一栅极驱动电路GOA1输出第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)，向第二栅极驱动电路输出第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)；其中，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各栅极驱动电路(GOA1和GOA2)用于在接收的对应组时序控制信号的控制下依次由驱动信号输出端Out输出扫描信号。
下面以第一栅极驱动电路GOA1为例，具体说明一组时序控制信号对一个栅极驱动电路的控制。第一栅极驱动电路GOA1如图6所示，驱动控制电路向第一级移位寄存器SR(1)输入第一触发信号STV1，分别向奇数级移位寄存器的第一时钟信号端ck1和偶数级移位寄存器的第二时钟信号端ckb1输入第一时钟信号CK1，向奇数级移位寄存器的第二时钟信号端ckb1和偶数级移位寄存器的第一时钟信号端ck1输入第二时钟信号CKB1。
当第一级移位寄存器SR(1)收到第一触发信号STV1后，当第一时钟信号端ck1第一次接收到第一时钟信号CK1时驱动信号输出端Out_1输出扫描信号，此时若对应的输出控制单元处于导通状态，则选择驱动输出端Output_1向第1条栅线gate1输出扫描信号，第一级移位寄存器SR(1)的驱动信号输出端Out_1输出的扫描信号提供给第二级移位寄存器SR(2)的输入信号端Input；当第二级移位寄存器SR(2)收到第一级移位寄存器SR(1)输出的扫描信号后，当其第一时钟信号端ck1第一次接收到第二时钟信号CKB1时驱动信号输出端Out_2输出扫描信号，此时若对应的输出控制单元处于导通状态，则选择驱动输出端Output_2向第2条栅线gate2输出扫描信号，第二级移位寄存器SR(2)的驱动信号输出端Out_2输出的扫描信号提供给第三级移位寄存器SR(3)的输入信号端Input；当第三级移位寄存器SR(3)收到第二级移位寄存器SR(2)输出的扫描信号后，当其第一时钟信号端ck1接收到第一时钟信号CK1时驱动信号输出端Out_3输出扫描信号，此时若对应的输出控制单元处于导通状态，则选择驱动输出端Output_3向第3条栅线gate3输出扫描信号，第三级移位寄存器SR(3)的驱动信号输出端Out_3输出的扫描信号提供给第四级移位寄存器SR(4)的输入信号端Input，依次类推，各级移位寄存器依次向对应的栅线输出扫描信号。具体第一栅极驱动电路GOA1对应的输入输出时序图如图8所示。
此外，驱动控制电路10向第二栅极驱动电路GOA2的第一级移位寄存器输入第二触发信号，分别向奇数级移位寄存器的第一时钟信号端和偶数级移位寄存器的第二时钟信号端输入第三时钟信号，向奇数级移位寄存器的第二时钟信号端和偶数级移位寄存器的第一时钟信号端输入第四时钟信号。第二栅极驱动电路的具体工作原理与第一栅极驱动电路的工作原理相同，在此不作赘述。
较佳地，在本发明实施例提供的上述显示面板中，如图9a所示，还包括： 与驱动控制电路10连接的模式切换电路20。
模式切换电路20在接收到第一模式控制信号时，控制驱动控制电路10，使得第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中各信号的时序比第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中对应信号的时序延迟一个触发信号宽度。具体两组时序控制信号的时序图如图9b所示；由此，使各级移位寄存器的驱动信号输出端依次有扫描信号输出；并且当第一驱动控制电路的第n级移位寄存器的驱动信号输出端输出扫描信号时，第二驱动控制电路的第n+1级移位寄存器的驱动信号输出端也输出扫描信号。
在此情况下，模式切换电路20还控制驱动控制电路10向第一栅极驱动电路GOA1中与奇数条栅线(gate1、gate3、gate5…)连接的移位寄存器(SR(1)、SR(3)、SR(5)…)的选择控制信号端均输出选择控制信号，向第二栅极驱动电路GOA2中与偶数条栅线(gate2、gate4、gate6…)连接的移位寄存器(SR(2)、SR(4)、SR(4)…)的选择控制信号端均输出选择控制信号。由此，使第一栅极驱动电路仅向奇数条栅线依次输出扫描信号，使第二栅极驱动电路仅向偶数条栅线依次输出扫描信号，从而实现沿扫描方向以相邻的两条栅线为一栅线组，各栅线组依次接收扫描信号，即显示面板是以两条栅线同时扫描的，显示面板的分辨率降低为1/2分辨率。
具体地，在图9a中，栅线起始端为黑点表示栅极驱动电路中的该移位寄存器的选择控制信号端是有选择控制信号的，对应的选择驱动输出端是可以输出扫描信号的，栅线起始端为圆圈表示栅极驱动电路中的该移位寄存器的选择控制信号端是没有选择控制信号的，对应的选择驱动输出端是不输出扫描信号的。
具体地，本发明实施例提供的上述显示面板，当模式切换电路20接收到第一模式控制信号时，显示面板上沿扫描方向各栅线上扫描信号的时序图如图9c所示。
较佳地，在本发明实施例提供的上述显示面板中，如图10a和图10d所示，还包括：分别连接在第一栅极驱动电路GOA1的第3n-2级移位寄存器的第三节点A与第3n级移位寄存器的第三节点A之间的第一开关器件30(具体结构图10a中未示出，参见图10d)，以及分别连接在第一栅极驱动电路 GOA1的第3n-2级移位寄存器的第四节点B与第3n级移位寄存器的第四节点B之间的第二开关器件40(具体结构图10a中未示出，参见图10d，图10d为图10a中虚线框的局部具体结构示意图)；其中n为大于1的整数。
模式切换电路20还在接收到第二模式控制信号时，控制所有第一开关器件30和所有第二开关器件40处于导通状态；使得第一栅极驱动电路GOA1的第3n-2级移位寄存器的第三节点A与第3n级移位寄存器的第三节点A的电位相同，以及使第一栅极驱动电路GOA1的第3n-2级移位寄存器的第四节点B与第3n级移位寄存器的第四节点B的电位相同，从而使第一栅极驱动电路GOA1的第3n-2级移位寄存器的选择驱动输出端Output的电位与第3n级移位寄存器的选择驱动输出端Output的电位相同，其中n为大于1的整数。
在此情况下，模式切换电路20还控制驱动控制电路10使得第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中各信号的时序比第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中对应信号的时序延迟一个触发信号宽度；具体两组时序控制信号的时序图如图10b所示。由此，使各级移位寄存器的驱动信号输出端依次有扫描信号输出；并且当第二驱动控制电路GOA2的第j级移位寄存器的驱动信号输出端输出扫描信号时，第一驱动控制电路GOA1的第j+1级移位寄存器的驱动信号输出端也输出扫描信号，其中j为大于等于1的整数。
在此情况下，模式切换电路20还控制驱动控制电路10向第一栅极驱动电路GOA1中与第3n条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，向第二栅极驱动电路GOA2中与第3n-1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号。由此，使第一栅极驱动电路GOA1仅向第3n条栅线依次输出扫描信号，使第二栅极驱动电路GOA2仅向第3n-1条栅线依次输出扫描信号，从而实现沿扫描方向以相邻的三条栅线为一栅线组，各栅线组依次接收扫描信号，即显示面板是以三条栅线同时扫描的，显示面板的分辨率降低为1/3分辨率。
具体地，在图10a中，栅线起始端为黑点表示栅极驱动电路中的该移位寄存器的选择控制信号端是有选择控制信号的，对应的选择驱动输出端是可以输出扫描信号的，栅线起始端为圆圈表示栅极驱动电路中的该移位寄存器的选择控制信号端是没有选择控制信号的，对应的选择驱动输出端是不输出 扫描信号的，然而由于第一栅极驱动电路GOA1中的所有第一开关器件30和所有第二开关器件40均处于导通状态，因此第一栅极驱动电路GOA1中第3n-2级移位寄存器的选择驱动输出端与第3n级移位寄存器的选择驱动输出端输出相同的扫描信号。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第二模式控制信号时，显示面板上沿扫描方向各栅线上扫描信号的时序图如图10c所示。
较佳地，在本发明实施例提供的上述显示面板中，如图11a所示，还包括：分别连接在第一栅极驱动电路GOA1的第4n-1级移位寄存器的第三节点A与第4n-3级移位寄存器的第三节点A之间的第三开关器件50，分别连接在第一栅极驱动电路GOA1的第4n-1级移位寄存器的第四节点B与第4n-3级移位寄存器的第四节点B之间的第四开关器件60，分别连接在第二栅极驱动电路GOA2的第4n级移位寄存器的第三节点A与第4n-2级移位寄存器的第三节点A之间的第五开关器件70，以及分别连接在第二栅极驱动电路GOA2的第4n级移位寄存器的第四节点B与第4n-2级移位寄存器的第四节点B之间的第六开关器件80，其中n为大于等于1的整数。
模式切换电路20在接收到第三模式控制信号时，控制所有的第一开关器件30和所有第二开关器件40处于关闭状态；控制所有的第三开关器件50、所有第四开关器件60、所有第五开关器件70和所有第六开关器件80处于导通状态。由此，使第一栅极驱动电路的第4n-1级移位寄存器的选择驱动输出端的电位与第4n-3级移位寄存器的选择驱动输出端的电位相同；使第二栅极驱动电路的第4n级移位寄存器的选择驱动输出端的电位与第4n-2级移位寄存器的选择驱动输出端的电位相同。
在此情况下，所述模式切换电路20还控制驱动控制电路10使得第一组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟一个触发信号宽度。由此，不仅使各级移位寄存器的驱动信号输出端依次有扫描信号输出；而且当第一驱动控制电路的第j级移位寄存器的驱动信号输出端输出扫描信号时，第二驱动控制电路的第j+1级移位寄存器的驱动信号输出端也输出扫描信号。
在此情况下，所述模式切换电路20还控制驱动控制电路10向第一栅极驱动电路GOA1中与第4n-1条栅线连接的移位寄存器的选择控制信号端均输 出选择控制信号，向第二栅极驱动电路中与第4n条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号。此时，如上所述，第一栅极驱动电路GOA1的第4n-1级移位寄存器的选择驱动输出端的电位与第4n-3级移位寄存器的选择驱动输出端的电位相同；第二栅极驱动电路GOA2的第4n级移位寄存器的选择驱动输出端的电位与第4n-2级移位寄存器的选择驱动输出端的电位相同。由此，第一栅极驱动电路GOA1同时向第4n-1条和第4n-3条栅线输出扫描信号，第二栅极驱动电路GOA2同时向第4n条和第4n-2条栅线输出扫描信号，从而实现沿扫描方向以相邻的四条栅线为一栅线组，各栅线组依次接收扫描信号，即显示面板是以四条栅线同时扫描的，显示面板的分辨率降低为1/4分辨率。
具体地，本发明实施例提供的上述显示面板，当模式切换电路接收到第三模式控制信号时，显示面板上沿扫描方向各栅线上扫描信号的时序图如图11b所示。
较佳地，在本发明实施例提供的上述显示面板中，模式切换电路20还用于，在接收到第四模式控制信号时：控制所有的开关器件处于关闭状态，以保证各栅线的信号之间互相不影响；
在此情况下，所述模式切换电路20还控制驱动控制电路10使第二组时序控制信号中各信号的时序与第一组时序控制信号中对应信号的时序相同；由此，使当第一驱动控制电路GOA1的第n级移位寄存器的驱动信号输出端输出扫描信号时，第二驱动控制电路GOA2的第n级移位寄存器的驱动信号输出端也输出扫描信号。
在此情况下，所述模式切换电路20还控制驱动控制电路10向所有移位寄存器的选择控制信号端均输出选择控制信号。由此，使第一栅极驱动电路向N条栅线依次输出扫描信号，使第二栅极驱动电路向N条栅线依次输出扫描信号，从而实现沿扫描方向逐行扫描的功能，即显示面板具有较高的分辨率。这样本发明实施例提供的上述显示面板，不仅可以在需要省电的时候实现低分辨率显示，并且可以在不需要省电的时候实现高分辨率显示。
具体地，本发明实施例提供的上述显示面板，当模式切换电路20接收到第四模式控制信号时，显示面板上沿扫描方向各栅线上扫描信号的时序图如图12所示。
需要说明的是，在本发明实施例提供的显示面板中，第一模式控制信号、 第二模式控制信号、第三模式控制信号和第四模式控制信号中，各模式控制信号的维持时长是扫描N条栅线所用的时长的整数倍，且任意两个模式控制信号之间的切换点与扫描栅线的起始点同步。
进一步地，本发明实施例提供的上述显示面板，开关器件可以是开关晶体管，也可以是其它电子开关控制模块，在此不作限定。
具体地，本发明实施例提供的上述显示面板，通过在移位寄存器中设置输出控制单元、第二上拉单元、第二下拉单元，在移位寄存器之间增加开关器件，以及控制两组时序控制信号的时序达到降低分辨率的目的，虽然本发明实施例只是给出了四种情况，但是基于上述思想得到的实现1/5分辨、1/6分辨等的显示面板也属于本发明的保护范围。
在具体实施时，在本发明实施例提供的上述显示面板，使用者可以根据实际需求通过该显示面板的操作界面向模式切换电路发送模式控制信号，在此不作限定。
进一步地，本发明实施例提供的上述显示面板，既可以是液晶显示面板，也可以是有机电致发光显示面板，在此不作限定。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述任一种显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了上述显示面板的驱动方法，包括：
当模式切换电路在接收到第一模式控制信号时：控制所有开关器件处于关闭状态；控制驱动控制电路使第一组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制驱动控制电路向第一栅极驱动电路中与奇数条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，向第二栅极驱动电路中与偶数条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
当模式切换电路在接收到第二模式控制信号时：控制所有的第一开关器件和所有第二开关器件处于导通状态；控制所有的第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于关闭状态；控制驱动 控制电路使第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制驱动控制电路向第一栅极驱动电路中与第3n条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，向第二栅极驱动电路中与第3n-1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，其中n为大于等于1的整数；
当模式切换电路在接收到第三模式控制信号时：控制所有的第一开关器件和所有第二开关器件处于关闭状态；控制所有的第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于导通状态；控制驱动控制电路使第一组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制驱动控制电路向第一栅极驱动电路中与第4n-1条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，向第二栅极驱动电路中与第4n条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
当模式切换电路在接收到第四模式控制信号时：控制所有的开关器件处于关闭状态；控制驱动控制电路使第二组时序控制信号中各信号的时序与第一组时序控制信号中对应信号的时序相同；并且控制驱动控制电路向所有移位寄存器的选择控制信号端均输出选择控制信号。
本发明实施例提供的一种移位寄存器、显示面板的驱动方法及相关装置，移位寄存器相当于在现有的移位寄存器的基础上增加了输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端；其中，输出控制单元用于在选择控制信号端接收到选择控制信号时，使第一节点和第三节点导通，以及使第二节点和第四节点导通；第二上拉单元用于在第三节点的控制下将第一时钟信号端的信号提供给选择驱动输出端；第二下拉单元用于在第四节点的控制下，将参考信号端的信号提供给选择驱动输出端。从而可以通过输出控制单元、第二上拉单元、第二下拉单元和选择控制信号端的控制来决定选择驱动输出端是否有扫描信号输出。从而，在采用上述移位寄存器构成的栅极驱动电路中，可以实现选择性的向部分栅线输出扫描信号。进一步，在本发明实施例提供的显示面板中在采用上述栅极驱动电路，并且还增加了分别连接两个移位寄存器的第三节点以及分别连接两个移位寄存器的第四节点之间的开关器件，以及与驱动控制电路连接的模式切换电路。这样当模式切换电路在接收到不同的模式控制信号时，可以使显示面板按不同的分辨率进行显示， 从而可以选择性的使显示面板降低功耗，延长待机时间。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求2015年8月6日提交的申请号为201510477631.7且发明名称为“一种移位寄存器、显示面板的驱动方法及相关装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (18)

  1. 一种移位寄存器，包括：第一上拉单元、第一下拉单元、输出控制单元、第二上拉单元以及第二下拉单元；其中，
    所述第一上拉单元与第一节点、第一时钟信号端和驱动信号输出端相连，并且在所述第一节点的控制下将第一时钟信号端的信号提供给驱动信号输出端；
    所述第一下拉单元与第二节点、参考信号端和驱动信号输出端相连，并且在所述第二节点的控制下将参考信号端的信号提供给所述提供给驱动信号输出端；
    所述输出控制单元与所述第一节点、所述第二节点相连、选择控制信号端、第三节点和第四节点相连，并且在所述选择控制信号端接收到选择控制信号时使所述第一节点和所述第三节点导通以及使所述第二节点和所述第四节点导通；
    所述第二上拉单元与所述第三节点、所述第一时钟信号端以及选择驱动输出端相连，并且在所述第三节点的控制下将所述第一时钟信号端的信号提供给所述选择驱动输出端；
    所述第二下拉单元与所述第四节点、所述参考信号端以及选择驱动输出端相连，并且在所述第四节点的控制下，将所述参考信号端的信号提供给所述选择驱动输出端。
  2. 如权利要求1所述的移位寄存器，其中，所述输出控制单元包括：第一开关晶体管和第二开关晶体管；其中，
    所述第一开关晶体管的栅极与所述选择控制信号端相连，源极与所述第一节点相连，漏极与所述第三节点相连；
    所述第二开关晶体管的栅极与所述选择控制信号端相连，源极与所述第二节点相连，漏极与所述第四节点相连。
  3. 如权利要求1所述的移位寄存器，其中，所述第二上拉单元包括：第三开关晶体管；其中，
    所述第三开关晶体管的栅极与所述第三节点相连，源极与所述第一时钟信号端相连，漏极与所述选择驱动输出端相连。
  4. 如权利要求1所述的移位寄存器，其中，所述第二下拉单元包括：第 四开关晶体管；其中，
    所述第四开关晶体管的栅极与所述第四节点相连，源极与所述参考信号端相连，漏极与所述选择驱动输出端相连。
  5. 一种栅极驱动电路，包括多个级联的如权利要求1-4任一项所述的移位寄存器；其中，所述移位寄存器还包括输入单元和复位单元，所述输入单元与输入信号端和所述第一节点相连，所述复位单元与复位信号端和所述第一节点相连；
    除最后一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的下一级移位寄存器的输入信号端相连；
    第一级移位寄存器的信号输入端用于接收触发信号；
    除第一级移位寄存器之外，其余每一级移位寄存器的驱动信号输出端分别与与其相邻的上一级移位寄存器的复位信号端相连；
    各级移位寄存器的选择驱动输出端用于与相应的栅线相连。
  6. 如权利要求5所述的栅极驱动电路，还包括：
    多个第一开关器件，第k个第一开关器件与第一开关控制端、第3k-2级移位寄存器中的第三节点、以及第3k级移位寄存器中的第三节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第三节点与第3k级移位寄存器中的第三节点导通；
    多个第二开关器件，第k个第二开关器件与第一开关控制端、第3k-2级移位寄存器中的第四节点、以及第3k级移位寄存器中的第四节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第四节点与第3k级移位寄存器中的第四节点导通；
    其中，k为大于等于1的整数。
  7. 如权利要求5所述的栅极驱动电路，还包括：
    多个第三开关器件，第n个第一开关器件与第二开关控制端、第4n-3级移位寄存器中的第三节点、以及第4n-1级移位寄存器中的第三节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第三节点与第4n-1级移位寄存器中的第三节点导通；
    多个第四开关器件，第n个第二开关器件与第二开关控制端、将第4n-3级移位寄存器中的第四节点、以及第4n-1级移位寄存器中的第四节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第四节点与 第4n-1级移位寄存器中的第四节点导通；
    其中，n为大于等于1的整数。
  8. 如权利要求5所述的栅极驱动电路，还包括：
    多个第五开关器件，第n个第一开关器件与第三开关控制端、第4n-2级移位寄存器中的第三节点、以及第4n级移位寄存器中的第三节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第三节点与第4n级移位寄存器中的第三节点导通；
    多个第六开关器件，第n个第二开关器件与第三开关控制端、将第4n-2级移位寄存器中的第四节点、以及第4n级移位寄存器中的第四节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第四节点与第4n级移位寄存器中的第四节点导通；
    其中，n为大于等于1的整数。
  9. 一种显示面板，包括N条栅线，分别位于显示面板两侧且均与所述N条栅线连接的第一栅极驱动电路和第二栅极驱动电路，所述第一栅极驱动电路和所述第二栅极驱动电路均为如权利要求5所述的栅极驱动电路；且各所述栅极驱动电路中的移位寄存器的选择驱动输出端与对应的栅线连接；
    所述显示面板还包括驱动控制电路，该驱动控制电路与所述第一和第二栅极驱动电路连接，向所述第一和第二栅极驱动电路输出选择控制信号，向所述第一栅极驱动电路输出第一组时序控制信号，以及向所述第二栅极驱动电路输出的第二组时序控制信号；
    其中，第一组时序控制信号至少包括第一触发信号和第一时钟信号，第二组时序控制信号至少包括第二触发信号和第三时钟信号，所述第一触发信号和第二触发信号的宽度相同，所述第一栅极驱动电路在第一组时序控制信号的控制下依序由各级移位寄存器的驱动信号输出端输出扫描信号，所述第二栅极驱动电路在第二组时序控制信号的控制下依序由各级移位寄存器的驱动信号输出端输出扫描信号。
  10. 如权利要求9所述的显示面板，还包括：与各所述驱动控制电路连接的模式切换电路；其中，所述模式切换电路在接收到第一模式控制信号时：
    控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；
    控制所述驱动控制电路向所述第一栅极驱动电路中第奇数级移位寄存器 的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中第偶数级移位寄存器的选择控制信号端输出选择控制信号。
  11. 如权利要求10所述的显示面板，其中，所述第一栅极驱动电路还包括：
    多个第一开关器件，第k个第一开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第三节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第三节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第三节点与第3k级移位寄存器中的第三节点导通；
    多个第二开关器件，第k个第二开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第四节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第四节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第四节点与第3k级移位寄存器中的第四节点导通；
    其中，k为大于等于1的整数，
    其中，所述模式切换电路在接收到第二模式控制信号时，控制所有第一开关器件和所有第二开关器件处于导通状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中的第3k级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第3k-1级移位寄存器的选择控制信号端输出选择控制信号。
  12. 如权利要求10所述的显示面板，其中，
    所述第一栅极驱动电路还包括：
    多个第三开关器件，第n个第一开关器件与第二开关控制端、所述第一栅极驱动电路中第4n-3级移位寄存器中的第三节点、以及所述第一栅极驱动电路中第4n-1级移位寄存器中的第三节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第三节点与第4n-1级移位寄存器中的第三节点导通；
    多个第四开关器件，第n个第二开关器件与第二开关控制端、将所述第一栅极驱动电路中第4n-3级移位寄存器中的第四节点、以及所述第 一栅极驱动电路中第4n-1级移位寄存器中的第四节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第四节点与第4n-1级移位寄存器中的第四节点导通；
    所述第二栅极驱动电路还包括：
    多个第五开关器件，第n个第一开关器件与第三开关控制端、所述第二栅极驱动电路中第4n-2级移位寄存器中的第三节点、以及所述第二栅极驱动电路中第4n级移位寄存器中的第三节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第三节点与第4n级移位寄存器中的第三节点导通；
    多个第六开关器件，第n个第二开关器件与第三开关控制端、将所述第二栅极驱动电路中第4n-2级移位寄存器中的第四节点、以及所述第二栅极驱动电路中第4n级移位寄存器中的第四节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第四节点与第4n级移位寄存器中的第四节点导通；
    其中，n为大于等于1的整数，
    其中，所述模式切换电路在接收到第三模式控制信号时，控制所有第三开关器件、所有第四开关器件、所有第五开关器件和所有第六开关器件处于导通状态；控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中的第4n-1级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第4n级移位寄存器的选择控制信号端输出选择控制信号。
  13. 如权利要求10所述的显示面板，其中，所述模式切换电路在接收到第四模式控制信号时，
    控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序与所述第一组时序控制信号中对应信号的时序相同；
    并且控制所述驱动控制电路向所述第一和第二栅极驱动电路中的所有移位寄存器的选择控制信号端均输出选择控制信号。
  14. 一种显示装置，包括如权利要求9-13任一项所述的显示面板。
  15. 一种如权利要求10所述的显示面板的驱动方法，其中，
    当所述模式切换电路接收到第一模式控制信号时，控制所述驱动控制电 路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中与奇数条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号，向所述第二栅极驱动电路中与偶数条栅线连接的移位寄存器的选择控制信号端均输出选择控制信号；
    当所述模式切换电路接收到第四模式控制信号时，控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序与所述第一组时序控制信号中对应信号的时序相同；并且控制所述驱动控制电路向所述第一和第二栅极驱动电路中的所有移位寄存器的选择控制信号端均输出选择控制信号。
  16. 如权利要求15所述的驱动方法，其中，所述第一栅极驱动电路还包括：
    多个第一开关器件，第k个第一开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第三节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第三节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第三节点与第3k级移位寄存器中的第三节点导通；
    多个第二开关器件，第k个第二开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第四节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第四节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第四节点与第3k级移位寄存器中的第四节点导通；其中，k为大于等于1的整数，
    其中，所述驱动方法还包括：
    当所述模式切换电路接收到第一模式控制信号或第四模式控制信号时，控制所述多个第一开关器件和多个第二开关器件处于关闭状态；
    当所述模式切换电路接收到第二模式控制信号时，控制所述多个第一开关器件和多个第二开关器件处于导通状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中的第3k级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第3k-1级移位寄存器的选择控制信号端输出选择控制信号。
  17. 如权利要求15所述的驱动方法，其中，
    所述第一栅极驱动电路还包括：
    多个第三开关器件，第n个第一开关器件与第二开关控制端、所述第一栅极驱动电路中第4n-3级移位寄存器中的第三节点、以及所述第一栅极驱动电路中第4n-1级移位寄存器中的第三节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第三节点与第4n-1级移位寄存器中的第三节点导通；
    多个第四开关器件，第n个第二开关器件与第二开关控制端、将所述第一栅极驱动电路中第4n-3级移位寄存器中的第四节点、以及所述第一栅极驱动电路中第4n-1级移位寄存器中的第四节点相连，并且在所述第二开关控制端的控制下将第4n-3级移位寄存器中的第四节点与第4n-1级移位寄存器中的第四节点导通；
    所述第二栅极驱动电路还包括：
    多个第五开关器件，第n个第一开关器件与第三开关控制端、所述第二栅极驱动电路中第4n-2级移位寄存器中的第三节点、以及所述第二栅极驱动电路中第4n级移位寄存器中的第三节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第三节点与第4n级移位寄存器中的第三节点导通；
    多个第六开关器件，第n个第二开关器件与第三开关控制端、将所述第二栅极驱动电路中第4n-2级移位寄存器中的第四节点、以及所述第二栅极驱动电路中第4n级移位寄存器中的第四节点相连，并且在所述第三开关控制端的控制下将第4n-2级移位寄存器中的第四节点与第4n级移位寄存器中的第四节点导通；其中，n为大于等于1的整数，
    其中，所述驱动方法还包括：
    当所述模式切换电路接收到第一模式控制信号或第四模式控制信号时，控制所述多个第三开关器件、多个第四开关器件、多个第五开关器件和多个第六开关器件处于关闭状态；
    当所述模式切换电路接收到第三模式控制信号时，控制所述多个第三开关器件、多个第四开关器件、多个第五开关器件和多个第六开关器件处于导通状态；控制所述驱动控制电路使所述第一组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且 控制所述驱动控制电路向与所述第一栅极驱动电路中的第4n-1级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第4n级移位寄存器的选择控制信号端输出选择控制信号。
  18. 如权利要求17所述的驱动方法，其中，所述第一栅极驱动电路还包括：
    多个第一开关器件，第k个第一开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第三节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第三节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第三节点与第3k级移位寄存器中的第三节点导通；
    多个第二开关器件，第k个第二开关器件与第一开关控制端、所述第一栅极驱动电路中第3k-2级移位寄存器中的第四节点、以及所述第一栅极驱动电路中第3k级移位寄存器中的第四节点相连，并且在所述第一开关控制端的控制下将第3k-2级移位寄存器中的第四节点与第3k级移位寄存器中的第四节点导通；其中，k为大于等于1的整数，
    其中，所述驱动方法还包括：
    当所述模式切换电路接收到第一模式控制信号或第四模式控制信号时，控制所述多个第一开关器件、多个第二开关器件、多个第三开关器件、多个第四开关器件、多个第五开关器件和多个第六开关器件处于关闭状态；
    当所述模式切换电路接收到第二模式控制信号时，控制所述多个第一开关器件和多个第二开关器件处于导通状态，并且控制所述多个第三开关器件、多个第四开关器件、多个第五开关器件和多个第六开关器件处于关闭状态；控制所述驱动控制电路使所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度；并且控制所述驱动控制电路向所述第一栅极驱动电路中的第3k级移位寄存器的选择控制信号端输出选择控制信号，向所述第二栅极驱动电路中的第3k-1级移位寄存器的选择控制信号端输出选择控制信号；
    当所述模式切换电路接收到第三模式控制信号时，控制所述多个第一开关器件和多个第二开关器件处于关闭状态。
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CN104966506B (zh) 2017-06-06
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US20170178581A1 (en) 2017-06-22
EP3333843A4 (en) 2019-01-23

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