WO2017000621A1 - 栅极驱动电路及其驱动方法、显示装置 - Google Patents

栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2017000621A1
WO2017000621A1 PCT/CN2016/078727 CN2016078727W WO2017000621A1 WO 2017000621 A1 WO2017000621 A1 WO 2017000621A1 CN 2016078727 W CN2016078727 W CN 2016078727W WO 2017000621 A1 WO2017000621 A1 WO 2017000621A1
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Prior art keywords
signal
compensation
voltage
shift register
terminal
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PCT/CN2016/078727
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English (en)
French (fr)
Inventor
马磊
陈希
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/314,405 priority Critical patent/US9875712B2/en
Publication of WO2017000621A1 publication Critical patent/WO2017000621A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present disclosure relates to a gate driving circuit, a driving method thereof, and a display device.
  • Liquid crystal display has the advantages of low radiation, small size and low energy consumption, and is widely used in electronic products such as tablet computers, televisions or mobile phones.
  • the display unit of the liquid crystal display is provided with a pixel unit defined by a plurality of horizontally and vertically intersecting gate lines and data lines.
  • the gate driving circuit can scan the gate lines line by line, and the data driving circuit charges the pixel units through the data lines.
  • the existing gate drive circuit often uses a Gate Driver on Array (GOA) design to integrate a thin film field effect transistor (TFT) gate switch circuit.
  • GOA Gate Driver on Array
  • TFT thin film field effect transistor
  • Such a gate switching circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • the Touch Screen Panel has gradually spread to people's lives. According to the composition of the touch display, it can be divided into: an add on mode touch panel and an incell touch panel. Compared with the external touch display, the in-cell touch display has the advantages of lightness, thinness and low cost because it integrates the touch screen and the display screen.
  • the in-cell touch display uses the principle of mutual capacitance or self-capacitance to detect the touch position of the finger.
  • the mutual capacitance type display screen is provided with mutual capacitances formed by mutually perpendicular touch driving lines (Tx lines) and touch sensing lines (Rx lines).
  • Tx lines mutually perpendicular touch driving lines
  • Rx lines touch sensing lines
  • the human body electric field acts on the mutual capacitance.
  • the capacitance value of the mutual capacitance changes.
  • each drive line can be scanned first, and then the capacitance value of the mutual capacitance interleaved with the drive line is measured to change the capacitance value of the mutual capacitance at a certain point, thereby obtaining the exact contact position.
  • the voltage of the gate of the driving transistor in the GOA circuit is leaked through the transistor connected to the gate, thereby reducing the gate scanning signal outputted by the GOA circuit.
  • the pixel unit is undercharged and there is insufficient dark or bright line.
  • Embodiments of the present disclosure provide a gate driving circuit, a driving method thereof, and a display device, which can solve the problem of prolonging the blanking time and causing insufficient charging of the pixel unit.
  • a gate driving circuit including at least two stages of shift register units, further comprising at least one compensation unit, wherein the compensation unit is disposed between two adjacent shift register units a scan signal output end of the first shift register unit of the two adjacent shift register units is connected to a first signal input end of the compensation unit; a first signal output end of the compensation unit is a reset signal end of the first shift register unit is connected; a scan signal output end of the second shift register unit of the two adjacent shift register units and a second signal input end of the compensation unit Connected to; the second signal output end of the compensation unit is connected to the control signal input end of the second shift register unit; the compensation unit is further connected to at least one compensation voltage terminal, the first voltage terminal and the second voltage The terminal is used to compensate the gate scan signal at the blanking time.
  • the compensation unit is configured to store, at a first moment of the blanking time, a signal of the compensation signal end under the control of the first voltage end, and at a second moment of the blanking time a signal of the compensation signal terminal is output to a reset signal terminal of the first shift register unit; a signal of the compensation signal terminal is output to a control signal of the second shift register unit at a third timing of the blanking time Input; or reset under the control of the second voltage terminal.
  • the compensation unit includes a control module, a reset module, and a voltage hold module; the control module is respectively connected to the reset module, the voltage hold module, the first signal input end, and the first voltage end, Outputting the voltage of the first voltage terminal to the voltage holding module under control of the first signal input terminal; the reset module further connecting the voltage holding module, the second signal input end, the Second voltage terminal for use in Controlling, by the second signal input terminal, a voltage of the second voltage terminal to the voltage holding module to reset the voltage holding module; the voltage holding module further connecting at least one of the compensation voltage terminals, The first signal output end and the second signal output end are configured to store the signal of the compensation signal end and output to the first signal output end or the second signal output end.
  • control module includes: a first transistor having a gate connected to the first signal input terminal, a first pole connected to the first voltage terminal, a second pole connected to the reset module, and the voltage holding The modules are connected.
  • the reset module includes: a second transistor having a gate connected to the second signal input terminal, a first pole connected to the second voltage terminal, a second pole connected to the control module, and the voltage The modules are connected.
  • the compensation voltage terminal includes a first compensation voltage terminal and a second compensation voltage terminal
  • the voltage holding module includes: a third transistor, a fourth transistor, a first capacitor, and a second capacitor; and the third transistor a gate connected to the control module, the reset module, a first pole connected to the first compensation voltage terminal, a second pole connected to the first signal output terminal, and a gate connection of the fourth transistor a control module, the reset module, a first pole connected to the second compensation voltage terminal, and a second pole connected to the second signal output terminal; one end of the first capacitor and a gate of the third transistor The other end is connected to the second pole of the third transistor; the second end of the second capacitor is connected to the gate of the fourth transistor, and the other end is connected to the second pole of the fourth transistor.
  • the compensation voltage terminal includes a first compensation voltage terminal and a second compensation voltage terminal
  • the voltage holding module includes: a fifth transistor, a sixth transistor, and a third capacitor; and a gate connection of the fifth transistor
  • the control module and the reset module have a first pole connected to the first compensation voltage terminal, a second pole connected to the first signal output end, and a gate of the sixth transistor connected to the control module
  • the reset module has a first pole connected to the second compensation voltage terminal and a second pole connected to the second signal output terminal; one end of the third capacitor is connected to the fifth transistor and the sixth transistor The gate is grounded at the other end.
  • the compensation voltage terminal includes a third compensation voltage terminal;
  • the voltage holding module includes: a seventh transistor and a fourth capacitor; a gate of the seventh transistor is connected to the control module, the reset module, a first pole is connected to the third compensation voltage terminal, a second pole is connected to the first signal output end and the second signal output end; and one end of the fourth capacitor The gate of the seventh transistor is connected, and the other end is connected to the second pole of the seventh transistor.
  • a display device comprising any one of the gate drive circuits as described above.
  • a driving method for driving any one of the above gate driving circuits including: in a first stage, a scan signal output end of the first shift register unit outputs a gate scan signal
  • the compensation unit receives the gate scan signal; in the second stage, under the control of the first voltage terminal, the compensation unit stores the signal of the compensation voltage terminal at the first moment of the blanking time, at the blanking time At a second time, the compensation unit outputs a signal of the compensation voltage terminal to a reset signal end of the first shift register unit; at a third timing of the blanking time, the compensation unit signals the compensation voltage terminal Outputting to a control signal input terminal of the second shift register unit; in a third stage, the scan signal output end of the second shift register unit outputs a gate scan signal; the compensation unit receives the gate scan signal, The reset is performed under the control of the second voltage terminal.
  • the compensation unit comprises a control module, a reset module and a voltage hold module; in the second phase, under the control of the first voltage end, the compensation unit will compensate the signal of the voltage end at the first moment of the blanking time Performing storage, at a second timing of the blanking time, the compensation unit outputs a signal of the compensation voltage terminal to a reset signal end of the first shift register unit; at a third moment of the blanking time
  • the control unit outputs a signal of the compensation voltage terminal to the control signal input end of the second shift register unit, including: a first signal input end input signal, the control module is turned on, and the voltage of the first voltage end is output to the a voltage holding module; the compensation voltage terminal input signal, the voltage holding module stores the signal of the compensation signal end, and outputs the signal to the first signal output end or the second signal output end; the second signal input end input signal
  • the reset module is turned on, and the voltage of the second voltage terminal is output to the voltage holding module to maintain the voltage Block reset.
  • Embodiments of the present disclosure provide a gate driving circuit, a driving method thereof, and a display device.
  • the gate driving circuit includes at least two stages of shift register units, and further includes at least one compensation unit, wherein the compensation unit is disposed at two adjacent Between the shift register units.
  • the scan signal output end of the first shift register unit of the two adjacent shift register units is connected to the first signal input end of the compensation unit; the first signal output end of the compensation unit and the first shift register The reset signal terminals of the unit are connected; the scan signal output end of the second shift register unit of the two adjacent shift register units is connected to the second signal input end of the compensation unit The second signal output end of the compensation unit is connected to the control signal input end of the second shift register unit; the compensation unit is further connected to the compensation voltage terminal, the first voltage terminal and the second voltage terminal for the first Under the control of the voltage terminal, the signal of the compensation signal terminal is stored at a first moment of the blanking time, and the signal of the compensation signal terminal is output to the first shift register unit at a second timing of the blanking time a reset signal terminal; outputting the signal of the compensation signal terminal to the control signal input terminal of the second shift register unit at a third timing of the blanking time; or performing resetting under the control of the second voltage terminal.
  • the compensation unit can receive the signal input by the scan signal output end of the first shift register unit, and store the signal of the compensation voltage terminal under the control of the first voltage terminal, and output the signal of the compensation voltage terminal to the first The reset signal terminal of the one-stage shift register, so that the first shift register unit can be reset.
  • the compensation unit may also output a signal of the compensation voltage terminal to the control signal input end of the second shift register unit at the blanking time, so that the second shift register unit can output the gate scan signal to the gate line connected thereto. .
  • the compensation unit Since the compensation unit is at the blanking time, the voltage supplied from the compensation voltage terminal is output to the second shift register unit, so that the gate scan signal reduced by the blanking time can be compensated, thereby being able to avoid the clock signal due to The blanking time increases, resulting in insufficient pixel charging.
  • the compensation unit can be reset by the second voltage terminal to prevent the residual signal of the frame from adversely affecting the next frame.
  • Figure 1 is a timing diagram of a known clock signal
  • FIG. 2 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural view of the compensation unit of FIG. 2;
  • FIG. 4 is a schematic diagram of a specific structure of each module in the compensation unit of FIG. 3;
  • Figure 5a is a signal timing diagram for controlling the compensation unit shown in Figure 4.
  • Figure 5b is another signal timing diagram for controlling the compensation unit shown in Figure 4.
  • FIG. 6 is another schematic structural diagram of each module in the compensation unit of FIG. 3;
  • FIG. 7 is a schematic diagram showing still another specific structure of each module in the compensation unit of FIG. 3;
  • Figure 8 is a signal timing diagram for controlling the compensation unit shown in Figure 7;
  • FIG. 9 is a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • Figure 1 shows a timing diagram of a known clock signal. As shown in FIG. 1, after the end of one frame scan, the clock signal CLK of the GOA circuit has a blanking time. Therefore, the blanking time can be used as the scan time of the touch driving line (Tx lines). .
  • FIG. 2 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit may include at least two stages of shift register units, and further includes at least one compensation unit 100 disposed between two adjacent shift register units.
  • the two adjacent shift register units may be any two adjacent shift register units in the GOA circuit, such as the first stage shift register unit RS1 and the second stage shift register unit RS2 as shown in FIG. . Or it may be the penultimate stage shift register unit RSn-1 and the last stage shift register unit RSn, n being an integer greater than or equal to 2.
  • the two adjacent shift register units are referred to as a first shift register unit and a second shift register unit, and in the embodiment of the present disclosure, the first level shift is as shown in FIG.
  • the bit register unit RS1 is taken as a first shift register unit
  • the second stage shift register unit RS2 is taken as an example of a second shift register unit.
  • the scan signal output terminal OUTPUT of the first shift register unit RS1 of the two adjacent shift register units is connected to the first signal input terminal In1 of the compensation unit 100.
  • the first signal output terminal O1 of the compensation unit 100 is connected to the reset signal terminal RESET of the first shift register unit RS1.
  • the scan signal output terminal OUTPUT of the second shift register unit RS2 of the two adjacent shift register units is connected to the second signal input terminal In2 of the compensation unit 100.
  • the second signal output terminal O2 of the compensation unit 100 is connected to the control signal input terminal INPUT of the second shift register unit RS2.
  • the compensation unit 100 is further connected to at least one compensation voltage terminal PRE, a first voltage terminal VDD and a second voltage terminal VSS for controlling the first voltage terminal VDD, as shown in FIG. 5a, at a blanking time (Blanking Time).
  • the first time T1 stores the signal of the compensation signal terminal PRE; at the second time T2 of the blanking time, the compensation signal end
  • the signal of the PRE is output to the reset signal terminal RESET of the first shift register unit RS1; the signal of the compensation signal terminal PRE is output to the control signal of the second shift register unit RS2 at the third timing T3 of the blanking time (Blanking Time)
  • the input terminal INPUT or under the control of the second voltage terminal VSS, reset.
  • the first embodiment of the present disclosure is an example in which the first voltage terminal VDD is input to the high level, and the second voltage terminal VSS is input to the low level.
  • the embodiment of the present disclosure does not limit the internal structure of the shift register unit, as long as the gate scan signal can be input to the gate line in the display panel, so that the gate circuit composed of the shift register unit can be displayed. All raster lines on the panel can be progressively scanned.
  • the structure of the shift register unit is different, and the number of clock signals CLK connected thereto is also different.
  • the present disclosure does not limit the number of clock signals CLK.
  • the description is made by taking one clock signal CLK as an example.
  • the number of the compensation unit 100 is not limited in the embodiment of the present disclosure, and the compensation unit 100 may be disposed between each adjacent two shift register units. In this way, the gate scan signal outputted by each stage of the shift register unit except the first stage can be compensated by the compensation unit 100.
  • the above-described compensation unit 100 may not be provided.
  • the scan signal output terminal OUTPUT and the next-stage shift register unit of the shift register unit of the previous stage may be The control signal input terminal INPUT.
  • the scan signal output terminal OUTPUT of the shift register unit RSn-1 is connected to the control signal input terminal INPUT of the shift register unit RSn.
  • the scan signal output terminal OUTPUT of the shift register unit of the next stage is connected to the reset signal terminal RESET of the shift register unit of the previous stage, for example, the scan signal output terminal OUTPUT of the shift register unit RSn and the shift register unit RSn-1
  • the reset signal terminal RESET is connected.
  • a gate driving circuit provided by an embodiment of the present disclosure includes at least two stages of shift register units, and further includes at least one compensation unit, wherein the compensation unit is disposed between two adjacent shift register units.
  • the scan signal output end of the first shift register unit of the two adjacent shift register units is connected to the first signal input end of the compensation unit; the first of the compensation unit The signal output end is connected to the reset signal end of the first shift register unit; the scan signal output end of the second shift register unit of the two adjacent shift register units is connected to the second signal input end of the compensation unit
  • the second signal output end of the compensation unit is connected to the control signal input end of the second shift register unit;
  • the compensation unit is further connected to the compensation voltage terminal, the first voltage terminal and the second voltage terminal for the first voltage Controlling, at the first moment of the blanking time, the signal of the compensation signal end is stored, and outputting the signal of the compensation signal end to the first shift register unit at the second timing of the blanking time And resetting the signal end; outputting the signal of the compensation signal end to the control
  • the compensation unit can receive the signal input by the scan signal output end of the first shift register unit, and store the signal of the compensation voltage terminal under the control of the first voltage terminal, and output the signal of the compensation voltage terminal to the first The reset signal terminal of the one-stage shift register, so that the first shift register unit can be reset.
  • the compensation unit may also output a signal of the compensation voltage terminal to the control signal input end of the second shift register unit at the blanking time, so that the second shift register unit can output the gate scan signal to the gate line connected thereto. .
  • the compensation unit Since the compensation unit is at the blanking time, the voltage supplied from the compensation voltage terminal is output to the second shift register unit, so that the gate scan signal reduced by the blanking time can be compensated, thereby being able to avoid the clock signal due to The blanking time increases, resulting in insufficient pixel charging.
  • the compensation unit can be reset by the second voltage terminal to prevent the residual signal of the frame from adversely affecting the next frame.
  • FIG. 3 shows a schematic structural view of the compensation unit 100 shown in FIG. 2.
  • the compensation module 100 may include a control module 1001 , a reset module 1002 , and a voltage hold module 1003 .
  • the control module 1001 is respectively connected to the reset module 1002, the voltage holding module 1003, the first signal input terminal In1, and the first voltage terminal VDD for controlling the first voltage terminal VDD under the control of In1 of the first signal input terminal.
  • the voltage is output to the voltage hold module 1003.
  • the reset module 1002 is further connected to the voltage holding module 1003, the second signal input terminal In2, and the second voltage terminal VSS for outputting the voltage of the second voltage terminal VSS to the voltage holding module 1003 under the control of the second signal input terminal In2. To reset the voltage hold module 1003.
  • the voltage holding module 1003 is further connected to at least one compensation voltage terminal PRE, a first signal output terminal O1, and a second signal output terminal O2 for storing the signal of the compensation signal terminal PRE and outputting to the first signal output terminal O1 or the first Two signal output terminals O2.
  • the voltage of the first voltage terminal VDD can be output to the voltage holding module 1003 through the control module 1001, so that the voltage holding module 1003 is turned on, and the signal of the compensation signal terminal PRE is stored and output to the first signal.
  • the output terminal O1 or the second signal output terminal O2 is configured to reset the first shift register unit RS1 connected to the first signal output terminal O1, and the second shift register unit RS2 connected to the second signal output terminal O2
  • the gate scan signal can be outputted to the gate line connected thereto, and the second signal output terminal O2 can supply the signal of the compensation signal terminal PRE stored by the voltage holding module 1003 to the second shift register unit RS2, thereby scanning the gate
  • the signal is compensated, so that the pixel charging is insufficient due to an increase in the blanking time of the clock signal.
  • the voltage holding module 1003 can also be reset by the reset module 1002, thereby preventing the signal remaining in the frame from adversely affecting the next frame.
  • each module in the above compensation unit 100 will be exemplified in detail by way of specific embodiments.
  • FIG. 4 is a schematic diagram showing a specific structure of each module in the compensation unit 100 shown in FIG.
  • the control module 1001 may include: a first transistor M1 having a gate connected to the first signal input terminal In1, a first pole connected to the first voltage terminal VDD, a second pole and a reset module 1002, and a voltage holding module 1003. Connected.
  • the reset module 1002 may include a second transistor M2 having a gate connected to the second signal input terminal In2, a first pole connected to the second voltage terminal VSS, and a second pole connected to the control module 1001 and the voltage holding module 1003.
  • the compensation voltage terminal PRE includes a first compensation voltage terminal PRE1 and a second compensation voltage terminal PRE2.
  • the voltage holding module 1003 may include a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2.
  • the gate of the third transistor M3 is connected to the control module 1001 and the reset module 1002.
  • the first pole is connected to the first compensation voltage terminal PRE1, and the second pole is connected to the first signal output terminal O1.
  • the gate of the third transistor M3 is connected to the second poles of the first transistor M1 and the second transistor M2.
  • the gate of the fourth transistor M4 is connected to the control module 1001 and the reset module 1002.
  • the first pole is connected to the second compensation voltage terminal PRE2, and the second pole is connected to the second signal output terminal O2.
  • the gate of the fourth transistor M4 is connected to the second poles of the first transistor M1 and the second transistor M2.
  • One end of the first capacitor C1 is connected to the gate of the third transistor M3, and the other end is connected to the second pole of the third transistor M3.
  • One end of the second capacitor C2 is connected to the gate of the fourth transistor M4, and the other end is connected to the second pole of the fourth transistor M4.
  • Fig. 5a shows a signal timing diagram for controlling the compensation unit shown in Fig. 4.
  • the blanking time of the clock signal is outputted at the clock signal terminal CLK, and the touch operation can be performed.
  • the compensation unit 100 can compensate the gate scan signal outputted by the shift register unit in the above Blanking Time as follows:
  • the first signal input terminal In1 of the compensation unit 100 receives the first shift register unit RS1 outputting the gate scan signal G1 as shown in FIG. 2, and the gate scan signal G1 passes through the compensation unit.
  • the first signal input terminal In1 of 100 is input to the gate of the first transistor M1, and the first transistor M1 is turned on, and the voltage signal of the first voltage terminal VDD is output to the node a such that the voltage Va of the node a is VDD.
  • the third transistor M3 and the fourth transistor M4 are turned on, and the first capacitor C1 and the second capacitor C2 store the voltage signal of the first voltage terminal VDD.
  • the signal input from the first compensation voltage terminal PRE1 is output to the first signal output terminal O1 through the third transistor M3.
  • the signal input from the second compensation voltage terminal PRE2 is output to the second signal output terminal O2 through the fourth transistor M4.
  • the second signal output terminal O2 and the second shift register The control signal input terminal INPUT of the unit RS2 is connected.
  • the second shift register unit RS2 starts to work, the signal input by the second compensation voltage terminal PRE2 can be output to the second shift register unit RS2 through the second signal output terminal O2.
  • the fourth transistor M4 in the Blanking Time of the clock signal, the fourth transistor M4 can remain in an on state, and the signal input by the second compensation voltage terminal PRE2 passes through the second signal output terminal O2 and continues to be output to the second shift register unit RS2.
  • Control signal input INPUT In this way, even if the clocking time of the clock signal is extended in order to ensure the response time of the touch signal, in the blanking time, the second signal output terminal O2 of the compensation unit 100 can continue to the shift register unit connected thereto.
  • the present disclosure can compensate the unit by inputting a signal to the control signal input terminal INPUT of the shift register unit connected thereto by the compensation unit 100 to compensate the gate scan signal outputted by the shift register unit, thereby avoiding the pixel. Insufficient charging.
  • the scan signal output terminal OUTPUT of the second shift register unit RS2 is coupled to the second signal input terminal In2 of the compensation unit 100. Connecting, so that the second transistor M2 can be turned on, so that the voltage signal of the second voltage terminal VSS is output to the node a, thereby discharging the first capacitor C1 and the second capacitor C2, and avoiding the residual voltage signal to the next frame. Have a bad influence.
  • the first and the above are only described by taking a clock signal terminal CLK in the GOA circuit as an example. Since the number of clock signal terminals used in the embodiment of the present disclosure is not limited, when multiple clock signal terminals are used, for example, as shown in FIG. 5b, four clock signal terminals are used, and clock signals CLK1, CLK2, and CLK3 are respectively output. CLK4 In this case, the first compensation voltage terminal PRE1 starts to input signals after all clock signals enter the Blanking Time, and the second compensation voltage terminal PRE2 ends the Blanking Time first among all the clock signals. Start the input signal before the moment.
  • the transistors in this embodiment are all described by taking an N-type transistor as an example.
  • the signal shown in FIG. 5a and FIG. 5b needs to be inverted, and in the circuit structure diagram shown in FIG. 4, the transistor connected to the first voltage terminal VDD is connected to the second voltage terminal VSS.
  • the transistor connected to the second voltage terminal VSS is connected to the first voltage terminal VDD.
  • the transistors in the following embodiments are all described by taking an N-type transistor as an example. When a P-type transistor is used, the setting is the same as described above.
  • FIG. 6 is a schematic diagram showing another specific structure of each module in the compensation unit 100 shown in FIG. This embodiment has the same structure as the control module 1001 and the reset module 1002 provided by the first embodiment.
  • the compensation voltage terminal includes a first compensation voltage terminal PRE1 and a second compensation voltage terminal PRE2.
  • the voltage holding module 1003, as shown in FIG. 6, may include a fifth transistor M5, a sixth transistor M6, and a third capacitor C3.
  • the gate of the fifth transistor M5 is connected to the control module 1001 and the reset module 1002.
  • the first pole is connected to the first compensation voltage terminal PRE1, and the second pole is connected to the first signal output terminal O1.
  • the gate of the fifth transistor M5 is connected to the second poles of the first transistor M1 and the second transistor M2.
  • the gate of the sixth transistor M6 is connected to the control module 1001 and the reset module 1002.
  • the first pole is connected to the second compensation voltage terminal PRE2, and the second pole is connected to the second signal output terminal O2.
  • the gate of the sixth transistor M6 is connected to the second poles of the first transistor M1 and the second transistor M2.
  • One end of the third capacitor C3 is connected to the gates of the fifth transistor M5 and the sixth transistor M6, and the other end is grounded.
  • a storage capacitor that is, a third capacitor C3 is used.
  • the first transistor M1 When the first transistor M1 is turned on, the voltage input from the first voltage terminal VDD can be stored, which can make compensation.
  • the sixth transistor M6 can remain turned on in the Blanking Time of the clock signal.
  • the signal input by the second compensation voltage terminal PRE2 is continuously outputted to the control signal input terminal INPUT of the second shift register unit RS2 through the second signal output terminal O2.
  • FIG. 7 is a schematic diagram showing still another specific structure of each module in the compensation unit 100 shown in FIG.
  • the embodiment has the same structure as the control module 1001 and the reset module 1002 provided by the first embodiment, except that it includes a compensation voltage terminal, that is, a third compensation voltage terminal PRE3; and the voltage holding module 1003 is as shown in FIG.
  • the seventh transistor M7 and the fourth capacitor C4 may be included.
  • the gate of the seventh transistor M7 is connected to the control module 1001 and the reset module 1002.
  • the first pole is connected to the third compensation voltage terminal PRE3, and the second pole is connected to the first signal output terminal O1 and the second signal output terminal O2.
  • the gate of the seventh transistor M7 is connected to the second poles of the first transistor M1 and the second transistor M2.
  • One end of the fourth capacitor C4 is connected to the gate of the seventh transistor M7, and the other end is connected to the second pole of the seventh transistor M7.
  • Fig. 8 shows a signal timing chart for controlling the compensation unit shown in Fig. 7.
  • the signal input by the third compensation voltage terminal PRE3 is as shown in FIG. 8.
  • the specific working process of the compensation unit 100 is:
  • the first signal input terminal In1 of the compensation unit 100 receives the first shift register unit RS1 outputting the gate scan signal G1 as shown in FIG. 2, and the gate scan signal G1 passes through the compensation unit.
  • the first signal input terminal In1 of 100 is input to the gate of the first transistor M1, and the first transistor M1 is turned on, and the voltage signal of the first voltage terminal VDD is output to the node a such that the voltage Va of the node a is VDD.
  • the seventh transistor M7 is turned on, and the fourth capacitor C4 stores the voltage signal of the first voltage terminal VDD.
  • the signal input by the third compensation voltage terminal PRE3 is output to the first signal output terminal O1 through the seventh transistor M7.
  • the signal input from the third compensation voltage terminal PRE3 is output to the second signal output terminal O2 through the seventh transistor M7.
  • the second signal output terminal O2 is connected to the control signal input terminal INPUT of the second shift register unit RS2, and when the second shift register unit RS2 starts to operate, the third compensation voltage terminal
  • the signal input by PRE3 can be output to the second shift register unit RS2 through the second signal output terminal O2, so that the second shift register unit RS2 outputs a gate scan signal to the gate line connected thereto.
  • the seventh transistor M7 in the Blanking Time of the clock signal, the seventh transistor M7 can remain in an on state, and the signal input from the third compensation voltage terminal PRE3 passes through the second signal output terminal O2 and continues to be output to the second shift register unit RS2. Control signal input INPUT.
  • the structure of the third embodiment shown in FIG. 7 is simpler, and thus it is advantageous to reduce power consumption and space occupied by the circuit.
  • Another aspect of an embodiment of the present disclosure provides a display device including any of the above-described gate driving circuits having the same structure and advantageous effects as the gate driving circuit provided in the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • the display device may specifically include a liquid crystal display device, for example, the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • FIG. 9 is a flow chart showing a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • a driving method of a gate driving circuit provided by an embodiment of the present disclosure may include the following working processes:
  • step S101 in the first stage P1 shown in FIG. 5a, the scan signal output terminal OUTPUT of the first shift register unit RS1 outputs the gate scan signal G1, and the compensation unit 100 receives the gate through the first signal input terminal In1.
  • step S102 in the second phase P2 (ie, Blanking Time), at the first voltage Under the control of the terminal VDD, the compensation unit 100 stores the signal of the compensation voltage terminal PRE at the first time T1 of the blanking time; at the second time T2 of the blanking time, the compensation unit 100 outputs the signal of the compensation voltage terminal PRE to The reset signal terminal RESET of the first shift register unit RS1; at the third timing T3 of the blanking time, the compensation unit 100 outputs a signal of the compensation voltage terminal PRE to the control signal input terminal INPUT of the second shift register unit RS2. Thereby, the compensation unit can output the voltage provided by the compensation voltage terminal to the second shift register unit at the blanking time to compensate the gate scan signal.
  • Blanking Time Blanking Time
  • step S103 in the third phase P3, the scan signal output terminal OUTPUT of the second shift register unit RS2 outputs the gate scan signal G2.
  • the compensation unit 100 receives the gate scan signal G2 and performs reset under the control of the second voltage terminal VSS. To avoid the residual signal of the frame, it will have an adverse effect on the next frame.
  • the driving method of the gate driving circuit includes: first, the first stage, the scan signal output end of the first shift register unit outputs a gate scan signal, and the compensation unit receives the gate scan signal; next, the second In the stage, under the control of the first voltage end, the compensation unit stores the signal of the compensation voltage terminal at the first moment of the blanking time; the compensation unit outputs the signal of the compensation voltage terminal to the first shift at the second moment of the blanking time a reset signal terminal of the register unit; at a third timing of the blanking time, the compensation unit outputs a signal of the compensation voltage terminal to a control signal input terminal of the second shift register unit; finally, a scan signal output terminal of the second shift register unit And outputting a gate scan signal; the compensation unit receives the gate scan signal and performs reset under the control of the second voltage terminal.
  • the compensation unit can receive the signal input by the scan signal output end of the first shift register unit, and store the signal of the compensation voltage terminal under the control of the first voltage terminal, and output the signal of the compensation voltage terminal to the first The reset signal terminal of the one-stage shift register, so that the first shift register unit can be reset.
  • the compensation unit may also output a signal of the compensation voltage terminal to the control signal input end of the second shift register unit at the blanking time, so that the second shift register unit can output the gate scan signal to the gate line connected thereto. .
  • the compensation unit Since the compensation unit is at the blanking time, the voltage supplied from the compensation voltage terminal is output to the second shift register unit, so that the gate scan signal reduced by the blanking time can be compensated, thereby being able to avoid the clock signal due to The blanking time increases, resulting in insufficient pixel charging.
  • the compensation unit can be reset by the second voltage terminal to prevent the residual signal of the frame from adversely affecting the next frame.
  • the above step S102 may include:
  • the first signal input terminal In1 inputs a signal, and the control module 1001 is turned on to output the voltage of the first voltage terminal VDD to the voltage holding module 1003.
  • the first signal input terminal In1 of the compensation unit 100 receives the first shift register unit RS1 output gate as shown in FIG. 2.
  • the gate scan signal G1 is input to the gate of the first transistor M1 through the first signal input terminal In1 of the compensation unit 100, and the first transistor M1 is turned on, and the voltage of the first voltage terminal VDD is turned on.
  • the third transistor M3 and the fourth transistor M4 are turned on, and the first capacitor C1 and the second capacitor C2 store the voltage signal of the first voltage terminal VDD.
  • the voltage terminal PRE input signal is compensated, and the voltage holding module 1003 stores the signal of the compensation signal terminal PRE and outputs it to the first signal output terminal O1 or the second signal output terminal O2.
  • the signal input by the first compensation voltage terminal PRE1 is output to the first signal output terminal O1 through the third transistor M3.
  • the first signal input terminal O1 is connected to the reset signal terminal RESET of the first shift register unit RS1, and when the shift register unit RS1 starts to operate, the first signal The signal output from the input terminal O1 can reset the first shift register unit RS1.
  • the signal input from the second compensation voltage terminal PRE2 is output to the second signal output terminal O2 through the fourth transistor M4.
  • the second signal output terminal O2 is connected to the control signal input terminal INPUT of the second shift register unit RS2, and when the second shift register unit RS2 starts operating, the second compensation voltage terminal
  • the signal input by PRE2 can be output to the second shift register unit RS2 through the second signal output terminal O2, so that the second shift register unit RS2 outputs a gate scan signal to the gate line connected thereto.
  • the second signal input terminal In2 inputs a signal
  • the reset module 1002 is turned on
  • the voltage of the second voltage terminal VSS is output to the voltage holding module 1003 to the voltage holding module 1003. Reset.
  • the scan signal output terminal OUTPUT of the second shift register unit RS2 is coupled to the second signal input terminal In2 of the compensation unit 100. Connecting, so that the second transistor M2 can be turned on, so that the voltage signal of the second voltage terminal VSS is output to the node a, thereby discharging the first capacitor C1 and the second capacitor C2, and avoiding the residual voltage signal to the next frame. Have a bad influence.

Abstract

一种栅极驱动电路及其驱动方法、显示装置。栅极驱动电路包括至少两级移位寄存器单元，还包括至少一个补偿单元（100），补偿单元（100）设置于两个相邻的移位寄存器单元之间；第一移位寄存器单元（RS1）的扫描信号输出端（OUTPUT）与补偿单元（100）的第一信号输入端（In1）相连接；补偿单元（100）的第一信号输出端（O1）与第一移位寄存器单元（RS1）的复位信号端（RESET）相连接，第二移位寄存器单元（RS2）的扫描信号输出端（OUTPUT）与补偿单元（100）的第二信号输入端（In2）相连接，补偿单元（100）的第二信号输出端（O2）与第二移位寄存器单元（RS2）的控制信号输入端（INPUT）相连接；补偿单元（100）还连接至少一个补偿电压端（PRE）、第一电压端（VDD）以及第二电压端（VSS）。用于在消隐时间（P2）对栅极扫描信号进行补偿，能够避免由于时钟信号消隐时间（P2）增加导致像素充电不足的现象。

Description

栅极驱动电路及其驱动方法、显示装置 技术领域
本公开涉及一种栅极驱动电路及其驱动方法、显示装置。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有低辐射、体积小及低耗能等优点，被广泛地应用在平板电脑、电视或手机等电子产品中。液晶显示器的显示屏上设置有由多条横纵交叉的栅线和数据线界定而成的像素单元。在显示过程中，栅极驱动电路可以逐行对栅线进行扫描，数据驱动电路通过数据线对像素单元进行充电。
为了进一步降低液晶显示器产品的生产成本，现有的栅极驱动电路常采用阵列基板行驱动(Gate Driver on Array，GOA)设计将薄膜场效应晶体管(Thin Film Transistor，TFT)栅极开关电路集成在显示面板的阵列基板上。这种利用GOA技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路。
此外，触控显示屏(Touch Screen Panel)也逐渐遍及至人们的生活中。触控显示屏按照组成结构可以分为：外挂式触控显示屏(Add on Mode Touch Panel)、以及内嵌式触控显示屏(In Cell Touch Panel)。相对于外挂式触控显示屏而言，内嵌式触控显示屏由于是将触摸屏与显示屏集成于一体，因此具有轻、薄以及成本低等优点。
通常，内嵌式触控显示屏是利用互电容或自电容的原理实现检测手指触摸位置。具体地，互电容式显示屏中设置有由相互垂直的触控驱动线(Tx lines)和触控感应线(Rx lines)构成的互电容，在触控的过程中，人体电场作用在互电容上，使互电容的电容值发生变化。具体的触控信号的采集，可以先依次扫描每一条驱动线，然后测量与这条驱动线交错的感应线是否在某点的互电容的电容值发生变化，从而获得确切的触点位置。
对于已知的触控显示装置而言，当位于相同行的栅线和触控驱动线(Tx lines)同时扫描时会互相干扰，所以栅线的扫描和触控驱动线(Tx lines)的扫描过程通常都是分时进行。然而，随着显示装置分辨率的不 断提高，上述消隐时间会被压缩，这样一来会导致触控驱动线(Tx lines)的扫描时间缩小，使得触控信号的响应时间不足，从而降低了触控显示屏的响应速度和灵敏度。如果为了保证上述触控信号的响应时间而延长消隐时间，则会导致GOA电路中驱动晶体管栅极的电压通过与该栅极相连的晶体管漏电，从而降低了GOA电路输出的栅极扫描信号，导致像素单元充电不足，出现暗线或亮线不足。
发明内容
本公开的实施例提供一种栅极驱动电路及其驱动方法、显示装置，能够解决延长消隐时间，导致像素单元充电不足的问题。
本公开实施例的一方面，提供一种栅极驱动电路，包括至少两级移位寄存器单元，还包括至少一个补偿单元，其中所述补偿单元设置于两个相邻的移位寄存器单元之间；所述两个相邻的移位寄存器单元中的第一移位寄存器单元的扫描信号输出端与所述补偿单元的第一信号输入端相连接；所述补偿单元的第一信号输出端与所述第一移位寄存器单元的复位信号端相连接；所述两个相邻的移位寄存器单元中的第二移位寄存器单元的扫描信号输出端与所述补偿单元的第二信号输入端相连接；所述补偿单元的第二信号输出端与所述第二移位寄存器单元的控制信号输入端相连接；所述补偿单元还连接至少一个补偿电压端、第一电压端以及第二电压端，用于在消隐时间对栅极扫描信号进行补偿。
可选择地，所述补偿单元用于在所述第一电压端的控制下，在消隐时间的第一时刻将所述补偿信号端的信号进行存储，在所述消隐时间的第二时刻将所述补偿信号端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻将所述补偿信号端的信号输出至所述第二移位寄存器单元的控制信号输入端；或者在所述第二电压端的控制下，进行复位。
可选择地，所述补偿单元包括控制模块、复位模块以及电压保持模块；所述控制模块分别与复位模块、电压保持模块、所述第一信号输入端、所述第一电压端相连接，用于在所述第一信号输入端的控制下，将所述第一电压端的电压输出至所述电压保持模块；所述复位模块还连接所述电压保持模块、所述第二信号输入端、所述第二电压端，用于在所 述第二信号输入端的控制下，将所述第二电压端的电压输出至所述电压保持模块，以对所述电压保持模块进行复位；所述电压保持模块还连接至少一个所述补偿电压端、所述第一信号输出端、所述第二信号输出端，用于将所述补偿信号端的信号进行存储，并输出至所述第一信号输出端或所述第二信号输出端。
可选择地，所述控制模块包括：第一晶体管，其栅极连接所述第一信号输入端，第一极连接所述第一电压端，第二极与所述复位模块、所述电压保持模块相连接。
可选择地，所述复位模块包括：第二晶体管，其栅极连接所述第二信号输入端，第一极连接所述第二电压端，第二极与所述控制模块、所述电压保持模块相连接。
可选择地，所述补偿电压端包括第一补偿电压端、第二补偿电压端；所述电压保持模块包括：第三晶体管、第四晶体管、第一电容以及第二电容；所述第三晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第一补偿电压端相连接，第二极连接所述第一信号输出端；所述第四晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第二补偿电压端相连接，第二极连接所述第二信号输出端；所述第一电容的一端与所述第三晶体管的栅极相连接，另一端连接所述第三晶体管的第二极；所述第二电容的一端与所述第四晶体管的栅极相连接，另一端连接所述第四晶体管的第二极。
可选择地，所述补偿电压端包括第一补偿电压端、第二补偿电压端；所述电压保持模块包括：第五晶体管、第六晶体管以及第三电容；所述第五晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第一补偿电压端相连接，第二极连接所述第一信号输出端；所述第六晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第二补偿电压端相连接，第二极连接所述第二信号输出端；所述第三电容的一端连接所述第五晶体管和所述第六晶体管的栅极，另一端接地。
可选择地，所述补偿电压端包括第三补偿电压端；所述电压保持模块包括：第七晶体管以及第四电容；所述第七晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第三补偿电压端相连接，第二极连接所述第一信号输出端和所述第二信号输出端；所述第四电容的一端 连接所述第七晶体管的栅极，另一端连接所述第七晶体管的第二极。
本公开实施例的另一方面，提供一种显示装置包括如上所述的任意一种栅极驱动电路。
本公开实施例提的又一方面，提供一种用于驱动上述任意一种栅极驱动电路的驱动方法，包括：第一阶段，第一移位寄存器单元的扫描信号输出端输出栅极扫描信号，补偿单元接收所述栅极扫描信号；第二阶段，在第一电压端的控制下，在消隐时间的第一时刻所述补偿单元将补偿电压端的信号进行存储，在所述消隐时间的第二时刻所述补偿单元将所述补偿电压端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻所述补偿单元将所述补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端；第三阶段，所述第二移位寄存器单元的扫描信号输出端输出栅极扫描信号；所述补偿单元接收所述栅极扫描信号，在第二电压端的控制下进行复位。
可选择地，所述补偿单元包括控制模块、复位模块以及电压保持模块；所述第二阶段，在第一电压端的控制下，在消隐时间的第一时刻所述补偿单元将补偿电压端的信号进行存储，在所述消隐时间的第二时刻所述补偿单元将所述补偿电压端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻所述补偿单元将所述补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端包括：第一信号输入端输入信号，所述控制模块开启，将所述第一电压端的电压输出至所述电压保持模块；所述补偿电压端输入信号，所述电压保持模块将所述补偿信号端的信号进行存储，并输出至第一信号输出端或第二信号输出端；第二信号输入端输入信号，所述复位模块开启，将所述第二电压端的电压输出至所述电压保持模块，以对所述电压保持模块进行复位。
本公开实施例提供一种栅极驱动电路及其驱动方法、显示装置，所述栅极驱动电路包括至少两级移位寄存器单元，还包括至少一个补偿单元，其中补偿单元设置于两个相邻的移位寄存器单元之间。所述两个相邻的移位寄存器单元中的第一移位寄存器单元的扫描信号输出端与补偿单元的第一信号输入端相连接；补偿单元的第一信号输出端与第一移位寄存器单元的复位信号端相连接；两个相邻的移位寄存器单元中的第二移位寄存器单元的扫描信号输出端与补偿单元的第二信号输入端相连 接；补偿单元的第二信号输出端与第二移位寄存器单元的控制信号输入端相连接；补偿单元还连接补偿电压端、第一电压端以及第二电压端，用于在所述第一电压端的控制下，在消隐时间的第一时刻将所述补偿信号端的信号进行存储，在所述消隐时间的第二时刻将所述补偿信号端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻将所述补偿信号端的信号输出至所述第二移位寄存器单元的控制信号输入端；或者在第二电压端的控制下，进行复位。
这样一来，补偿单元可以接收第一移位寄存器单元的扫描信号输出端输入的信号，并在第一电压端的控制下，将补偿电压端的信号进行存储，并将该补偿电压端的信号输出至第一级移位寄存器的复位信号端，从而可以对第一移位寄存器单元进行复位。此外，补偿单元还可以在消隐时间，将补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端，以使得第二移位寄存器单元能够对与其相连的栅线输出栅极扫描信号。由于补偿单元是在消隐时间，将补偿电压端提供的电压输出至第二移位寄存器单元，因此可以对由于消隐时间延长而降低的栅极扫描信号进行补偿，从而能够避免由于时钟信号的消隐时间增加，导致像素充电不足的现象。此外，通过第二电压端还可以对补偿单元进行复位，以避免该帧残留的信号对下一帧画面造成不良的影响。
附图说明
图1为一种已知的时钟信号时序图；
图2为本公开实施例提供的一种栅极驱动电路的结构示意图；
图3为图2中补偿单元的结构示意图；
图4为图3中补偿单元中各个模块的一种具体结构示意图；
图5a为一种控制图4所示的补偿单元的信号时序图；
图5b为另一种控制图4所示的补偿单元的信号时序图；
图6为图3中补偿单元中各个模块的另一种具体结构示意图；
图7为图3中补偿单元中各个模块的又一种具体结构示意图；
图8为一种控制图7所示的补偿单元的信号时序图；
图9为本公开实施例提供的一种栅极驱动电路的驱动方法流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
图1示出一种已知的时钟信号的时序图。如图1所示，在一帧扫描结束后，GOA电路的时钟信号CLK会有一段消隐时间(Blanking Time)，因此，可以利用上述消隐时间作为触控驱动线(Tx lines)的扫描时间。
图2示出本公开实施例提供一种栅极驱动电路的结构示意图。如图2所示，该栅极驱动电路可以包括至少两级移位寄存器单元，还包括至少一个补偿单元100，所述补偿单元设置于两个相邻的移位寄存器单元之间。
上述两个相邻的移位寄存器单元可以是GOA电路中任意两个相邻的移位寄存器单元，例如如图2所示的第一级移位寄存器单元RS1和第二级移位寄存器单元RS2。或者可以是倒数第二级移位寄存器单元RSn-1和最后一级移位寄存器单元RSn，n为大于等于2的整数。以下为了方面说明，将相邻的两个移位寄存器单元称为第一移位寄存器单元和第二移位寄存器单元，并且本公开实施例中均是以如图2所示的第一级移位寄存器单元RS1作为第一移位寄存器单元，第二级移位寄存器单元RS2作为第二移位寄存器单元为例进行的说明。
如图2所示，两个相邻的移位寄存器单元中的第一移位寄存器单元RS1的扫描信号输出端OUTPUT与补偿单元100的第一信号输入端In1相连接。补偿单元100的第一信号输出端O1与第一移位寄存器单元RS1的复位信号端RESET相连接。
两个相邻的移位寄存器单元中的第二移位寄存器单元RS2的扫描信号输出端OUTPUT与补偿单元100的第二信号输入端In2相连接。补偿单元100的第二信号输出端O2与第二移位寄存器单元RS2的控制信号输入端INPUT相连接。
补偿单元100还连接至少一个补偿电压端PRE、第一电压端VDD以及第二电压端VSS，用于在第一电压端VDD的控制下，如图5a所示，在消隐时间(Blanking Time)的第一时刻T1将补偿信号端PRE的信号进行存储；在消隐时间(Blanking Time)的第二时刻T2将补偿信号端 PRE的信号输出至第一移位寄存器单元RS1的复位信号端RESET；在消隐时间(Blanking Time)的第三时刻T3将补偿信号端PRE的信号输出至第二移位寄存器单元RS2的控制信号输入端INPUT；或者在第二电压端VSS的控制下，进行复位。
需要说明的是，第一、本公开实施例是以第一电压端VDD输入高电平，第二电压端VSS输入低电平为例进行的说明。
第二、本公开实施例对移位寄存器单元的内部结构不做限定，只要能够向显示面板中的栅线输入栅极扫描信号，以使得由该移位寄存器单元构成的栅极电路能够对显示面板上的所有栅线实现逐行扫描即可。
此外，移位寄存器单元的结构不同，其连接的时钟信号CLK的数量也不相同。本公开对时钟信号CLK的数量不做限定，为了方便说明均是以一个时钟信号CLK为例进行的说明。
第三、本公开实施例对补偿单元100的个数并不做限定，可以在每相邻的两个移位寄存器单元之间均设置上述补偿单元100。这样一来，可以通过补偿单元100对除了第一级以外的每一级移位寄存器单元输出的栅极扫描信号进行补偿。
或者，为了节约成本，可以无需在每相邻的两个移位寄存器单元之间设置上述补偿单元100，例如图2中，移位寄存器单元RSn-1和最后一级移位寄存器单元RSn之间可以不设置上述补偿单元100。
对于相邻的两个移位寄存器单元之间未设置上述补偿单元100的移位寄存器单元的连接关系，可以是上一级移位寄存器单元的扫描信号输出端OUTPUT与下一级移位寄存器单元的控制信号输入端INPUT相连接，例如移位寄存器单元RSn-1的扫描信号输出端OUTPUT与移位寄存器单元RSn的控制信号输入端INPUT相连接。下一级移位寄存器单元的扫描信号输出端OUTPUT与上一级移位寄存器单元的复位信号端RESET相连接，例如移位寄存器单元RSn的扫描信号输出端OUTPUT与移位寄存器单元RSn-1的复位信号端RESET相连接。
本公开实施例提供的栅极驱动电路，包括至少两级移位寄存器单元，还包括至少一个补偿单元，其中补偿单元设置于两个相邻的移位寄存器单元之间。所述两个相邻的移位寄存器单元中的第一移位寄存器单元的扫描信号输出端与补偿单元的第一信号输入端相连接；补偿单元的第一 信号输出端与第一移位寄存器单元的复位信号端相连接；两个相邻的移位寄存器单元中的第二移位寄存器单元的扫描信号输出端与补偿单元的第二信号输入端相连接；补偿单元的第二信号输出端与第二移位寄存器单元的控制信号输入端相连接；补偿单元还连接补偿电压端、第一电压端以及第二电压端，用于在所述第一电压端的控制下，在消隐时间的第一时刻将所述补偿信号端的信号进行存储，在所述消隐时间的第二时刻将所述补偿信号端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻将所述补偿信号端的信号输出至所述第二移位寄存器单元的控制信号输入端；或者在第二电压端的控制下，进行复位。
这样一来，补偿单元可以接收第一移位寄存器单元的扫描信号输出端输入的信号，并在第一电压端的控制下，将补偿电压端的信号进行存储，并将该补偿电压端的信号输出至第一级移位寄存器的复位信号端，从而可以对第一移位寄存器单元进行复位。此外，补偿单元还可以在消隐时间，将补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端，以使得第二移位寄存器单元能够对与其相连的栅线输出栅极扫描信号。由于补偿单元是在消隐时间，将补偿电压端提供的电压输出至第二移位寄存器单元，因此可以对由于消隐时间延长而降低的栅极扫描信号进行补偿，从而能够避免由于时钟信号的消隐时间增加，导致像素充电不足的现象。此外，通过第二电压端还可以对补偿单元进行复位，以避免该帧残留的信号对下一帧画面造成不良的影响。
以下对上述补偿单元100的具体结构进行详细说明。
图3示出图2所示补偿单元100的结构示意图。如图3所示，所述补偿模块100可以包括控制模块1001、复位模块1002以及电压保持模块1003。
其中，控制模块1001分别与复位模块1002、电压保持模块1003、第一信号输入端In1、第一电压端VDD相连接，用于在第一信号输入端的In1控制下，将第一电压端VDD的电压输出至电压保持模块1003。
复位模块1002还连接电压保持模块1003、第二信号输入端In2、第二电压端VSS，用于在第二信号输入端In2的控制下，将第二电压端VSS的电压输出至电压保持模块1003，以对电压保持模块1003进行复位。
电压保持模块1003还连接至少一个补偿电压端PRE、第一信号输出端O1、第二信号输出端O2，用于将补偿信号端PRE的信号进行存储，并输出至第一信号输出端O1或第二信号输出端O2。
这样一来，可以通过控制模块1001，将第一电压端VDD的电压输出至电压保持模块1003，以使得电压保持模块1003开启，并将补偿信号端PRE的信号进行存储，并输出至第一信号输出端O1或第二信号输出端O2，以使得与第一信号输出端O1相连接的第一移位寄存器单元RS1进行复位，与第二信号输出端O2相连接的第二移位寄存器单元RS2能够对与其相连的栅线输出栅极扫描信号，由于第二信号输出端O2可以将电压保持模块1003存储的补偿信号端PRE的信号提供至第二移位寄存器单元RS2，从而以对栅极扫描信号进行补偿，因此能够避免由于时钟信号的消隐时间增加，导致像素充电不足的现象。此外，通过复位模块1002，还可以对电压保持模块1003进行复位，从而避免该帧残留的信号对下一帧画面造成不良的影响。
以下通过具体的实施例对上述补偿单元100中的各个模块具体的结构进行详细的举例说明。
第一实施例
图4示出图3所示补偿单元100中各个模块的一种具体结构示意图。如图4所示，控制模块1001可以包括：第一晶体管M1，其栅极连接第一信号输入端In1，第一极连接第一电压端VDD，第二极与复位模块1002、电压保持模块1003相连接。
复位模块1002可以包括：第二晶体管M2，其栅极连接第二信号输入端In2，第一极连接第二电压端VSS，第二极与控制模块1001、电压保持模块1003相连接。
补偿电压端PRE包括第一补偿电压端PRE1、第二补偿电压端PRE2；电压保持模块1003可以包括：第三晶体管M3、第四晶体管M4、第一电容C1以及第二电容C2。
第三晶体管M3的栅极连接控制模块1001、复位模块1002，第一极与第一补偿电压端PRE1相连接，第二极连接第一信号输出端O1。当控制模块1001和复位模块1002的结构如上所述时，第三晶体管M3的栅极连接第一晶体管M1和第二晶体管M2的第二极。
第四晶体管M4的栅极连接控制模块1001、复位模块1002，第一极与第二补偿电压端PRE2相连接，第二极连接第二信号输出端O2。当控制模块1001和复位模块1002的结构如上所述时，第四晶体管M4的栅极连接第一晶体管M1和第二晶体管M2的第二极。
第一电容C1的一端与第三晶体管M3的栅极相连接，另一端连接第三晶体管M3的第二极。
第二电容C2的一端与第四晶体管M4的栅极相连接，另一端连接第四晶体管M4的第二极。
图5a示出一种控制图4所示的补偿单元的信号时序图。如图5a所示，对于内嵌式触控显示装置而言，在时钟信号端CLK输出时钟信号的Blanking Time(消隐时间)，可以执行触控操作。而补偿单元100可以在上述Blanking Time对移位寄存器单元输出的栅极扫描信号进行补偿的过程为：
在Blanking Time的第一时刻T1，补偿单元100的第一信号输入端In1接收如图2所示的第一移位寄存器单元RS1输出栅极扫描信号G1，该栅极扫描信号G1会通过补偿单元100的第一信号输入端In1输入至第一晶体管M1的栅极，所述第一晶体管M1导通，将第一电压端VDD的电压信号输出至节点a，使得节点a的电压Va＝VDD。在此情况下，第三晶体管M3和第四晶体管M4导通，且第一电容C1和第二电容C2将第一电压端VDD的电压信号进行存储。
此时，第一补偿电压端PRE1输入的信号通过第三晶体管M3输出至第一信号输出端O1。通过第一电容C1的自举作用，使得节点a的电压升为Va＝VDD+PRE1。
在Blanking Time的第二时刻T2，如图2所示，第一信号输入端O1与第一移位寄存器单元RS1的复位信号端RESET相连接，当移位寄存器单元RS1开始工作时，第一信号输入端O1输出的信号能够对第一移位寄存器单元RS1进行复位，此时节点a的电压升为Va＝VDD。
在Blanking Time的第三时刻T3，由于第四晶体管M4导通，因此第二补偿电压端PRE2输入的信号通过第四晶体管M4输出至第二信号输出端O2。通过第二电容C2的自举作用，使得节点a的电压升为Va＝VDD+PRE2。在此情况下，如图2所示，第二信号输出端O2与第二移位寄存 器单元RS2的控制信号输入端INPUT相连接，当第二移位寄存器单元RS2开始工作，第二补偿电压端PRE2输入的信号能够通过第二信号输出端O2输出至第二移位寄存器单元RS2，使得第二移位寄存器单元RS2向与其相连接的栅线输出栅极扫描信号。此时，节点a的电压为Va＝VDD。
综上所述，通过第二电容C2，能够使得补偿单元100的第二信号输出端O2在向第二移位寄存器单元RS2输出信号时，节点a的电压能够保持Va＝VDD。在此情况下，在时钟信号的Blanking Time中，第四晶体管M4能够保持开启状态，第二补偿电压端PRE2输入的信号通过第二信号输出端O2，持续输出至第二移位寄存器单元RS2的控制信号输入端INPUT。这样一来，即使为了保证上述触控信号的响应时间而延长时钟信号的Blanking Time，但是在该Blanking Time中，补偿单元100的第二信号输出端O2仍然能够持续向与其相连的移位寄存器单元的控制信号输入端INPUT输入信号。而现有技术中，在Blanking Time内移位寄存器单元的控制信号输入端INPUT无信号输入，因此移位寄存器单元的驱动晶体管栅极的电压会通过与该栅极相连的晶体管漏电，使得该移位寄存器单元输出的栅极扫描信号降低。因此，本公开能够通过补偿单元100，在Blanking Time向与其相连接的移位寄存器单元的控制信号输入端INPUT输入信号，以对该移位寄存器单元输出的栅极扫描信号进行补偿，避免了像素充电不足的现象。
此外，当如图2所示的第二移位寄存器单元RS2输出栅极扫描信号G2后，由于第二移位寄存器单元RS2的扫描信号输出端OUTPUT与补偿单元100的第二信号输入端In2相连接，从而可以将第二晶体管M2导通，使得第二电压端VSS的电压信号输出至节点a，从而对第一电容C1和第二电容C2进行放电，避免残留的电压信号对下一帧画面产生不良的影响。
需要说明的是，第一、上述仅仅是以GOA电路中采用一个时钟信号端CLK为例进行的说明。由于本公开实施例对采用的时钟信号端的个数不做限定，当采用多个时钟信号端时，例如如图5b所示，采用四个时钟信号端，分别输出时钟信号CLK1、CLK2、CLK3以及CLK4在此情况下，第一补偿电压端PRE1在所有时钟信号均进入Blanking Time后开始输入信号，而第二补偿电压端PRE2在所有时钟信号中最先结束Blanking Time 的时刻前开始输入信号。上述仅仅是以GOA电路采用一个或四个时钟信号端时，第一补偿电压端PRE1以及第二补偿电压端PRE2输入信号的举例说明，采用其它个数的时钟信号端时，第一补偿电压端PRE1以及第二补偿电压端PRE2如何输入信号同理可得，在此不再一一赘述。
第二、本实施例中的晶体管均是以N型晶体管为例进行的说明。当采用P型晶体管时，需要将图5a、图5b所示的信号进行翻转，并将图4所示的电路结构图中，连接有第一电压端VDD的晶体管与第二电压端VSS相连接，同时将连接有第二电压端VSS的晶体管与第一电压端VDD相连接。为了方便说明，以下实施例中的晶体管均是以N型晶体管为例进行的说明。当采用P型晶体管时，设置方式同上所述。
第二实施例
图6示出图3所示补偿单元100中各个模块的另一种具体结构示意图。本实施例与第一实施例提供的控制模块1001和复位模块1002的结构相同。不同的是，补偿电压端包括第一补偿电压端PRE1、第二补偿电压端PRE2；电压保持模块1003如图6所示，可以包括：第五晶体管M5、第六晶体管M6以及第三电容C3。
图6中，第五晶体管M5的栅极连接控制模块1001、复位模块1002，第一极与第一补偿电压端PRE1相连接，第二极连接第一信号输出端O1。当控制模块1001、复位模块1002的结构如上所述时，第五晶体管M5的栅极连接第一晶体管M1和第二晶体管M2的第二极。
第六晶体管M6的栅极连接控制模块1001、复位模块1002，第一极与第二补偿电压端PRE2相连接，第二极连接第二信号输出端O2。当控制模块1001、复位模块1002的结构如上所述时，第六晶体管M六的栅极连接第一晶体管M1和第二晶体管M2的第二极。
第三电容C3的一端连接第五晶体管M5和第六晶体管M6的栅极，另一端接地。
本实施例，与第一实施例的原理相同，采用了一个存储电容，即第三电容C3，当第一晶体管M1导通时，能够将第一电压端VDD输入的电压进行存储，能够使得补偿单元100的第二信号输出端O2在向第二移位寄存器单元RS2输出信号时，节点a的电压能够保持Va＝VDD。在此情况下，在时钟信号的Blanking Time中，第六晶体管M6能够保持开启 状态，第二补偿电压端PRE2输入的信号通过第二信号输出端O2，持续输出至第二移位寄存器单元RS2的控制信号输入端INPUT。
第三实施例
图7示出图3所示补偿单元100中各个模块的又一种具体结构示意图。本实施例与第一实施例提供的控制模块1001和复位模块1002的结构相同，不同的是，至包括一个补偿电压端，即第三补偿电压端PRE3；电压保持模块1003如图7所示，可以包括：第七晶体管M7以及第四电容C4。
其中，第七晶体管M7的栅极连接控制模块1001、复位模块1002，第一极与第三补偿电压端PRE3相连接，第二极连接第一信号输出端O1和第二信号输出端O2。当控制模块1001、复位模块1002的结构如上所述时，第七晶体管M7的栅极连接第一晶体管M1和第二晶体管M2的第二极。
第四电容C4的一端连接第七晶体管M7的栅极，另一端连接第七晶体管M7的第二极。
图8示出一种控制图7所示的补偿单元的信号时序图。图7中，第三补偿电压端PRE3输入的信号如图8所示，此时，补偿单元100的具体工作过程为：
在Blanking Time的第一时刻T1，补偿单元100的第一信号输入端In1接收如图2所示的第一移位寄存器单元RS1输出栅极扫描信号G1，该栅极扫描信号G1会通过补偿单元100的第一信号输入端In1输入至第一晶体管M1的栅极，所述第一晶体管M1导通，将第一电压端VDD的电压信号输出至节点a，使得节点a的电压Va＝VDD。在此情况下，第七晶体管M7导通，且第四电容C4将第一电压端VDD的电压信号进行存储。
此时，第三补偿电压端PRE3输入的信号通过第七晶体管M7输出至第一信号输出端O1。通过第四电容C1的自举作用，使得节点a的电压升为Va＝VDD+PRE1。
在Blanking Time的第二时刻T2，如图2所示，第一信号输入端O1与第一移位寄存器单元RS1的复位信号端RESET相连接，当移位寄存器单元RS1开始工作时，第一信号输入端O1输出的信号能够对第一移位 寄存器单元RS1进行复位，此时节点a的电压升为Va＝VDD。
在Blanking Time的第三时刻T3，由于第七晶体管M7导通，因此第三补偿电压端PRE3输入的信号通过第七晶体管M7输出至第二信号输出端O2。通过第四电容C4的自举作用，使得节点a的电压升为Va＝VDD+PRE2。在此情况下，如图2所示，第二信号输出端O2与第二移位寄存器单元RS2的控制信号输入端INPUT相连接，当第二移位寄存器单元RS2开始工作，第三补偿电压端PRE3输入的信号能够通过第二信号输出端O2输出至第二移位寄存器单元RS2，使得第二移位寄存器单元RS2向与其相连接的栅线输出栅极扫描信号。此时，节点a的电压为Va＝VDD。
综上所述，通过第四电容C4，能够使得补偿单元100的第二信号输出端O2在向第二移位寄存器单元RS2输出信号时，节点a的电压能够保持Va＝VDD。在此情况下，在时钟信号的Blanking Time中，第七晶体管M7能够保持开启状态，第三补偿电压端PRE3输入的信号通过第二信号输出端O2，持续输出至第二移位寄存器单元RS2的控制信号输入端INPUT。
综上所述，上述三个实施例中，相比较而言，图7所示第三实施例的结构更简单，因此有利于减小功耗和电路的占用空间。
本公开实施例的另一方面提供一种显示装置，包括上述任意一种栅极驱动电路，具有与前述实施例提供的栅极驱动电路相同的结构和有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
在本公开实施例中，显示装置具体可以包括液晶显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
图9示出本公开实施例提供的一种栅极驱动电路的驱动方法流程图。如图9所示，本公开实施例提供的一种栅极驱动电路的驱动方法，可以包括以下工作过程：
在步骤S101中，在如图5a所示的第一阶段P1，第一移位寄存器单元RS1的扫描信号输出端OUTPUT输出栅极扫描信号G1，补偿单元100通过第一信号输入端In1接收该栅极扫描信号G1。
在步骤S102中，在第二阶段P2(即Blanking Time)，在第一电压 端VDD的控制下，在消隐时间的第一时刻T1补偿单元100将补偿电压端PRE的信号进行存储；在消隐时间的第二时刻T2补偿单元100并将补偿电压端PRE的信号输出至第一移位寄存器单元RS1的复位信号端RESET；在消隐时间的第三时刻T3补偿单元100并将补偿电压端PRE的信号输出至第二移位寄存器单元RS2的控制信号输入端INPUT。从而使得补偿单元可以在消隐时间，将补偿电压端提供的电压输出至第二移位寄存器单元，以对栅极扫描信号进行补偿。
在步骤S103中，在第三阶段P3，第二移位寄存器单元RS2的扫描信号输出端OUTPUT输出栅极扫描信号G2。补偿单元100接收栅极扫描信号G2，在第二电压端VSS的控制下进行复位。以避免该帧残留的信号对下一帧画面造成不良的影响。
本公开实施例提供的栅极驱动电路的驱动方法包括，首先第一阶段，第一移位寄存器单元的扫描信号输出端输出栅极扫描信号，补偿单元接收栅极扫描信号；接下来，第二阶段，在第一电压端的控制下，在消隐时间的第一时刻补偿单元将补偿电压端的信号进行存储；在消隐时间的第二时刻补偿单元并将补偿电压端的信号输出至第一移位寄存器单元的复位信号端；在消隐时间的第三时刻补偿单元并将补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端；最后，第二移位寄存器单元的扫描信号输出端输出栅极扫描信号；补偿单元接收所述栅极扫描信号，在第二电压端的控制下进行复位。
这样一来，补偿单元可以接收第一移位寄存器单元的扫描信号输出端输入的信号，并在第一电压端的控制下，将补偿电压端的信号进行存储，并将该补偿电压端的信号输出至第一级移位寄存器的复位信号端，从而可以对第一移位寄存器单元进行复位。此外，补偿单元还可以在消隐时间，将补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端，以使得第二移位寄存器单元能够对与其相连的栅线输出栅极扫描信号。由于补偿单元是在消隐时间，将补偿电压端提供的电压输出至第二移位寄存器单元，因此可以对由于消隐时间延长而降低的栅极扫描信号进行补偿，从而能够避免由于时钟信号的消隐时间增加，导致像素充电不足的现象。此外，通过第二电压端还可以对补偿单元进行复位，以避免该帧残留的信号对下一帧画面造成不良的影响。
当补偿单元100包括控制模块1001、复位模块1002以及电压保持模块1003时，上述步骤S102可以包括：
首先，第一信号输入端In1输入信号，控制模块1001开启，将第一电压端VDD的电压输出至电压保持模块1003。
例如，当控制模块1001、复位模块1002以及电压保持模块1003的结构如图4所示时，补偿单元100的第一信号输入端In1接收如图2所示的第一移位寄存器单元RS1输出栅极扫描信号G1，该栅极扫描信号G1会通过补偿单元100的第一信号输入端In1输入至第一晶体管M1的栅极，所述第一晶体管M1导通，将第一电压端VDD的电压信号输出至节点a，使得节点a的电压Va＝VDD。在此情况下，第三晶体管M3和第四晶体管M4导通，且第一电容C1和第二电容C2将第一电压端VDD的电压信号进行存储。
接下来，补偿电压端PRE输入信号，电压保持模块1003将补偿信号端PRE的信号进行存储，并输出至第一信号输出端O1或第二信号输出端O2。
例如，在Blanking Time的第一时刻T1，第一补偿电压端PRE1输入的信号通过第三晶体管M3输出至第一信号输出端O1。
在Blanking Time的第二时刻T2，由图2所示，第一信号输入端O1与第一移位寄存器单元RS1的复位信号端RESET相连接，当移位寄存器单元RS1开始工作时，第一信号输入端O1输出的信号能够对第一移位寄存器单元RS1进行复位。
在Blanking Time的第三时刻T3，由于第四晶体管M4导通，因此第二补偿电压端PRE2输入的信号通过第四晶体管M4输出至第二信号输出端O2。通过第二电容C2的自举作用，使得节点a的电压升为Va＝VDD+PRE2。在此情况下，由图2所示，第二信号输出端O2与第二移位寄存器单元RS2的控制信号输入端INPUT相连接，当第二移位寄存器单元RS2开始工作，第二补偿电压端PRE2输入的信号能够通过第二信号输出端O2输出至第二移位寄存器单元RS2，使得第二移位寄存器单元RS2向与其相连接的栅线输出栅极扫描信号。
最后，第二信号输入端In2输入信号，复位模块1002开启，将第二电压端VSS的电压输出至电压保持模块1003，以对电压保持模块1003 进行复位。
例如，当如图2所示的第二移位寄存器单元RS2输出栅极扫描信号G2后，由于第二移位寄存器单元RS2的扫描信号输出端OUTPUT与补偿单元100的第二信号输入端In2相连接，从而可以将第二晶体管M2导通，使得第二电压端VSS的电压信号输出至节点a，从而对第一电容C1和第二电容C2进行放电，避免残留的电压信号对下一帧画面产生不良的影响。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年6月30日递交的中国专利申请第201510375407.7号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (11)

  1. 一种栅极驱动电路，包括至少两级移位寄存器单元，其中，还包括至少一个补偿单元，所述补偿单元设置于两个相邻的移位寄存器单元之间；
    所述两个相邻的移位寄存器单元中的第一移位寄存器单元的扫描信号输出端与所述补偿单元的第一信号输入端相连接，所述第一移位寄存器单元的复位信号端与所述补偿单元的第一信号输出端相连接；
    所述两个相邻的移位寄存器单元中的第二移位寄存器单元的扫描信号输出端与所述补偿单元的第二信号输入端相连接，所述第二移位寄存器单元的控制信号输入端与所述补偿单元的第二信号输出端相连接；
    所述补偿单元还连接至少一个补偿电压端、第一电压端以及第二电压端，用于在消隐时间对栅极扫描信号进行补偿。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述补偿单元在所述第一电压端的控制下，在消隐时间的第一时刻将所述补偿信号端的信号进行存储；在所述消隐时间的第二时刻将所述补偿信号端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻将所述补偿信号端的信号输出至所述第二移位寄存器单元的控制信号输入端；或者在所述第二电压端的控制下，进行复位。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述补偿单元包括控制模块、复位模块以及电压保持模块；
    所述控制模块分别与复位模块、电压保持模块、所述第一信号输入端、所述第一电压端相连接，用于在所述第一信号输入端的控制下，将所述第一电压端的电压输出至所述电压保持模块；
    所述复位模块还连接所述电压保持模块、所述第二信号输入端、所述第二电压端，用于在所述第二信号输入端的控制下，将所述第二电压端的电压输出至所述电压保持模块，以对所述电压保持模块进行复位；
    所述电压保持模块还连接至少一个所述补偿电压端、所述第一信号输出端、所述第二信号输出端，用于将所述补偿信号端的信号进行存储，并输出至所述第一信号输出端或所述第二信号输出端。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述控制模块包括：
    第一晶体管，其栅极连接所述第一信号输入端，第一极连接所述第一电压端，第二极与所述复位模块、所述电压保持模块相连接。
  5. 根据权利要求3所述的栅极驱动电路，其中，所述复位模块包括：
    第二晶体管，其栅极连接所述第二信号输入端，第一极连接所述第二电压端，第二极与所述控制模块、所述电压保持模块相连接。
  6. 根据权利要求3所述的栅极驱动电路，其中，所述补偿电压端包括第一补偿电压端、第二补偿电压端；所述电压保持模块包括：第三晶体管、第四晶体管、第一电容以及第二电容；
    所述第三晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第一补偿电压端相连接，第二极连接所述第一信号输出端；
    所述第四晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第二补偿电压端相连接，第二极连接所述第二信号输出端；
    所述第一电容的一端与所述第三晶体管的栅极相连接，另一端连接所述第三晶体管的第二极；
    所述第二电容的一端与所述第四晶体管的栅极相连接，另一端连接所述第四晶体管的第二极。
  7. 根据权利要求3所述的栅极驱动电路，其中，所述补偿电压端包括第一补偿电压端、第二补偿电压端；所述电压保持模块包括：第五晶体管、第六晶体管以及第三电容；
    所述第五晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第一补偿电压端相连接，第二极连接所述第一信号输出端；
    所述第六晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第二补偿电压端相连接，第二极连接所述第二信号输出端；
    所述第三电容的一端连接所述第五晶体管和所述第六晶体管的栅极，另一端接地。
  8. 根据权利要求3所述的栅极驱动电路，其中，所述补偿电压端包括第三补偿电压端；所述电压保持模块包括：第七晶体管以及第四电容；
    所述第七晶体管的栅极连接所述控制模块、所述复位模块，第一极与所述第三补偿电压端相连接，第二极连接所述第一信号输出端和所述第二信号输出端；
    所述第四电容的一端连接所述第七晶体管的栅极，另一端连接所述 第七晶体管的第二极。
  9. 一种显示装置，包括如权利要求1-7任一项所述的栅极驱动电路。
  10. 一种用于驱动如权利要求1-8任一项栅极驱动电路的驱动方法，包括：
    第一阶段，第一移位寄存器单元的扫描信号输出端输出栅极扫描信号，补偿单元接收所述栅极扫描信号；
    第二阶段，在第一电压端的控制下，在消隐时间的第一时刻所述补偿单元将补偿电压端的信号进行存储，在所述消隐时间的第二时刻所述补偿单元将所述补偿电压端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻所述补偿单元将所述补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端；
    第三阶段，所述第二移位寄存器单元的扫描信号输出端输出栅极扫描信号；所述补偿单元接收所述栅极扫描信号，在第二电压端的控制下进行复位。
  11. 根据权利要求10所述的栅极驱动电路的驱动方法，其中，所述补偿单元包括控制模块、复位模块以及电压保持模块；所述第二阶段，在第一电压端的控制下，在消隐时间的第一时刻所述补偿单元将补偿电压端的信号进行存储，在所述消隐时间的第二时刻所述补偿单元将所述补偿电压端的信号输出至所述第一移位寄存器单元的复位信号端；在所述消隐时间的第三时刻所述补偿单元将所述补偿电压端的信号输出至第二移位寄存器单元的控制信号输入端包括：
    第一信号输入端输入信号，所述控制模块开启，将所述第一电压端的电压输出至所述电压保持模块；
    所述补偿电压端输入信号，所述电压保持模块将所述补偿信号端的信号进行存储，并输出至第一信号输出端或第二信号输出端；
    第二信号输入端输入信号，所述复位模块开启，将所述第二电压端的电压输出至所述电压保持模块，以对所述电压保持模块进行复位。
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