WO2016184269A1 - 移位寄存器单元及其驱动方法、移位寄存器和显示装置 - Google Patents

移位寄存器单元及其驱动方法、移位寄存器和显示装置 Download PDF

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Publication number
WO2016184269A1
WO2016184269A1 PCT/CN2016/078730 CN2016078730W WO2016184269A1 WO 2016184269 A1 WO2016184269 A1 WO 2016184269A1 CN 2016078730 W CN2016078730 W CN 2016078730W WO 2016184269 A1 WO2016184269 A1 WO 2016184269A1
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Prior art keywords
transistor
signal
shift register
capacitor
register unit
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PCT/CN2016/078730
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English (en)
French (fr)
Inventor
马占洁
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京东方科技集团股份有限公司
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Priority to US15/321,887 priority Critical patent/US10283211B2/en
Publication of WO2016184269A1 publication Critical patent/WO2016184269A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to a shift register unit and a driving method thereof, a shift register, and a display device.
  • the shift register includes a multi-stage shift register unit, and each shift register unit corresponds to one row of pixel units.
  • a progressive scan of a pixel unit in a display device is implemented by a multi-stage shift register unit to display an image.
  • each stage of the shift register unit includes a two-stage circuit.
  • the number of transistors used in the shift register unit is large, which makes the structure of the shift register unit complicated.
  • the present disclosure provides a shift register unit and a driving method thereof, a shift register and a display device for simplifying a circuit structure of a shift register unit while ensuring normal operation of the shift register unit.
  • a shift register unit including: an input module connected to a first clock signal terminal, a second clock signal terminal, and a data carry signal terminal, according to the first clock signal terminal, a signal input from the second clock signal end and the data carry signal end, providing a selection signal; the output module is connected to the high level end, the low level end, and the output end of the shift register unit for selecting a signal according to the input module Select either high or low at the output.
  • the input module may include a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor, and a gate of the first transistor is connected to the first clock signal terminal a gate of the second transistor and a drain of the third transistor, a source connected to a gate of the third transistor, a gate of the fifth transistor, a gate of the sixth transistor, and a first end of the second capacitor has a drain connected to the data carry signal end; a source of the second transistor is connected to the low level end, and a drain thereof is connected to the source of the fourth transistor, the third transistor a source and a first end of the first capacitor; a drain of the third transistor is coupled to the first clock signal end; a gate of the fourth transistor is coupled to a second clock signal end and the first a second end of the capacitor, a source connected to the first end of the first capacitor, a drain connected to the drain of the fifth transistor, the seventh crystal a gate of the tube and a second end of the third capacitor, and a gate of the first transistor
  • the output module may include a fifth transistor, a sixth transistor, a seventh transistor, a second capacitor, and a third capacitor, and a gate of the fifth transistor is connected to the second capacitor a first end and a gate of the sixth transistor, a source connected to the first end of the third capacitor, a drain and a high end of the seventh transistor, and a drain connected to the third capacitor a second end and a gate of the seventh transistor; a gate of the sixth transistor is connected to the first end of the second capacitor, a source is connected to the low end, and a drain is connected to the second capacitor a second end, a source of the seventh transistor, and an output of the shift register unit; a gate of the seventh transistor is connected to a second end of the third capacitor, and a source thereof is connected to the first The second end of the second capacitor and the output end of the shift register unit have a drain connected to the first end and the high end of the third capacitor.
  • a driving method of a shift register unit including:
  • the signal of the data carry signal end and the signal of the first clock signal end are both low level signals
  • the signal of the second clock signal end is a high level signal
  • the signal of the data carry signal end and the first clock signal end The signal turns on the sixth transistor and charges the second capacitor such that the output of the shift register unit is a low level signal
  • the signal of the first clock signal end and the signal of the second clock signal end are both high level signals
  • the signal of the data carry signal end is a low level signal
  • the second capacitor will be in the a low level signal held in the first stage is supplied to the sixth transistor, and the sixth transistor is turned on, so that an output of the shift register unit is a low level signal;
  • the signal of the first clock signal end is a high level signal
  • the signal of the second clock signal end and the signal of the data carry signal end are both low level signals
  • the high level signal of the high level end is The third capacitor is charged, the second capacitor supplies a low level signal held in the second phase to the sixth transistor, and turns on the sixth transistor such that an output of the shift register unit is Low level signal;
  • the signal of the second clock signal end and the signal of the data carry signal end are both high level signals
  • the signal of the first clock signal end is a low level signal
  • the signal of the data carry signal end is a signal of the first clock signal terminal turns off the sixth transistor and charges the second capacitor
  • the third capacitor supplies a high level signal held in the third phase to the seventh transistor, and turns off
  • the seventh transistor the equivalent capacitance of the output end of the shift register unit is such that the output of the shift register unit is a low level signal and is a high level signal;
  • the signal of the first clock signal end and the data carry signal end is a high level signal
  • the signal of the second clock signal end is a low level signal
  • the second capacitor will be in the a four-stage held high level signal is supplied to the sixth transistor, and the sixth transistor is turned off, and the bootstrap function of the first capacitor causes the source of the fourth transistor to be a low level signal and the fourth transistor to be turned on.
  • the signal of the second clock signal end and the data carry signal end is a high level signal
  • the signal of the first clock signal end is a low level signal
  • the signal of the data carry signal end is The signal of the first clock signal end turns off the sixth transistor
  • the signal of the data carry signal terminal charges the second capacitor through the first transistor
  • the low level terminal charges the first capacitor through the second transistor
  • the first The three capacitors supply a low level signal held in the fifth stage to the seventh transistor, and turn on the seventh transistor such that an output of the shift register unit is a high level signal
  • the signal of the first clock signal end is a high level signal
  • the signal of the second clock signal end and the data carry signal end is a low level signal
  • the second capacitor is in the a six-stage held high level signal is supplied to the sixth transistor, and the sixth transistor is turned off, and a low level signal of the second clock signal terminal turns on the fourth transistor, and the first capacitor is in the
  • the low level signal held in the sixth stage is supplied to the seventh transistor, and the seventh transistor is turned on, so that the output of the shift register unit is a high level signal.
  • a shift register comprising a multi-pole shift register unit as described in the above technical solution;
  • the output of the other stage of each stage of the shift register unit is connected to the data carry signal end of the next stage shift register unit adjacent thereto.
  • a display device comprising the shift register in the above technical solution.
  • each stage shift register unit includes only one stage circuit, and this stage circuit includes 7 transistors and 3 capacitors.
  • the shift register unit in the present disclosure utilizes the shift register unit in the prior art as compared with the shift register unit in the prior art which requires two stages of circuits and two stages of circuits including a total of 12 transistors and 3 capacitors to operate normally.
  • a first-stage circuit including 7 transistors and 3 capacitors can ensure the normal operation of the shift register unit, thereby simplifying the circuit structure of the shift register unit.
  • 1 is a schematic structural diagram of a known shift register unit
  • FIG. 2 is a schematic structural diagram of a shift register unit according to a first embodiment of the present disclosure
  • FIG. 3 is a signal timing diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a shift register according to a second embodiment of the present disclosure.
  • Fig. 1 shows a schematic structural diagram of a known shift register unit.
  • each stage of the shift register unit includes a two-stage circuit.
  • the first stage circuit 10 is a signal trigger circuit
  • the second stage circuit 11 is a normally open type output circuit.
  • the first stage circuit 10 contains 8 transistors and 2 capacitors.
  • the second stage circuit 11 includes four transistors and one capacitor. The number of transistors in the shift register unit is large, which makes the structure of the shift register unit more complicated.
  • FIG. 2 shows a schematic structural diagram of a shift register unit according to a first embodiment of the present disclosure.
  • the shift register unit in the embodiment of the present disclosure includes an input module P1 and an output module P2.
  • the input module P1 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first capacitor C1.
  • the output module P2 may include a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a second capacitor C2, and a third capacitor C3.
  • the input module P1 is configured to provide a selection signal to the output module P2 according to the signals input by the first clock signal terminal Clk1, the second clock signal terminal Clk2, and the data carry signal terminal STV.
  • the output module P2 is configured to select to output a high level or a low level according to the selection signal provided by the input module P1.
  • the gate of the first transistor M1 is connected to the first clock signal terminal Clk1, the gate of the second transistor M2, and the drain of the third transistor M3, and the source of the first transistor M1 is connected.
  • the gate of the third transistor M3, the gate of the fifth transistor M5, the gate of the sixth transistor M6, and the first end of the second capacitor C2, the drain of the first transistor M1 is connected to the data carry signal terminal STV.
  • the source of the second transistor M2 is connected to the low-level terminal VGL, and the drain of the second transistor M2 is connected.
  • the source of the fourth transistor M4 the source of the third transistor M3, and the first end of the first capacitor C1.
  • the drain of the third transistor M3 is connected to the first clock signal terminal Clk1.
  • the gate of the fourth transistor M4 is connected to the second clock signal terminal Clk2 and the second terminal of the first capacitor C1, the source of the fourth transistor M4 is connected to the first end of the first capacitor C1, and the drain of the fourth transistor M4 is connected.
  • the gate of the fifth transistor M5 is connected to the first end of the second capacitor C2 and the gate of the sixth transistor M6, and the source of the fifth transistor M5 is connected to the first end of the third capacitor C3, the drain of the seventh transistor M7, and
  • the high level terminal VGH, the drain of the fifth transistor M5 is connected to the input module P1, the second end of the third capacitor C3, and the gate of the seventh transistor M7.
  • the gate of the sixth transistor M6 is connected to the first end of the second capacitor C2, the source of the sixth transistor M6 is connected to the low-level terminal VGL, and the drain of the sixth transistor M6 is connected to the second end of the second capacitor C2, the seventh transistor The source of M7 and the output of the shift register unit Output.
  • the gate of the seventh transistor M7 is connected to the second end of the third capacitor C3, the source of the seventh transistor M7 is connected to the second end of the second capacitor C2 and the output terminal of the shift register unit, the drain of the seventh transistor M7 The first terminal of the third capacitor C3 and the high level terminal VGH are connected.
  • the shift register unit includes only one level circuit, and the stage circuit includes 7 transistors and 3 capacitors.
  • the shift register unit of the embodiment of the present disclosure utilizes 7 transistors and 3 as compared with the shift register unit shown in FIG. 1 which requires two stages of circuits and two stages of circuits including 12 transistors and 3 capacitors to operate normally.
  • the primary circuit of the capacitor can ensure the normal operation of the shift register unit, thereby simplifying the circuit structure of the shift register unit.
  • first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 in the above shift register unit may both be N. Type transistor or P type transistor.
  • Fig. 3 shows a signal timing diagram corresponding to the shift register unit described above.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all P-type transistors, and the signal of FIG. 3 is referred to.
  • the timing diagram illustrates the operation of the shift register unit. Wherein, when the transistor is turned on, the source and the drain of the transistor are turned on; the transistor is turned off, and the source and the drain of the transistor are turned off.
  • the signals of the data carry signal terminal STV and the first clock signal terminal Clk1 are both low level signals, and the signal of the second clock signal terminal Clk2 is a high level signal.
  • the first transistor The gate of M1 and the gate of the second transistor M2 receive a low level signal from the first clock signal terminal Clk1, the source and the drain of the first transistor M1 are turned on, and the low level signal of the data carry signal terminal STV
  • the first transistor M1 is transmitted to the gate of the third transistor M3, the source and the drain of the third transistor M3 are turned on, and the low-level signal of the first clock signal terminal Clk1 is transmitted to the fourth transistor M4 through the third transistor M3.
  • the source and the drain of the second transistor M2 are turned on, and the low-level signal of the low-level terminal VGL is passed through the second transistor M2 to charge the first capacitor C1;
  • the low level signal of the carry signal terminal STV is transmitted to the gate of the sixth transistor M6 through the first transistor M1, and charges the second capacitor C2, and the source and the drain of the sixth transistor M6 are turned on; the data carry signal terminal
  • the low level signal of the STV is transmitted to the gate of the fifth transistor M5 through the first transistor M1, the source and the drain of the fifth transistor M5 are turned on, and the high level signal of the high level terminal VGH is the third capacitor for C3 charging.
  • the high level signal of the high level terminal VGH passes The fifth transistor M5 is transmitted to the gate of the seventh transistor M7, the source and the drain of the seventh transistor M7 are turned off; the gate of the fourth transistor M4 receives the high level signal from the second clock signal terminal Clk2, and the fourth transistor M4 The source and drain are turned off, so the low level signal of the source of the fourth transistor M4 does not affect the high level signal of the gate of the seventh transistor M7, so that the sixth transistor M6 is turned on, and the seventh transistor M7 is turned off.
  • the output of the shift register unit is a low level signal.
  • the signals of the first clock signal terminal Clk1 and the second clock signal terminal Clk2 are both high level signals, and the signal of the data carry signal terminal STV is a low level signal, and the first transistor M1 is The gate of the gate and the second transistor M2 receives the high level signal from the first clock signal terminal Clk1, the source and the drain of the first transistor M1 are turned off, and the source and the drain of the second transistor M2 are turned off;
  • the low level signal obtained by charging the second capacitor C2 in the AB phase continues to act such that the gate of the third transistor M3 receives the low level signal from the second capacitor C2, and the source and drain of the third transistor M3
  • the high level signal sent from the first clock signal terminal Clk1 is transmitted to the source of the fourth transistor M4 through the third transistor M3, and is charged to the first capacitor C1; the gate of the seventh transistor M7 receives the fourth transistor.
  • the high level signal of the source of M4 is transmitted, the source and the drain of the seventh transistor M7 are turned off; the gate of the fifth transistor M5 and the gate of the sixth transistor M6 receive the low level signal of the second capacitor C2. , the source and drain of the fifth transistor M5 Turned on, the sixth transistor M6 is turned on the source and drain, the sixth transistor M6 is turned on continuously, so that the output terminal Output of the shift register cells remains at a low level signal.
  • the signal of the first clock signal terminal Clk1 is a high level signal
  • the signals of the second clock signal terminal Clk2 and the data carry signal terminal STV are both low level signals
  • the fourth crystal The gate of the body tube M4 receives the low level signal from the second clock signal terminal Clk2, the source and the drain of the fourth transistor M4 are turned on, the high level terminal VGH charges the third capacitor C3, and the source of the fourth transistor M4
  • the pole and the drain are both high level signals
  • the gate of the seventh transistor M7 receives the high level signal of the drain of the fourth transistor M4, the source and the drain of the seventh transistor M7 are turned off; the second capacitor C2
  • the low level signal continues to act, similar to the BC stage, and the output of the CD stage shift register unit is still a low level signal.
  • the signals of the second clock signal terminal Clk2 and the data carry signal terminal STV are both high level signals, and the signal of the first clock signal terminal Clk1 is a low level signal, and the first transistor M1 is a gate of the gate and the second transistor M2 receives a low level signal from the first clock signal terminal Clk1, a source and a drain of the first transistor M1 are turned on, and a source and a drain of the second transistor M2 are turned on;
  • the high level signal of the data carry signal terminal STV is transmitted through the first transistor M1 to the gate of the third transistor M3, the gate of the fifth transistor M5 and the gate of the sixth transistor M6, and charges the second capacitor C2,
  • the source and the drain of the three-transistor M3 are turned off, the source and the drain of the fifth transistor M5 are turned off, the source and the drain of the sixth transistor M6 are turned off, and the low-level signal from the low-level terminal VGL is passed through the second transistor M2.
  • the third capacitor C3 maintains the high level signal of the CD stage, and is transmitted to the gate of the seventh transistor M7, the source of the seventh transistor M7 And drain cutoff, but due to the shift register unit Output terminal exists equivalent capacitance of the equivalent capacitor such that the shift register unit as a high level signal output terminal Output.
  • the signals of the first clock signal terminal Clk1 and the data carry signal terminal STV are both high level signals
  • the signal of the second clock signal terminal Clk2 is a low level signal
  • the second capacitor C2 remains.
  • a high level signal of the DE stage a gate of the third transistor M3, a gate of the fifth transistor M5, and a gate of the sixth transistor M6 receive a high level signal from the second capacitor C2, the third transistor M3
  • the source and the drain are turned off, the source and the drain of the fifth transistor M5 are turned off, the source and the drain of the sixth transistor M6 are turned off, and the gate of the fourth transistor M4 receives the low level of the second clock signal terminal Clk2.
  • the source and the drain of the fourth transistor M4 are turned on; the first capacitor C1 passes its own bootstrap function, so that the source of the fourth transistor M4 is at a low level signal, so that the gate of the seventh transistor M7 is low.
  • the signal is leveled, and the third capacitor C3 is charged by the low level signal, the source and the drain of the seventh transistor M7 are turned on, and the output terminal Output of the shift register unit is a high level signal.
  • the second clock signal terminal Clk2 and the data carry signal terminal STV The signal is a high level signal, the signal of the first clock signal terminal Clk1 is a low level signal, and the gate of the first transistor M1 and the gate of the second transistor M2 receive the low power of the first clock signal terminal Clk1.
  • a flat signal the source and the drain of the first transistor M1 are turned on, the source and the drain of the second transistor M2 are turned on, and the high level signal of the data carry signal terminal STV is transmitted to the third transistor M3 through the first transistor M1.
  • the pole is turned off, the source and the drain of the sixth transistor M6 are turned off; the low level signal of the low level terminal is transmitted to the source of the fourth transistor M4 through the second transistor M2, and the first capacitor C1 is charged; the third capacitor C3 is kept at a low level in the EF phase, and the source and the drain of the seventh transistor M7 are turned on, so that the output terminal Output of the shift register unit is a high level signal.
  • the signal of the first clock signal terminal Clk1 is a high level signal
  • the signals of the second clock signal terminal Clk2 and the data carry signal terminal STV are both low level signals
  • the second capacitor C2 remains.
  • the source and the drain of the sixth transistor are turned off, the gate of the fourth transistor M4 receives the low level signal from the second clock signal terminal Clk2, and the source and the drain of the fourth transistor M4.
  • the first capacitor C1 maintains a low level signal of the FG phase, and the low level signal of the first capacitor C1 is transmitted to the gate of the seventh transistor M7 through the fourth transistor M4, and the source and drain of the seventh transistor M7 Turned on, so that the output terminal of the shift register unit is a high level signal.
  • the signal of the second clock signal terminal Clk2 is a high level signal
  • the signals of the first clock signal terminal Clk1 and the data carry signal terminal STV are both low level signals, and the process is the same as the AB phase, and details are not described herein again. .
  • the signals of the first clock signal terminal Clk1 and the second clock signal terminal Clk2 are both high level signals, and the signal of the data carry signal terminal STV is a low level signal, and the process is the same as the BC phase, and details are not described herein again. .
  • the width of the high level of the signal of the data carry signal terminal STV by adjusting the width of the high level of the signal of the data carry signal terminal STV, the width of the high level of the signal of the output terminal Output of the shift register unit can be controlled, and the data carry signal end The wider the width of the high level of the signal of the STV, the wider the width of the high level of the signal of the output terminal of the shift register unit.
  • FIG. 4 shows a schematic structural diagram of a shift register according to a second embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a shift register including a plurality of shift register units in the above embodiment. Except for the first stage shift register unit, the data carry signal terminal STV of each of the shift register units of each stage is connected to the output terminal of the previous stage shift register unit adjacent thereto. Output; In addition to the last stage shift register unit, the output terminal of the current stage of each stage of the shift register unit is connected to the data carry signal terminal STV of the next shift register unit adjacent thereto.
  • the output terminal Output n of the nth stage shift register unit is connected to the data carry signal terminal STV(n+1) of the (n+1)th stage shift register unit. See Figure 3 for the signal timing of the output of the nth stage shift register unit Output n and the output of the (n+1)th stage shift register unit Output(n+1).
  • shift register unit in the shift register has the same advantages as the shift register unit in the above embodiment, and details are not described herein again.
  • the embodiment of the present disclosure further provides a display device including the shift register in the above embodiment, and the shift register in the display device has the same advantages as the shift register in the above embodiment, where No longer.
  • the display device may be any product or component having an display function such as an organic light emitting diode display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元及其驱动方法、移位寄存器和显示装置。所述移位寄存器单元，包括：输入模块(P1)，连接到第一时钟信号端(Clk1)、第二时钟信号端(Clk2)和数据进位信号端(STV)，用于根据第一时钟信号端(Clk1)、第二时钟信号端(Clk2)和数据进位信号端(STV)输入的信号，提供选择信号；输出模块(P2)，连接到高电平端(VGH)、低电平端(VGL)、移位寄存器单元的输出端(Output)，用于根据所述输入模块(P1)提供的选择信号，选择在所述输出端(Output)输出高电平或低电平。移位寄存器包括多级移位寄存器单元，显示装置包括移位寄存器。信利用一级电路就能够保证移位寄存器单元的正常工作，简化了移位寄存器单元的电路结构。

Description

移位寄存器单元及其驱动方法、移位寄存器和显示装置 技术领域
本公开涉及一种移位寄存器单元及其驱动方法、移位寄存器和显示装置。
背景技术
显示装置在进行显示时，需要利用移位寄存器实现对像素单元的扫描。移位寄存器包括多级移位寄存器单元，每级移位寄存器单元对应一行像素单元。由多级移位寄存器单元实现对显示装置中像素单元的逐行扫描，以显示图像。
在现有技术中，每级移位寄存器单元包括两级电路。移位寄存器单元中采用的晶体管的数目较多，这使得移位寄存器单元的结构较为复杂。
发明内容
本公开提供一种移位寄存器单元及其驱动方法、移位寄存器和显示装置，用于在保证移位寄存器单元正常工作的前提下，简化移位寄存器单元的电路结构。
在本公开的第一方面，提供了一种移位寄存器单元，包括：输入模块，连接到第一时钟信号端、第二时钟信号端和数据进位信号端，用于根据第一时钟信号端、第二时钟信号端和数据进位信号端输入的信号，提供选择信号；输出模块，连接到高电平端、低电平端、移位寄存器单元的输出端，用于根据所述输入模块提供的选择信号，选择在所述输出端高电平或低电平。
可替换地，在上述移位寄存器单元中，输入模块可以包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第一电容，所述第一晶体管的栅极连接第一时钟信号端、所述第二晶体管的栅极和所述第三晶体管的漏极，其源极连接所述第三晶体管的栅极、所述第五晶体管的栅极、所述第六晶体管的栅极和所述第二电容的第一端，其漏极连接数据进位信号端；所述第二晶体管的源极连接低电平端，其漏极连接所述第四晶体管的源极、所述第三晶体管的源极和所述第一电容的第一端；所述第三晶体管的漏极连接所述第一时钟信号端；所述第四晶体管的栅极连接第二时钟信号端和所述第一电容的第二端，其源极连接所述第一电容的第一端，其漏极连接所述第五晶体管的漏极、所述第七晶体 管的栅极和所述第三电容的第二端。
可替换地，在上述移位寄存器单元中，输出模块可以包括第五晶体管、第六晶体管、第七晶体管、第二电容和第三电容，所述第五晶体管的栅极连接所述第二电容的第一端和所述第六晶体管的栅极，其源极连接所述第三电容的第一端、所述第七晶体管的漏极和高电平端，其漏极连接所述第三电容的第二端和所述第七晶体管的栅极；所述第六晶体管的栅极连接所述第二电容的第一端，其源极连接低电平端，其漏极连接所述第二电容的第二端、所述第七晶体管的源极和所述移位寄存器单元的输出端；所述第七晶体管的栅极连接所述第三电容的第二端，其源极连接所述第二电容的第二端和所述移位寄存器单元的输出端，其漏极连接第三电容的第一端和高电平端。
在本公开的第二方面，还提供了一种移位寄存器单元的驱动方法，包括：
第一阶段，数据进位信号端的信号与第一时钟信号端的信号均为低电平信号，第二时钟信号端的信号为高电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号开启第六晶体管，并为所述第二电容进行充电，使得所述移位寄存器单元的输出为低电平信号；
第二阶段，所述第一时钟信号端的信号和所述第二时钟信号端的信号均为高电平信号，所述数据进位信号端的信号为低电平信号，所述第二电容将在所述第一阶段保持的低电平信号提供给所述第六晶体管，并开启所述第六晶体管，使得所述移位寄存器单元的输出为低电平信号；
第三阶段，所述第一时钟信号端的信号为高电平信号，所述第二时钟信号端的信号与所述数据进位信号端的信号均为低电平信号，高电平端的高电平信号为第三电容进行充电，所述第二电容将在所述第二阶段保持的低电平信号提供给所述第六晶体管，并开启所述第六晶体管，使得所述移位寄存器单元的输出为低电平信号；
第四阶段，所述第二时钟信号端的信号与所述数据进位信号端的信号均为高电平信号，所述第一时钟信号端的信号为低电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号关闭第六晶体管，并为所述第二电容进行充电，所述第三电容将在所述第三阶段保持的高电平信号提供给所述第七晶体管，并关闭所述第七晶体管，所述移位寄存器单元的输出端的等效电容使得所述移位寄存器单元的输出为低电平信号为高电平信号；
第五阶段，所述第一时钟信号端与所述数据进位信号端的信号均为高电平信号，所述第二时钟信号端的信号为低电平信号，所述第二电容将在所述第四阶段保持的高电平信号提供给所述第六晶体管，并关闭所述第六晶体管，所述第一电容的自举功能使得第四晶体管的源极为低电平信号，第四晶体管开启，为所述第三电容进行充电，并开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号；
第六阶段，所述第二时钟信号端与所述数据进位信号端的信号均为高电平信号，所述第一时钟信号端的信号为低电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号关闭第六晶体管，所述数据进位信号端的信号通过第一晶体管为所述第二电容进行充电，低电平端通过第二晶体管为所述第一电容进行充电，所述第三电容将在所述第五阶段保持的低电平信号提供给所述第七晶体管，开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号；
第七阶段，所述第一时钟信号端的信号为高电平信号，所述第二时钟信号端与所述数据进位信号端的信号均为低电平信号，所述第二电容将在所述第六阶段保持的高电平信号提供给所述第六晶体管，并关闭所述第六晶体管，所述第二时钟信号端的低电平信号开启所述第四晶体管，所述第一电容将在所述第六阶段保持的低电平信号提供给所述第七晶体管，并开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号。
在本公开的第三方面，还提供了一种移位寄存器，包括多极上述技术方案中所述的移位寄存器单元；
除第一级移位寄存器单元外，其余每级移位寄存器单元的数据进位信号端连接与其相邻的上一级移位寄存器单元的本级输出端；
除最后一级移位寄存器单元外，其余每级移位寄存器单元的本级输出端连接与其相邻的下一级移位寄存器单元的数据进位信号端。
在本公开的第四方面，提供了一种显示装置，包括上述技术方案中的所述移位寄存器。
本公开提供的移位寄存器单元及其驱动方法、移位寄存器和显示装置中，每级移位寄存器单元中只包含一级电路，且这一级电路包括7个晶体管和3个电容。与现有技术中需要设置两级电路且两级电路共包括12个晶体管和3个电容才能正常工作的移位寄存器单元相比，本公开中的移位寄存器单元利用 包括7个晶体管和3个电容的一级电路就能够保证移位寄存器单元正常工作，从而简化了移位寄存器单元的电路结构。
附图说明
图1为一种已知的移位寄存器单元的结构示意图；
图2为根据本公开第一实施例的移位寄存器单元的结构示意图；
图3为根据本公开实施例的移位寄存器单元的信号时序图；
图4为根据本公开第二实施例的移位寄存器的结构示意图。
具体实施方式
为了进一步说明本公开实施例提供的移位寄存器单元及其驱动方法、移位寄存器和显示装置，下面结合附图进行详细描述。本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。
图1示出一种已知的移位寄存器单元的结构示意图。如图1所示，每级移位寄存器单元包括两级电路。第一级电路10为信号触发极电路，第二级电路11为常开型输出电路。第一级电路10包含8个晶体管和2个电容。第二级电路11包含4个晶体管和1个电容。该移位寄存器单元中晶体管的数目较多，使得移位寄存器单元的结构较为复杂。
图2示出根据本公开第一实施例的移位寄存器单元的结构示意图。
请参阅图2，本公开实施例中的移位寄存器单元包括输入模块P1和输出模块P2。输入模块P1可以包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4和第一电容C1。输出模块P2可以包括第五晶体管M5、第六晶体管M6、第七晶体管M7、第二电容C2和第三电容C3。输入模块P1用于根据第一时钟信号端Clk1、第二时钟信号端Clk2和数据进位信号端STV输入的信号，向输出模块P2提供选择信号。输出模块P2用于根据输入模块P1提供的选择信号，选择输出高电平或低电平。
在图2所示移位寄存器单元中，第一晶体管M1的栅极连接第一时钟信号端Clk1、第二晶体管M2的栅极和第三晶体管M3的漏极，第一晶体管M1的源极连接第三晶体管M3的栅极、第五晶体管M5的栅极、第六晶体管M6的栅极和第二电容C2的第一端，第一晶体管M1的漏极连接数据进位信号端STV。第二晶体管M2的源极连接低电平端VGL，第二晶体管M2的漏极连接 第四晶体管M4的源极、第三晶体管M3的源极和第一电容C1的第一端。第三晶体管M3的漏极连接第一时钟信号端Clk1。第四晶体管M4的栅极连接第二时钟信号端Clk2和第一电容C1的第二端，第四晶体管M4的源极连接第一电容C1的第一端，第四晶体管M4的漏极连接第五晶体管M5的漏极、第七晶体管M7的栅极和第三电容C3的第二端。第五晶体管M5的栅极连接第二电容C2的第一端和第六晶体管M6的栅极，第五晶体管M5的源极连接第三电容C3的第一端、第七晶体管M7的漏极和高电平端VGH，第五晶体管M5的漏极连接输入模块P1、第三电容C3的第二端和第七晶体管M7的栅极。第六晶体管M6的栅极连接第二电容C2的第一端，第六晶体管M6的源极连接低电平端VGL，第六晶体管M6的漏极连接第二电容C2的第二端、第七晶体管M7的源极和移位寄存器单元的输出端Output。第七晶体管M7的栅极连接第三电容C3的第二端，第七晶体管M7的源极连接第二电容C2的第二端和移位寄存器单元的输出端Output，第七晶体管M7的漏极连接第三电容C3的第一端和高电平端VGH。
如图2所示，在本公开提供的移位寄存器单元中，该移位寄存器单元中只包含一级电路，且这一级电路包括7个晶体管和3个电容。与图1所示需要设置两级电路且两级电路共包括12个晶体管和3个电容才能正常工作的移位寄存器单元相比，本公开实施例的移位寄存器单元利用包括7个晶体管和3个电容的一级电路就能够保证移位寄存器单元正常工作，从而简化了移位寄存器单元的电路结构。
需要说明的是，上述移位寄存器单元中的第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7可以均为N型晶体管或P型晶体管。
图3示出与上述移位寄存器单元对应的信号时序图。下面将以第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管M7均为P型晶体管为例，参照图3的信号时序图对移位寄存器单元的工作过程进行说明。其中，晶体管开启，则晶体管的源极和漏极导通；晶体管关闭，晶体管的源极和漏极截止。
如图3所示，在A-B阶段(即第一阶段)，数据进位信号端STV与第一时钟信号端Clk1的信号均为低电平信号，第二时钟信号端Clk2的信号为高电平信号。此时，参见图2所示的移位寄存器单元的结构示意图，第一晶体管 M1的栅极和第二晶体管M2的栅极接收到第一时钟信号端Clk1发出的低电平信号，第一晶体管M1的源极和漏极导通，数据进位信号端STV的低电平信号通过第一晶体管M1传输至第三晶体管M3的栅极，第三晶体管M3的源极和漏极导通，第一时钟信号端Clk1的低电平信号通过第三晶体管M3传输至第四晶体管M4的源极，并为第一电容C1进行充电；第二晶体管M2的源极和漏极导通，低电平端VGL的低电平信号通过第二晶体管M2，为第一电容C1进行充电；数据进位信号端STV的低电平信号通过第一晶体管M1传输至第六晶体管M6的栅极，并为第二电容C2进行充电，第六晶体管M6的源极和漏极导通；数据进位信号端STV的低电平信号通过第一晶体管M1传输至第五晶体管M5的栅极，第五晶体管M5的源极和漏极导通，高电平端VGH的高电平信号为第三电容进行C3充电，高电平端VGH的高电平信号通过第五晶体管M5传输至第七晶体管M7的栅极，第七晶体管M7的源极和漏极截止；第四晶体管M4的栅极接收第二时钟信号端Clk2发出的高电平信号，第四晶体管M4的源极和漏极截止，因此第四晶体管M4的源极的低电平信号并不会影响第七晶体管M7栅极的高电平信号，从而使得第六晶体管M6开启，第七晶体管M7关闭，移位寄存器单元的输出Output为低电平信号。
在B-C阶段(即第二阶段)，第一时钟信号端Clk1和第二时钟信号端Clk2的信号均为高电平信号，数据进位信号端STV的信号为低电平信号，第一晶体管M1的栅极和第二晶体管M2的栅极接收到第一时钟信号端Clk1发出的高电平信号，第一晶体管M1的源极和漏极截止，第二晶体管M2的源极和漏极截止；由于第二电容C2在A-B阶段充电得到的低电平信号持续发生作用，使得第三晶体管M3的栅极接收到第二电容C2发出的低电平信号，第三晶体管M3的源极和漏极导通，第一时钟信号端Clk1发出的高电平信号通过第三晶体管M3传输至第四晶体管M4的源极，并为第一电容C1进行充电；第七晶体管M7的栅极接收到第四晶体管M4的源极传输的高电平信号，第七晶体管M7的源极和漏极截止；第五晶体管M5的栅极和第六晶体管M6的栅极接收到第二电容C2发出的低电平信号，第五晶体管M5的源极和漏极导通，第六晶体管M6的源极和漏极导通，第六晶体管M6持续开启，使得移位寄存器单元的输出端Output仍为低电平信号。
在C-D阶段(即第三阶段)，第一时钟信号端Clk1的信号为高电平信号，第二时钟信号端Clk2与数据进位信号端STV的信号均为低电平信号，第四晶 体管M4的栅极接收第二时钟信号端Clk2发出的低电平信号，第四晶体管M4的源极和漏极导通，高电平端VGH为第三电容C3充电，第四晶体管M4的源极和漏极均为高电平信号，第七晶体管M7的栅极接收到第四晶体管M4的漏极的高电平信号，第七晶体管M7的源极和漏极截止；第二电容C2上的低电平信号持续作用，与B-C阶段相似，C-D阶段移位寄存器单元的输出端Output仍为低电平信号。
在D-E阶段(即第四阶段)，第二时钟信号端Clk2与数据进位信号端STV的信号均为高电平信号，第一时钟信号端Clk1的信号为低电平信号，第一晶体管M1的栅极和第二晶体管M2的栅极接收第一时钟信号端Clk1发出的低电平信号，第一晶体管M1的源极和漏极导通，第二晶体管M2的源极和漏极导通；数据进位信号端STV的高电平信号通过第一晶体管M1传输到第三晶体管M3的栅极、第五晶体管M5的栅极和第六晶体管M6的栅极，并为第二电容C2充电，第三晶体管M3的源极和漏极截止，第五晶体管M5的源极和漏极截止，第六晶体管M6的源极和漏极截止；低电平端VGL发出的低电平信号通过第二晶体管M2传输至第四晶体管M4的源极，并为第一电容C1充电；第三电容C3保持着C-D阶段的高电平信号，并传输至第七晶体管M7的栅极，第七晶体管M7的源极和漏极截止，但由于移位寄存器单元的输出端Output存在等效电容，该等效电容使得移位寄存器单元的输出端Output为高电平信号。
在E-F阶段(即第五阶段)，第一时钟信号端Clk1与数据进位信号端STV的信号均为高电平信号，第二时钟信号端Clk2的信号为低电平信号，第二电容C2保持着D-E阶段的高电平信号，第三晶体管M3的栅极、第五晶体管M5的栅极和第六晶体管M6的栅极接收到第二电容C2发出的高电平信号，第三晶体管M3的源极和漏极截止，第五晶体管M5的源极和漏极截止，第六晶体管M6的源极和漏极截止；第四晶体管M4的栅极接收第二时钟信号端Clk2发出的低电平信号，第四晶体管M4的源极和漏极导通；第一电容C1通过自身的自举功能，使得第四晶体管M4的源极为低电平信号，从而使得第七晶体管M7的栅极为低电平信号，并由低电平信号为第三电容C3进行充电，第七晶体管M7的源极和漏极导通，移位寄存器单元的输出端Output为高电平信号。
在F-G阶段(即第六阶段)，第二时钟信号端Clk2与数据进位信号端STV 的信号均为高电平信号，第一时钟信号端Clk1的信号为低电平信号，第一晶体管M1的栅极和第二晶体管M2的栅极接收到第一时钟信号端Clk1发出的低电平信号，第一晶体管M1的源极和漏极导通，第二晶体管M2的源极和漏极导通，数据进位信号端STV的高电平信号通过第一晶体管M1传输至第三晶体管M3的栅极、第五晶体管M5的栅极和第六晶体管M6的栅极，并为第二电容C2进行充电，第三晶体管M3的源极和漏极截止，第五晶体管M5的源极和漏极截止，第六晶体管M6的源极和漏极截止；低电平端的低电平信号通过第二晶体管M2传输至第四晶体管M4的源极，并为第一电容C1进行充电；第三电容C3保持在E-F阶段的低电平，第七晶体管M7的源极和漏极导通，使得移位寄存器单元的输出端Output为高电平信号。
在G-H阶段(即第七阶段)，第一时钟信号端Clk1的信号为高电平信号，第二时钟信号端Clk2与数据进位信号端STV的信号均为低电平信号，第二电容C2保持在F-G阶段的高电平，第六晶体管的源极和漏极截止，第四晶体管M4的栅极接收第二时钟信号端Clk2发出的低电平信号，第四晶体管M4的源极和漏极导通，第一电容C1保持F-G阶段的低电平信号，第一电容C1的低电平信号通过第四晶体管M4传输至第七晶体管M7的栅极，第七晶体管M7的源极和漏极导通，使得移位寄存器单元的输出端Output为高电平信号。
在H-J阶段，第二时钟信号端Clk2的信号为高电平信号，第一时钟信号端Clk1与数据进位信号端STV的信号均为低电平信号，过程与A-B阶段相同，在此不再赘述。
在J-K阶段，第一时钟信号端Clk1与第二时钟信号端Clk2的信号均为高电平信号，数据进位信号端STV的信号为低电平信号，过程与B-C阶段相同，在此不再赘述。
需要说明的是，在本实施例中，通过调整数据进位信号端STV的信号的高电平的宽度，能够控制移位寄存器单元的输出端Output的信号的高电平的宽度，数据进位信号端STV的信号的高电平的宽度越宽，移位寄存器单元的输出端Output的信号的高电平的宽度越宽。
图4示出根据本公开第二实施例的移位寄存器的结构示意图。请参阅图4，本公开实施例还提供一种移位寄存器，该移位寄存器包括多级上述实施例中的移位寄存器单元。除第一级移位寄存器单元外，其余每级移位寄存器单元的数据进位信号端STV连接与其相邻的上一级移位寄存器单元的本级输出端 Output；除最后一级移位寄存器单元外，其余每级移位寄存器单元的本级输出端Output连接与其相邻的下一级移位寄存器单元的数据进位信号端STV。
例如：如图4所示，第n级移位寄存器单元的输出端Output n与第(n+1)级移位寄存器单元的数据进位信号端STV(n+1)相连。第n级移位寄存器单元的输出端Output n与第(n+1)级移位寄存器单元的输出端Output(n+1)的信号时序请参见图3。
需要说明的是，所述移位寄存器中的移位寄存器单元与上述实施例中的移位寄存器单元具有的优势相同，此处不再赘述。
本公开实施例还提供一种显示装置，所述显示装置包括上述实施例中的移位寄存器，所述显示装置中的移位寄存器与上述实施例中的移位寄存器具有的优势相同，此处不再赘述。示例性地，显示装置可以为有机发光二极管显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年5月21日递交的中国专利申请第201510263844.X号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (8)

  1. 一种移位寄存器单元，包括：
    输入模块(P1)，连接到第一时钟信号端(Clk1)、第二时钟信号端(Clk2)和数据进位信号端(STV)，用于根据第一时钟信号端(Clk1)、第二时钟信号端(Clk2)和数据进位信号端(STV)输入的信号，提供选择信号；
    输出模块(P2)，连接到高电平端(VGH)、低电平端(VGL)、移位寄存器单元的输出端(Output)，用于根据所述输入模块(P1)提供的选择信号，选择在所述输出端(Output)输出高电平或低电平。
  2. 如权利要求1所述的移位寄存器单元，其中，所述输入模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第一电容，所述第一晶体管的栅极连接第一时钟信号端、所述第二晶体管的栅极和所述第三晶体管的漏极，其源极连接所述第三晶体管的栅极、所述第五晶体管的栅极、所述第六晶体管的栅极和所述第二电容的第一端，其漏极连接数据进位信号端；所述第二晶体管的源极连接低电平端，其漏极连接所述第四晶体管的源极、所述第三晶体管的源极和所述第一电容的第一端；所述第三晶体管的漏极连接所述第一时钟信号端；所述第四晶体管的栅极连接第二时钟信号端和所述第一电容的第二端，其源极连接所述第一电容的第一端，其漏极连接所述第五晶体管的漏极、所述第七晶体管的栅极和所述第三电容的第二端。
  3. 如权利要求2所述的移位寄存器单元，其中，所述输出模块包括第五晶体管、第六晶体管、第七晶体管、第二电容和第三电容，所述第五晶体管的栅极连接所述第二电容的第一端和所述第六晶体管的栅极，其源极连接所述第三电容的第一端、所述第七晶体管的漏极和高电平端，其漏极连接所述第三电容的第二端和所述第七晶体管的栅极；所述第六晶体管的栅极连接所述第二电容的第一端，其源极连接低电平端，其漏极连接所述第二电容的第二端、所述第七晶体管的源极和所述移位寄存器单元的输出端；所述第七晶体管的栅极连接所述第三电容的第二端，其源极连接所述第二电容的第二端和所述移位寄存器单元的输出端，其漏极连接第三电容的第一端和高电平端。
  4. 根据权利要求3所述的移位寄存器单元，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为N型晶体管或P型晶体管。
  5. 一种移位寄存器单元的驱动方法，包括：
    由输入模块根据第一时钟信号端、第二时钟信号端和数据进位信号端输入的信号，提供选择信号；
    根据所述输入模块提供的选择信号，选择在移位寄存器单元的输出端输出高电平或低电平。
  6. 如权利要求5所述的驱动方法，包括：
    第一阶段，数据进位信号端的信号与第一时钟信号端的信号均为低电平信号，第二时钟信号端的信号为高电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号开启第六晶体管，并为所述第二电容进行充电，使得所述移位寄存器单元的输出为低电平信号；
    第二阶段，所述第一时钟信号端的信号和所述第二时钟信号端的信号均为高电平信号，所述数据进位信号端的信号为低电平信号，所述第二电容将在所述第一阶段保持的低电平信号提供给所述第六晶体管，并开启所述第六晶体管，使得所述移位寄存器单元的输出为低电平信号；
    第三阶段，所述第一时钟信号端的信号为高电平信号，所述第二时钟信号端的信号与所述数据进位信号端的信号均为低电平信号，高电平端的高电平信号为第三电容进行充电，所述第二电容将在所述第二阶段保持的低电平信号提供给所述第六晶体管，并开启所述第六晶体管，使得所述移位寄存器单元的输出为低电平信号；
    第四阶段，所述第二时钟信号端的信号与所述数据进位信号端的信号均为高电平信号，所述第一时钟信号端的信号为低电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号关闭第六晶体管，并为所述第二电容进行充电，所述第三电容将在所述第三阶段保持的高电平信号提供给所述第七晶体管，并关闭所述第七晶体管，所述移位寄存器单元的输出端的等效电容使得所述移位寄存器单元的输出为低电平信号为高电平信号；
    第五阶段，所述第一时钟信号端与所述数据进位信号端的信号均为高电平信号，所述第二时钟信号端的信号为低电平信号，所述第二电容将在所述第四阶段保持的高电平信号提供给所述第六晶体管，并关闭所述第六晶体管，所述第一电容的自举功能使得第四晶体管的源极为低电平信号，第四晶体管开启，为所述第三电容进行充电，并开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号；
    第六阶段，所述第二时钟信号端与所述数据进位信号端的信号均为高电平信号，所述第一时钟信号端的信号为低电平信号，所述数据进位信号端的信号与所述第一时钟信号端的信号关闭第六晶体管，所述数据进位信号端的信号通过第一晶体管为所述第二电容进行充电，低电平端通过第二晶体管为所述第一电容进行充电，所述第三电容将在所述第五阶段保持的低电平信号提供给所述第七晶体管，开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号；
    第七阶段，所述第一时钟信号端的信号为高电平信号，所述第二时钟信号端与所述数据进位信号端的信号均为低电平信号，所述第二电容将在所述第六阶段保持的高电平信号提供给所述第六晶体管，并关闭所述第六晶体管，所述第二时钟信号端的低电平信号开启所述第四晶体管，所述第一电容将在所述第六阶段保持的低电平信号提供给所述第七晶体管，并开启所述第七晶体管，使得所述移位寄存器单元的输出为高电平信号。
  7. 一种移位寄存器，包括多极上述权利要求1-4中任意一项所述的移位寄存器单元；
    除第一级移位寄存器单元外，其余每级移位寄存器单元的数据进位信号端连接与其相邻的上一级移位寄存器单元的本级输出端；
    除最后一级移位寄存器单元外，其余每级移位寄存器单元的本级输出端连接与其相邻的下一级移位寄存器单元的数据进位信号端。
  8. 一种显示装置，包括上述权利要求7所述的移位寄存器。
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