WO2016206151A1 - 低温多晶硅tft基板结构的制作方法及低温多晶硅tft基板结构 - Google Patents

低温多晶硅tft基板结构的制作方法及低温多晶硅tft基板结构 Download PDF

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WO2016206151A1
WO2016206151A1 PCT/CN2015/084868 CN2015084868W WO2016206151A1 WO 2016206151 A1 WO2016206151 A1 WO 2016206151A1 CN 2015084868 W CN2015084868 W CN 2015084868W WO 2016206151 A1 WO2016206151 A1 WO 2016206151A1
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segment
substrate
amorphous silicon
insulating layer
polysilicon
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French (fr)
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张良芬
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D86/01—Manufacture or treatment
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    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a low temperature polysilicon TFT substrate structure and a low temperature polysilicon TFT substrate structure.
  • LTPS Low Temperature Poly-silicon
  • TFT Thin Film Transistor
  • AMLCD Active Matrix Liquid Crystal Display
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • LTPS TFT Compared with amorphous silicon (a-Si) technology, LTPS TFT has high mobility and good device stability.
  • the mobility of LTPS TFTs can reach tens to hundreds of cm 2 /Vs, which can meet the requirements of high-resolution AMLCD and AMOLED displays. Therefore, the low-temperature polysilicon display has a faster reaction speed and has advantages of high brightness, high resolution, and low power consumption.
  • LTPS TFTs can also be used to build peripheral driver circuits for on-chip integrated systems.
  • Excimer Laser Annealing is a technique in which a laser is used to irradiate a surface of an amorphous silicon to dissolve and recrystallize it. Since the AMOLED driver requires a switching TFT and a driving TFT, the driving TFT should have a relatively uniform electrical property to have a uniform driving capability to prevent a problem of color unevenness during display. This requires a good uniformity of the crystal grains of the polysilicon driving the TFT region, and the size of the crystal grains is large.
  • the current ELA crystallization technology cannot effectively control the grain uniformity and the grain size, so the crystallization condition is uneven in the distribution of the entire substrate, resulting in poor uniformity of the polycrystalline silicon grains in the driving TFT region, and The crystal grains are relatively small, so that the electrical consistency and electrical stability of the driving TFT are poor, which may easily lead to phenomena such as poor image quality.
  • the object of the present invention is to provide a method for fabricating a low-temperature polysilicon TFT substrate structure, which can make the crystal grains of the polysilicon in the driving TFT region have good uniformity, and the crystal grains are relatively large, thereby ensuring electrical consistency of the driving TFT. .
  • Another object of the present invention is to provide a low-temperature polysilicon TFT substrate structure.
  • the crystal grains of the driving TFT region have good grain uniformity, and the crystal grains are relatively large, and the electrical consistency of the driving TFT is good.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate structure, comprising the following steps:
  • Step 1 Providing a substrate, the substrate comprising a switching TFT region and a driving TFT region, depositing a thermally conductive insulating film on the substrate, and patterning the thermally conductive insulating film to obtain a thermal conductive insulation located in the driving TFT region Floor;
  • Step 2 depositing a buffer layer on the substrate, the buffer layer covering the thermally conductive insulating layer;
  • Step 3 depositing an amorphous silicon layer on the buffer layer, and patterning the amorphous silicon layer to obtain a first amorphous silicon segment located in the switching TFT region, and located in the driving TFT region Second amorphous silicon segment;
  • Step 4 performing an excimer laser annealing treatment on the first amorphous silicon segment and the second amorphous silicon segment, so that the first amorphous silicon segment and the second amorphous silicon segment are crystallized and converted into the first plurality a crystalline silicon segment and a second polysilicon segment;
  • Step 5 depositing an interlayer insulating layer on the buffer layer, the interlayer insulating layer covering the first polysilicon segment and the second polysilicon segment;
  • Step 6 depositing a metal layer on the interlayer insulating layer, and patterning the metal layer, respectively forming a first gate corresponding to the first polysilicon segment and the second polysilicon segment With the second grid.
  • the substrate is a glass substrate or a silicon substrate.
  • the material of the thermally conductive insulating layer is magnesium oxide or aluminum oxide.
  • the pattern of the thermally conductive insulating layer is a circular shape or a square shape uniformly distributed and uniform in size.
  • the step 2 is performed by chemical vapor deposition to obtain the buffer layer.
  • the material of the buffer layer is silicon oxide, silicon nitride, or a combination of the two.
  • the step 3 is performed by a vapor deposition method to obtain the amorphous silicon layer.
  • the step 4 performs excimer laser annealing treatment on the first amorphous silicon segment and the second amorphous silicon segment by using a furnace tube, an excimer laser annealing processing device, or a chemical vapor deposition heating chamber.
  • the invention also provides a method for fabricating a low temperature polysilicon TFT substrate structure, comprising the following steps:
  • Step 1 Providing a substrate, the substrate comprising a switching TFT region and a driving TFT region, depositing a thermally conductive insulating film on the substrate, and patterning the thermally conductive insulating film to obtain a thermal conductive insulation located in the driving TFT region Floor;
  • Step 2 depositing a buffer layer on the substrate, the buffer layer covering the thermally conductive insulating layer;
  • Step 3 depositing an amorphous silicon layer on the buffer layer, and patterning the amorphous silicon layer to obtain a first amorphous silicon segment located in the switching TFT region, and located in the driving TFT region Second amorphous silicon segment;
  • Step 4 performing an excimer laser annealing treatment on the first amorphous silicon segment and the second amorphous silicon segment, so that the first amorphous silicon segment and the second amorphous silicon segment are crystallized and converted into the first plurality a crystalline silicon segment and a second polysilicon segment;
  • Step 5 depositing an interlayer insulating layer on the buffer layer, the interlayer insulating layer covering the first polysilicon segment and the second polysilicon segment;
  • Step 6 depositing a metal layer on the interlayer insulating layer, and patterning the metal layer, respectively forming a first gate corresponding to the first polysilicon segment and the second polysilicon segment And a second grid;
  • the substrate is a glass substrate or a silicon substrate
  • the material of the thermally conductive insulating layer is magnesium oxide or aluminum oxide
  • the pattern of the thermally conductive insulating layer is a circular shape or a square shape uniformly distributed and uniform in size.
  • the invention also provides a low temperature polysilicon TFT substrate structure, comprising a switching TFT region and a driving TFT region;
  • the switching TFT region includes a substrate, a buffer layer disposed on the substrate, a first polysilicon segment disposed on the buffer layer, and a buffer layer disposed on the buffer layer to cover the first polysilicon segment An interlayer insulating layer, and a first gate corresponding to the first polysilicon segment disposed on the interlayer insulating layer;
  • the driving TFT region includes a substrate, a thermally conductive insulating layer disposed on the substrate, a buffer layer disposed on the substrate to cover the thermally conductive insulating layer, and a second polysilicon segment disposed on the buffer layer.
  • the substrate is a glass substrate or a silicon substrate; the material of the thermally conductive insulating layer is magnesium oxide or aluminum oxide; the pattern of the thermally conductive insulating layer is a uniformly distributed circle or square; the material of the buffer layer is silicon oxide. , silicon nitride, or a combination of the two.
  • the method for fabricating a low-temperature polysilicon TFT substrate structure of the present invention is characterized in that a regular and uniform thermal conductive insulating layer pattern is disposed under the buffer layer of the driving TFT region, and subsequent excimer laser annealing treatment is performed to make the amorphous During the crystallization of the silicon layer, the thermally conductive insulating layer absorbs heat, thereby accelerating the cooling rate of the amorphous silicon, forming a crystal nucleus, and gradually growing during the annealing process, since the thermally conductive insulating layer has a regular pattern of uniform size, thereby The crystal grains of the polysilicon layer formed in the driving TFT region have good uniformity, and the crystal grains are relatively large, thereby ensuring the electrical consistency of the driving TFT, improving the electrical stability of the driving TFT, and avoiding poor image quality, etc.
  • the phenomenon is produced.
  • the low-temperature polysilicon TFT substrate structure of the invention drives the buffer of the TFT region
  • a pattern of a thermally conductive insulating layer having a regular and uniform size is disposed under the layer, and the polycrystalline silicon layer in the driving TFT region has good grain uniformity, and the crystal grains are relatively large, and the electrical consistency of the driving TFT is good, and electrical stability is good. better.
  • FIG. 1 is a flow chart of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 1 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • FIG. 7 is a schematic view showing the step 6 of the method for fabricating the low-temperature polysilicon TFT substrate structure of the present invention and a cross-sectional view showing the structure of the low-temperature polysilicon TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a low temperature polysilicon TFT substrate structure, including the following steps:
  • a substrate 1 is provided.
  • the substrate 1 includes a switching TFT region and a driving TFT region.
  • a thermally conductive insulating film is deposited on the substrate 1, and the thermally conductive insulating film is patterned.
  • a thermally conductive insulating layer 10 located in the driving TFT region.
  • the substrate 1 may be a glass substrate or a silicon substrate.
  • the material of the thermally conductive insulating layer 10 is magnesium oxide or aluminum oxide.
  • the thermally conductive insulating film is patterned by a photomask,
  • the driving TFT region is provided with a thermally conductive insulating layer 10 of a circular, square, or the like pattern which is uniformly distributed and uniform in size.
  • Step 2 As shown in FIG. 3, a buffer layer 2 is deposited on the substrate 1, and the buffer layer 2 covers the thermally conductive insulating layer 10.
  • the buffer layer 2 is obtained by a chemical vapor deposition (CVD) method.
  • the material of the buffer layer 2 may be silicon oxide, silicon nitride, or a combination of the two.
  • Step 3 depositing an amorphous silicon layer on the buffer layer 2, and patterning the amorphous silicon layer to obtain a first amorphous silicon segment 31 located in the switching TFT region. And a second amorphous silicon segment 32 located in the driving TFT region.
  • the amorphous silicon layer is obtained by a vapor deposition method.
  • Step 4 as shown in FIG. 5, the first amorphous silicon segment 31 and the second amorphous silicon segment 32 are subjected to excimer laser annealing (ELA) to make the first amorphous silicon segment 31.
  • ELA excimer laser annealing
  • the second amorphous silicon segment 32 is crystallized and converted into a first polysilicon segment 301 and a second polysilicon segment 302, respectively.
  • the thermally conductive insulating layer 10 absorbs heat, thereby accelerating the cooling rate of the amorphous silicon, forming a crystal nucleus, and gradually growing during the annealing process, since the thermally conductive insulating layer 10 has regularity and The pattern of uniform size is such that the grains of the second polysilicon segment 302 formed by the driving TFT region have a good uniformity and the crystal grains are relatively large.
  • the first amorphous silicon segment 31 and the second amorphous silicon segment 32 are subjected to excimer laser annealing treatment using a furnace tube, an excimer laser annealing treatment device, or a CVD Heating Chamber.
  • Step 5 As shown in FIG. 6, an interlayer insulating layer 4 is deposited on the buffer layer 2, and the interlayer insulating layer 4 covers the first polysilicon segment 301 and the second polysilicon segment 302.
  • Step 6 depositing a metal layer on the interlayer insulating layer 4, and patterning the metal layer to correspond to the first polysilicon segment 301 and the second polysilicon, respectively.
  • the first gate 51 and the second gate 52 are formed above the segment 302, and subsequent processes such as making source/drain can be implemented by using the prior art.
  • the method for fabricating the low-temperature polysilicon TFT substrate structure is characterized in that a regular and uniform thermal conductive insulating layer pattern is disposed under the buffer layer of the driving TFT region, and heat is transferred during the subsequent excimer laser annealing treatment to crystallize the amorphous silicon layer.
  • the insulating layer absorbs heat, thereby accelerating the cooling rate of the amorphous silicon, forming a crystal nucleus, and gradually growing during the annealing process. Since the thermally conductive insulating layer has a regular and uniform pattern, the polysilicon layer formed by the driving TFT region is formed.
  • the crystal grains have good uniformity and the crystal grains are relatively large, which ensures the electrical consistency of the driving TFT, improves the electrical stability of the driving TFT, and avoids the occurrence of poor image quality and the like.
  • the present invention also provides a low temperature polysilicon TFT substrate structure including a switching TFT region and a driving TFT region.
  • the switching TFT region includes a substrate 1 , a buffer layer 2 disposed on the substrate 1 , a first polysilicon segment 301 disposed on the buffer layer 2 , and a buffer layer 2 disposed on the buffer layer 2
  • the driving TFT region includes a substrate 1 , a thermally conductive insulating layer 10 disposed on the substrate 1 , a buffer layer 2 disposed on the substrate 1 and covering the thermally conductive insulating layer 10 , and a buffer layer 2 disposed on the buffer layer 2 .
  • the second gate 52 on the insulating layer 4.
  • the substrate 1 is a glass substrate or a silicon substrate.
  • the material of the thermally conductive insulating layer 10 is magnesium oxide or aluminum oxide.
  • the pattern of the thermally conductive insulating layer 10 is a circular, square, or other pattern uniformly distributed and uniform in size.
  • the material of the buffer layer 2 is silicon oxide, silicon nitride, or a combination of the two.
  • a pattern of a thermally conductive insulating layer having a regular and uniform size is disposed under the buffer layer of the driving TFT region, and the polycrystalline silicon layer in the driving TFT region has a good grain uniformity and a relatively large crystal grain, and the driving TFT is driven.
  • the electrical consistency is good and the electrical stability is good.
  • the low-temperature polysilicon TFT substrate structure of the present invention is fabricated by performing a subsequent excimer laser annealing treatment to form amorphous silicon by providing a pattern of a uniform and uniform thermal conductive insulating layer under the buffer layer of the driving TFT region.
  • the thermally conductive insulating layer absorbs heat, thereby accelerating the cooling rate of the amorphous silicon, forming a crystal nucleus, and gradually growing during the annealing process, since the thermally conductive insulating layer has a regular and uniform pattern, thereby driving
  • the crystal grains of the polysilicon layer formed in the TFT region have good uniformity, and the crystal grains are relatively large, thereby ensuring the electrical consistency of the driving TFT, improving the electrical stability of the driving TFT, and avoiding poor image quality and the like. The production.
  • a pattern of a thermally conductive insulating layer having a regular and uniform size is disposed under the buffer layer of the driving TFT region, and the polycrystalline silicon layer in the driving TFT region has good grain uniformity and a relatively large crystal grain.
  • the driving TFT has good electrical consistency and good electrical stability.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

一种低温多晶硅TFT基板结构的制作方法及低温多晶硅TFT基板结构，低温多晶硅TFT基板结构的制作方法通过在驱动TFT区域的缓冲层（2）下方设置有规律且大小一致的导热绝缘层图案，使其在后续准分子激光退火处理过程中吸收热量，从而使非晶硅的冷却速度加快，形成晶核，并在退火过程逐渐生长，由于导热绝缘层（10）具有规律且大小一致的图案，从而使驱动TFT区域形成的多晶硅的晶粒具有较好的一致性，且晶粒相对较大，保证了驱动TFT的电性一致性。低温多晶硅TFT基板结构包括在驱动TFT区域的缓冲层（2）下方设置有规律且大小一致的导热绝缘层图案，驱动TFT区域的多晶硅的晶粒一致性较好，且晶粒相对较大，驱动TFT的电性一致性较好。

Description

低温多晶硅TFT基板结构的制作方法及低温多晶硅TFT基板结构 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板结构的制作方法及低温多晶硅TFT基板结构。
背景技术
低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)在高分辨率有源液晶显示(Active MatrixLiquid Crystal Display，AMLCD)以及有机发光二极管(Active-Matrix Organic Light Emitting Diode，AMOLED)显示器领域有很大的应用价值和潜力。
与非晶硅(a-Si)技术相比，LTPS TFT的迁移率高，器件稳定性好。LTPS TFT的迁移率可达几十至几百cm2/Vs，可以满足高分辨率AMLCD及AMOLED显示器的要求。因此，低温多晶硅显示器的反应速度较快，且有高亮度、高解析度与低耗电量等优点。除了作为像素开关，LTPS TFT还可以构建周边驱动电路，实现片上集成系统。
准分子激光退火处理(Excimer Laser Annealing，ELA)是利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶的技术。因为AMOLED驱动需要开关TFT和驱动TFT，其中，驱动TFT应具有较一致的电性从而具有一致的驱动能力，以防止在显示过程中导致颜色不均等问题。这就需要驱动TFT区域的多晶硅的晶粒具有较好的一致性，并且晶粒的尺寸较大。
然而目前的ELA结晶技术对于晶粒的一致性和晶粒的大小不能做到有效控制，所以结晶状况在整个基板的分布上很不均匀，导致驱动TFT区域多晶硅晶粒的一致性较差，且晶粒相对较小，使得驱动TFT的电性一致性和电性稳定性较差，容易导致画质不良等现象的产生。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板结构的制作方法，可以使驱动TFT区域的多晶硅的晶粒具有较好的一致性，且晶粒相对较大，可保证驱动TFT的电性一致性。
本发明的目的还在于提供一种低温多晶硅TFT基板结构，驱动TFT区域的多晶硅的晶粒一致性较好，且晶粒相对较大，驱动TFT的电性一致性较好。
为实现上述目的，本发明提供一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括开关TFT区域与驱动TFT区域，在所述基板上沉积导热绝缘薄膜，并对所述导热绝缘薄膜进行图案化处理，得到位于所述驱动TFT区域的导热绝缘层；
步骤2、在所述基板上沉积缓冲层，所述缓冲层覆盖所述导热绝缘层；
步骤3、在所述缓冲层上沉积非晶硅层，并对所述非晶硅层进行图案化处理，得到位于所述开关TFT区域的第一非晶硅段、及位于所述驱动TFT区域的第二非晶硅段；
步骤4、对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理，使所述第一非晶硅段、第二非晶硅段结晶，分别转变为第一多晶硅段、第二多晶硅段；
步骤5、在所述缓冲层上沉积层间绝缘层，所述层间绝缘层覆盖所述第一多晶硅段、第二多晶硅段；
步骤6、在所述层间绝缘层上沉积金属层，并对所述金属层进行图案化处理，分别对应所述第一多晶硅段、第二多晶硅段的上方形成第一栅极与第二栅极。
所述基板为玻璃基板或硅基板。
所述导热绝缘层的材料为氧化镁或氧化铝。
所述导热绝缘层的图案为均匀分布且大小一致的圆形、或方形。
所述步骤2采用化学气相沉积法制得所述缓冲层。
所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
所述步骤3采用气相沉积法制得所述非晶硅层。
所述步骤4采用炉管、准分子激光退火处理设备、或化学气相沉积加热室对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理。
本发明还提供一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括开关TFT区域与驱动TFT区域，在所述基板上沉积导热绝缘薄膜，并对所述导热绝缘薄膜进行图案化处理，得到位于所述驱动TFT区域的导热绝缘层；
步骤2、在所述基板上沉积缓冲层，所述缓冲层覆盖所述导热绝缘层；
步骤3、在所述缓冲层上沉积非晶硅层，并对所述非晶硅层进行图案化处理，得到位于所述开关TFT区域的第一非晶硅段、及位于所述驱动TFT区域的第二非晶硅段；
步骤4、对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理，使所述第一非晶硅段、第二非晶硅段结晶，分别转变为第一多晶硅段、第二多晶硅段；
步骤5、在所述缓冲层上沉积层间绝缘层，所述层间绝缘层覆盖所述第一多晶硅段、第二多晶硅段；
步骤6、在所述层间绝缘层上沉积金属层，并对所述金属层进行图案化处理，分别对应所述第一多晶硅段、第二多晶硅段的上方形成第一栅极与第二栅极；
其中，所述基板为玻璃基板或硅基板；
其中，所述导热绝缘层的材料为氧化镁或氧化铝；
其中，所述导热绝缘层的图案为均匀分布且大小一致的圆形、或方形。
本发明还提供一种低温多晶硅TFT基板结构，包括开关TFT区域和驱动TFT区域；
所述开关TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层上覆盖所述第一多晶硅段的层间绝缘层、及对应所述第一多晶硅段上方设于所述层间绝缘层上的第一栅极；
所述驱动TFT区域包括基板、设于所述基板上的导热绝缘层、设于所述基板上覆盖所述导热绝缘层的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层上覆盖所述第二多晶硅段的层间绝缘层、及对应所述第二多晶硅段上方设于所述层间绝缘层上的第二栅极。
所述基板为玻璃基板或硅基板；所述导热绝缘层的材料为氧化镁或氧化铝；所述导热绝缘层的图案为均匀分布的圆形、或方形；所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
本发明的有益效果：本发明的低温多晶硅TFT基板结构的制作方法，通过在驱动TFT区域的缓冲层下方设置有规律且大小一致的导热绝缘层图案，在进行后续准分子激光退火处理使非晶硅层结晶的过程中，导热绝缘层会吸收热量，从而使非晶硅的冷却速度加快，形成晶核，并在退火过程逐渐生长，由于导热绝缘层具有有规律且大小一致的图案，从而使驱动TFT区域形成的多晶硅层的晶粒具有较好的一致性，且晶粒相对较大，保证了驱动TFT的电性一致性，提升了驱动TFT的电性稳定性，避免了画质不良等现象的产生。本发明的低温多晶硅TFT基板结构，驱动TFT区域的缓冲 层下方设置有有规律且大小一致的导热绝缘层图案，驱动TFT区域的多晶硅层的晶粒一致性较好，且晶粒相对较大，驱动TFT的电性一致性较好，电性稳定性较好。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的低温多晶硅TFT基板结构的制作方法的流程图；
图2为本发明的低温多晶硅TFT基板结构的制作方法的步骤1的示意图；
图3为本发明的低温多晶硅TFT基板结构的制作方法的步骤2的示意图；
图4为本发明的低温多晶硅TFT基板结构的制作方法的步骤3的示意图；
图5为本发明的低温多晶硅TFT基板结构的制作方法的步骤4的示意图；
图6为本发明的低温多晶硅TFT基板结构的制作方法的步骤5的示意图；
图7为本发明的低温多晶硅TFT基板结构的制作方法的步骤6的示意图暨本发明的低温多晶硅TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
步骤1、如图2所示，提供基板1，所述基板1包括开关TFT区域与驱动TFT区域，在所述基板1上沉积导热绝缘薄膜，并对所述导热绝缘薄膜进行图案化处理，得到位于所述驱动TFT区域的导热绝缘层10。
具体的，所述基板1可以是玻璃基板或硅基板。
具体的，所述导热绝缘层10的材料为氧化镁或氧化铝。
具体的，通过一道光罩对所述导热绝缘薄膜进行图案化处理，于所述 驱动TFT区域得到呈均匀分布且大小一致的圆形、方形等图案的导热绝缘层10。
步骤2、如图3所示，在所述基板1上沉积缓冲层2，所述缓冲层2覆盖所述导热绝缘层10。
具体的，采用化学气相沉积(CVD)法制得所述缓冲层2。
具体的，所述缓冲层2的材料可以是氧化硅、氮化硅、或二者的组合。
步骤3、如图4所示，在所述缓冲层2上沉积非晶硅层，并对所述非晶硅层进行图案化处理，得到位于所述开关TFT区域的第一非晶硅段31、及位于所述驱动TFT区域的第二非晶硅段32。
具体的，采用气相沉积法制得所述非晶硅层。
步骤4、如图5所示，对所述第一非晶硅段31、第二非晶硅段32进行准分子激光退火处理(Excimer Laser Annealer，ELA)使所述第一非晶硅段31、第二非晶硅段32结晶，分别转变为第一多晶硅段301、第二多晶硅段302。
在准分子激光退火处理的过程中，所述导热绝缘层10会吸收热量，从而使非晶硅的冷却速度加快，形成晶核，并在退火过程逐渐生长，由于导热绝缘层10具有有规律且大小一致的图案，从而使驱动TFT区域形成的第二多晶硅段302的晶粒具有较好的一致性，且晶粒相对较大。
具体的，采用炉管、准分子激光退火处理设备、或化学气相沉积加热室(CVD Heating Chamber)对所述第一非晶硅段31、第二非晶硅段32进行准分子激光退火处理。
步骤5、如图6所示，在所述缓冲层2上沉积层间绝缘层4，所述层间绝缘层4覆盖所述第一多晶硅段301、第二多晶硅段302。
步骤6、如图7所示，在所述层间绝缘层4上沉积金属层，并对所述金属层进行图案化处理，分别对应所述第一多晶硅段301、第二多晶硅段302的上方形成第一栅极51与第二栅极52，后续制作源/漏极等制程均可以采用现有技术实现。
上述低温多晶硅TFT基板结构的制作方法，通过在驱动TFT区域的缓冲层下方设置有规律且大小一致的导热绝缘层图案，在进行后续准分子激光退火处理使非晶硅层结晶的过程中，导热绝缘层会吸收热量，从而使非晶硅的冷却速度加快，形成晶核，并在退火过程逐渐生长，由于导热绝缘层具有有规律且大小一致的图案，从而使驱动TFT区域形成的多晶硅层的晶粒具有较好的一致性，且晶粒相对较大，保证了驱动TFT的电性一致性，提升了驱动TFT的电性稳定性，避免了画质不良等现象的产生。
请参阅图7，本发明还提供一种低温多晶硅TFT基板结构，包括开关TFT区域和驱动TFT区域。
所述开关TFT区域包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的第一多晶硅段301、设于所述缓冲层2上覆盖所述第一多晶硅段301的层间绝缘层4、及对应所述第一多晶硅段301上方设于所述层间绝缘层4上的第一栅极51。
所述驱动TFT区域包括基板1、设于所述基板1上的导热绝缘层10、设于所述基板1上覆盖所述导热绝缘层10的缓冲层2、设于所述缓冲层2上的第二多晶硅段302、设于所述缓冲层2上覆盖所述第二多晶硅段302的层间绝缘层4、及对应所述第二多晶硅段302上方设于所述层间绝缘层4上的第二栅极52。
具体的，所述基板1为玻璃基板或硅基板。
具体的，所述导热绝缘层10的材料为氧化镁或氧化铝。
具体的，所述导热绝缘层10的图案为均匀分布且大小一致的圆形、方形、或者其他图形。
具体的，所述缓冲层2的材料为氧化硅、氮化硅、或二者的组合。
上述低温多晶硅TFT基板结构，驱动TFT区域的缓冲层下方设置有有规律且大小一致的导热绝缘层图案，驱动TFT区域的多晶硅层的晶粒一致性较好，且晶粒相对较大，驱动TFT的电性一致性较好，电性稳定性较好。
综上所述，本发明的低温多晶硅TFT基板结构的制作方法，通过在驱动TFT区域的缓冲层下方设置有规律且大小一致的导热绝缘层图案，在进行后续准分子激光退火处理使非晶硅层结晶的过程中，导热绝缘层会吸收热量，从而使非晶硅的冷却速度加快，形成晶核，并在退火过程逐渐生长，由于导热绝缘层具有有规律且大小一致的图案，从而使驱动TFT区域形成的多晶硅层的晶粒具有较好的一致性，且晶粒相对较大，保证了驱动TFT的电性一致性，提升了驱动TFT的电性稳定性，避免了画质不良等现象的产生。本发明的低温多晶硅TFT基板结构，驱动TFT区域的缓冲层下方设置有有规律且大小一致的导热绝缘层图案，驱动TFT区域的多晶硅层的晶粒一致性较好，且晶粒相对较大，驱动TFT的电性一致性较好，电性稳定性较好。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (15)

  1. 一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括开关TFT区域与驱动TFT区域，在所述基板上沉积导热绝缘薄膜，并对所述导热绝缘薄膜进行图案化处理，得到位于所述驱动TFT区域的导热绝缘层；
    步骤2、在所述基板上沉积缓冲层，所述缓冲层覆盖所述导热绝缘层；
    步骤3、在所述缓冲层上沉积非晶硅层，并对所述非晶硅层进行图案化处理，得到位于所述开关TFT区域的第一非晶硅段、及位于所述驱动TFT区域的第二非晶硅段；
    步骤4、对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理，使所述第一非晶硅段、第二非晶硅段结晶，分别转变为第一多晶硅段、第二多晶硅段；
    步骤5、在所述缓冲层上沉积层间绝缘层，所述层间绝缘层覆盖所述第一多晶硅段、第二多晶硅段；
    步骤6、在所述层间绝缘层上沉积金属层，并对所述金属层进行图案化处理，分别对应所述第一多晶硅段、第二多晶硅段的上方形成第一栅极与第二栅极。
  2. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述基板为玻璃基板或硅基板。
  3. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述导热绝缘层的材料为氧化镁或氧化铝。
  4. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述导热绝缘层的图案为均匀分布且大小一致的圆形、或方形。
  5. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤2采用化学气相沉积法制得所述缓冲层。
  6. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
  7. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤3采用气相沉积法制得所述非晶硅层。
  8. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤4采用炉管、准分子激光退火处理设备、或化学气相沉积加热室对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理。
  9. 一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括开关TFT区域与驱动TFT区域，在所述基板上沉积导热绝缘薄膜，并对所述导热绝缘薄膜进行图案化处理，得到位于所述驱动TFT区域的导热绝缘层；
    步骤2、在所述基板上沉积缓冲层，所述缓冲层覆盖所述导热绝缘层；
    步骤3、在所述缓冲层上沉积非晶硅层，并对所述非晶硅层进行图案化处理，得到位于所述开关TFT区域的第一非晶硅段、及位于所述驱动TFT区域的第二非晶硅段；
    步骤4、对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理，使所述第一非晶硅段、第二非晶硅段结晶，分别转变为第一多晶硅段、第二多晶硅段；
    步骤5、在所述缓冲层上沉积层间绝缘层，所述层间绝缘层覆盖所述第一多晶硅段、第二多晶硅段；
    步骤6、在所述层间绝缘层上沉积金属层，并对所述金属层进行图案化处理，分别对应所述第一多晶硅段、第二多晶硅段的上方形成第一栅极与第二栅极；
    其中，所述基板为玻璃基板或硅基板；
    其中，所述导热绝缘层的材料为氧化镁或氧化铝；
    其中，所述导热绝缘层的图案为均匀分布且大小一致的圆形、或方形。
  10. 如权利要求9所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤2采用化学气相沉积法制得所述缓冲层。
  11. 如权利要求9所述的低温多晶硅TFT基板结构的制作方法，其中，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
  12. 如权利要求9所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤3采用气相沉积法制得所述非晶硅层。
  13. 如权利要求9所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤4采用炉管、准分子激光退火处理设备、或化学气相沉积加热室对所述第一非晶硅段、第二非晶硅段进行准分子激光退火处理。
  14. 一种低温多晶硅TFT基板结构，包括开关TFT区域和驱动TFT区域；
    所述开关TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层上覆盖所述第一多晶硅段的层间绝缘层、及对应所述第一多晶硅段上方设于所述层间绝缘层上的第一栅极；
    所述驱动TFT区域包括基板、设于所述基板上的导热绝缘层、设于所 述基板上覆盖所述导热绝缘层的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层上覆盖所述第二多晶硅段的层间绝缘层、及对应所述第二多晶硅段上方设于所述层间绝缘层上的第二栅极。
  15. 如权利要求14所述的低温多晶硅TFT基板结构，其中，所述基板为玻璃基板或硅基板；所述导热绝缘层的材料为氧化镁或氧化铝；所述导热绝缘层的图案为均匀分布的圆形、或方形；所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
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