WO2016203967A1 - 半導体装置、電子機器、並びに製造方法 - Google Patents
半導体装置、電子機器、並びに製造方法 Download PDFInfo
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- WO2016203967A1 WO2016203967A1 PCT/JP2016/066348 JP2016066348W WO2016203967A1 WO 2016203967 A1 WO2016203967 A1 WO 2016203967A1 JP 2016066348 W JP2016066348 W JP 2016066348W WO 2016203967 A1 WO2016203967 A1 WO 2016203967A1
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Definitions
- the present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method, and more particularly, to a semiconductor device, an electronic device, and a manufacturing method that can maintain underfill mounting reliability.
- underfill resin (UF resin) is filled between the chip and the substrate in order to improve mounting reliability. Since UF resin usually crawls to the side of the chip, there is a risk of breakage of the chip end.
- CSP Chip Size Package
- CIS CMOS Image Sensor
- the present disclosure has been made in view of such a situation, and can maintain the mounting reliability of the underfill.
- a semiconductor device includes a first substrate on which a circuit is formed, a second substrate made of a material different from the first substrate, and the second substrate on the first substrate.
- a CSP Chip Size ⁇ ⁇ Package
- the CSP includes an underfill used for mounting on the mounting substrate. It is formed in a structure that does not adhere to the side walls of the second substrate.
- the CSP is formed in a structure in which the underfill is not adhered to a part or almost all of the side wall of the CSP.
- the CSP is formed in such a structure that the underfill is not adhered to a part or almost all of the side wall of the CSP by removing the photosensitive material formed on a part or all of the side wall of the CSP. .
- the CSP is formed in a structure in which the underfill is not adhered to a part or almost all of the side wall of the CSP by forming a hydrophobic material on part or almost all of the side wall of the CSP.
- the CSP is formed in a structure that prevents the underfill from adhering to the side wall of the second substrate by forming one or more irregularities on a part of the side wall of the first substrate.
- the bottom surface of the first substrate is exposed, a through-hole for connecting to the connection pad of the circuit is opened, the insulating film of the first substrate is deposited, the connection pad is exposed, and a rewiring is formed Thereafter, a creeping prevention pattern is formed, and after the insulating film portion is formed, the creeping prevention pattern is removed, and a recess is formed in the insulating film portion, whereby a part of the side wall of the first substrate or One or more irregularities are formed on substantially the entire surface.
- the creeping prevention pattern is arranged across the parts to be separated.
- the bottom surface of the first substrate is exposed, a through-hole for connecting to the connection pad of the circuit is opened, the insulating film of the first substrate is deposited, the connection pad is exposed, and a rewiring is formed Then, after forming the insulating film portion and opening the first substrate, the first substrate is retracted, whereby a part of or substantially all of the sidewalls of the first substrate is made uneven. Form one or more.
- the retracted portion of the first substrate is disposed across the part to be separated.
- an image sensor and a logic circuit are formed as the circuit, exposing a bottom surface of the first substrate, and opening a through hole for connecting to a connection pad of the circuit, After depositing the insulating film of the first substrate, exposing the connection pads, forming rewiring, forming an insulating film portion, opening an interlayer insulating film of the logic circuit, and then interlayer insulating the logic circuit.
- the receded portion of the interlayer insulating film of the logic circuit is disposed across the part to be separated.
- a manufacturing apparatus includes a first substrate on which a circuit is formed, a second substrate made of a material different from the first substrate, and the first substrate.
- An underfill used when mounting a CSP (Chip Size Package) composed of a bonding portion for bonding the second substrate on a mounting substrate for mounting the CSP is adhered to the side wall of the second substrate. It is formed in a structure that does not.
- An electronic device includes a first substrate on which a circuit is formed, a second substrate made of a material different from the first substrate, and the second substrate on the first substrate.
- a CSP Chip Size ⁇ ⁇ Package
- the CSP includes an underfill used for mounting on the mounting substrate.
- a solid-state imaging device formed in a structure that is not bonded to the side wall of the substrate, a signal processing circuit that processes an output signal output from the solid-state imaging device, and an optical system that makes incident light incident on the solid-state imaging device; Have
- the first substrate on which a circuit is formed the second substrate made of a material different from the first substrate, and the second substrate on the first substrate.
- a CSP Chip Size Package
- a CSP composed of a bonding portion to be bonded is formed in a structure that does not adhere to an underfill used for mounting on a mounting substrate for mounting the CSP and a side wall of the second substrate.
- the mounting reliability of the underfill can be maintained.
- FIG. 1 It is a block diagram which shows the schematic structural example of the solid-state imaging device to which this technique is applied. It is sectional drawing which shows the structural example of CPS of the image pick-up element of this technique. It is a flowchart explaining the manufacturing process of CPS of FIG. It is a flowchart explaining the manufacturing process of CPS of FIG. It is a flowchart explaining the manufacturing process of CPS of FIG. It is a figure which shows the example of a process of the manufacturing process of CPS of FIG. It is a figure which shows the example of a process of the manufacturing process of CPS of FIG. It is a figure which shows the example of a process of the manufacturing process of CPS of FIG. It is a figure which shows the example of a process of the manufacturing process of CPS of FIG. It is a figure which shows the example of a process of the manufacturing process of CPS of FIG.
- FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.
- CMOS complementary metal oxide semiconductor
- a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.
- the pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors).
- the plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.
- the pixel 2 can have a pixel sharing structure.
- the pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared.
- the photodiode is a photoelectric conversion element.
- the peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
- the control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.
- the vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.
- the column signal processing circuit 5 is disposed, for example, for each column of the pixels 2 and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixel 2, signal amplification, A / D (Analog / Digital) conversion, and the like. .
- a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.
- the horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
- the output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.
- the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
- the input / output terminal 12 is provided for exchanging signals with the outside.
- FIG. 2 is a cross-sectional view showing a structural example of a CPS (Chip Scale Package) of the imaging device of the present technology.
- CPS Chip Scale Package
- a circuit of an image sensor is created on the Si substrate 22 which is the first substrate, and a second substrate 24 is created on the adhesive 23 formed on the circuit. Is formed.
- the circuit may be a circuit other than the image sensor.
- a photosensitive material (photosensitive material 31 in FIG. 6B) is formed around the chip 26 after being mounted on the mounting substrate 21 with the solder balls 27 or in the state of the chip 26.
- a photosensitive material photosensitive material 31 in FIG. 6B
- step S11 the manufacturing apparatus prepares the Si substrate 22 (A in FIG. 5), and creates a predetermined circuit (such as an image sensor circuit) on the Si substrate 22.
- a predetermined circuit such as an image sensor circuit
- the manufacturing apparatus forms an adhesive 23 (B in FIG. 5) on the created circuit.
- the adhesive 23 is a resin such as acrylic, epoxy, or silicon, or a composite thereof, and the type is not limited.
- the film thickness is preferably about 5 to 100 um. If it is too thin, adhesive strength and TTV (total thickness variation) of the Si substrate cannot be included, and if it is too thick, it becomes difficult to control the wafer warp and the tilt of the second substrate to be joined thereafter.
- step S13 the manufacturing apparatus forms the second substrate 24 (for example, glass, other acrylic transparent cured resin, quartz, Si, etc.) on the adhesive 23 as shown in FIG. 5C.
- the In step S14 although not shown, the manufacturing apparatus forms TSV (Through-Silicon Via) on the back surface of the Si substrate 22, forms a wiring layer, and is electrically connected to the circuit formed on the Si substrate 22. .
- step S15 the manufacturing apparatus cuts 30 (A in FIG. 6) into the scribe line on the back surface of the Si substrate 22 by dicing.
- dicing using a blade is performed.
- Dicing is for physically providing a space (cut 30) in the scribe line, and other methods for providing the space in the scribe line include, but are not limited to, dry etching, wet etching, laser ablation, and the like.
- the dicing width depends on the width of the scribe line and is usually 40 to 200 ⁇ m.
- the depth of dicing should be such that the first substrate (Si substrate 22) and the second substrate 24 are handled and are not damaged at the wafer level.
- the manufacturing apparatus usually leaves 100 to 300 ⁇ m of the second substrate 24 or temporarily attaches a support substrate (not shown) on the second substrate 24 to fully cut the second substrate 24.
- step S16 the manufacturing apparatus coats and vacuum embeds a photosensitive material 31 (eg, photosensitive resist, photosensitive insulating material, photosensitive resin, etc.) on the Si substrate 22, as shown in FIG. 6B.
- a photosensitive material 31 eg, photosensitive resist, photosensitive insulating material, photosensitive resin, etc.
- the scribe line is embedded in the cut 30 by a method such as the above.
- the photosensitive material 31 is also formed on the Si substrate 22.
- step S17 the manufacturing apparatus selectively removes the photosensitive material 31 by lithography 32 (C in FIG. 6) as shown in FIG. 7A in order to leave the photosensitive material 31 on the scribe line.
- the photosensitive material 31 is used.
- a resin or the like that dissolves in a chemical solution may be used.
- the surface of the second substrate 24 may be entirely removed by plasma processing or the like instead of lithography. Is possible.
- step S17 any method may be used, such as selectively leaving the photosensitive material 31 on the scribe line in the lithography 32 or selectively leaving it in the plasma processing. It is important to leave the photosensitive material 31 only on the scribe line.
- step S18 the manufacturing apparatus forms solder balls 27 (B in FIG. 7) as connection terminals on the Si substrate 22.
- a temperature at which the photosensitive material 31 does not change when the solder ball 27 is formed For example, it is set to 250 degrees or less. Depending on the heat-resistant temperature of the photosensitive material 31, this is not restrictive.
- step S19 the manufacturing apparatus cuts the scribe line (cut 30) on the back surface of the Si substrate 22 again by dicing.
- dicing using a blade is performed.
- Dicing is for separating the chips, and the method is not limited to this. For example, dry etching, wet etching, laser ablation, or the like is also used.
- the dicing width depends on the width of the scribe line and is not limited, but is usually 40 to 200 um.
- the second substrate 24 is also completely separated for each chip 26 by this dicing. At that time, the photosensitive material 31 on the side wall of the chip 26 is left.
- step S20 the manufacturing apparatus connects the chip 26 to the mounting substrate 21 by reflow as shown in FIG.
- step S20 the manufacturing apparatus connects the chip 26 to the mounting substrate 21 by reflow as shown in FIG.
- step S20 the manufacturing apparatus connects the chip 26 to the mounting substrate 21 by reflow as shown in FIG.
- step S21 the manufacturing apparatus forms the underfill 25 (B in FIG. 8) in order to stably fix the chip 26 to the mounting substrate 21.
- the underfill 25 is formed under conditions that do not cover the surface of the second substrate 24.
- step S22 the manufacturing apparatus removes the photosensitive material 31 formed on the side wall of the chip 26 by a solvent or plasma treatment.
- FIG. 9 is a cross-sectional view showing another structural example of CPS (Chip Scale Package) of the image sensor of FIG. Note that, in the example of FIG. 9, parts corresponding to those in the example of FIG.
- the hydrophobic material 61 is formed on the side wall of the chip 26 after the chip 26 is mounted on the mounting substrate 21 with the solder balls 27 or in the state of the chip 26.
- An underfill 25 is formed between the bottom surface of the chip 26 (the solder ball 27 surface) and the mounting substrate 21.
- the chip 26 is configured such that an image pickup device circuit is formed on the Si substrate 22 which is the first substrate, and the second substrate is formed on the adhesive 23 formed on the circuit. 24 is created and formed.
- the hydrophobic material 61 is formed at the end portion of the chip 26, the adhesive underfill 25 is not formed at the end of the chip. That is, the underfill 25 is hardly adhered to the side wall of the CPS 51. Therefore, the influence of expansion / contraction of the underfill 25 bonded to the substrate can be prevented from being exerted on the chip end.
- Steps S51 to S60 in FIGS. 10 and 11 are basically the same as steps S11 to S20 in FIGS. 3 and 4 except that the photosensitive material 31 is replaced with the hydrophobic material 61. Is omitted because it is repeated.
- step S60 the manufacturing apparatus connects the chip 26 to the mounting substrate 21 by reflow as shown in FIG.
- step S61 the manufacturing apparatus forms the underfill 25 (B in FIG. 12) in order to stably fix the chip 26 to the mounting substrate 21.
- a hydrophobic material 61 is used for the side wall of the chip 26.
- a fluoride material is used for the hydrophobic material 61. Since the fluoride material includes many hydrophobic materials such as UF material epoxy, silicon, and phenol resin, the underfill 25 does not go up to the side wall of the chip 26.
- the underfill 25 does not crawl up on the side wall portion of the chip 26, a space that cannot be formed is formed, and the bottom surface (surface of the solder ball 27) of the chip 26 is stably fixed. That is, the underfill 25 is hardly adhered to the side wall of the CPS 15. Therefore, peeling of the chip side wall can be suppressed without impairing the original function of the underfill 25.
- the underfill resin to be physically bonded is not formed at the chip end. Therefore, the expansion / contraction of the underfill bonded to the mounting substrate is not affected on the chip end.
- FIG. 13 is a cross-sectional view showing a structural example of a CPS (Chip Scale Package) of the imaging device of the present technology.
- CPS Chip Scale Package
- the underfill 125 is filled between the chip 120 and the mounting substrate 126.
- the chip 120 is formed by forming a glass substrate 122 on a bonding resin 123 formed on the image sensor 121.
- the image pickup device 121 is composed of, in order from the top, an Si substrate 131 on which an image pickup device circuit is formed, an insulating film 132, and an insulating film 133 formed after the rewiring is formed.
- a recess 134 is formed on the end face (side wall) of the insulating film 133 in a direction parallel to the upper and lower surfaces of the chip 120.
- the height of the underfill 125 is not more than the imaging element 121, that is, not more than the dotted line shown in FIG. 13, and does not reach the side surface of the bonding resin 123. Therefore, the underfill 125 does not adhere to the side surface of the bonding resin 123. Thereby, the creeping of the side surface of the underfill 125 can be suppressed, and the mounting reliability can be improved.
- step S111 the manufacturing apparatus applies the CPS 111 of the semiconductor element (chip) 120 in which the imaging element 121 and the glass substrate 122 are bonded to each other with the bonding resin 123 to the Si substrate 131 opposite to the light receiving surface (upper in the drawing).
- a through-hole 144 is opened in order to expose the surface to form a thin film and connect it to a connection pad of the element.
- step S112 the manufacturing apparatus deposits an insulating film 132 for insulating from the Si substrate 131, exposes the connection pads 141 using a technique such as etch back, and then forms the rewiring 143 (FIG. 16). A).
- the manufacturing apparatus forms a scooping prevention pattern 151 (B in FIG. 16) to prevent scooping of the underfill.
- the creeping prevention pattern 151 include an insulating film such as Si02 and SiC, and metal films such as AL, Ti, and W. Since the material is removed in a later process, the material is not particularly limited as long as the material is easy to be removed and formed. And a manufacturing apparatus arrange
- step S114 the manufacturing apparatus then forms an insulating film 133 (A in FIG. 17).
- the manufacturing apparatus forms by performing heat treatment after patterning by lithography using a solder mask resist.
- step S115 the manufacturing apparatus also forms a slit opening 162 when patterning by lithography, and exposes the creeping prevention pattern 151.
- step S116 the manufacturing apparatus removes the creeping prevention pattern 151 and removes it using a technique such as WET etching to form a recess 134 that is recessed from the side surface of the insulating film 132 (FIG. 17B). This is set back from the end face of the insulating film 132.
- step S117 the manufacturing apparatus straddles the part to be singulated and forms the slit 181 (A in FIG. 18) in the image sensor 121.
- step S118 the solder ball 124 which is an external terminal is formed.
- step S119 the manufacturing apparatus is singulated as chips 120 using a technique such as dicing.
- step S120 the manufacturing apparatus mounts the chip 120 on the mounting substrate 126 and fills the underfill 125.
- the concave portion 134 is formed on the end surface (side portion) of the image sensor 121 (the insulating film 132), the underfill 125 can be prevented from creeping up. As a result, the height of the underfill 125 becomes equal to or less than the height of the image sensor 121, and no underfill is formed on the side surface of the glass substrate 122.
- the scooping prevention pattern is created after the rewiring is formed.
- the order of the creating processes such as creating before the rewiring is not limited to this.
- FIG. 21 is a cross-sectional view showing another structural example of CPS (Chip Scale Package) of the image sensor of FIG. Note that, in the example of FIG. 21, parts corresponding to those in the example of FIG.
- the underfill 125 is filled between the chip 120 and the mounting board 126.
- the chip 120 is formed by forming a glass substrate 122 on a bonding resin 123 formed on the image sensor 221.
- the image sensor 221 includes, in order from the top, the insulating film 140, the Si substrate 131 on which the circuit of the image sensor is formed, the insulating film 132, and the insulation formed after the rewiring is formed.
- a recess portion 222 is formed on the end surface (side wall) of the Si substrate 131 in a direction parallel to the upper and lower surfaces of the chip 120.
- the height of the underfill 125 is not more than the image sensor 221, that is, not more than the dotted line shown in FIG. 21, and does not reach the side surface of the bonding resin 123. Thereby, the creeping of the side surface of the underfill 125 can be suppressed, and the mounting reliability can be improved.
- step S211 the manufacturing apparatus applies the CPS 211 of the semiconductor element (chip) 120 in which the imaging element 221 and the glass substrate 122 are bonded to each other with the bonding resin 123 to the Si substrate 131 opposite to the light receiving surface (upper in the drawing).
- a through-hole 144 is opened in order to expose the surface to form a thin film and connect it to a connection pad of the element.
- step S212 the manufacturing apparatus deposits an insulating film 132 for insulating from the Si substrate 131, exposes the connection pad 141 using a technique such as etch back, and then forms the rewiring 143.
- the manufacturing apparatus forms the insulating film 133 (A in FIG. 23).
- the manufacturing apparatus forms by performing heat treatment after patterning by lithography using a solder mask resist. Further, when patterning by lithography, a slit opening 231 which is a portion where a slit is formed is opened in advance.
- step S214 the manufacturing apparatus opens the slit 232 (B in FIG. 23) using lithography, dry processing technology, or the like.
- step S215 the manufacturing apparatus performs an Si receding process using a technique such as an isotropic dry etching process or a WET etching process in order to form an uneven structure on the end face of the image sensor 221.
- a technique such as an isotropic dry etching process or a WET etching process
- the Si substrate 131 is formed with a recess 222, and the end surface of the Si substrate 131 recedes from the insulating film 140 and the insulating film 133.
- part of Si receding process straddles the location separated into pieces at a post process.
- step S216 the manufacturing apparatus forms solder balls 124 (B in FIG. 24) that are external terminals.
- step S217 the manufacturing apparatus divides into chips 120 as shown in FIG. 25 using a technique such as dicing.
- step S218 the manufacturing apparatus mounts the chip 120 on the mounting substrate 126 and fills the underfill 125 as shown in FIG.
- the underfill 125 can be prevented from creeping up. Thereby, the height of the underfill 125 becomes equal to or less than the height of the image sensor 221, and no underfill is formed on the side surface of the glass substrate 122.
- the recess 134 is formed in the insulating film 132 in the image sensor 121 and the example in which the recess 222 is formed in the Si substrate 131 in the image sensor 221 have been described.
- the recesses may be formed. In the case of a plurality, even if the first recess does not sufficiently prevent the underfill from flowing out and scoops up, it can be suppressed by the second recess, which is more effective.
- the concave portion 222 is formed in the Si substrate has been described.
- the concave portion may be formed in the insulating film 140 with respect to the insulating film 133 and the Si substrate 131.
- step S311 the manufacturing apparatus performs CPS 311 of a semiconductor element (chip) in which a semiconductor element 321 in which an imaging element 325 and a logic circuit 324 are stacked and a glass substrate 122 are bonded together with a bonding resin 123 as illustrated in FIG.
- the surface of the Si substrate 131 opposite to the light receiving surface is exposed to form a thin film, and a through hole 144 is opened for connection to a connection pad of the element.
- step S312 the manufacturing apparatus deposits an insulating film 132 for insulating from the Si substrate 131, exposes the connection pad 141 using a technique such as etch back, and then forms the rewiring 143.
- the manufacturing apparatus forms the insulating film 133.
- the manufacturing apparatus forms by performing heat treatment after patterning by lithography using a solder mask resist. Further, when patterning by lithography, a portion where a slit is to be formed is opened in advance.
- step S314 the manufacturing apparatus opens the slit 322 (FIG. 28) using lithography, dry processing technology, or the like.
- FIG. 28 is a cross-sectional view showing an example of a CPS structure of a multilayer image sensor.
- parts corresponding to those in the example of FIG. 13 or FIG. Moreover, in the example of FIG. 27, the structure before a recessed part is formed is shown.
- the semiconductor element 321 in which the imaging element 325 and the logic circuit 324 are stacked includes a wiring layer 323 to which the imaging element 325 is bonded by the bonding portion 331, the insulating film 140, the Si substrate 131, the insulating film 132, in order from the top. And an insulating film 133 formed after the rewiring is formed.
- the logic circuit 324 is configured to include a wiring layer 323, an insulating film 140, and a Si substrate 131.
- the wiring layer 323 generally uses Cu wiring as a lower layer, and an interlayer film 332 of Cu damascene wiring uses an insulating film such as SiO or SiOC, and a cap film 333 of Cu wiring is made of SiC or SiN. , SiCN or the like is used.
- the interlayer film configuration in the case where the number of wiring layers is four layers including the Cu wiring and the Al wiring is shown, but the number of wiring layers is not limited.
- step S315 the manufacturing apparatus performs an interlayer film receding process using a technique such as an isotropic dry etching process or a WET etching process in order to form an uneven structure on the end surface of the wiring layer 323 of the logic circuit 324. Do. Since there is a difference in etching rate between the interlayer film and the cap film, an uneven structure is formed in the wiring layer 323 of the logic circuit 324 by this interlayer film receding process.
- a technique such as an isotropic dry etching process or a WET etching process
- the insulating film 140 and the interlayer film 332 in the wiring layer 323 retreat, and the retracted portion becomes a recess. It should be noted that the part of the interlayer curtain retreat process straddles the part to be separated in the subsequent process.
- the interlayer insulating film has different film formation conditions, materials, etc. depending on the wiring layer, the amount of retraction may be different for each interlayer film. And the case where an unevenness
- step S316 the manufacturing apparatus forms solder balls that are external terminals.
- step S317 the manufacturing apparatus is separated into chips using a technique such as dicing.
- step S3108 the manufacturing apparatus mounts the chip on the mounting substrate and fills the underfill.
- the uneven structure is formed on the end face (side part) of the logic circuit, it is possible to prevent the underfill from creeping up. Thereby, the height of an underfill becomes below the height of an image pick-up element, and an underfill is not formed in the side surface of a glass substrate.
- the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.
- the present technology is not limited to a solid-state imaging device, and can be applied to a semiconductor device.
- FIG. 30 is a diagram illustrating a usage example in which the above-described solid-state imaging device is used.
- the solid-state imaging device (image sensor) described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
- Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
- Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
- Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
- Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus
- the present technology is not limited to application to a solid-state imaging device, but can also be applied to an imaging device.
- the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone.
- a module-like form mounted on an electronic device that is, a camera module is used as an imaging device.
- the 31 includes a solid-state imaging device (element chip) 501, an optical lens 502, a shutter device 503, a drive circuit 504, and a signal processing circuit 505.
- the solid-state imaging device 501 the chip (semiconductor element in which an imaging element is formed) of the first embodiment and the second embodiment of the present technology described above is provided. Thereby, the reliability of the solid-state imaging device 501 of the electronic device 500 can be improved.
- the optical lens 502 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 501. As a result, signal charges are accumulated in the solid-state imaging device 501 for a certain period.
- the shutter device 503 controls the light irradiation period and the light shielding period for the solid-state imaging device 501.
- the drive circuit 504 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 501 and the shutter operation of the shutter device 503.
- the solid-state imaging device 501 performs signal transfer according to a drive signal (timing signal) supplied from the drive circuit 504.
- the signal processing circuit 505 performs various types of signal processing on the signal output from the solid-state imaging device 501.
- the video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.
- steps describing the series of processes described above are not limited to the processes performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually.
- the process to be executed is also included.
- the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
- the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
- a configuration other than that described above may be added to the configuration of each device (or each processing unit).
- a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
- this technique can also take the following structures.
- CSP Chip Size Package
- the CSP is formed to have a structure in which an underfill used for mounting on the mounting substrate is not adhered to a side wall of the second substrate.
- the CSP is formed in a structure in which the underfill is not adhered to a part or almost all of the side wall of the CSP by removing the photosensitive material formed on a part or all of the side wall of the CSP.
- the CSP is formed in a structure that does not adhere the underfill to a part or substantially all of the side wall of the CSP by forming a hydrophobic material on a part or substantially all of the side wall of the CSP.
- the CSP is formed in a structure that does not allow the underfill to adhere to the side wall of the second substrate by forming one or more irregularities on a part of the side wall of the first substrate.
- An image sensor and a logic circuit are formed as the circuit on the first substrate, The bottom surface of the first substrate is exposed, a through-hole for connecting to the connection pad of the circuit is opened, the insulating film of the first substrate is deposited, the connection pad is exposed, and a rewiring is formed Then, after forming an insulating film portion and opening the interlayer insulating film of the logic circuit, a process of retracting the interlayer insulating film of the logic circuit from the cap film is performed, so that one side wall of the wiring layer of the logic circuit is formed.
- the semiconductor device according to (5) wherein one or a plurality of irregularities are formed in a part or substantially all.
- the manufacturing equipment A CSP comprising a first substrate on which a circuit is formed, a second substrate made of a material different from that of the first substrate, and a joint for joining the second substrate on the first substrate.
- CSP Chip Size Package
- the CSP is a solid-state imaging device that is formed in a structure that does not adhere an underfill used when mounted on the mounting substrate to the side wall of the second substrate; A signal processing circuit for processing an output signal output from the solid-state imaging device; And an optical system that makes incident light incident on the solid-state imaging device.
- 1 solid-state imaging device 15 CPS, 21 mounting substrate, 22 Si substrate, 23 adhesive, 24 second substrate, 25 underfill, 26 chips, 27 solder balls, 28 spaces, 30 cuts, 31 photosensitive material, 32 lithography , 51 CPS, 61 hydrophobic material, 111 CPS, 120 chips, 121 imaging device, 122 glass substrate, 123 bonding resin, 124 solder ball, 125 underfill, 126 mounting substrate, 131 Si substrate, 132 insulating film, 133 insulating film , 134 recess, 140 insulating film, 141 connection pad, 143 rewiring, 151 creeping prevention pattern, 162 slit opening, 181 slit, 211 CPS, 221 Image sensor, 222 recess, 231 slit opening, 232 slit, 311 CPS, 321 semiconductor element, 322 slit, 323 wiring layer, 324 logic circuit, 325 image sensor, 331 junction, 332 interlayer film, 333 cap film, 500 electronic device , 501 solid-state
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Abstract
Description
1.第1の実施の形態
2.第2の実施の形態
3.第3の実施の形態(イメージセンサの使用例)
4.第4の実施の形態(電子機器の例)
<固体撮像装置の概略構成例>
図1は、本技術の各実施の形態に適用されるCMOS(Complementary Metal Oxide Semiconductor)固体撮像装置の一例の概略構成例を示している。
図2は、本技術の撮像素子のCPS(Chip Scale Packege)の構造例を示す断面図である。
次に、図3および図4のフローチャートを参照して、図2のCPS15の製造処理について説明する。なお、この説明おいては、図5乃至図8の工程図も参照される。
図9は、図2の撮像素子のCPS(Chip Scale Packege)の他の構造例を示す断面図である。なお、図9の例においては、図2の例と対応する部には対応する符号が付されている。
次に、図10および図11のフローチャートを参照して、図8のCPS51の製造処理について説明する。なお、この説明おいては、図12の工程図も参照される。また、図10および図11のステップS51乃至S60は、感光性材料31が疎水性材料61に入れ替わった以外は、図3および図4のステップS11乃至S20と基本的に同様であるため、その説明は繰り返しになるので省略される。
<本技術のCPS構造>
図13は、本技術の撮像素子のCPS(Chip Scale Packege)の構造例を示す断面図である。
次に、図14および図15のフローチャートを参照して、図13のCPS111の製造処理について説明する。なお、この説明おいては、図16乃至図20の工程図も参照される。
図21は、図13の撮像素子のCPS(Chip Scale Packege)の他の構造例を示す断面図である。なお、図21の例においては、図13の例と対応する部には対応する符号が付されている。
次に、図22のフローチャートを参照して、図21のCPS211の製造処理について説明する。なお、この説明おいては、図23乃至図26の工程図も参照される。
次に、図27のフローチャートを参照して、積層型の撮像素子のCPSの製造処理について説明する。なお、この説明おいては、図28および図29の工程図も参照される。
図30は、上述の固体撮像装置を使用する使用例を示す図である。
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置
<電子機器の構成例>
(1) 回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)と、
前記CSPを実装するための実装基板と
を備え、
前記CSPは、前記実装基板に実装する際に用いられるアンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている
半導体装置。
(2) 前記CSPは、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
前記(1)に記載の半導体装置。
(3) 前記CSPは、前記CSPの側壁の一部または全部に形成された感光性材料を除去することで、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
前記(1)または(2)に記載の半導体装置。
(4) 前記CSPは、前記CSPの側壁の一部または略全部に疎水性材料を形成することで、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
前記(1)または(2)に記載の半導体装置。
(5) 前記第1の基板の側壁の一部に凹凸を1つまたは複数形成することで、前記CSPは、前記アンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている
前記(1)に記載の半導体装置。
(6) 前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、這い上がり防止パターンを形成し、絶縁膜部の形成後に、前記這い上がり防止パターンを除去して、前記絶縁膜部に凹部を形成することで、前記第1の基板の側壁の一部または略全部に凹凸を1つまたは複数形成する
前記(5)に記載の半導体装置。
(7) 前記這い上がり防止パターンは、個片化する箇所を跨いで配置されている
前記(6)に記載の半導体装置。
(8) 前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、絶縁膜部の形成し、前記第1の基板を開口した後に、前記第1の基板を後退させる処理を行うことで、前記第1の基板の側壁の一部または略全部に凹凸を1つまたは複数形成する
前記(5)に記載の半導体装置。
(9) 前記第1の基板の後退された部分は、個片化する箇所を跨いで配置されている
前記(8)に記載の半導体装置。
(10) 前記第1の基板には、前記回路として、撮像素子とロジック回路が形成されており、
前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、絶縁膜部を形成し、前記ロジック回路の層間絶縁膜を開口した後に、前記ロジック回路の層間絶縁膜をキャップ膜より後退させる処理を行うことで、前記ロジック回路の配線層の側壁の一部または略全部に凹凸を1つまたは複数形成する
前記(5)に記載の半導体装置。
(11) 前記ロジック回路の層間絶縁膜の後退された部分は、個片化する箇所を跨いで配置されている
前記(10)に記載の半導体装置。
(12) 製造装置が、
回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)を、前記CSPを実装するための実装基板に実装する際に用いられるアンダーフィルが、前記第2の基板の側壁に接着させない構造に形成する
製造方法。
(13) 回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)と、
前記CSPを実装するための実装基板と
を備え、
前記CSPは、前記実装基板に実装する際に用いられるアンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている固体撮像装置と、
前記固体撮像装置から出力される出力信号を処理する信号処理回路と、
入射光を前記固体撮像装置に入射する光学系と
を有する電子機器。
Claims (13)
- 回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)と、
前記CSPを実装するための実装基板と
を備え、
前記CSPは、前記実装基板に実装する際に用いられるアンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている
半導体装置。 - 前記CSPは、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
請求項1に記載の半導体装置。 - 前記CSPは、前記CSPの側壁の一部または略全部に形成された感光性材料を除去することで、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
請求項2に記載の半導体装置。 - 前記CSPは、前記CSPの側壁の一部または略全部に疎水性材料を形成することで、前記アンダーフィルを、前記CSPの側壁の一部または略全部に接着させない構造に形成されている
請求項2に記載の半導体装置。 - 前記第1の基板の側壁の一部に凹凸を1つまたは複数形成することで、前記CSPは、前記アンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている
請求項1に記載の半導体装置。 - 前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、這い上がり防止パターンを形成し、絶縁膜部の形成後に、前記這い上がり防止パターンを除去して、前記絶縁膜部に凹部を形成することで、前記第1の基板の側壁の一部または略全部に凹凸を1つまたは複数形成する
請求項5に記載の半導体装置。 - 前記這い上がり防止パターンは、個片化する箇所を跨いで配置されている
請求項6に記載の半導体装置。 - 前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、絶縁膜部の形成し、前記第1の基板を開口した後に、前記第1の基板を後退させる処理を行うことで、前記第1の基板の側壁の一部または略全部に凹凸を1つまたは複数形成する
請求項5に記載の半導体装置。 - 前記第1の基板の後退された部分は、個片化する箇所を跨いで配置されている
請求項8に記載の半導体装置。 - 前記第1の基板には、前記回路として、撮像素子とロジック回路が形成されており、
前記第1の基板の底面を露出し、前記回路の接続パッドと接続するための貫通孔を開口し、前記第1の基板の絶縁膜を堆積後、前記接続パッドを露出させ、再配線を形成後、絶縁膜部を形成し、前記ロジック回路の層間絶縁膜を開口した後に、前記ロジック回路の層間絶縁膜をキャップ膜より後退させる処理を行うことで、前記ロジック回路の配線層の側壁の一部または略全部に凹凸を1つまたは複数形成する
請求項5に記載の半導体装置。 - 前記ロジック回路の層間絶縁膜の後退された部分は、個片化する箇所を跨いで配置されている
請求項10に記載の半導体装置。 - 製造装置が、
回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)を、前記CSPを実装するための実装基板に実装する際に用いられるアンダーフィルが、前記第2の基板の側壁に接着させない構造に形成する
製造方法。 - 回路が形成される第1の基板と、前記第1の基板と異なる材料からなる第2の基板と、前記第1の基板の上に、前記第2の基板を接合する接合部とからなるCSP(Chip Size Package)と、
前記CSPを実装するための実装基板と
を備え、
前記CSPは、前記実装基板に実装する際に用いられるアンダーフィルを、前記第2の基板の側壁に接着させない構造に形成されている固体撮像装置と、
前記固体撮像装置から出力される出力信号を処理する信号処理回路と、
入射光を前記固体撮像装置に入射する光学系と
を有する電子機器。
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