FR3093861B1 - Procédé d’enrobage de puces - Google Patents
Procédé d’enrobage de puces Download PDFInfo
- Publication number
- FR3093861B1 FR3093861B1 FR1902486A FR1902486A FR3093861B1 FR 3093861 B1 FR3093861 B1 FR 3093861B1 FR 1902486 A FR1902486 A FR 1902486A FR 1902486 A FR1902486 A FR 1902486A FR 3093861 B1 FR3093861 B1 FR 3093861B1
- Authority
- FR
- France
- Prior art keywords
- inter
- chip
- coating film
- sub
- photosensitive coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000576 coating method Methods 0.000 title abstract 3
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 238000004090 dissolution Methods 0.000 abstract 1
- 230000000284 resting effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Materials For Photolithography (AREA)
Abstract
L’invention concerne un procédé d’enrobage de puces (110) reposant, par une face arrière opposée à une face avant, sur une face principale d’un substrat support (100), et séparées les unes des autres par un espace inter puce, le procédé comprend les étapes suivantes :a) une étape de formation d’un film d’enrobage photosensible en recouvrement des faces avant et des espaces inter puce,b) une première séquence photo lithographique qui comprend une sous-étape b1) d’insolation, et une sous-étape b2) de dissolution, ladite séquence conduisant à un retrait partiel du film d’enrobage photosensible de manière à conserver ledit film exclusivement au niveau des espaces inter puce et, avantageusement en retrait par rapport aux faces avant. Figure pour l’abrégé : figure 2d.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1902486A FR3093861B1 (fr) | 2019-03-12 | 2019-03-12 | Procédé d’enrobage de puces |
US17/435,102 US11955585B2 (en) | 2019-03-12 | 2020-03-02 | Method for coating chips |
EP20725802.1A EP3921862A1 (fr) | 2019-03-12 | 2020-03-02 | Procede d'enrobage de puces |
PCT/FR2020/050410 WO2020183090A1 (fr) | 2019-03-12 | 2020-03-02 | Procede d'enrobage de puces |
TW109107858A TW202105538A (zh) | 2019-03-12 | 2020-03-10 | 用於晶片之塗層方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1902486A FR3093861B1 (fr) | 2019-03-12 | 2019-03-12 | Procédé d’enrobage de puces |
FR1902486 | 2019-03-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3093861A1 FR3093861A1 (fr) | 2020-09-18 |
FR3093861B1 true FR3093861B1 (fr) | 2021-09-17 |
Family
ID=67107845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1902486A Active FR3093861B1 (fr) | 2019-03-12 | 2019-03-12 | Procédé d’enrobage de puces |
Country Status (5)
Country | Link |
---|---|
US (1) | US11955585B2 (fr) |
EP (1) | EP3921862A1 (fr) |
FR (1) | FR3093861B1 (fr) |
TW (1) | TW202105538A (fr) |
WO (1) | WO2020183090A1 (fr) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8507320B2 (en) | 2008-03-18 | 2013-08-13 | Infineon Technologies Ag | Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof |
US8470641B2 (en) * | 2009-12-17 | 2013-06-25 | Texas Instruments Incorporated | Exposed mold |
US9508623B2 (en) | 2014-06-08 | 2016-11-29 | UTAC Headquarters Pte. Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
FR3031242B1 (fr) * | 2014-12-29 | 2016-12-30 | Aledia | Procede de fabrication de nanofils ou de microfils semiconducteurs a pieds isoles |
US10403669B2 (en) * | 2015-06-15 | 2019-09-03 | Sony Corporation | Semiconductor device and electronic device having a chip size package (CSP) stack |
CN106887488B (zh) * | 2015-12-15 | 2019-06-11 | 群创光电股份有限公司 | 发光二极管及使用此发光二极管所制得的显示装置 |
FR3053530B1 (fr) | 2016-06-30 | 2018-07-27 | Aledia | Dispositif optoelectronique a pixels a contraste et luminance ameliores |
JP2018067659A (ja) * | 2016-10-20 | 2018-04-26 | 日立化成株式会社 | 半導体装置の製造方法 |
-
2019
- 2019-03-12 FR FR1902486A patent/FR3093861B1/fr active Active
-
2020
- 2020-03-02 WO PCT/FR2020/050410 patent/WO2020183090A1/fr unknown
- 2020-03-02 EP EP20725802.1A patent/EP3921862A1/fr active Pending
- 2020-03-02 US US17/435,102 patent/US11955585B2/en active Active
- 2020-03-10 TW TW109107858A patent/TW202105538A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
EP3921862A1 (fr) | 2021-12-15 |
US11955585B2 (en) | 2024-04-09 |
US20220149245A1 (en) | 2022-05-12 |
TW202105538A (zh) | 2021-02-01 |
WO2020183090A1 (fr) | 2020-09-17 |
FR3093861A1 (fr) | 2020-09-18 |
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