WO2016194033A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2016194033A1 WO2016194033A1 PCT/JP2015/065519 JP2015065519W WO2016194033A1 WO 2016194033 A1 WO2016194033 A1 WO 2016194033A1 JP 2015065519 W JP2015065519 W JP 2015065519W WO 2016194033 A1 WO2016194033 A1 WO 2016194033A1
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- conductive
- conductive portion
- insulating substrate
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000000034 method Methods 0.000 title claims description 14
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- 238000012545 processing Methods 0.000 claims description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
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- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- an inverter device that converts DC power input from a DC power source into AC power and outputs the AC power.
- the inverter device is used, for example, to convert a DC voltage into a three-phase AC voltage and drive a three-phase motor.
- semiconductor devices are increasingly required to be smaller and more efficient.
- Patent Document 1 describes an inverter device for the purpose of reducing inductance and downsizing the device.
- the power supply terminal (inverter input terminal) and the ground terminal (inverter ground terminal) are not bundled together but are arranged in one direction (see FIG. 20 of Patent Document 1).
- Patent Document 2 describes an inverter device intended to reduce loss and noise.
- a power supply block electrically connected to a power supply terminal and a ground block connected to the ground are disposed adjacent to each other (see FIG. 15 of Patent Document 2).
- an object of the present invention is to provide a highly efficient semiconductor device that can be miniaturized and has low wiring resistance.
- a semiconductor device includes: A semiconductor device that converts DC power into AC power, An insulating substrate; A first conductive portion provided on the insulating substrate so as to extend in a first direction; A second conductive portion provided on the insulating substrate so as to be separated from the first conductive portion in a second direction different from the first direction and to extend in the first direction; A plurality of third conductive portions provided on the insulating substrate so as to be arranged along the first direction between the first conductive portion and the second conductive portion; A first main electrode; a second main electrode; and a control electrode, wherein the first main electrode is mounted on the first conductive portion along the first direction, and the first main electrode is the first conductive portion.
- the fourth main electrode of the second switch and the second conductive portion are electrically connected by a conductive wire, and one end of the conductive wire is connected to the fourth main electrode, The other end of the second conductive portion may be connected to a region sandwiched between adjacent output terminals.
- the tip portions of the plurality of signal terminals may be arranged in a staggered manner along the first direction.
- Tip portions of the power supply terminal and the ground terminal may be arranged in a staggered manner with respect to the plurality of signal terminals.
- At least one of the power supply terminal, the ground terminal, and the output terminal may have a planar shape that avoids a conductive portion provided at a corner of the insulating substrate.
- the planar shape may be L-shaped.
- a method for manufacturing a semiconductor device includes: A method of manufacturing a semiconductor device that converts DC power into AC power, An insulating substrate; a first conductive portion provided on the insulating substrate so as to extend in the first direction; and a second direction different from the first direction from the first conductive portion. And in the first direction between the second conductive part provided on the insulating substrate so as to extend in the first direction, and between the first conductive part and the second conductive part.
- the bonding step includes a first connection step of connecting one end of the conductive wire to the main electrode of the second switch, and after the first connection step, the other end of the conductive wire is connected to the second conductive And a second connection step of connecting to a region sandwiched between adjacent output terminals.
- the first conductive portion extending in the first direction and the second conductive portion spaced apart in the second direction different from the first direction and extending in the first direction
- a plurality of third conductive parts arranged along the first direction between the first conductive part and the second conductive part, and mounted on the first conductive part along the first direction.
- the first conductive portion is located between the plurality of first switches, the plurality of second switches each mounted on the corresponding third conductive portion, and the plurality of third conductive portions.
- a plurality of signal terminals arranged along the first direction, a power supply terminal electrically connected to the first conductive part, a ground terminal electrically connected to the second conductive part, And a plurality of output terminals each electrically connected to the corresponding third conductive portion.
- the power supply terminal and the ground terminal are arranged on one end side of the insulating substrate provided with the plurality of signal terminals, and the plurality of output terminals are arranged along the first direction on the other end side of the insulating substrate.
- Each output terminal straddles a straight line that passes through the second conductive portion and extends in the first direction.
- FIG. 1 is a plan view showing a schematic configuration of a semiconductor device 1 according to an embodiment.
- 1 is a circuit diagram showing a circuit configuration of a semiconductor device 1 according to an embodiment.
- 4 is a plan view of a lead frame 70 used for manufacturing the semiconductor device 1 according to the embodiment.
- FIG. 1 is a plan view showing a schematic configuration of a semiconductor device 1 according to an embodiment.
- 1 is a circuit diagram showing a circuit configuration of a semiconductor device 1 according to an embodiment.
- 4 is a plan view of a lead frame 70 used for manufacturing the semiconductor device 1 according to the embodiment.
- the semiconductor device 1 converts DC power input from a DC power source (not shown) connected to the power terminal 21 and the ground terminal 22 into three-phase AC power.
- the semiconductor device inverter device outputs from the output terminals 23, 24, 25.
- the high-side switches 11, 12, 13 and the low-side switches 14, 15, 16 are mounted on the insulating substrate 2 provided with the conductive portions 3 to 7 on the upper surface to constitute a three-phase full bridge circuit. is doing.
- the semiconductor device 1 includes an insulating substrate 2 such as a ceramic substrate, a conductive portion 3 (first conductive portion), a conductive portion 4 (second conductive portion), and a plurality of conductive portions 5.
- a conductive portion 3 first conductive portion
- a conductive portion 4 second conductive portion
- a plurality of conductive portions 5 Fifth conductive portion
- conductive portion 6 fourth conductive portion
- conductive portion 7 high-side switches 11, 12, 13 (a plurality of first switches), low-side switches 14, 15, 16 (a plurality of second switches)
- control terminals 31 to 36 monitor terminals 41 to 45
- Conductive wires 51 to 53 such as Al wires and a sealing portion 60 are provided.
- each component of the semiconductor device 1 will be described in detail.
- the conductive portions 3 to 7 are conductive patterns provided on the upper surface of the insulating substrate 2.
- the conductive portions 3 to 7 are made of a metal such as copper or aluminum. Note that the lower surface of the insulating substrate 2 may be covered with a metal layer (not shown) in order to improve heat dissipation.
- the conductive portion 3 is provided on the insulating substrate 2 so as to extend in the first direction.
- High side switches 11, 12, and 13 are mounted on the conductive portion 3.
- the conductive portion 4 is provided on the insulating substrate 2 so as to be separated from the conductive portion 3 in the second direction and extend in the first direction. That is, the conductive part 4 is provided substantially parallel to the conductive part 3.
- the second direction is a direction different from the first direction, for example, a direction orthogonal to the first direction.
- the conductive part 4 is electrically connected to the ground terminal 22 via the conductive part 6.
- the conductive portion 6 is connected to the conductive portion 4 and extends in the second direction.
- the conductive portion 6 is not an essential configuration, and the conductive portion 4 may be directly connected to the ground terminal 22.
- a terminal that is formed longer than the length of the conductive portion 6 is used as the ground terminal 22, and a terminal (I-shaped or the like) that does not interfere with the ground terminal 22 is used as the output terminal 25. Is done.
- the plurality of conductive portions 5 are provided on the insulating substrate 2 so as to be arranged along the first direction between the conductive portions 3 and 4.
- One low-side switch 14, 15, 16 is mounted on each conductive portion 5.
- the conductive portion 7 is provided in an island shape at the corner of the insulating substrate 2.
- the conductive portion 7 is a portion with which a mold die comes into contact when the sealing portion 60 is formed in the manufacture of the semiconductor device 1.
- the high-side switches 11, 12, and 13 have a drain electrode (first main electrode), a source electrode (second main electrode), and a gate electrode (control electrode).
- the drain electrode, the source electrode, and the gate electrode are provided on the lower surface, the upper surface, and the side surfaces of the high-side switches 11, 12, and 13, respectively.
- the high-side switches 11 to 13 and the low-side switches 14 to 16 are, for example, power MOSFETs, but may be other semiconductor switching elements such as IGBTs.
- the high-side switches 11, 12, and 13 are mounted on the conductive portion 3 along the first direction.
- the drain electrodes of the high-side switches 11, 12, and 13 are electrically connected to the conductive portion 3 via solder (not shown).
- the source electrodes of the high-side switches 11, 12, 13 are electrically connected to the drain electrodes of the corresponding low-side switches 14, 15, 16 via conductive wires such as Al wires and the conductive part 5.
- the gate electrodes of the high side switches 11, 12, 13 are electrically connected to the control terminals 31, 33, 35 via metal thin wires 54 such as gold wires, respectively.
- the low-side switches 14, 15, and 16 include a drain electrode (third main electrode), a source electrode (fourth main electrode), and a gate electrode (control electrode).
- the drain electrode, the source electrode, and the gate electrode are provided on the lower surface, the upper surface, and the side surfaces of the low-side switches 14, 15, and 16, respectively.
- the low side switches 14, 15, 16 are mounted on the corresponding conductive parts 5.
- the drain electrodes of the low-side switches 14, 15, 16 are electrically connected to the source electrodes of the corresponding high-side switches 11, 12, 13 via the conductive part 5 and conductive wires.
- the source electrodes of the low-side switches 14, 15, 16 are electrically connected to the conductive part 4 via conductive wires 51, 52, 53.
- the gate electrodes of the low-side switches 14, 15, and 16 are electrically connected to the control terminals 32, 34, and 36 through fine metal wires, respectively.
- the semiconductor device 1 has control terminals 31 to 36 and monitor terminals 41 to 45 as signal terminals.
- the control terminals 31, 33, and 35 are terminals for on / off control of the high-side switches 11, 12, and 13, and the control terminals 32, 34, and 36 are for on-off control of the low-side switches 14, 15, and 16. Terminal.
- Monitor terminals 41, 42 and 43 are terminals for monitoring the output voltage of each phase.
- the monitor terminal 41 is electrically connected to the source electrode of the high side switch 11 and the drain electrode of the low side switch 14.
- the monitor terminal 42 is electrically connected to the source electrode of the high side switch 12 and the drain electrode of the low side switch 15, and the monitor terminal 43 is electrically connected to the source electrode of the high side switch 13 and the drain electrode of the low side switch 16. Connected.
- Monitor terminals 44 and 45 are terminals for monitoring the thermistor 17 voltage.
- the thermistor 17 is provided for measuring the internal temperature of the semiconductor device 1.
- this thermistor 17 for example, an NTC type whose resistance decreases as the temperature increases is used.
- control terminals 31 to 36 and the monitor terminals 41 to 45 are arranged side by side along one end of the insulating substrate 2.
- control terminals 31 to 36 and the monitor terminals 41 to 45 are arranged along the first direction so that the conductive part 3 is located between the plurality of conductive parts 5.
- tip part of a some signal terminal may be arrange
- the tip portions of the control terminals 31 to 36 and the monitor terminals 41 to 45 are alternately shifted in the second direction. Thereby, the pitch of the through holes of the control board (not shown) on which the semiconductor device 1 is mounted can be relaxed.
- the power supply terminal 21 is a terminal for connecting to a DC power supply
- the ground terminal 22 is a grounding terminal. As shown in FIG. 1, the power supply terminal 21 and the ground terminal 22 have distal ends disposed on one end side of the insulating substrate 2 provided with a plurality of signal terminals.
- the power supply terminal 21 is electrically connected to the conductive portion 3. More specifically, the power supply terminal 21 is soldered to the conductive portion 3 at the base portion 21a.
- the ground terminal 22 is electrically connected to the conductive portion 4. More specifically, the ground terminal 22 is soldered to the conductive portion 6 at the base portion 22a. As shown in FIG. 1, the power terminal 21 and the ground terminal 22 are provided so as to sandwich the control terminals 31 to 36 and the monitor terminals 41 to 45.
- the tip ends of the power supply terminal 21 and the ground terminal 22 may be arranged in a staggered manner with respect to the control terminals 31 to 36 and the monitor terminals 41 to 45 (a plurality of signal terminals). .
- the output terminals 23, 24, and 25 are terminals for outputting a three-phase alternating current converted by a three-phase full bridge circuit, and each is electrically connected to the corresponding conductive portion 5. Yes. More specifically, the output terminals 23, 24, and 25 are soldered to the corresponding conductive portions 5 at the base portions 23a, 24a, and 25a.
- the output terminals 23, 24 and 25 are arranged on the opposite side of the control terminals 31 to 36 and the monitor terminals 41 to 45. That is, the output terminals 23, 24, and 25 are arranged along the first direction on the other end side opposite to the one end side of the insulating substrate 2. The front ends of the output terminals 23, 24, 25 are disposed on the other end side of the insulating substrate 2. The output terminals 23, 24, and 25 are provided so as to straddle the straight line L as shown in FIG.
- the straight line L is a straight line that passes through the conductive portion 4 and extends in the first direction.
- the power terminal 21, the ground terminal 22, and the output terminals 23, 24, and 25 may have a planar shape that avoids the conductive portions 7 at the four corners of the insulating substrate 2. Thereby, when forming the sealing part 60, it can prevent that a terminal interferes with a mold die.
- the power terminal 21, the ground terminal 22, and the output terminals 23 and 25 are L-shaped in plan so as to avoid the conductive portion 7, as shown in FIG.
- the planar shape is not limited to the L shape, and may be another shape (for example, an arc shape) as long as the conductive portion 7 is avoided.
- the source electrode of the low-side switch 14 and the conductive portion 4 are electrically connected by the conductive wire 51.
- one end of the conductive wire 51 is connected to the source electrode of the low-side switch 14, and the other end of the conductive portion 4 is in a region A sandwiched between the adjacent output terminal 23 and output terminal 24. It is connected.
- the conductive wire 52 that electrically connects the source electrode of the low-side switch 15 and the conductive portion 4 has one end connected to the source electrode of the low-side switch 15 and the other end connected to the region A. As shown in FIG.
- one end of the conductive wire 53 that electrically connects the source electrode of the low-side switch 16 and the conductive portion 4 is connected to the source electrode of the low-side switch 16, and the adjacent output of the conductive portion 4.
- the other end is connected to a region B sandwiched between the terminal 24 and the output terminal 25.
- the sealing portion 60 is provided on the upper surface side of the insulating substrate 2, the conductive portions 3 to 7, the high side switches 11, 12, 13, the low side switches 14, 15, 16, the thermistor 17, the conductive wires 51, 52, 53, and various terminals. A part is sealed.
- the semiconductor device 1 includes the conductive portion 3 extending in the first direction and the second direction different from the first direction, and extends in the first direction.
- the power terminal 21 and the ground terminal 22 are arranged on one end side of the insulating substrate 2 provided with a plurality of signal terminals, and the output terminals 23, 24, and 25 are in the first direction on the other end side of the insulating substrate 2.
- the output terminals 23, 24, and 25 are provided so as to straddle a straight line L that passes through the conductive portion 4 and extends in the first direction.
- the semiconductor device can be reduced in size, and a highly efficient semiconductor device with low wiring resistance can be provided.
- the lead frame 70 includes a first terminal group including a plurality of signal terminals (control terminals 31 to 36, monitor terminals 41 to 45), a power supply terminal 21 and a ground terminal 22, and a plurality of outputs. And a second terminal group including terminals 23, 24, and 25.
- the terminal bases included in the first terminal group and the terminal bases included in the second terminal group are provided so as to face each other.
- the high-side switches 11, 12, 13 are placed on the conductive part 3 via cream solder along the first direction, and the low-side switches 14, 15, 16 is placed.
- the thermistor 17 is also placed at a predetermined location on the wiring board.
- the base portion 21a of the power terminal 21, the base portion 22a of the ground terminal 22, and the base portions 23a, 24a, and 25a of the output terminals 23, 24, and 25 are respectively on the conductive portion 3, the conductive portion 6, and the conductive portion 5.
- the wiring board and the lead frame 70 are aligned so as to be in contact with each other via cream solder.
- the high side switches 11, 12, 13 and the low side switches 14, 15, 16 may be placed on the wiring board after the wiring board and the lead frame 70 are aligned. .
- the power supply terminal 21, the ground terminal 22, and the output terminals 23, 24, and 25 are joined to the conductive portion 3, the conductive portion 4, and the conductive portion 5, respectively, by reflow processing. Thereafter, the flux residue is washed and removed.
- This bonding process includes a first connection process in which one end of the conductive wires 51, 52, 53 is connected to the source electrodes of the low-side switches 14, 15, 16, and after the first connection process, in addition to the conductive wires 51, 52, 53.
- the upper surface side of the insulating substrate 2, the high side switches 11, 12, 13, the low side switches 14, 15, 16, the conductive wires 51, 52, 53, and some of the various terminals are sealed by transfer molding.
- the sealing part 60 shown in FIG. 1 is formed.
- unnecessary portions (tie bars or the like) of the lead frame 70 are cut, and various terminals are formed, whereby the semiconductor device 1 is obtained.
- various terminals may be formed such that the tip portions of the plurality of signal terminals are arranged in a staggered manner along the first direction.
- the bonding device and the output terminals 23, 24, 25 interfere with each other by connecting the other ends of the conductive wires 51, 52, 53 to the regions A, B between the output terminals during the bonding process.
- the bonding apparatus can easily cut the conductive wire on the conductive portion 4. As a result, according to the present embodiment, the manufacturability of the semiconductor device can be improved.
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Abstract
Description
直流電力を交流電力に変換する半導体装置であって、
絶縁基板と、
第1の方向に延在するように前記絶縁基板上に設けられた第1の導電部と、
前記第1の導電部から前記第1の方向と異なる第2の方向に離間し且つ前記第1の方向に延在するように前記絶縁基板上に設けられた第2の導電部と、
前記第1の導電部と前記第2の導電部との間に前記第1の方向に沿って並ぶように前記絶縁基板上に設けられた複数の第3の導電部と、
第1の主電極、第2の主電極および制御電極を有し、前記第1の方向に沿って前記第1の導電部上に実装され、前記第1の主電極が前記第1の導電部に電気的に接続された複数の第1のスイッチと、
第3の主電極、第4の主電極および制御電極を有し、各々が対応する前記第3の導電部上に実装され、前記第3の主電極が前記第1のスイッチの前記第2の主電極に電気的に接続され、前記第4の主電極が前記第2の導電部に電気的に接続された複数の第2のスイッチと、
前記複数の第3の導電部との間に前記第1の導電部が位置するように前記第1の方向に沿って配列された複数の信号端子と、
前記第1の導電部に電気的に接続され、前記複数の信号端子が設けられた前記絶縁基板の一端側に配置された電源端子と、
前記第2の導電部に電気的に接続され、前記絶縁基板の前記一端側に配置されたグランド端子と、
各々が対応する前記第3の導電部に電気的に接続され、前記絶縁基板の前記一端側の反対側である他端側に前記第1の方向に沿って配列され、前記第2の導電部を通り且つ前記第1の方向に延びる直線を跨ぐ複数の出力端子と、
を備えることを特徴とする。
前記第2のスイッチの前記第4の主電極と、前記第2の導電部とは導電ワイヤーにより電気的に接続されており、前記導電ワイヤーは、前記第4の主電極に一端が接続され、前記第2の導電部のうち、隣り合う前記出力端子に挟まれた領域に他端が接続されていてもよい。
前記複数の信号端子の先端部は、前記第1の方向に沿って千鳥状に配置されているようにしてもよい。
前記電源端子および前記グランド端子の先端部は、前記複数の信号端子に対して千鳥状に配置されているようにしてもよい。
前記電源端子、前記グランド端子および前記出力端子のうち少なくともいずれか一つは、前記絶縁基板の隅部に設けられた導電部を回避する平面形状を有するようにしてもよい。
前記平面形状はL字型であるようにしてもよい。
直流電力を交流電力に変換する半導体装置の製造方法であって、
絶縁基板と、第1の方向に延在するように前記絶縁基板上に設けられた第1の導電部と、前記第1の導電部から前記第1の方向と異なる第2の方向に離間し且つ前記第1の方向に延在するように前記絶縁基板上に設けられた第2の導電部と、前記第1の導電部と前記第2の導電部との間に前記第1の方向に沿って並ぶように前記絶縁基板上に設けられた複数の第3の導電部とを有する配線板を用意する工程と、
複数の信号端子、電源端子およびグランド端子を含む第1の端子群と、複数の出力端子を含む第2の端子群とを有するリードフレームを用意する工程と、
前記第1の導電部上にクリームはんだを介して複数の第1のスイッチを前記第1の方向に沿って載置し、前記各第3の導電部上にクリームはんだを介して第2のスイッチを載置する工程と、
前記電源端子の基部、前記グランド端子の基部、および前記出力端子の基部が、前記第1の導電部上、前記第2の導電部に接続され前記第2の方向に延在する第4の導電部上、および前記第3の導電部上にクリームはんだを介してそれぞれ接するように前記配線板と前記リードフレームとを位置合わせする工程と、
リフロー処理により、前記電源端子、前記グランド端子および前記出力端子を、前記第1の導電部、前記第2の導電部および前記第3の導電部にそれぞれ接合させる工程と、
前記第2の導電部と前記第2のスイッチの主電極とを導電ワイヤーで接続するボンディング工程と、
を備えることを特徴とする。
前記ボンディング工程は、前記導電ワイヤーの一端を前記第2のスイッチの前記主電極に接続する第1接続工程と、前記第1接続工程の後、前記導電ワイヤーの他端を、前記第2の導電部のうち、隣り合う前記出力端子に挟まれた領域に接続する第2接続工程と、を有してもよい。
本発明の実施形態に係る半導体装置1について図1および図2を参照して説明する。実施形態に係る半導体装置1は、図2の回路図に示すように、電源端子21とグランド端子22に接続された直流電源(図示せず)から入力した直流電力を3相の交流電力に変換して出力端子23,24,25から出力する半導体装置(インバータ装置)である。
次に、上記の半導体装置1の製造方法について説明する。
2 絶縁基板
3,4,5,6,7 導電部
11,12,13 ハイサイドスイッチ
14,15,16 ローサイドスイッチ
17 サーミスタ
21 電源端子
22 グランド端子
23,24,25 出力端子
21a,22a,23a,24a,25a 基部
31~36 制御端子
41~45 モニタ端子
51~53 導電ワイヤー
54 金属細線
60 封止部
70 リードフレーム
A,B 領域
L 直線
Claims (8)
- 直流電力を交流電力に変換する半導体装置であって、
絶縁基板と、
第1の方向に延在するように前記絶縁基板上に設けられた第1の導電部と、
前記第1の導電部から前記第1の方向と異なる第2の方向に離間し且つ前記第1の方向に延在するように前記絶縁基板上に設けられた第2の導電部と、
前記第1の導電部と前記第2の導電部との間に前記第1の方向に沿って並ぶように前記絶縁基板上に設けられた複数の第3の導電部と、
第1の主電極、第2の主電極および制御電極を有し、前記第1の方向に沿って前記第1の導電部上に実装され、前記第1の主電極が前記第1の導電部に電気的に接続された複数の第1のスイッチと、
第3の主電極、第4の主電極および制御電極を有し、各々が対応する前記第3の導電部上に実装され、前記第3の主電極が前記第1のスイッチの前記第2の主電極に電気的に接続され、前記第4の主電極が前記第2の導電部に電気的に接続された複数の第2のスイッチと、
前記複数の第3の導電部との間に前記第1の導電部が位置するように前記第1の方向に沿って配列された複数の信号端子と、
前記第1の導電部に電気的に接続され、前記複数の信号端子が設けられた前記絶縁基板の一端側に配置された電源端子と、
前記第2の導電部に電気的に接続され、前記絶縁基板の前記一端側に配置されたグランド端子と、
各々が対応する前記第3の導電部に電気的に接続され、前記絶縁基板の前記一端側の反対側である他端側に前記第1の方向に沿って配列され、前記第2の導電部を通り且つ前記第1の方向に延びる直線を跨ぐ複数の出力端子と、
を備えることを特徴とする半導体装置。 - 前記第2のスイッチの前記第4の主電極と、前記第2の導電部とは導電ワイヤーにより電気的に接続されており、前記導電ワイヤーは、前記第4の主電極に一端が接続され、前記第2の導電部のうち、隣り合う前記出力端子に挟まれた領域に他端が接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記複数の信号端子の先端部は、前記第1の方向に沿って千鳥状に配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記電源端子および前記グランド端子の先端部は、前記複数の信号端子に対して千鳥状に配置されていることを特徴とする請求項3に記載の半導体装置。
- 前記電源端子、前記グランド端子および前記出力端子のうち少なくともいずれか一つは、前記絶縁基板の隅部に設けられた導電部を回避する平面形状を有することを特徴とする請求項1に記載の半導体装置。
- 前記平面形状はL字型であることを特徴とする請求項5に記載の半導体装置。
- 直流電力を交流電力に変換する半導体装置の製造方法であって、
絶縁基板と、第1の方向に延在するように前記絶縁基板上に設けられた第1の導電部と、前記第1の導電部から前記第1の方向と異なる第2の方向に離間し且つ前記第1の方向に延在するように前記絶縁基板上に設けられた第2の導電部と、前記第1の導電部と前記第2の導電部との間に前記第1の方向に沿って並ぶように前記絶縁基板上に設けられた複数の第3の導電部とを有する配線板を用意する工程と、
複数の信号端子、電源端子およびグランド端子を含む第1の端子群と、複数の出力端子を含む第2の端子群とを有するリードフレームを用意する工程と、
前記第1の導電部上にクリームはんだを介して複数の第1のスイッチを前記第1の方向に沿って載置し、前記各第3の導電部上にクリームはんだを介して第2のスイッチを載置する工程と、
前記電源端子の基部、前記グランド端子の基部、および前記出力端子の基部が、前記第1の導電部上、前記第2の導電部に接続され前記第2の方向に延在する第4の導電部上、および前記第3の導電部上にクリームはんだを介してそれぞれ接するように前記配線板と前記リードフレームとを位置合わせする工程と、
リフロー処理により、前記電源端子、前記グランド端子および前記出力端子を、前記第1の導電部、前記第2の導電部および前記第3の導電部にそれぞれ接合させる工程と、
前記第2の導電部と前記第2のスイッチの主電極とを導電ワイヤーで接続するボンディング工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記ボンディング工程は、前記導電ワイヤーの一端を前記第2のスイッチの前記主電極に接続する第1接続工程と、前記第1接続工程の後、前記導電ワイヤーの他端を、前記第2の導電部のうち、隣り合う前記出力端子に挟まれた領域に接続する第2接続工程と、を有することを特徴とする請求項7に記載の半導体装置の製造方法。
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