JP4977407B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4977407B2 JP4977407B2 JP2006161618A JP2006161618A JP4977407B2 JP 4977407 B2 JP4977407 B2 JP 4977407B2 JP 2006161618 A JP2006161618 A JP 2006161618A JP 2006161618 A JP2006161618 A JP 2006161618A JP 4977407 B2 JP4977407 B2 JP 4977407B2
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- bus bar
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- voltage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Description
上記において、上記の半導体チップの電力用半導体素子がIGBT素子(Nチャンネル型)である場合、一方の半導体チップの一面はコレクタ側の面、他面はエミッタ側の面であり、他方の半導体チップの一面はエミッタ側の面、他面はコレクタ側の面である。
まず高圧側の半導体チップ(IGBT素子402とダイオード素子409)の下面と高圧バスバー21とを半田ペーストを介してセットし、さらに併せて当該半導体チップの上面と第1金属配線板25を半田ペーストを介してセットする。
次に、低圧側の半導体チップ(IGBT素子404とダイオード素子410)の下面と第2金属配線板26とを半田ペーストを介してセットし、さらに併せて当該半導体チップの上面と低圧バスバー23を半田ペーストを介してセットする。
次に、第1金属配線板25と第2金属配線板26を半田ペーストを介してセットする。このときにおいて、高圧バスバー21の下面と第2金属配線板26の下面との面位置を同一平面になるように一致させる。この場合、精度の高い台座がセット用ツールとして使用される。
上記のようにセットされたセット物をリフロー炉に入れ、そこで半田付け処理を行う。セット物の各要素は接合される。
次に、ヒートシンク32の上面に絶縁層22を介して高圧バスバー21と第2金属配線板26をセットする。
次に、ヒートシンク32の上面に信号コネクタ406,407を接着する。
次に、信号コネクタ406,407との間で所要の信号ワイヤをワイヤ・ボンディングする。
最後に樹脂モールド(ブロック11)を行う。
また電力用半導体素子としてIGBT素子の以外のその他の任意の電力用半導体素子を使用する場合には、その一面と他面は、上記IGBT素子の上記の各面に対して機能的に対応する面となる。例えばNチャンネルのMOS−FETの場合には、IGBT素子のコレクタは「ドレイン」に対応し、IGBT素子のエミッタは「ソース」に対応する。
12 IGBTモジュール
21 高圧バスバー
22 絶縁膜
23 低圧バスバー
24 出力バスバー
25 第1金属配線板
26 第2金属配線板
402,404 IGBT素子
409,410 ダイオード素子
Claims (3)
- 同一平面上に並置した一対の半導体チップと、
一方の前記半導体チップの一面に接合されると共に高圧端子を有する高圧バスバーと、
他方の前記半導体チップの一面に接合されると共に低圧端子を有する低圧バスバーと、
前記一方の半導体チップの他面に接合される第1金属配線板と、
前記他方の半導体チップの他面に接合される第2金属配線板と、
前記第1金属配線板と前記第2金属配線板のそれぞれの端部から延在する出力端子を有する出力バスバーと、
を備え、
前記高圧バスバーの前記高圧端子と前記低圧バスバーの前記低圧端子は同一側に配置され、前記出力バスバーの前記出力端子は、前記高圧端子と前記低圧端子の間の電流経路の中間位置に配置され、
前記高圧バスバー、前記低圧バスバー、前記第1金属配線板、前記第2金属配線板及び前記出力バスバーをそれぞれ別部材として形成し、前記第1金属配線板と前記第2金属配線板との接合部に前記出力バスバーが接合されることを特徴とする半導体装置。 - 前記高圧端子から前記一方の半導体チップを経由した前記出力端子までの電流経路の長さと、前記低圧端子から前記他方の半導体チップを経由した前記出力端子までの電流経路の長さとを実質的に等しくしたことを特徴とする請求項1に記載の半導体装置。
- 一対の前記半導体チップの各々は電力用半導体素子と整流用半導体素子を備え、
前記整流用半導体素子に比べて前記電力用半導体素子に流れる電流の割合が多くなる半導体装置の駆動を行う場合、前記一方の半導体チップの前記電力用半導体素子は前記高圧バスバーで前記高圧端子に対して遠い側に配置され、前記他方の半導体チップの前記電力用半導体素子は前記第2金属配線板で前記低圧端子に対して遠い側に配置され、
前記整流用半導体素子に比べて前記電力用半導体素子に流れる電流の割合が少なくなる半導体装置の駆動を行う場合、前記一方の半導体チップの前記電力用半導体装置は前記高圧バスバーで前記高圧端子に対して近い側に配置され、前記他方の半導体チップの前記電力用半導体素子は前記第2金属配線板で前記低圧端子に対して近い側に配置されている、
ことを特徴とする請求項1または2に記載の半導体装置。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006161618A JP4977407B2 (ja) | 2006-06-09 | 2006-06-09 | 半導体装置 |
PCT/JP2007/060563 WO2007142038A1 (ja) | 2006-06-09 | 2007-05-17 | 半導体装置 |
CN2010101775292A CN101819965B (zh) | 2006-06-09 | 2007-05-17 | 半导体装置 |
EP20100158346 EP2202793A3 (en) | 2006-06-09 | 2007-05-17 | Semiconductor device |
EP10158345.8A EP2202792B1 (en) | 2006-06-09 | 2007-05-17 | Semiconductor device |
EP20070743997 EP2028692A4 (en) | 2006-06-09 | 2007-05-17 | SEMICONDUCTOR COMPONENT |
CN200780021119.5A CN101467252B (zh) | 2006-06-09 | 2007-05-17 | 半导体装置 |
US12/303,865 US8129836B2 (en) | 2006-06-09 | 2007-05-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006161618A JP4977407B2 (ja) | 2006-06-09 | 2006-06-09 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007329428A JP2007329428A (ja) | 2007-12-20 |
JP4977407B2 true JP4977407B2 (ja) | 2012-07-18 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006161618A Expired - Fee Related JP4977407B2 (ja) | 2006-06-09 | 2006-06-09 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10658344B2 (en) | 2018-09-14 | 2020-05-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5451994B2 (ja) * | 2008-07-30 | 2014-03-26 | 本田技研工業株式会社 | 電力変換装置の導体配置構造 |
WO2010131679A1 (ja) * | 2009-05-14 | 2010-11-18 | ローム株式会社 | 半導体装置 |
JP5703008B2 (ja) * | 2010-12-16 | 2015-04-15 | 新電元工業株式会社 | フレーム組立体、半導体装置及びその製造方法 |
JP5793295B2 (ja) * | 2010-12-16 | 2015-10-14 | 新電元工業株式会社 | 半導体装置 |
KR101246651B1 (ko) | 2011-04-13 | 2013-03-25 | 서울특별시도시철도공사 | 전동차 추진제어장치의 igbt 스택 |
US11271491B2 (en) | 2017-09-27 | 2022-03-08 | Aisin Corporation | Inverter module |
JP6852011B2 (ja) * | 2018-03-21 | 2021-03-31 | 株式会社東芝 | 半導体装置 |
CN112204733A (zh) * | 2018-05-30 | 2021-01-08 | 三菱电机株式会社 | 半导体模块以及电力变换装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4192396B2 (ja) * | 2000-04-19 | 2008-12-10 | 株式会社デンソー | 半導体スイッチングモジュ−ル及びそれを用いた半導体装置 |
JP4277169B2 (ja) * | 2003-01-06 | 2009-06-10 | 富士電機デバイステクノロジー株式会社 | 電力用半導体モジュール |
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- 2006-06-09 JP JP2006161618A patent/JP4977407B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10658344B2 (en) | 2018-09-14 | 2020-05-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10957673B2 (en) | 2018-09-14 | 2021-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
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JP2007329428A (ja) | 2007-12-20 |
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