WO2016183994A1 - 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2016183994A1
WO2016183994A1 PCT/CN2015/090500 CN2015090500W WO2016183994A1 WO 2016183994 A1 WO2016183994 A1 WO 2016183994A1 CN 2015090500 W CN2015090500 W CN 2015090500W WO 2016183994 A1 WO2016183994 A1 WO 2016183994A1
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Prior art keywords
transistor
clock signal
node
input
signal
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PCT/CN2015/090500
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English (en)
French (fr)
Inventor
郑灿
宋松
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京东方科技集团股份有限公司
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Priority to US15/300,930 priority Critical patent/US10290261B2/en
Publication of WO2016183994A1 publication Critical patent/WO2016183994A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • shift register unit in the related art which generally controls the level of the potential of the circuit output signal through a plurality of transistors and capacitors.
  • the inventors have found that the above method has at least the following drawbacks: the circuit structure of the shift register unit in the prior art is usually complicated, the control process is cumbersome, and the output pulse width cannot be adjusted.
  • the present disclosure provides a shift register unit, a driving method, a gate driving circuit, and a display device. .
  • the technical solution is as follows:
  • a shift register unit comprising: a first output module, a second output module, an input module, and a control module,
  • the first output module is respectively connected to the first signal end, the first node and the output end, and is configured to output, by the first node, a first control signal from the first signal end to the output end ;
  • the second output module is respectively connected to the output end, the second node, and the second signal end, and is configured to output a second from the second signal end to the output end under the control of the second node control signal;
  • the control module is respectively connected to the first node, the second node, the first signal end, the second signal end, the first clock signal end, and the second clock signal end, respectively Control of the first control signal of the first signal end, the second control signal of the second signal end, the first clock signal of the first clock signal end, and the second clock signal of the second clock signal end And controlling a potential of the first node and the second node;
  • the input module is respectively connected to the input end, the second node, and the second clock signal end, and is configured to be sent to the second node under the control of the second clock signal from the second clock signal end An input signal from the input is output.
  • the first output module includes: a first transistor and a first capacitor,
  • a first pole of the first transistor is connected to the first signal end, a second pole of the first transistor is connected to the output end, and a third pole of the first transistor is connected to the first node;
  • a first pole of the first capacitor is coupled to a first pole of the first transistor, and a second pole of the first capacitor is coupled to a third pole of the first transistor.
  • the second output module includes: a second transistor and a third capacitor,
  • a first pole of the second transistor is coupled to the second signal terminal, a second pole of the second transistor is coupled to the output terminal, and a third pole of the second transistor is coupled to the second node ;
  • a first pole of the third capacitor is coupled to a second pole of the second transistor, and a second pole of the third capacitor is coupled to a third pole of the second transistor.
  • control module includes: a pull-up control sub-module and a reset sub-module;
  • the pull-up control sub-module is respectively connected to the first clock signal end, the second clock signal end, the second signal end, the first node, and the third node, for Control of a second control signal of the second signal terminal, a reset control signal from the third node, the first clock signal from the first clock signal terminal, and the second clock signal from the second clock signal terminal Controlling a potential of the first node;
  • the reset submodule is respectively connected to the first node, the second node, the third node, the first signal end, and the second clock signal end, for the first control signal Controlling a potential of the first node, a potential of the second node, and a potential of the third node under control of the second clock signal, the first control signal being from the first signal end, Second time
  • the clock signal is from the second clock signal terminal.
  • the pull-up control sub-module includes: a second capacitor, a seventh transistor, an eighth transistor, and a ninth transistor,
  • a first pole of the seventh transistor is connected to the fourth node, a second pole of the seventh transistor is connected to the first node, and a third pole of the seventh transistor is connected to the first clock signal end ;
  • a second pole of the eighth transistor is connected to the fourth node, a first pole of the eighth transistor is connected to the first clock signal end, and a third pole of the eighth transistor is opposite to the third Node connection
  • a second pole of the ninth transistor is connected to the third node, a first pole of the ninth transistor is connected to the second signal terminal, and a third pole of the ninth transistor is opposite to the second clock Signal terminal connection;
  • a first pole of the second capacitor is coupled to the third node, and a second pole of the second capacitor is coupled to the fourth node.
  • the reset submodule includes: a fourth transistor, a fifth transistor, and a sixth transistor.
  • a second pole of the fourth transistor is connected to the first node, a first pole of the fourth transistor is connected to the first signal end, and a third pole of the fourth transistor is connected to the second node connection;
  • a first pole of the fifth transistor is connected to the second node, a second pole of the fifth transistor is connected to a third pole of the sixth transistor, and a third pole of the fifth transistor is The second clock signal terminal is connected;
  • the second pole of the sixth transistor is connected to the third node, and the first pole of the sixth transistor is connected to the first signal end.
  • the input module includes: a third transistor,
  • a second pole of the third transistor is connected to the second node, a first pole of the third transistor is connected to the input end, and a third pole of the third transistor and the second clock signal end connection.
  • the transistors are all P-type transistors.
  • a shift register unit driving method for driving the shift register unit of the first aspect comprising: a first output module, a second output module, An input module and a control module, the method comprising:
  • the first stage the input signal input to the input terminal is the first potential, and the input signal of the second clock signal terminal is input.
  • the second clock signal is a second potential, and the input module inputs the input signal to the second node under the control of the second clock signal input by the second clock signal end;
  • the first clock signal input by the first clock signal terminal is a second potential
  • the second clock signal input by the second clock signal terminal is a first potential
  • the control module is controlled to input to the first node.
  • the first clock signal from the first clock signal end, under the control of the first node, the first output module inputs a first control signal from the first signal end to the output end;
  • the second node maintains a first potential
  • the second output module, the input module, and the control module repeatedly perform the processes of the first phase and the second phase
  • the second clock signal end inputs the second clock signal
  • the input module outputs the source to the second node under the control of the second clock signal from the second clock signal end
  • the input signal at the input end, the input signal is at a second potential
  • the second output module inputs a second control signal from the second signal end to the output end
  • the control module inputs the first control signal from the first signal end to the first node.
  • the first output module includes: a first transistor and a first capacitor,
  • the control module inputs the first clock signal from the first clock signal end to the first node, the first clock signal is at a second potential, and the first transistor is turned on.
  • the first capacitor is charged, and the first transistor inputs the first control signal from the first signal end to the output terminal;
  • control module inputs the first control signal from the first signal end to the first node, and the first transistor is turned off.
  • the second output module includes: a second transistor and a third capacitor,
  • the input module outputs the input signal from the input terminal to the second node, the input signal is at a first potential, the second transistor is turned off, and the third capacitor is Charging
  • the input module outputs the input signal from the input terminal to the second node, the input signal is at a second potential, the second transistor is turned on, and the second transistor is turned to The output terminal outputs the second control signal from the second signal terminal.
  • control module includes: a pull-up control sub-module and a reset sub-module,
  • the first clock signal terminal inputs the first clock signal, the first clock signal is at a second potential, and the second clock signal terminal inputs the second clock signal,
  • the second clock signal is at a first potential, and the pull-up control sub-module resets the first node to a second potential;
  • the input signal input by the input terminal is at a second potential
  • the reset submodule inputs the first control signal from the first signal end to a third node.
  • the pull-up control sub-module includes: a second capacitor, a seventh transistor, an eighth transistor, and a ninth transistor,
  • the second clock signal end inputs the second clock signal, the second clock signal is at a second potential, the ninth transistor is turned on, and the second signal end is Three nodes input the second control signal;
  • the first clock signal terminal inputs the first clock signal
  • the first clock signal is at a second potential
  • the second clock signal terminal inputs the second clock signal
  • the second clock signal is at a first potential
  • the ninth transistor is turned off
  • the seventh transistor is turned on
  • the eighth transistor is turned on
  • the first clock signal end inputs the first clock signal to a fourth node
  • the fourth node resets the first node to a second potential
  • the reset submodule includes: a fourth transistor, a fifth transistor, and a sixth transistor.
  • the second clock signal end inputs the second clock signal
  • the second clock signal is at a second potential
  • the input module inputs the input from the input end to the second node.
  • An input signal, the input signal is at a second potential
  • the fourth transistor is turned on
  • the fifth transistor is turned on
  • the sixth transistor is turned on
  • the first signal end is toward the first node
  • the first The three nodes input the first control signal.
  • the input module includes: a third transistor,
  • the input terminal outputs the input signal, the input signal is at a first potential, the second clock signal terminal inputs the second clock signal, and the second clock signal is at a second a potential to control the third transistor to be turned on, the third transistor inputting the input signal from the input terminal to the second node;
  • the third transistor is turned off under the control of the second clock signal from the second clock signal terminal, and the second clock signal is at a first potential;
  • the second clock signal terminal inputs the second clock signal, the second clock signal is at a second potential, and the third transistor is located at a second from the second clock signal end. Controlling, by the second clock signal of the potential, a second potential from the input terminal to the second node, and when the second clock signal input by the second clock signal terminal jumps to a first potential, The third transistor is turned off.
  • the transistors are all P-type transistors.
  • the first potential is at a high potential relative to the second potential.
  • a gate driving circuit comprising at least two cascaded shift register units as described in the first aspect.
  • a display device comprising the gate drive circuit of the third aspect.
  • the first output module, the second output module, the input module and the control module are used to control the potential level of the output of the output terminal, which solves the problem that the circuit structure of the shift register unit in the related art is usually complicated and the control process is cumbersome;
  • the circuit structure is simple and the output pulse width can be adjusted.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an exemplary embodiment
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an exemplary embodiment
  • FIG. 3 is a schematic structural diagram of another shift register unit according to an exemplary embodiment
  • FIG. 4 is a flowchart of a shift register unit driving method according to an exemplary embodiment
  • FIG. 5 is a first stage of the shift register unit driving method provided by the embodiment shown in FIG. Effective circuit diagram
  • FIG. 6 is an equivalent circuit diagram of a second stage of the shift register unit driving method provided by the embodiment shown in FIG. 4;
  • FIG. 7 is an equivalent circuit diagram of a third stage of the shift register unit driving method provided by the embodiment shown in FIG. 4;
  • FIG. 8 is an equivalent circuit diagram of a fourth stage of the shift register unit driving method provided by the embodiment shown in FIG. 4;
  • FIG. 9 is an equivalent circuit diagram of the fifth stage of the shift register unit driving method provided by the embodiment shown in FIG. 4; FIG.
  • FIG. 10 is a schematic diagram showing potential changes of a first clock signal terminal, a second clock signal terminal, an input terminal, an output terminal, a first node, a second node, a third node, and a fourth node in various embodiments of the present disclosure.
  • the transistors employed in all of the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first stage, the drain is referred to as a second stage, and the gate is referred to as a third level. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure is generally a P-type switching transistor, and the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the plurality of signals in various embodiments of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential represent only two state quantities of the potential of the signal. It does not mean that the first potential or the second potential in the full text has a specific value.
  • the first control signal can be a high potential signal and the second control signal can be a low potential signal.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an exemplary embodiment.
  • the shift register unit may include a first output module 110, a second output module 120, a control module 130, and an input module 140.
  • the first output module 110 is respectively connected to the first signal terminal VGH, the first node B and the output terminal Out_EM for outputting the first control signal from the first signal terminal VGH to the output terminal Out_EM under the control of the first node B. .
  • the second output module 120 is respectively connected to the output terminal Out_EM, the second node A and the second signal terminal VGL for outputting the second control signal from the second signal terminal VGL to the output terminal Out_EM under the control of the second node A. .
  • the control module 130 is respectively connected to the first node B, the second node A, the first signal terminal VGH, the second signal terminal VGL, the first clock signal terminal CKB and the second clock signal terminal CK for being used from the first signal terminal. Controlling the first node B and the first control signal of the VGH, the second control signal of the second signal terminal VGL, the first clock signal of the first clock signal terminal CKB, and the second clock signal of the second clock signal terminal CK The potential of the second node A.
  • the input module 140 is respectively connected to the input terminal STV, the second node A, and the second clock signal terminal CK for outputting the second node A from the input terminal STV under the control of the second clock signal from the second clock signal terminal CK. Input signal.
  • the shift register unit provided by the embodiment of the present disclosure controls the output level of the output terminal through the first output module, the second output module, the input module, and the control module, thereby solving the problem.
  • the circuit structure of the shift register unit is usually complicated, and the control process is cumbersome; the circuit structure is simple and the output pulse width can be adjusted.
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • the shift register unit adds a more preferable structure to the shift register unit shown in FIG. 1 .
  • control module 130 includes: a pull-up control sub-module 131 and a reset sub-module 132.
  • the pull-up control sub-module 131 is respectively connected to the first clock signal terminal CKB, the second clock signal terminal CK, the second signal terminal VGL, the first node B and the third node E for the second signal terminal VGL.
  • the potential of the first node B is controlled under the control of the second control signal, the reset control signal from the third node E, the first clock signal from the first clock signal terminal CKB, and the second clock signal from the second clock signal terminal CK.
  • the reset sub-module 132 is respectively connected to the third node E, the first signal terminal VGH, the second clock signal terminal CK, the second node A and the first node B for controlling under the first control signal and the second clock signal
  • the potential of the first node B, the potential of the second node A, and the potential of the third node E are controlled, the first control signal is from the first signal terminal VGH, and the second clock signal is from the second clock signal terminal CK.
  • FIG. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • the pull-up control sub-module 131 includes: a second capacitor C2, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the first pole of the seventh transistor M7 is connected to the fourth node C
  • the second pole of the seventh transistor M7 is connected to the first node B
  • the third pole of the seventh transistor M7 is connected to the first clock signal terminal CKB.
  • the second pole of the eighth transistor M8 is connected to the fourth node C
  • the first pole of the eighth transistor M8 is connected to the first clock signal terminal CKB
  • the third pole of the eighth transistor M8 is connected to the third node E.
  • the second pole of the ninth transistor M9 is connected to the third node E, the first pole of the ninth transistor M9 is connected to the second signal terminal VGL, and the third pole of the ninth transistor M9 is connected to the second clock signal terminal CK.
  • the first pole of the second capacitor C2 is connected to the third node E, and the second pole of the second capacitor C2 is connected to the fourth node C.
  • the reset sub-module 132 includes: a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the second pole of the fourth transistor M4 is connected to the first node B, the first pole of the fourth transistor M4 is connected to the first signal terminal VGH, and the third pole of the fourth transistor M4 is connected to the second node A.
  • the first pole of the fifth transistor M5 is connected to the second node A, the second pole of the fifth transistor M5 is connected to the third pole of the sixth transistor M6, and the third pole of the fifth transistor M5 is connected to the second clock signal terminal CK. .
  • the second pole of the sixth transistor M6 is connected to the third node E, and the first pole of the sixth transistor M6 is connected to the first signal terminal VGH.
  • the first output module 110 includes: a first transistor M1 and a first capacitor C1.
  • the first pole of the first transistor M1 is connected to the first signal terminal VGH, the second pole of the first transistor M1 is connected to the output terminal OUT_EM, and the third pole of the first transistor M1 is connected to the first node B.
  • the first pole of the first capacitor C1 is connected to the first pole of the first transistor M1, and the second pole of the first capacitor C1 is connected to the third pole of the first transistor M1.
  • the second output module 120 includes: a second transistor M2 and a third capacitor C3.
  • the first pole of the second transistor M2 is connected to the second signal terminal VGL, the second pole of the second transistor M2 is connected to the output terminal OUT_EM, and the third pole of the second transistor M2 is connected to the second node A.
  • the first pole of the third capacitor C3 is connected to the second pole of the second transistor M2, and the second pole of the third capacitor C3 is connected to the third pole of the second transistor M2.
  • the input module 140 includes: a third transistor M3.
  • the second pole of the third transistor M3 is connected to the second node, the first pole of the third transistor M3 is connected to the input terminal STV, and the third pole of the third transistor M3 is connected to the second clock signal terminal CK.
  • the shift register unit provided by the embodiment of the present disclosure completes the control of the potential of the output terminal through nine transistors and three capacitors, simplifies the structure of the shift register unit, and reduces the shift.
  • the effect of the register layout area is advantageous for the manufacture of high resolution display devices.
  • the shift register unit provided by the embodiment of the present disclosure controls the potential level of the output terminal through the first output module, the second output module, the input module, and the control module, and solves the related art shift register unit.
  • the circuit structure is usually complicated, and the control process is cumbersome.
  • the problem is achieved: the circuit structure is simple and the output pulse width can be adjusted.
  • FIG. 4 is a flowchart of a shift register unit driving method according to an exemplary embodiment.
  • the structure of the shift register unit can be as shown in FIG. 1 , including: a first output module 110 , a second output module 120 , a control module 130 , and an input module 140 .
  • the shift register unit driving method includes:
  • Step 401 the first stage: the input signal input by the input terminal STV is the first potential, and the second clock signal input by the second clock signal terminal CK is the second potential.
  • the input module 140 inputs an input signal to the second node A under the control of the second clock signal input by the second clock signal terminal CK.
  • the equivalent circuit diagram of the first stage can be as shown in FIG. 5, wherein the meanings of the respective labels are the same as those in FIG.
  • the first phase is the preparatory phase.
  • Step 402 The second phase: the first clock signal input by the first clock signal terminal CKB is the second potential, the second clock signal input by the second clock signal terminal CK is the first potential, and the control control module 130 is directed to the first node B.
  • the first clock signal from the first clock signal terminal is input, and under the control of the first node B, the first output module 110 outputs a first control signal from the first signal terminal VGH to the output terminal OUT_EM.
  • the equivalent circuit diagram of the second stage can be as shown in FIG. 6, wherein the meanings of the respective labels are the same as those in FIG.
  • the second phase is the pull-up phase.
  • Step 403 the third stage: the second node A maintains the first potential, and the second output module 120, the input module 140, and the control module 130 repeatedly perform the processes of the first phase and the second phase.
  • the equivalent circuit diagram of the third stage can be as shown in FIG. 7, wherein the meanings of the respective labels are the same as those in FIG.
  • the third stage is the high potential maintenance phase.
  • Step 404 the fourth stage: the second clock signal terminal CK inputs the second clock signal, and the input module 140 outputs the second input node STV to the second node A under the control of the second clock signal from the second clock signal terminal CK.
  • the equivalent circuit diagram of the fourth stage can be as shown in FIG. 8, wherein the meanings of the respective labels are the same as those in FIG.
  • the fourth stage is the pull-down stage.
  • Step 405 the fifth stage: the input terminal STV maintains the second potential, periodically repeats the fourth phase, so that the first node B maintains the first potential, the second node A maintains the second potential, and the output terminal OUT_EM maintains the second potential.
  • the equivalent circuit diagram of the fifth step can be as shown in FIG. 9, wherein each label has the meaning and Consistent in Figure 3.
  • the fifth stage is the low potential maintenance phase.
  • the shift register unit driving method provided by the embodiment of the present disclosure can control the potential level of the output terminal OUT_EM output by controlling the input terminal STV at the holding time of the first potential.
  • control module 130 includes: a pull-up control sub-module 131 and a reset sub-module 132.
  • the step 402 may include: in the second phase, the first clock signal terminal CKB inputs the first clock signal, the first clock signal is at the second potential, and the second clock signal terminal CK is input to the second clock signal, the second clock signal At the first potential, the pull up control sub-module 131 resets the first node B to the second potential.
  • the equivalent circuit diagram of the second stage can be as shown in FIG. 6.
  • Step 404 may include: in the fourth stage, the second clock signal terminal CK inputs a second clock signal, the input terminal STV inputs a second potential, and the reset sub-module 132 inputs the first control from the first signal terminal VGH to the third node E. signal.
  • the equivalent circuit diagram of the fourth stage can be as shown in FIG.
  • the pull-up control sub-module 131 includes a second capacitor C2, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the step 401 may include: in the first phase, the second clock signal terminal CK inputs the second clock signal, the second clock signal is at the second potential, the ninth transistor M9 is turned on, and the second signal terminal VGL is turned to the third node E. Enter the second control signal.
  • the equivalent circuit diagram of the first stage can be as shown in Figure 5.
  • Step 402 may include: in the second phase, the first clock signal terminal CKB inputs a first clock signal, the first clock signal is at a second potential, the second clock signal terminal CK inputs a second clock signal, and the second clock signal is at the first Potential, the ninth transistor M9 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, the first clock signal terminal CKB inputs the first clock signal to the fourth node C to the second potential, and the fourth node C is to the first node. B enters the second potential.
  • the eighth transistor M8 since the eighth transistor M8 is turned on in the first stage, the fourth node C is pulled to the first potential by the first clock signal terminal CKB, so the third node E to the fourth node of the two ends of the second capacitor C2 C stores a negative potential.
  • the eighth transistor M8 can be turned on very well. After the first clock signal terminal CKB jumps to the input first potential, the seventh transistor M7 is turned off, and the first potential of the first clock signal terminal CKB is input. Will not be input to the first node B.
  • the equivalent circuit diagram of the second stage can be as shown in FIG. 6.
  • the reset sub-module 132 includes: a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the second clock signal terminal CK inputs the second clock signal
  • the second clock signal is at the second potential
  • the input module 140 inputs the input signal from the input terminal STV to the second node A to the second potential
  • the fourth transistor. M4 is turned on
  • the fifth transistor M5 is turned on
  • the sixth transistor M6 is turned on
  • the first signal terminal VGH inputs the first control signal to the first node B and the third node E.
  • the equivalent circuit diagram of the fourth stage can be as shown in FIG.
  • the first output module 110 includes: a first transistor M1 and a first capacitor C1.
  • Step 402 may include: the second stage control module 130 inputs a first clock signal to the first node B, the first clock signal is at the second potential, the first transistor M1 is turned on, the first capacitor C1 is charged, and the first transistor M1 is output to the output end.
  • OUT_EM outputs a first control signal from the first signal terminal VGH.
  • Step 404 can include, in the fourth phase, the control module 130 inputs a first potential to the first node B, and the first transistor M1 is turned off.
  • the four-stage equivalent circuit diagram can be as shown in Figure 8.
  • the second output module 120 includes: a second transistor M2 and a third capacitor C3.
  • step 401 may include: in the first stage, the input module 140 outputs an input signal from the input terminal STV to the second node A, the input signal is at the first potential, the second transistor M2 is turned off, and the third capacitor C3 is charged.
  • the equivalent circuit diagram of the first stage can be as shown in Figure 5.
  • Step 404 may include: in the fourth stage, the input module 140 outputs an input signal from the input terminal STV to the second node A, the input signal is at the second potential, the second transistor M2 is turned on, and the second transistor M2 is outputted to the output terminal OUT_EM. a second control signal of the second signal terminal VGL.
  • the four-stage equivalent circuit diagram can be as shown in Figure 8.
  • the input module 140 includes: a third transistor M3.
  • the step 401 may include: in the first stage, the input terminal STV outputs an input signal, the input signal is at the first potential, the second clock signal terminal CK inputs the second clock signal, and the second clock signal is at the second potential, and the control
  • the three transistor M3 is turned on, and the third transistor M3 inputs an input signal from the input terminal STV to the second node A.
  • the equivalent circuit diagram of the first stage can be as shown in Figure 5.
  • Step 403 may include: in the third phase, the input signal at the input terminal STV jumps to the second Before the potential, the third transistor M3 is turned off under the control of the second clock signal from the second clock signal terminal CK, at which time the second clock signal is at the first potential.
  • the equivalent circuit diagram of the third stage can be as shown in FIG.
  • Step 404 may include: in the fourth phase, the second clock signal terminal CK inputs a second clock signal, the second clock signal is at a second potential, and the third transistor M3 is at a second clock signal from the second clock signal terminal CK.
  • the input signal from the input terminal STV is output to the second node A as the second potential under the control of the two potentials.
  • the third transistor M3 is turned off.
  • the four-stage equivalent circuit diagram can be as shown in Figure 8.
  • first clock signal terminal CKB the second clock signal terminal CK, the input terminal STV, the output terminal OUT_EM, the first node B, the second node A, the third node E, and the fourth node involved in various embodiments of the present disclosure are involved.
  • the potential change of C in the first phase t1, the second phase t2, the third phase t3, the fourth phase t4, and the fifth phase t5 can be referred to FIG. 10.
  • the horizontal axis represents time and the vertical axis represents potential.
  • the shift register unit provided by the embodiment of the present disclosure completes the control of the potential of the output terminal through nine transistors and three capacitors, simplifies the structure of the shift register unit, and reduces the shift.
  • the effect of the register layout area is advantageous for the manufacture of high resolution display devices.
  • the shift register unit driving method controls the output level of the output terminal through the first output module, the second output module, the input module, and the control module, thereby solving the shift in the related art.
  • the circuit structure of the register unit is usually complicated, and the control process is cumbersome; the circuit structure is simple and the output pulse width can be adjusted.
  • the present disclosure provides a gate drive circuit comprising at least two cascaded shift register units as shown in FIG. 1, FIG. 2 or FIG.
  • the present disclosure also provides a display device including the gate drive circuit.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。移位寄存器单元包括：第一输出模块（110）、第二输出模块（120）、输入模块（140）和控制模块（130），第一输出模块（110）分别与第一信号端（VGH）、第一节点（B）和输出端（OUT_EM）连接；第二输出模块（120）分别与输出端（OUT_EM）、第二节点（A）和第二信号端（VGL）连接；控制模块（130）分别与第一节点（B）、第二节点（A）、第一信号端（VGH）、第二信号端（VGL）、第一时钟信号端（CKB）和第二时钟信号端（CK）连接；输入模块（140）分别与输入端（STV）、第二节点（A）、第二时钟信号端（CK）连接。

Description

移位寄存器单元、驱动方法、栅极驱动电路及显示装置
相关申请的交叉引用
本申请主张在2015年5月21日在中国提交的中国专利申请号No.201510263912.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
背景技术
在显示技术领域，为了不断改善显示画面，提高用户体验，高清、窄边框显示成了研究的热门。但随着像素数目的提高，移位寄存器(栅极开关电路)在一帧时间内所需扫描的行数增加，这就要求移位寄存器单元的版图面积要更小，电路结构需要更简单。
相关技术中有一种移位寄存器单元，它通常通过多个晶体管和电容器来控制电路输出信号的电位的高低。
发明人在实现本公开的过程中，发现上述方式至少存在如下缺陷：现有技术中的移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐，无法调节输出脉宽。
发明内容
为了解决相关技术中移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐，无法调节输出脉宽的问题，本公开提供了一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。所述技术方案如下：
根据本公开的第一方面，提供一种移位寄存器单元，所述移位寄存器单元包括：第一输出模块、第二输出模块、输入模块和控制模块，
所述第一输出模块分别与第一信号端、第一节点和输出端连接，用于在所述第一节点的控制下，向所述输出端输出来自所述第一信号端的第一控制信号；
所述第二输出模块分别与所述输出端、第二节点和第二信号端连接，用于在所述第二节点的控制下，向所述输出端输出来自所述第二信号端的第二 控制信号；
所述控制模块分别与所述第一节点、所述第二节点、所述第一信号端、所述第二信号端、第一时钟信号端和第二时钟信号端连接，用于在来自所述第一信号端的所述第一控制信号、所述第二信号端的所述第二控制信号、所述第一时钟信号端的第一时钟信号和所述第二时钟信号端的第二时钟信号的控制下，控制所述第一节点和所述第二节点的电位；
所述输入模块分别与输入端、所述第二节点、所述第二时钟信号端连接，用于在来自所述第二时钟信号端的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的输入信号。
可选的，所述第一输出模块包括：第一晶体管和第一电容器，
所述第一晶体管的第一极与所述第一信号端连接，所述第一晶体管的第二极与所述输出端连接，所述第一晶体管的第三极与第一节点连接；
所述第一电容器的第一极与所述第一晶体管的第一极连接，所述第一电容器的第二极与所述第一晶体管的第三极连接。
可选的，所述第二输出模块包括：第二晶体管和第三电容器，
所述第二晶体管的第一极与所述第二信号端连接，所述第二晶体管的第二极与所述输出端连接，所述第二晶体管的第三极与所述第二节点连接；
所述第三电容器的第一极与所述第二晶体管的第二极连接，所述第三电容器的第二极与所述第二晶体管的第三极连接。
可选的，所述控制模块包括：上拉控制子模块和复位子模块；
所述上拉控制子模块分别与所述第一时钟信号端、所述第二时钟信号端、所述第二信号端、所述第一节点和第三节点连接，用于在来自所述第二信号端的第二控制信号、来自所述第三节点的复位控制信号、来自所述第一时钟信号端的所述第一时钟信号和所述第二时钟信号端的所述第二时钟信号的控制下控制所述第一节点的电位；
所述复位子模块分别与所述第一节点、所述第二节点、所述第三节点、所述第一信号端和所述第二时钟信号端连接，用于在所述第一控制信号和所述第二时钟信号的控制下控制所述第一节点的电位、所述第二节点的电位和所述第三节点的电位，所述第一控制信号来自所述第一信号端，所述第二时 钟信号来自所述第二时钟信号端。
可选的，所述上拉控制子模块包括：第二电容器、第七晶体管、第八晶体管和第九晶体管，
所述第七晶体管的第一极与第四节点连接，所述第七晶体管的第二极与所述第一节点连接，所述第七晶体管的第三极与所述第一时钟信号端连接；
所述第八晶体管的第二极与所述第四节点连接，所述第八晶体管的第一极与所述第一时钟信号端连接，所述第八晶体管的第三极与所述第三节点连接；
所述第九晶体管的第二极与所述第三节点连接，所述第九晶体管的第一极与所述第二信号端连接，所述第九晶体管的第三极与所述第二时钟信号端连接；
所述第二电容器的第一极与所述第三节点连接，所述第二电容器的第二极与所述第四节点连接。
可选的，所述复位子模块包括：第四晶体管、第五晶体管和第六晶体管，
所述第四晶体管的第二极与所述第一节点连接，所述第四晶体管的第一极与所述第一信号端连接，所述第四晶体管的第三极与所述第二节点连接；
所述第五晶体管的第一极与所述第二节点连接，所述第五晶体管的第二极与所述第六晶体管的第三极连接，所述第五晶体管的第三极与所述第二时钟信号端连接；
所述第六晶体管的第二极与所述第三节点连接，所述第六晶体管的第一极与所述第一信号端连接。
可选的，所述输入模块包括：第三晶体管，
所述第三晶体管的第二极与所述第二节点连接，所述第三晶体管的第一极与所述输入端连接，所述第三晶体管的第三极与所述第二时钟信号端连接。
可选的，所述晶体管均为P型晶体管。
根据本公开的第二方面，提供一种移位寄存器单元驱动方法，用于驱动第一方面所述的移位寄存器单元，所述移位寄存器单元包括：第一输出模块、第二输出模块、输入模块和控制模块，所述方法包括：
第一阶段：输入端输入的输入信号为第一电位，第二时钟信号端输入的 第二时钟信号为第二电位，所述输入模块在所述第二时钟信号端输入的所述第二时钟信号的控制下，向第二节点输入所述输入信号；
第二阶段：第一时钟信号端输入的第一时钟信号为第二电位，所述第二时钟信号端输入的所述第二时钟信号为第一电位，控制所述控制模块向第一节点输入来自所述第一时钟信号端的所述第一时钟信号，在所述第一节点的控制下，所述第一输出模块向输出端输入来自第一信号端的第一控制信号；
第三阶段：所述第二节点保持第一电位，所述第二输出模块、所述输入模块和所述控制模块重复执行所述第一阶段和所述第二阶段的过程；
第四阶段：所述第二时钟信号端输入所述第二时钟信号，所述输入模块在来自所述第二时钟信号端的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，在所述第二节点的控制下，所述第二输出模块向所述输出端输入来自第二信号端的第二控制信号，所述控制模块向所述第一节点输入来自所述第一信号端的所述第一控制信号。
可选的，所述第一输出模块包括：第一晶体管和第一电容器，
所述第二阶段中，所述控制模块向所述第一节点输入来自所述第一时钟信号端的所述第一时钟信号，所述第一时钟信号处于第二电位，所述第一晶体管开启，所述第一电容器充电，所述第一晶体管向所述输出端输入来自所述第一信号端的所述第一控制信号；
所述第四阶段中，所述控制模块向所述第一节点输入来自所述第一信号端的所述第一控制信号，所述第一晶体管关断。
可选的，所述第二输出模块包括：第二晶体管和第三电容器，
所述第一阶段中，所述输入模块向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第一电位，所述第二晶体管关断，所述第三电容器充电；
所述第四阶段中，所述输入模块向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第二晶体管开启，所述第二晶体管向所述输出端输出来自所述第二信号端的所述第二控制信号。
可选的，所述控制模块包括：上拉控制子模块和复位子模块，
所述第二阶段中，所述第一时钟信号端输入所述第一时钟信号，所述第一时钟信号处于第二电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第一电位，所述上拉控制子模块将所述第一节点复位到第二电位；
所述第四阶段中，所述输入端输入的输入信号处于第二电位，所述复位子模块向第三节点输入来自所述第一信号端的所述第一控制信号。
可选的，所述上拉控制子模块包括：第二电容器、第七晶体管、第八晶体管和第九晶体管，
所述第一阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述第九晶体管开启，所述第二信号端向所述第三节点输入所述第二控制信号；
所述第二阶段中，所述第一时钟信号端输入所述第一时钟信号，所述第一时钟信号处于第二电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第一电位，所述第九晶体管关断，所述第七晶体管开启，所述第八晶体管开启，所述第一时钟信号端向第四节点输入所述第一时钟信号，所述第四节点将所述第一节点复位到第二电位，所述第一时钟信号端输入的所述第一时钟信号跳变为第一电位后，所述第七晶体管关断。
可选的，所述复位子模块包括：第四晶体管、第五晶体管和第六晶体管，
所述第四阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述输入模块向所述第二节点输入来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第四晶体管开启，所述第五晶体管开启，所述第六晶体管开启，所述第一信号端向所述第一节点和所述第三节点输入所述第一控制信号。
可选的，所述输入模块包括：第三晶体管，
所述第一阶段中，所述输入端输出所述输入信号，所述输入信号处于第一电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，控制所述第三晶体管开启，所述第三晶体管向所述第二节点输入来自所述输入端的所述输入信号；
所述第三阶段中，在所述输入端的所述输入信号跳变为第二电位前，所 述第三晶体管在来自所述第二时钟信号端的所述第二时钟信号的控制下关断，所述第二时钟信号处于第一电位；
所述第四阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述第三晶体管在来自所述第二时钟信号端的位于第二电位的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的第二电位，所述第二时钟信号端输入的所述第二时钟信号跳变为第一电位时，所述第三晶体管关断。
可选的，所述晶体管均为P型晶体管。
可选的，所述第一电位相对于所述第二电位为高电位。
根据本公开的第三方面，提供一种栅极驱动电路，包括至少两个级联的如第一方面所述的移位寄存器单元。
根据本公开的第四方面，提供一种显示装置，所述显示装置包括第三方面所述的栅极驱动电路。
本公开实施例提供的技术方案可以包括以下有益效果：
通过第一输出模块、第二输出模块、输入模块和控制模块来控制输出端输出的电位高低，解决了相关技术中移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐的问题；达到了电路结构简单且输出脉宽可调节的效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1是根据一示例性实施例示出的一种移位寄存器单元的结构示意图；
图2是根据一示例性实施例示出的另一种移位寄存器单元的结构示意图；
图3是根据一示例性实施例示出的另一种移位寄存器单元的结构示意图；
图4是根据一示例性实施例示出的一种移位寄存器单元驱动方法的流程图；
图5是图4所示实施例提供的移位寄存器单元驱动方法中第一阶段的等 效电路图；
图6是图4所示实施例提供的移位寄存器单元驱动方法中第二阶段的等效电路图；
图7是图4所示实施例提供的移位寄存器单元驱动方法中第三阶段的等效电路图；
图8是图4所示实施例提供的移位寄存器单元驱动方法中第四阶段的等效电路图；
图9是图4所示实施例提供的移位寄存器单元驱动方法中第五阶段的等效电路图；
图10是本公开各个实施例中的第一时钟信号端、第二时钟信号端、输入端、输出端、第一节点、第二节点、第三节点和第四节点的电位变化示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用，本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级，栅极称为第三极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开实施例所采用的开关晶体管通常为P型开关晶体管，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量。 不代表全文中第一电位或第二电位具有特定的数值。例如，第一控制信号可以为高电位信号，第二控制信号可以为低电位信号。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
图1是根据一示例性实施例示出的一种移位寄存器单元的结构示意图。该移位寄存器单元可以包括：第一输出模块110、第二输出模块120、控制模块130和输入模块140。
第一输出模块110分别与第一信号端VGH、第一节点B和输出端Out_EM连接，用于在第一节点B的控制下，向输出端Out_EM输出来自第一信号端VGH的第一控制信号。
第二输出模块120分别与输出端Out_EM、第二节点A和第二信号端VGL连接，用于在第二节点A的控制下，向输出端Out_EM输出来自第二信号端VGL的第二控制信号。
控制模块130分别与第一节点B、第二节点A、第一信号端VGH、第二信号端VGL、第一时钟信号端CKB和第二时钟信号端CK连接，用于在来自第一信号端VGH的第一控制信号、第二信号端VGL的第二控制信号、第一时钟信号端CKB的第一时钟信号和第二时钟信号端CK的第二时钟信号的控制下控制第一节点B和第二节点A的电位。
输入模块140分别与输入端STV、第二节点A、第二时钟信号端CK连接，用于在来自第二时钟信号端CK的第二时钟信号的控制下向第二节点A输出来自输入端STV的输入信号。
综上所述，本公开实施例提供的移位寄存器单元，通过第一输出模块、第二输出模块、输入模块和控制模块来控制输出端输出的电位高低，解决了 相关技术中移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐的问题；达到了电路结构简单且输出脉宽可调节的效果。
进一步的，请参考图2，其为本公开实施例提供的另一种移位寄存器单元的结构示意图，该移位寄存器单元在图1所示的移位寄存器单元的基础上增加了更优选的部件，从而使得本公开实施例提供的移位寄存器单元具有更好的性能。
可选的，控制模块130包括：上拉控制子模块131和复位子模块132。
上拉控制子模块131分别与第一时钟信号端CKB、第二时钟信号端CK、第二信号端VGL、第一节点B和第三节点E连接，用于在来自第二信号端VGL的第二控制信号、来自第三节点E的复位控制信号、来自第一时钟信号端CKB的第一时钟信号和第二时钟信号端CK的第二时钟信号的控制下控制第一节点B的电位。
复位子模块132分别与第三节点E、第一信号端VGH、第二时钟信号端CK、第二节点A和第一节点B连接，用于在第一控制信号和第二时钟信号的控制下控制第一节点B的电位、第二节点A的电位和第三节点E的电位，第一控制信号来自第一信号端VGH，第二时钟信号来自第二时钟信号端CK。
如图3所示，其为本公开实施例提供的另一种移位寄存器单元的结构示意图。
可选的，上拉控制子模块131包括：第二电容器C2、第七晶体管M7、第八晶体管M8和第九晶体管M9。
第七晶体管M7的第一极与第四节点C连接，第七晶体管M7的第二极与第一节点B连接，第七晶体管M7的第三极与第一时钟信号端CKB连接。
第八晶体管M8的第二极与第四节点C连接，第八晶体管M8的第一极与第一时钟信号端CKB连接，第八晶体管M8的第三极与第三节点E连接。
第九晶体管M9的第二极与第三节点E连接，第九晶体管M9的第一极与第二信号端VGL连接，第九晶体管M9的第三极与第二时钟信号端CK连接。
第二电容器C2的第一极与第三节点E连接，第二电容器C2的第二极与第四节点C连接。
可选的，复位子模块132包括：第四晶体管M4、第五晶体管M5和第六晶体管M6。
第四晶体管M4的第二极与第一节点B连接，第四晶体管M4的第一极与第一信号端VGH连接，第四晶体管M4的第三极与第二节点A连接。
第五晶体管M5的第一极与第二节点A连接，第五晶体管M5的第二极与第六晶体管M6的第三极连接，第五晶体管M5的第三极与第二时钟信号端CK连接。
第六晶体管M6的第二极与第三节点E连接，第六晶体管M6的第一极与第一信号端VGH连接。
可选的，第一输出模块110包括：第一晶体管M1和第一电容器C1。
第一晶体管M1的第一极与第一信号端VGH连接，第一晶体管M1的第二极与输出端OUT_EM连接，第一晶体管M1的第三极与第一节点B连接。
第一电容器C1的第一极与第一晶体管M1的第一极连接，第一电容器C1的第二极与第一晶体管M1的第三极连接。
可选的，第二输出模块120包括：第二晶体管M2和第三电容器C3。
第二晶体管M2的第一极与第二信号端VGL连接，第二晶体管M2的第二极与输出端OUT_EM连接，第二晶体管M2的第三极与第二节点A连接。
第三电容器C3的第一极与第二晶体管M2的第二极连接，第三电容器C3的第二极与第二晶体管M2的第三极连接。
可选的，输入模块140包括：第三晶体管M3。
第三晶体管M3的第二极与第二节点连接，第三晶体管M3的第一极与输入端STV连接，第三晶体管M3的第三极与第二时钟信号端CK连接。
需要补充说明的是，本公开实施例提供的移位寄存器单元，通过九个晶体管和三个电容器即完成了对输出端电位高低的控制，简化了移位寄存器单元结构，达到了减小移位寄存器版图面积的效果，有利于高分辨率显示装置的制造。
综上所述，本公开实施例提供的移位寄存器单元，通过第一输出模块、第二输出模块、输入模块和控制模块来控制输出端输出的电位高低，解决了相关技术中移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐的 问题；达到了电路结构简单且输出脉宽可调节的效果。
图4是根据一示例性实施例示出的一种移位寄存器单元驱动方法的流程图。移位寄存器单元的结构可以如图1所示，包括：第一输出模块110、第二输出模块120、控制模块130和输入模块140，该移位寄存器单元驱动方法包括：
步骤401，第一阶段：输入端STV输入的输入信号为第一电位，第二时钟信号端CK输入的第二时钟信号为第二电位。输入模块140在第二时钟信号端CK输入的第二时钟信号的控制下，向第二节点A输入输入信号。第一阶段的等效电路图可以如图5所示，其中各标号含义与图3中一致。第一阶段为预备阶段。
步骤402，第二阶段：第一时钟信号端CKB输入的第一时钟信号为第二电位，第二时钟信号端CK输入的第二时钟信号为第一电位，控制控制模块130向第一节点B输入来自第一时钟信号端的第一时钟信号，在第一节点B的控制下，第一输出模块110向输出端OUT_EM输出来自第一信号端VGH的第一控制信号。第二阶段的等效电路图可以如图6所示，其中各标号含义与图3中一致。第二阶段为上拉阶段。
步骤403，第三阶段：第二节点A保持第一电位，第二输出模块120、输入模块140和控制模块130重复执行第一阶段和第二阶段的过程。第三阶段的等效电路图可以如图7所示，其中各标号含义与图3中一致。第三阶段为高电位维持阶段。
步骤404，第四阶段：第二时钟信号端CK输入第二时钟信号，输入模块140在来自第二时钟信号端CK的第二时钟信号的控制下向第二节点A输出来自输入端STV的第二电位，在第二节点A的控制下，第二输出模块120向输出端OUT_EM输出来自第二信号端VGL的第二控制信号。第四阶段的等效电路图可以如图8所示，其中各标号含义与图3中一致。第四阶段为下拉阶段。
步骤405，第五阶段：输入端STV保持第二电位，周期性重复第四阶段，使第一节点B保持第一电位，第二节点A保持第二电位，输出端OUT_EM保持第二电位。第五步骤的等效电路图可以如图9所示，其中各标号含义与 图3中一致。第五阶段为低电位维持阶段。
即本公开实施例提供的移位寄存器单元驱动方法，可以通过控制输入端STV在第一电位的维持时间来控制输出端OUT_EM输出的电位高低。
可选的，如图2所示，控制模块130包括：上拉控制子模块131和复位子模块132。
此时，步骤402可以包括：第二阶段中，第一时钟信号端CKB输入第一时钟信号，第一时钟信号处于第二电位，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第一电位，上拉控制子模块131将第一节点B复位到第二电位。第二阶段的等效电路图可以如图6所示。
步骤404可以包括：第四阶段中，第二时钟信号端CK输入第二时钟信号，输入端STV输入第二电位，复位子模块132向第三节点E输入来自第一信号端VGH的第一控制信号。第四阶段的等效电路图可以如图8所示。
可选的，如图3所示，上拉控制子模块131包括：第二电容器C2、第七晶体管M7、第八晶体管M8和第九晶体管M9。
此时，步骤401可以包括：第一阶段中，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第二电位，第九晶体管M9开启，第二信号端VGL向第三节点E输入第二控制信号。第一阶段的等效电路图可以如图5所示。
步骤402可以包括：第二阶段中，第一时钟信号端CKB输入第一时钟信号，第一时钟信号处于第二电位，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第一电位，第九晶体管M9关断，第七晶体管M7开启，第八晶体管M8开启，第一时钟信号端CKB向第四节点C输入第一时钟信号为第二电位，第四节点C向第一节点B输入第二电位。这里需要说明的是，由于在第一阶段第八晶体管M8开启，第四节点C被第一时钟信号端CKB拉至第一电位，所以第二电容器C2的两端的第三节点E到第四节点C存储一个负电位，当第一时钟信号端CKB跳变到第二电位时，第一时钟信号端CKB的第二电位被传递到第四节点C，第三节点E会被第二电容器C2举到一个更低的电位，第八晶体管M8可以很好的开启。第一时钟信号端CKB跳变为输入第一电位后，第七晶体管M7关断，第一时钟信号端CKB输入的第一电位 不会输入至第一节点B。第二阶段的等效电路图可以如图6所示。
可选的，复位子模块132包括：第四晶体管M4、第五晶体管M5和第六晶体管M6。
第四阶段中，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第二电位，输入模块140向第二节点A输入来自输入端STV的输入信号为第二电位，第四晶体管M4开启，第五晶体管M5开启，第六晶体管M6开启，第一信号端VGH向第一节点B和第三节点E输入第一控制信号。第四阶段的等效电路图可以如图8所示。
可选的，第一输出模块110包括：第一晶体管M1和第一电容器C1。
步骤402可以包括：第二阶段控制模块130向第一节点B输入第一时钟信号，第一时钟信号处于第二电位，第一晶体管M1开启，第一电容器C1充电，第一晶体管M1向输出端OUT_EM输出来自第一信号端VGH的第一控制信号。
步骤404可以包括：第四阶段中，控制模块130向第一节点B输入第一电位，第一晶体管M1关断。四阶段的等效电路图可以如图8所示。
可选的，第二输出模块120包括：第二晶体管M2和第三电容器C3。
此时，步骤401可以包括：第一阶段中，输入模块140向第二节点A输出来自输入端STV的输入信号，输入信号处于第一电位，第二晶体管M2关断，第三电容器C3充电。第一阶段的等效电路图可以如图5所示。
步骤404可以包括：第四阶段中，输入模块140向第二节点A输出来自输入端STV的输入信号，输入信号处于第二电位，第二晶体管M2开启，第二晶体管M2向输出端OUT_EM输出来自第二信号端VGL的第二控制信号。四阶段的等效电路图可以如图8所示。
可选的，输入模块140包括：第三晶体管M3。
此时，步骤401可以包括：第一阶段中，输入端STV输出输入信号，输入信号处于第一电位，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第二电位，控制第三晶体管M3开启，第三晶体管M3向第二节点A输入来自输入端STV的输入信号。第一阶段的等效电路图可以如图5所示
步骤403可以包括：第三阶段中，在输入端STV的输入信号跳变为第二 电位前，第三晶体管M3在来自第二时钟信号端CK的第二时钟信号的控制下关断，此时，第二时钟信号处于第一电位。第三阶段的等效电路图可以如图7所示。
步骤404可以包括：第四阶段中，第二时钟信号端CK输入第二时钟信号，第二时钟信号处于第二电位，第三晶体管M3在来自第二时钟信号端CK的第二时钟信号为第二电位的控制下向第二节点A输出来自输入端STV的输入信号为第二电位。而第二时钟信号端CK输入的第二时钟信号跳变为输出第一电位时，第三晶体管M3关断。四阶段的等效电路图可以如图8所示。
此外，本公开各个实施例中涉及的第一时钟信号端CKB、第二时钟信号端CK、输入端STV、输出端OUT_EM、第一节点B、第二节点A、第三节点E和第四节点C在第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4和第五阶段t5的电位变化可以参照图10，在图10中，横轴代表时间，纵轴代表电位。
需要补充说明的是，本公开实施例提供的移位寄存器单元，通过九个晶体管和三个电容器即完成了对输出端电位高低的控制，简化了移位寄存器单元结构，达到了减小移位寄存器版图面积的效果，有利于高分辨率显示装置的制造。
综上所述，本公开实施例提供的移位寄存器单元驱动方法，通过第一输出模块、第二输出模块、输入模块和控制模块来控制输出端输出的电位高低，解决了相关技术中移位寄存器单元的电路结构通常较为复杂，控制过程较为繁琐的问题；达到了电路结构简单且输出脉宽可调节的效果。
本公开提供一种栅极驱动电路，包括至少两个级联的如图1、图2或图3所示的移位寄存器单元。
另外，本公开还提供一种显示装置，显示装置包括该栅极驱动电路。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公 开的保护范围之内。

Claims (19)

  1. 一种移位寄存器单元，其中，所述移位寄存器单元包括：第一输出模块、第二输出模块、输入模块和控制模块，
    所述第一输出模块分别与第一信号端、第一节点和输出端连接，用于在所述第一节点的控制下，向所述输出端输出来自所述第一信号端的第一控制信号；
    所述第二输出模块分别与所述输出端、第二节点和第二信号端连接，用于在所述第二节点的控制下，向所述输出端输出来自所述第二信号端的第二控制信号；
    所述控制模块分别与所述第一节点、所述第二节点、所述第一信号端、所述第二信号端、第一时钟信号端和第二时钟信号端连接，用于在来自所述第一信号端的所述第一控制信号、所述第二信号端的所述第二控制信号、所述第一时钟信号端的第一时钟信号和所述第二时钟信号端的第二时钟信号的控制下，控制所述第一节点和所述第二节点的电位；
    所述输入模块分别与输入端、所述第二节点、所述第二时钟信号端连接，用于在来自所述第二时钟信号端的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的输入信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述第一输出模块包括：第一晶体管和第一电容器，
    所述第一晶体管的第一极与所述第一信号端连接，所述第一晶体管的第二极与所述输出端连接，所述第一晶体管的第三极与第一节点连接；
    所述第一电容器的第一极与所述第一晶体管的第一极连接，所述第一电容器的第二极与所述第一晶体管的第三极连接。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第二输出模块包括：第二晶体管和第三电容器，
    所述第二晶体管的第一极与所述第二信号端连接，所述第二晶体管的第二极与所述输出端连接，所述第二晶体管的第三极与所述第二节点连接；
    所述第三电容器的第一极与所述第二晶体管的第二极连接，所述第三电 容器的第二极与所述第二晶体管的第三极连接。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述控制模块包括：上拉控制子模块和复位子模块；
    所述上拉控制子模块分别与所述第一时钟信号端、所述第二时钟信号端、所述第二信号端、所述第一节点和第三节点连接，用于在来自所述第二信号端的第二控制信号、来自所述第三节点的复位控制信号、来自所述第一时钟信号端的所述第一时钟信号和所述第二时钟信号端的所述第二时钟信号的控制下控制所述第一节点的电位；
    所述复位子模块分别与所述第一节点、所述第二节点、所述第三节点、所述第一信号端和所述第二时钟信号端连接，用于在所述第一控制信号和所述第二时钟信号的控制下控制所述第一节点的电位、所述第二节点的电位和所述第三节点的电位，所述第一控制信号来自所述第一信号端，所述第二时钟信号来自所述第二时钟信号端。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述上拉控制子模块包括：第二电容器、第七晶体管、第八晶体管和第九晶体管，
    所述第七晶体管的第一极与第四节点连接，所述第七晶体管的第二极与所述第一节点连接，所述第七晶体管的第三极与所述第一时钟信号端连接；
    所述第八晶体管的第二极与所述第四节点连接，所述第八晶体管的第一极与所述第一时钟信号端连接，所述第八晶体管的第三极与所述第三节点连接；
    所述第九晶体管的第二极与所述第三节点连接，所述第九晶体管的第一极与所述第二信号端连接，所述第九晶体管的第三极与所述第二时钟信号端连接；
    所述第二电容器的第一极与所述第三节点连接，所述第二电容器的第二极与所述第四节点连接。
  6. 根据权利要求4所述的移位寄存器单元，其中，所述复位子模块包括：第四晶体管、第五晶体管和第六晶体管，
    所述第四晶体管的第二极与所述第一节点连接，所述第四晶体管的第一极与所述第一信号端连接，所述第四晶体管的第三极与所述第二节点连接；
    所述第五晶体管的第一极与所述第二节点连接，所述第五晶体管的第二极与所述第六晶体管的第三极连接，所述第五晶体管的第三极与所述第二时钟信号端连接；
    所述第六晶体管的第二极与所述第三节点连接，所述第六晶体管的第一极与所述第一信号端连接。
  7. 根据权利要求1所述的移位寄存器单元，其中，所述输入模块包括：第三晶体管，
    所述第三晶体管的第二极与所述第二节点连接，所述第三晶体管的第一极与所述输入端连接，所述第三晶体管的第三极与所述第二时钟信号端连接。
  8. 根据权利要求2至7任一所述的移位寄存器单元，其中，
    所述晶体管均为P型晶体管。
  9. 一种移位寄存器单元驱动方法，用于驱动权利要求1至8任一所述的移位寄存器单元，其中，所述移位寄存器单元包括：第一输出模块、第二输出模块、输入模块和控制模块，所述方法包括：
    第一阶段：输入端输入的输入信号为第一电位，第二时钟信号端输入的第二时钟信号为第二电位，所述输入模块在所述第二时钟信号端输入的所述第二时钟信号的控制下，向第二节点输入所述输入信号；
    第二阶段：第一时钟信号端输入的第一时钟信号为第二电位，所述第二时钟信号端输入的所述第二时钟信号为第一电位，控制所述控制模块向第一节点输入来自所述第一时钟信号端的所述第一时钟信号，在所述第一节点的控制下，所述第一输出模块向输出端输入来自第一信号端的第一控制信号；
    第三阶段：所述第二节点保持第一电位，所述第二输出模块、所述输入模块和所述控制模块重复执行所述第一阶段和所述第二阶段的过程；
    第四阶段：所述第二时钟信号端输入所述第二时钟信号，所述输入模块在来自所述第二时钟信号端的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，在所述第二节点的控制下，所述第二输出模块向所述输出端输入来自第二信号端的第二控制信号，所述控制模块向所述第一节点输入来自所述第一信号端的所述第一控制信号。
  10. 根据权利要求9所述的方法，其中，所述第一输出模块包括：第一晶体管和第一电容器，
    所述第二阶段中，所述控制模块向所述第一节点输入来自所述第一时钟信号端的所述第一时钟信号，所述第一时钟信号处于第二电位，所述第一晶体管开启，所述第一电容器充电，所述第一晶体管向所述输出端输入来自所述第一信号端的所述第一控制信号；
    所述第四阶段中，所述控制模块向所述第一节点输入来自所述第一信号端的所述第一控制信号，所述第一晶体管关断。
  11. 根据权利要求9所述的方法，其中，所述第二输出模块包括：第二晶体管和第三电容器，
    所述第一阶段中，所述输入模块向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第一电位，所述第二晶体管关断，所述第三电容器充电；
    所述第四阶段中，所述输入模块向所述第二节点输出来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第二晶体管开启，所述第二晶体管向所述输出端输出来自所述第二信号端的所述第二控制信号。
  12. 根据权利要求9所述的方法，其中，所述控制模块包括：上拉控制子模块和复位子模块，
    所述第二阶段中，所述第一时钟信号端输入所述第一时钟信号，所述第一时钟信号处于第二电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第一电位，所述上拉控制子模块将所述第一节点复位到第二电位；
    所述第四阶段中，所述输入端输入的输入信号处于第二电位，所述复位子模块向第三节点输入来自所述第一信号端的所述第一控制信号。
  13. 根据权利要求12所述的方法，其中，所述上拉控制子模块包括：第二电容器、第七晶体管、第八晶体管和第九晶体管，
    所述第一阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述第九晶体管开启，所述第二信号端向所述第三节点输入所述第二控制信号；
    所述第二阶段中，所述第一时钟信号端输入所述第一时钟信号，所述第一时钟信号处于第二电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第一电位，所述第九晶体管关断，所述第七晶体管开启，所述第八晶体管开启，所述第一时钟信号端向第四节点输入所述第一时钟信号，所述第四节点将所述第一节点复位到第二电位，所述第一时钟信号端输入的所述第一时钟信号跳变为第一电位后，所述第七晶体管关断。
  14. 根据权利要求12所述的方法，其中，所述复位子模块包括：第四晶体管、第五晶体管和第六晶体管，
    所述第四阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述输入模块向所述第二节点输入来自所述输入端的所述输入信号，所述输入信号处于第二电位，所述第四晶体管开启，所述第五晶体管开启，所述第六晶体管开启，所述第一信号端向所述第一节点和所述第三节点输入所述第一控制信号。
  15. 根据权利要求9所述的方法，其中，所述输入模块包括：第三晶体管，
    所述第一阶段中，所述输入端输出所述输入信号，所述输入信号处于第一电位，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，控制所述第三晶体管开启，所述第三晶体管向所述第二节点输入来自所述输入端的所述输入信号；
    所述第三阶段中，在所述输入端的所述输入信号跳变为第二电位前，所述第三晶体管在来自所述第二时钟信号端的所述第二时钟信号的控制下关断，所述第二时钟信号处于第一电位；
    所述第四阶段中，所述第二时钟信号端输入所述第二时钟信号，所述第二时钟信号处于第二电位，所述第三晶体管在来自所述第二时钟信号端的位于第二电位的所述第二时钟信号的控制下向所述第二节点输出来自所述输入端的第二电位，所述第二时钟信号端输入的所述第二时钟信号跳变为第一电位时，所述第三晶体管关断。
  16. 根据权利要求10至15任一所述的方法，其中，
    所述晶体管均为P型晶体管。
  17. 根据权利要求9至15任一所述的方法，其中，
    所述第一电位相对于所述第二电位为高电位。
  18. 一种栅极驱动电路，包括至少两个级联的如权利要求1至8任一所述的移位寄存器单元。
  19. 一种显示装置，其中，所述显示装置包括权利要求18所述的栅极驱动电路。
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