WO2016176836A1 - 一种缓冲器电路和采用该电路的电子设备 - Google Patents

一种缓冲器电路和采用该电路的电子设备 Download PDF

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WO2016176836A1
WO2016176836A1 PCT/CN2015/078369 CN2015078369W WO2016176836A1 WO 2016176836 A1 WO2016176836 A1 WO 2016176836A1 CN 2015078369 W CN2015078369 W CN 2015078369W WO 2016176836 A1 WO2016176836 A1 WO 2016176836A1
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buffer
stage
output
pmos transistor
nmos transistor
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PCT/CN2015/078369
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English (en)
French (fr)
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麦日锋
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京微雅格（北京）科技有限公司
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Priority to US14/902,241 priority Critical patent/US9979398B2/en
Priority to PCT/CN2015/078369 priority patent/WO2016176836A1/zh
Priority to CN201580000994.XA priority patent/CN106664090B/zh
Publication of WO2016176836A1 publication Critical patent/WO2016176836A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

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  • This invention relates to electronic devices, and more particularly to buffer circuits for use in electronic devices.
  • Buffers are widely used in a variety of electronic devices, such as timing and driving. In some cases, such as clock trees, hierarchical drives are required due to the increasing complexity of the design.
  • Figure 1 illustrates an example of a buffer cascade. In this figure, there are two levels of buffers.
  • the buffer is generally composed of one inverter, and its output driving capability is determined only by the characteristics of the tube of the output stage, regardless of the logic state of each input.
  • the buffer of the later stage because the number of units driven, requires more energy, and therefore requires more driving capability.
  • the present invention provides a buffer circuit in a first aspect.
  • the buffer circuit includes a buffer group including an odd number of buffers connected in series with each other, each of the buffers being different from each other; a PMOS transistor and an NMOS transistor; wherein a source of the PMOS transistor is coupled to the power source and a drain is connected to The output of the buffer bank is connected to the input of the buffer bank; the source of the NMOS transistor is coupled to ground, the drain is coupled to the output of the buffer bank, and the gate is coupled to the input of the buffer bank.
  • the driving capability of the PMOS transistor and the NMOS transistor is one-half or one-quarter of the driving capability of the last-stage buffer in the buffer group.
  • the invention provides, in a second aspect, an electronic device comprising the buffer circuit of the first aspect.
  • the embodiment of the invention effectively increases the response speed of the buffer, and the peak current is also reduced (about 20%-30%), thereby reducing the possibility of circuit damage and malfunction.
  • Figure 1 illustrates an example of a buffer cascade
  • FIG. 2 is a schematic diagram of a buffer circuit of one embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a buffer circuit of another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a buffer circuit in accordance with still another embodiment of the present invention.
  • the buffer circuit includes a first stage buffer 22, a second stage buffer 24, a PMOS transistor 26 and an NMOS transistor 28.
  • the source of PMOS transistor 26 is coupled to a power supply, the drain is coupled to the output of second stage buffer 24, and the gate is coupled to the output of first stage buffer 22.
  • the source of NMOS transistor 28 is coupled to ground, the drain is coupled to the output of second stage buffer 24, and the gate is coupled to the output of first stage buffer 22.
  • the second stage buffer 24 changes slowly due to the large volume, and fails to follow the transition temporarily.
  • the transistor 26 is first turned on under the effect that the gate voltage becomes low, so that its drain rapidly jumps to a high level.
  • the driving capability of the PMOS transistor can be set to 1/2 times the driving capability of the second-stage buffer 24, so the current at this time is only a conventional 1/2.
  • the second stage buffer 24 also completes a low to high transition, at which point the drive current at the output of the buffer 24 is 1 + 1/2.
  • the second stage buffer 24 changes slowly due to the large volume, and fails to follow the transition temporarily.
  • the transistor 28 is first turned on under the effect that the gate voltage becomes high, so that its drain rapidly jumps to a low level.
  • the driving capability of the NMOS transistor can be set to 1/2 times that of the second-stage buffer, so the current at this time is only a conventional 1/2.
  • the second stage buffer 24 also completes a low to high transition, at which point the drive current at the output of the buffer 24 is 1 + 1/2.
  • the embodiment of the invention effectively improves the response speed of the buffer, and the peak current is also reduced (about 20%-30%) compared to the conventional (usually requiring 2 times drive current), thereby reducing circuit damage and malfunction. possibility.
  • Embodiments of the present invention are also applicable to the case where a plurality of buffers are connected in series.
  • FIG. 3 is a schematic diagram of a buffer circuit in accordance with an embodiment of the present invention. Different from FIG. 2, FIG. 3 includes 4-stage buffers 31-34, and further includes a PMOS transistor 35 and an NMOS transistor 36.
  • the buffers 32-34 are connected in series to each other to form a buffer group.
  • Each of the buffers can have different sizes and thus different drive capabilities.
  • the source of the PMOS transistor 35 is connected to the power supply, the drain is connected to the output of the fourth stage buffer 34, and the gate is connected to the output of the first stage buffer 31.
  • the source of the NMOS transistor 36 is connected to ground, the drain is connected to the output of the fourth stage buffer 34, and the gate is connected to the output of the first stage buffer 31.
  • the fourth stage buffer 34 fails to follow the transition due to the delay and volume; the PMOS transistor 35 is turned on first under the action of the gate voltage becoming low, so that its drain rapidly jumps to a high level, and the driving capability of the PMOS transistor is 1/2 times, so the current at the output end of the fourth stage buffer 34 is only Regular 1/2.
  • the fourth stage buffer 34 also completes the transition from low to high. If the driving capability of the fourth stage driver 34 is 2X times and the driving capability of the PMOS transistor 35 is 1/2X times, then the driving current at the output of the buffer 34 is 2+1/2.
  • the fourth stage buffer 34 has failed to follow the transition; the NMOS transistor 36 is first turned on under the effect that the gate voltage becomes high, so that its drain rapidly jumps to a low level.
  • the driving capability of the NMOS transistor is assumed to be 1/2 times that of the conventional one, so that the current at the output of the fourth-stage buffer 34 is only a conventional 1/2.
  • the fourth stage buffer 34 also completes a low-to-high transition, at which time the drive current at the output of the buffer 24 is 2. +1/2.
  • the buffer circuit includes level 1-8 buffers 401-408 that are cascaded with each other.
  • a PMOS transistor 412 and an NMOS transistor 414 are disposed between the input of the buffer 403 and the output of the buffer 405;
  • a PMOS transistor 422 and an NMOS transistor are disposed between the input of the buffer 406 and the output of the buffer 408.
  • a PMOS transistor 432 and an NMOS transistor 434 are disposed between the input of the buffer 402 and the output of the buffer 408.
  • the roles of PMOS transistor 412 and NMOS transistor 414, PMOS transistor 422 and NMOS transistor 424, PMOS transistor 432 and NMOS transistor 434 are similar to those previously described and will not be described again.
  • each buffer in the buffer bank can have different buffer (drive) capabilities.
  • the buffer of the later stage has a larger driving capability, such as 3X, 10X, 32X, 100X.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

一种缓冲器电路，包括缓冲器组，该缓冲器组包括奇数个彼此串联的缓冲器（32，33，34），各缓冲器可以彼此不同；PMOS晶体管（35）和NMOS晶体管（36）；其中，PMOS晶体管（35）的源极耦接至电源，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端；NMOS晶体管（36）的源极耦接至地，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端。

Description

一种缓冲器电路和采用该电路的电子设备 技术领域
本发明涉及电子设备，具体地说涉及用于电子设备中的缓冲器电路。
背景技术
缓冲器广泛应用在各种电子设备中，比如定时和驱动。在某些场合，比如时钟树，由于设计越来越复杂，需要采用分级驱动。图1示意了一种缓冲器级联的例子。该图中，有两级缓冲器。缓冲器一般都由1个反相器构成，其输出驱动能力仅由该输出级的管子特性决定，与各输入端所处逻辑状态无关。越后级的缓冲器，由于驱动的单元数越多，需要消耗更多的能量，因此，需要更大的驱动能力。
然而，随着级数的增加，时延和功率消耗也显著增加。越到后级，由于要驱动的器件多，对驱动能力的要求越大，对功率消耗也就越大。峰值电流变大的结果是，可能瞬间的峰值电流/电压超过电源的能力，造成器件损害，功能故障等等。
发明内容
本发明在第一方面提供一种缓冲器电路。该缓冲器电路包括缓冲器组，该缓冲器组包括奇数个彼此串联的缓冲器，各缓冲器可以彼此不同；PMOS晶体管和NMOS晶体管；其中，PMOS晶体管的源极耦合至电源，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端；NMOS晶体管的源极耦合至地，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端。
优选地，PMOS晶体管和NMOS晶体管的驱动能力为缓冲器组中最后一级缓冲器的驱动能力的一半或四分之一。
本发明在第二方面提供一种电子设备，其包括如第一方面所述的缓冲器电路。
本发明实施例有效提高了缓冲器的反应速度，并且峰值电流也有所降低(大约20％-30％)，从而减少了电路损坏和功能故障的可能性。
附图说明
图1示意了一种缓冲器级联的例子；
图2是本发明一个实施例的缓冲器电路的示意图；
图3是本发明另一个实施例的缓冲器电路的示意图；
图4是本发明再一个实施例的缓冲器电路的示意图。
具体实施方式
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
图2是本发明实施例的缓冲器电路的示意图。如图2所示，缓冲器电路包括第一级缓冲器22，第二级缓冲器24，PMOS晶体管26和NMOS晶体管28。第二级缓冲器24和第一级缓冲器22之间有一个电阻23，电阻23具有较小的阻值。PMOS晶体管26的源极耦合至电源，漏极连接至第二级缓冲器24的输出端，栅极连接至第一级缓冲器22的输出端。NMOS晶体管28的源极耦合至地，漏极连接至第二级缓冲器24的输出端，栅极连接至第一级缓冲器22的输出端。
工作时，当第一级缓冲器22的输出端信号出现跳变，例如从上到下的跳变，第二级缓冲器24由于体积较大，变化较慢，暂未能跟随跳变，PMOS晶体管26在栅电压变低的作用下首先导通，使得其漏极迅速跳变为高电平。PMOS晶体管的驱动能力可以设定为第二级缓冲器24驱动能力的1/2倍，因此此时的电流仅为常规的1/2。在稍后的时间，第二级缓冲器24也完成从低到高的跳变，此时在缓冲器24输出端的驱动电流为1+1/2。
同理，当第一级缓冲器22的输出端信号出现跳变，例如从下到上的跳变，第二级缓冲器24由于体积较大，变化较慢，暂未能跟随跳变，NMOS晶体管28在栅电压变高的作用下首先导通，使得其漏极迅速跳变为低电平。NMOS晶体管的驱动能力可以设定为第二级缓冲器的1/2倍，因此此时的电流仅为常规的1/2。在稍后的时间，第二级缓冲器24也完成从低到高的跳变，此时在缓冲器24输出端的驱动电流为1+1/2。本发明实施例有效提高了缓冲器的反应速度，并且峰值电流相比常规下(通常需要2倍的驱动电流)也有所降低(大约20％-30％)，从而减少了电路损坏和功能故障的可能性。
本发明实施例还可以适用于多个缓冲器串联的情形。
图3是本发明实施例的缓冲器电路的示意图。和图2不同的是，图3包括了4级缓冲器31-34，还包括PMOS晶体管35和NMOS晶体管36。
缓冲器32-34彼此串联，而构成一个缓冲器组。各缓冲器可以具有不同的尺寸并且因此不同的驱动能力。
PMOS晶体管35的源极连接至电源，漏极连接至第四级缓冲器34的输出端，栅极连接至第一级缓冲器31的输出端。NMOS晶体管36的源极连接至地，漏极连接至第四级缓冲器34的输出端，栅极连接至第一级缓冲器31的输出端。
工作时，当第一级缓冲器31的输出端信号出现跳变，例如从上到下的跳变，由于时延以及体积的原因，第四级缓冲器34暂未能跟随跳变；PMOS晶体管35在栅电压变低的作用下首先导通，使得其漏极迅速跳变为高电平，PMOS晶体管的驱动能力为1/2倍，因此此时第四级缓冲器34输出端的电流仅为常规的1/2。在稍后的时间，随着第二缓冲器32、第三缓冲器33的翻转，第四级缓冲器34也完成从低到高的跳变。如果第四级驱动器34的驱动能力为2X倍，PMOS管35的驱动能力为1/2X倍，那么此时在缓冲器34输出端的驱动电流为2+1/2。
同理，当第一级缓冲器31的输出端信号出现跳变，例如从下到上的跳变， 第四级缓冲器34暂未能跟随跳变；NMOS晶体管36在栅电压变高的作用下首先导通，使得其漏极迅速跳变为低电平。NMOS晶体管的驱动能力假定为常规的1/2倍，因此此时第四级缓冲器34输出端的电流仅为常规的1/2。在稍后的时间，随着第二缓冲器32、第三缓冲器33的翻转，第四级缓冲器34也完成从低到高的跳变，此时在缓冲器24输出端的驱动电流为2+1/2。
图4是本发明实施例的缓冲器电路的示意图。如图4所示，缓冲器电路包括彼此级联的第1-8级缓冲器401-408。从缓冲器403的输入端到缓冲器405的输出端之间设置了PMOS晶体管412和NMOS晶体管414；从缓冲器406的输入端到缓冲器408的输出端之间设置了PMOS晶体管422和NMOS晶体管424；从缓冲器402的输入端到缓冲器408的输出端之间设置了PMOS晶体管432和NMOS晶体管434。PMOS晶体管412和NMOS晶体管414，PMOS晶体管422和NMOS晶体管424，PMOS晶体管432和NMOS晶体管434的作用类似前文，不复赘述。
需要指出，缓冲器组中各缓冲器可以具有不同的缓冲(驱动)能力。例如，越后级的缓冲器，驱动能力越大，比如3X,10X，32X，100X。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (3)

  1. 一种缓冲器电路，包括缓冲器组，该缓冲器组包括奇数个彼此串联的缓冲器(24)，各缓冲器可以彼此不同；PMOS晶体管(26)和NMOS晶体管(28)；其中，PMOS晶体管的源极耦合至电源，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端；NMOS晶体管的源极耦合至地，漏极连接至缓冲器组的输出端，栅极连接至缓冲器组的输入端。
  2. 如权利要求1所述的缓冲器电路，其中PMOS晶体管和NMOS晶体管的驱动能力为缓冲器组中最后一级缓冲器的驱动能力的一半或四分之一。
  3. 电子设备，包括如权利要求1-2之一的缓冲器电路。
PCT/CN2015/078369 2015-05-06 2015-05-06 一种缓冲器电路和采用该电路的电子设备 WO2016176836A1 (zh)

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US14/902,241 US9979398B2 (en) 2015-05-06 2015-05-06 Buffer circuit and electronic device using same
PCT/CN2015/078369 WO2016176836A1 (zh) 2015-05-06 2015-05-06 一种缓冲器电路和采用该电路的电子设备
CN201580000994.XA CN106664090B (zh) 2015-05-06 2015-05-06 一种缓冲器电路和采用该电路的电子设备

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