WO2016106822A1 - 用于氧化物半导体薄膜晶体管的扫描驱动电路 - Google Patents

用于氧化物半导体薄膜晶体管的扫描驱动电路 Download PDF

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Publication number
WO2016106822A1
WO2016106822A1 PCT/CN2015/070516 CN2015070516W WO2016106822A1 WO 2016106822 A1 WO2016106822 A1 WO 2016106822A1 CN 2015070516 W CN2015070516 W CN 2015070516W WO 2016106822 A1 WO2016106822 A1 WO 2016106822A1
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Prior art keywords
electrically connected
clock signal
node
transistor
gate
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PCT/CN2015/070516
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English (en)
French (fr)
Inventor
戴超
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深圳市华星光电技术有限公司
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Priority to RU2017125769A priority Critical patent/RU2667457C1/ru
Priority to JP2017534673A priority patent/JP6570639B2/ja
Priority to DE112015005388.3T priority patent/DE112015005388B4/de
Priority to KR1020177021416A priority patent/KR101989720B1/ko
Priority to GB1708784.2A priority patent/GB2548046B/en
Priority to US14/437,828 priority patent/US9524689B2/en
Publication of WO2016106822A1 publication Critical patent/WO2016106822A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a scan driving circuit for an oxide semiconductor thin film transistor.
  • GOA Gate Drive On Array
  • TFT thin film transistor
  • Array liquid crystal display array
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
  • the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • the scan driving circuit of the oxide semiconductor thin film transistor is generally cascaded by multiple stages of the same GOA circuit, and the pull-down sustain circuits of each stage of the GOA circuit are the same, but due to the pull-down
  • the sustain circuit contains more TFT components, which increases the GOA layout space and also increases circuit power consumption.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor, which can realize a pull-down sustain circuit of a multi-stage GOA circuit. Sharing, thereby reducing the number of TFT components to reduce GOA layout space and reduce circuit power consumption.
  • a first technical solution adopted by the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor, a scan driving circuit for an oxide semiconductor thin film transistor, the circuit including cascaded P GOA units
  • Each GOA unit includes a pull-up control portion, a pull-up portion, a downlink portion, a first pull-down portion, a bootstrap capacitor portion, and a main inverter portion; the circuit further includes an auxiliary inverter, each stage connection relationship
  • the main inverter portion is connected to the auxiliary inverter to form a corresponding pull-down maintaining portion of the GOA unit; setting P, N are positive integers, and N ⁇ P; wherein, the Nth level connection In the relationship, the main inverter portion includes: a fifty-first transistor (T51), the gate and the drain are electrically connected to a constant voltage high potential (DCH), and the source is electrically connected to the fourth node (S (N)); a fifty-second transistor (T52), the gate is electrically connected to the first node (
  • the downstream portion includes: a twenty-second transistor (T22), the gate is electrically connected to the first node (Q(N)), and the drain is electrically connected to the clock signal (CK(M)), and the source is electrically Connected to the drive output (ST ( N)); wherein the first waveform of the first node (Q(1)) in the first cascade relationship of the scan driving circuit has a "convex" shape, and the cascade relationship of the last stage The signal output second waveform of the first node (Q(P)) is in a "convex" shape, and the auxiliary inverter is controlled according to the signal corresponding to the first waveform and the second waveform overlapping portion. .
  • a second technical solution adopted by the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor, the circuit including cascaded P GOA units, each of which includes a pull-up control portion and a pull-up portion a downstream portion, a first pull-down portion, a bootstrap capacitor portion, and a main inverter portion; the circuit further includes an auxiliary inverter, the main inverter portion in each stage connection relationship and the auxiliary reverse The phase converters are connected to form a corresponding pull-down maintaining portion of the GOA unit; the settings P and N are positive integers, and N ⁇ P; wherein, in the Nth-level connection relationship, the main inverter portion includes: Eleven transistors (T51), the gate and the drain are electrically connected to a constant voltage high potential (DCH), the source is electrically connected to the fourth node (S(N)); the fifty-second transistor (T52), The gate is electrically connected to the first node (Q(N)), the drain is electrically connected to the fourth node (S(N
  • the fourth node (S(P)) of the main inverter is electrically connected, the drain is electrically connected to the third node (K), and the source is electrically connected to the seventh thirteenth transistor ( a source of T73); a seventh-fifth transistor (T75), the first node (Q(1)) of the main inverter in the gate-to-first-order connection relationship is electrically connected, and the drain is electrically connected
  • the source is electrically connected to a constant voltage low potential (DCL);
  • the seventy-sixth transistor (T76) the gate is connected to the last stage of the main inverter
  • the first node (Q(P)) is electrically connected, and the drain is electrically connected to the constant voltage low potential (DCL), Electrically connecting said third node (K).
  • the pull-up portion includes a twenty-first transistor (T21), and a gate of the twenty-first transistor (T21) is electrically connected to the first node (Q(N))
  • the drain is electrically connected to a clock signal (CK(n)), the source is electrically connected to the output terminal (G(N));
  • the downstream portion includes a 22nd transistor (T22), and the 22nd transistor (T22)
  • the gate is electrically connected to the first node (Q(N)), the drain is electrically connected to the clock signal (CK(M)), and the source is electrically connected to the driving output terminal (ST(N));
  • the capacitor portion includes a capacitor (Cb), one end of the capacitor (Cb) is electrically connected to the first node (Q(N)), and the other end is electrically connected to the output terminal (G(N)).
  • the clock signal (CK(M)) includes four groups of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)).
  • the clock signal (CK(M)) includes eight sets of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)), fifth clock signal (CK(5)), sixth clock signal (CK(6)), seventh clock signal (CK(7)) , the eighth clock signal (CK (8)).
  • the clock signal (CK(M)) has a waveform duty ratio of not more than 25/75.
  • the clock signal (CK(M)) includes four groups of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)).
  • the clock signal (CK(M)) includes eight sets of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)), fifth clock signal (CK(5)), sixth clock signal (CK(6)), seventh clock signal (CK(7)) , the eighth clock signal (CK (8)).
  • the clock duty of the clock signal (CK(M)) is equal to 25/75.
  • the clock signal (CK(M)) includes four groups of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)).
  • the clock signal (CK(M)) includes eight sets of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal. (CK(3)), fourth clock signal (CK(4)), fifth clock signal (CK(5)), sixth clock signal (CK(6)), seventh clock signal (CK(7)) , the eighth clock signal (CK (8)).
  • the signal output first waveform of the first node (Q(1)) in the first cascade relationship of the scan driving circuit is in a "convex" shape, and the cascading relationship in the last stage is
  • the signal output second waveform of the first node (Q(P)) is in a "convex" shape, and the auxiliary inverter is controlled according to the signal corresponding to the first waveform and the second waveform overlap portion.
  • the stage transmission mode adopted by the scan driving circuit is the Nth level and is transmitted to the Nth stage.
  • the gate and the drain of the eleventh transistor (T11) are electrically connected to the start signal terminal (STV) of the circuit.
  • the gate of the forty-first transistor (T41) is electrically connected to the start signal terminal (STV) of the circuit.
  • the present invention provides a scan driving circuit for an oxide semiconductor thin film transistor, the pull-down sustain circuit portion of the scan driving circuit for an oxide semiconductor thin film transistor has a main inverter, and further includes A common auxiliary inverter capable of being connected to each main inverter to form a corresponding pull-down sustain circuit portion, which can realize sharing of the pull-down sustain circuit of the multi-stage GOA circuit, thereby reducing the number of TFT elements.
  • the pull-down sustain circuit portion of the scan driving circuit for an oxide semiconductor thin film transistor has a main inverter, and further includes A common auxiliary inverter capable of being connected to each main inverter to form a corresponding pull-down sustain circuit portion, which can realize sharing of the pull-down sustain circuit of the multi-stage GOA circuit, thereby reducing the number of TFT elements.
  • FIG. 1 is a circuit diagram of an Nth stage GOA unit of a scan driving circuit for an oxide semiconductor thin film transistor in the prior art
  • FIG. 2 is a circuit diagram of a pull-down sustain circuit for a scan driving circuit of an oxide semiconductor thin film transistor according to the first embodiment of the present invention
  • FIG. 3 is a waveform diagram showing waveform settings and key waveforms of a scan driving circuit for an oxide semiconductor thin film transistor having the pull-down sustain circuit shown in FIG. 2;
  • FIG. 4 is a circuit diagram of a pull-down sustain circuit for a scan driving circuit of an oxide semiconductor thin film transistor in a second embodiment of the present invention
  • Fig. 5 is a waveform diagram showing waveform settings and key nodes of a scan driving circuit for an oxide semiconductor thin film transistor having the pull-down sustaining circuit shown in Fig. 4.
  • FIG. 1 is a scanning drive circuit for an oxide semiconductor thin film transistor in the prior art.
  • the GOA unit 10 includes a pull-up control portion 100, a pull-up portion 200, a downlink portion 300, a first pull-down portion 400, a bootstrap capacitor portion 500, and a pull-down sustain circuit portion 600.
  • the pull-up control portion 100 includes an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is electrically connected to the driving output terminal ST of the first two-stage GOA unit of the N-th stage GOA unit. (N-2), the drain level is electrically connected to the output terminal G(N-2) of the first two-stage GOA unit of the Nth stage GOA unit, and the source is electrically connected to the first node. Q(N).
  • the pull-up portion 200 includes a twenty-first transistor T21, the gate of the twenty-first transistor T21 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(P), the source Electrically connected to the output terminal G (N).
  • the downstream portion 300 includes a twenty-second transistor T22.
  • the gate of the second twelve transistor T22 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(P), the source. Electrically connected to the drive output ST (N).
  • the first pull-down portion 400 includes a forty-first transistor T41, and the gate of the forty-first transistor T41 is electrically connected to the N+2th GOA unit of the lower two stages of the GOA unit of the Nth stage GOA unit.
  • the output terminal G(N+2) has a drain electrically connected to the first node Q(N) and a source electrically connected to the second negative potential VSS2.
  • the bootstrap capacitor portion 500 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
  • the pull-down maintaining portion 600 includes a fifty-first transistor T51.
  • the gate and the drain of the fifty-first transistor T51 are electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the fourth node S(N). .
  • the gate of the fifty-second transistor T52 is electrically connected to the first node Q(N), the drain is electrically connected to the fourth node S(N), and the source is electrically connected to the first node A negative potential VSS1.
  • the gate of the fifty-third transistor T53 is electrically connected to the fourth node S(N), the drain is electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the second node P(N).
  • the gate of the fifty-fourth transistor T54 is electrically connected to the first node Q(N), the drain is electrically connected to the second node P(N), and the source is electrically connected to the third Node K(N).
  • the seventh eleventh transistor T71, the gate and the drain of the seventy-first transistor T71 are electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the gate of the seventy-third transistor T73.
  • the seventy-second transistor T72, the gate of the seventy-second transistor T72 is electrically connected to the first node Q(N), and the drain is electrically connected to the gate of the seventy-third transistor T73, and the source is electrically connected. At constant voltage low potential DCL.
  • the seventh thirty-third transistor T73 the gate of the seventy-third transistor T73 is electrically connected to the source of the seventy-first transistor T71, the drain is electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the first Three nodes K(N).
  • a seventy-fourth transistor T74 the gate of the seventy-fourth transistor T74 is electrically connected to the first node Q(N), the drain is electrically connected to the third node K(N), and the source is electrically connected to the constant Press down the potential DCL.
  • the forty-second transistor T42, the gate of the forty-second transistor T42 is electrically connected to the second node P(N), the drain is electrically connected to the first node Q(N), and the source is electrically connected to the first Two negative potentials VSS2.
  • the thirty-second transistor T32, the gate of the thirty-second transistor T32 is electrically connected to the second node P(N), the drain is electrically connected to the output terminal G(N), and the source is electrically connected to the first Negative potential VSS1.
  • FIG. 2 is a circuit diagram of a pull-down sustain circuit for a scan driving circuit of an oxide semiconductor thin film transistor according to a first embodiment of the present invention, wherein the scan driving circuit for the oxide semiconductor thin film transistor is indium gallium zinc
  • P and N be positive integers, and N ⁇ P, then the Nth stage GOA unit includes pull-up control portion 100, pull-up portion 200, downlink portion 300, first pull-down portion 400, bootstrap capacitor portion 500, and pull-down The circuit portion 600 is maintained.
  • the pull-up control portion 100 includes an eleventh transistor T11.
  • the gate of the eleventh transistor T11 is electrically connected to the driving output terminal ST of the first two-stage GOA unit of the N-th stage GOA unit. (N-2), the drain level is electrically connected to the output terminal G(N-2) of the first two-stage GOA unit of the Nth stage GOA unit, and the source is electrically connected to the first node. Q(N).
  • the pull-up portion 200 includes a twenty-first transistor T21, the gate of the twenty-first transistor T21 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(P), the source Electrically connected to the output terminal G (N).
  • the downstream portion 300 includes a twenty-second transistor T22.
  • the gate of the second twelve transistor T22 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(P), the source. Electrically connected to the drive output ST (N).
  • the first pull-down portion 400 includes a forty-first transistor T41, and the gate of the forty-first transistor T41 is electrically connected to the N+2th GOA unit of the lower two stages of the GOA unit of the Nth stage GOA unit.
  • the output terminal G(N+2) has a drain electrically connected to the first node Q(N) and a source electrically connected to the second negative potential VSS2.
  • the bootstrap capacitor portion 500 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
  • the pull-down maintaining portion 600 includes a main inverter 600a, a thirty-second transistor T32, and a forty-second transistor T42.
  • the main inverter 600a includes:
  • the gate and the drain are electrically connected to the constant voltage high potential (DCH), and the source is electrically connected to the fourth node (S(N)).
  • T52 a fifty-second transistor (T52), the gate is electrically connected to the first node (Q(N)), the drain is electrically connected to the fourth node (S(N)), and the source is electrically connected to the A negative potential (VSS1).
  • T53 a fifty-third transistor (T53), the gate is electrically connected to the fourth node (S(N)), the drain is electrically connected to the constant voltage high potential (DCH), and the source is electrically connected to the first Two nodes (P(N)).
  • T54 a fifty-fourth transistor (T54), the gate is electrically connected to the first node (Q(N)), the drain is electrically connected to the second node (P(N)), and the source is electrically connected At the third node (K).
  • the forty-second transistor T42, the gate of the forty-second transistor T42 is electrically connected to the second node P(N), the drain is electrically connected to the first node Q(N), and the source is electrically connected to the first Two negative potentials VSS2;
  • the thirty-second transistor T32, the gate of the thirty-second transistor T32 is electrically connected to the second node P(N), the drain is electrically connected to the output terminal G(N), and the source is electrically connected to the first Negative potential VSS1.
  • the GOA unit further includes an auxiliary inverter 700, and the main inverter portion 600a in each stage of the connection relationship is connected to the auxiliary inverter 700 to form a pull-down maintaining portion 600 of the corresponding GOA unit. That is, the pull-down sustaining portion 600 of the multi-stage GOA unit shares the same auxiliary inverter 700.
  • the auxiliary inverter 700 includes:
  • the seventy-third transistor (T73), the gate is electrically connected to the fourth node (S(1)) of the main inverter in the first-stage connection relationship, and the drain is electrically connected to the constant voltage high potential (DCH) ).
  • T74 a seventy-fourth transistor (T74), the fourth node (S(P)) of the main inverter in the gate-to-last level connection relationship is electrically connected, and the drain is electrically connected to the third node (K) The source is electrically connected to the source of the seventy-third transistor (T73).
  • T75 a seventy-fifth transistor (T75), the first node (Q(1)) of the main inverter in the gate-to-first-order connection relationship is electrically connected, and the drain is electrically connected to the third node (K) ), the source is electrically connected to a constant voltage low potential (DCL).
  • DCL constant voltage low potential
  • the seventy-sixth transistor (T76) is electrically connected to the first node (Q(P)) of the main inverter in the connection relationship between the gate and the last stage, and the drain is electrically connected to the constant voltage low potential ( DCL), the source is electrically connected to the third node (K).
  • the relationship between the first negative potential VSS1, the second negative potential VSS2, and the constant voltage low potential DCL is: the constant voltage low potential DCL ⁇ the second negative potential VSS2 ⁇ the first negative potential VSS1.
  • the level transmission mode adopted by the scan driving circuit is the Nth level is transmitted to the Nth stage.
  • the gate and the drain of the eleventh transistor T11 are electrically connected to the start signal terminal STV of the circuit.
  • the gate and the drain of the eleventh transistor T11 are electrically connected to the start signal terminal STV of the circuit.
  • the gate of the forty-first transistor T41 is electrically connected to the start signal terminal STV of the circuit.
  • the gate of the forty-first transistor T41 is electrically connected to the start signal terminal STV of the circuit.
  • P 3, that is, the three-level GOA unit is connected.
  • the same level of the main inverter 600a and the auxiliary inverter 700 are connected to form a corresponding pull-down maintaining circuit 600, and in the three-level connection relationship, a three-stage pull-down sustaining circuit is required to form a transistor.
  • the number is 22.
  • the pull-down sustaining circuit 600 in each stage connection relationship is the same, and each has 8 transistors, forming a three-stage.
  • the total number of transistors required for the pull-down sustain circuit is 24. Therefore, with the embodiment of the present invention, when a three-level connection relationship is formed, two transistors are correspondingly reduced.
  • the forty-first transistor T41 of the first pull-down portion 400 is responsible for pulling down the first node Q(N), and the gate of the forty-first transistor T41 is electrically connected to the N+2
  • the output terminal G(N+2) of the stage GOA unit, the source of T41 is electrically connected to the second negative potential VSS2.
  • the clock signal CK(M) includes four sets of clock signals: a first clock signal CK(1), a second clock signal CK(2), and a third clock signal CK ( 3), the fourth clock signal CK (4), and the duty ratio setting of the clock signal CK (M) needs to be no more than 25 / 75, to ensure that the first node Q (N) is "convex" shape, preferably, the The waveform duty cycle of the clock signal CK(P) is 25/75.
  • the main inverter 600a composed of four transistors of the fifty-first transistor T51, the fifty-second transistor T52, the fifty-third transistor T53, and the fifty-fourth transistor T54 functions as a control
  • Thirty-two transistor T32 and forty-second transistor T42 are two transistors.
  • the auxiliary inverter 700 functions to provide a low potential to the main inverter 600a during the active period, and to provide an appropriate high potential to the main inverter 600a during the inactive period to reduce the leakage of the fifty-fourth transistor T54. It is ensured that the main inverter 600a is capable of generating a higher potential during inactive periods.
  • the fifty-second transistor T52 is pulled down to the first negative The potential VSS1, the seventy-fourth transistor T74, and the seventy-second transistor T72 turn on and pull down the constant voltage high potential DCH when the first node Q(N) is high, causing the third node K(N) to be lower.
  • the second node P(N) is also pulled down to a lower potential, that is, the auxiliary inverter 700 provides a low potential to the main inverter 600a during the operation, thereby eliminating the thirty-second transistor T32, the forty-second Transistor T42 occurs due to a leakage condition caused by a lower threshold voltage or a physical characteristic approaching 0V, ensuring that the pull-down sustain circuit portion 600 can be normally pulled low during operation.
  • the fifty-second transistor T52, the fifty-fourth transistor T54, the seventy-second transistor T72, and the seventy-fourth transistor T74 are all turned off. Since the gate of the fifty-fourth transistor T54 is electrically connected to the first node Q(N), the source is electrically connected to the third node K(N), and the gate of the fifty-fourth transistor T54 is at a negative potential. Extremely positive, so that Vgs is a relatively very negative potential, which can turn off the fifty-fourth transistor T54 very well, reducing its leakage, that is, the auxiliary inverter provides the main inverter during the inactive period.
  • a suitable high potential is applied to reduce the leakage of the fifty-fourth transistor T54, ensuring that the pull-down sustain circuit portion 600 is at a higher potential during the inactive period, effectively maintaining the first node Q(N) and the output terminal G(N). At a low potential.
  • the third node K(N) is high,
  • resistor division which can push the potential of the second node P(N) higher, thereby stabilizing the potential of the second node P(N).
  • FIG. 3 is a waveform diagram of an output of a scan driving circuit for an oxide semiconductor thin film transistor and an output waveform of a key node according to the first embodiment of the present invention.
  • STV is the start signal of the circuit
  • CK(1)-CK(4) is the clock signal of the circuit, it can be seen that the duty cycle of the clock signal waveform shown here is 25/75, which can ensure the Q of the first node ( The signal output waveform of N) is "convex" shaped.
  • Other output signal waveforms generated for critical nodes of the circuit are examples of the clock signal waveform shown here.
  • the first waveform of the first node (Q(N)) in the first cascade relationship of the scan driving circuit has a "convex" shape, and the first one in the cascade relationship of the last stage
  • the signal output second waveform of the node (Q(N+2)) is in a "convex" shape, and the corresponding output terminal G(N) of the first waveform and the second waveform overlapping portion is normally output.
  • the first waveform of the first node (Q(N)) in the first cascade relationship is at a low potential, and the first node in the cascade relationship of the last stage (Q(N+) 2))
  • the signal output second waveform is also at a low potential, at which time the output terminal G(N) is at a low potential.
  • FIG. 4 is a circuit diagram of a pull-down sustain circuit for a scan driving circuit of an oxide semiconductor thin film transistor according to a second embodiment of the present invention.
  • the same level of the main inverter 600a and the auxiliary inverter 700 are connected to form a corresponding pull-down maintaining circuit 600, and in the three-level connection relationship, a three-stage pull-down sustaining circuit is required to form a transistor.
  • the number is 34.
  • the pull-down sustaining circuit 600 in each stage connection relationship is the same, and each has 8 transistors, forming a three-stage.
  • the total number of transistors required for the pull-down sustain circuit is 40. Therefore, with the embodiment of the present invention, when a three-level connection relationship is formed, six transistors are correspondingly reduced.
  • the clock signal CK(M) includes eight sets of clock signals: a first clock signal (CK(1)), a second clock signal (CK(2)), and a third clock signal (CK(3)), Four clock signals (CK(4)), fifth clock signal (CK(5)), sixth clock signal (CK(6)), seventh clock signal (CK(7)), eighth clock signal (CK() 8)).
  • the duty ratio setting of the clock signal CK(M) needs to be no more than 25/75 to ensure that the first node Q(N) has a "convex" shape.
  • the waveform of the clock signal CK(P) is occupied. The ratio is 25/75.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 4 and FIG. 2 are the same, and are not described herein again.
  • FIG. 5 is a scan for an oxide semiconductor thin film transistor according to a first embodiment of the present invention. Trace the waveform settings of the driver circuit and the output waveform of the key nodes. Among them, STV is the start signal of the circuit; CK(1)-CK(4) is the clock signal of the circuit, it can be seen that the duty cycle of the clock signal waveform shown here is 25/75, which can ensure the Q of the first node ( The signal output waveform of N) is "convex" shaped. Other output signal waveforms generated for critical nodes of the circuit.
  • the first waveform of the first node (Q(N)) in the first cascade relationship of the scan driving circuit has a "convex" shape, and the first one in the cascade relationship of the last stage
  • the signal output second waveform of the node (Q(N+2)) is in a "convex" shape, and the corresponding output terminal G(N) of the first waveform and the second waveform overlapping portion is normally output.
  • the first waveform of the first node (Q(N)) in the first cascade relationship is at a low potential, and the first node in the cascade relationship of the last stage (Q(N+) 4))
  • the signal output second waveform is also at a low potential, at which time the output terminal G(N) is at a low potential.
  • the present invention provides a scan driving circuit for an oxide semiconductor thin film transistor having a pull-down sustain circuit portion of a scan driving circuit for an oxide semiconductor thin film transistor having a main inverter and a common auxiliary inverter
  • the auxiliary inverter can be connected with each main inverter to form a corresponding pull-down sustain circuit portion, which can realize the sharing of the pull-down sustain circuit of the multi-level GOA circuit, thereby reducing the number of TFT elements, thereby reducing the GOA layout space and reducing Circuit power consumption.

Abstract

一种用于氧化物半导体薄膜晶体管的扫描驱动电路，该驱动电路包括多个级联的GOA单元（10）以及共享的辅助反相器（700），每个GOA单元（10）均包括主反相器（600a）。该辅助反相器（700）与每个主反相器（600a）连接形成对应的下拉维持电路部分（600），能够实现多级GOA电路的下拉维持电路的共享，从而减少TFT元件的数量，以减少GOA版图空间和降低电路功耗。

Description

用于氧化物半导体薄膜晶体管的扫描驱动电路 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种用于氧化物半导体薄膜晶体管的扫描驱动电路。
【背景技术】
GOA(Gate Drive On Array)，是利用薄膜晶体管(thin filp transistor，TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。
而现有技术中(如图1所示)，氧化物半导体薄膜晶体管的扫描驱动电路一般是多级相同的GOA电路进行级联连接，每一级GOA电路的下拉维持电路都相同，但是由于下拉维持电路包含较多的TFT元件，这样会增加GOA版图空间，而且也会增加电路功耗。
【发明内容】
为了至少部分解决以上问题，本发明主要解决的技术问题是提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路，能够实现多级GOA电路的下拉维持电路 的共享，从而减少TFT元件的数量，以减少GOA版图空间和降低电路功耗。
本发明采用的第一种技术方案是提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路，一种用于氧化物半导体薄膜晶体管的扫描驱动电路，所述电路包括级联的P个GOA单元，每个GOA单元包括上拉控制部分、上拉部分、下传部分、第一下拉部分、自举电容部分和主反相器部分；所述电路还包括辅助反相器，每级连接关系中的所述主反相器部分与所述辅助反相器连接形成对应的所述GOA单元的下拉维持部分；设定P、N均为正整数，且N≤P；其中，第N级连接关系中，所述主反相器部分包括：第五十一晶体管(T51)，栅极与漏极均电性连接于恒压高电位(DCH)，源极电性连接于第四节点(S(N))；第五十二晶体管(T52)，栅极电性连接于第一节点(Q(N))，漏极电性连接于所述第四节点(S(N))，源极电性连接于第一负电位(VSS1)；第五十三晶体管(T53)，栅极电性连接于所述第四节点(S(N))，漏极电性连接于所述恒压高电位(DCH)，源极电性连接于第二节点(P(N))；第五十四晶体管(T54)，栅极电性连接于所述第一节点(Q(N))，漏极电性连接于所述第二节点(P(N))，源极电性连接于第三节点(K)；所述辅助反相器包括：第七十三晶体管(T73)，栅极与第1级连接关系中的所述主反相器的第四节点(S(1))电性连接，漏极电性连接于恒压高电位(DCH)；第七十四晶体管(T74)，栅极与最后一级连接关系中的所述主反相器的第四节点(S(P))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于所述第七十三晶体管(T73)的源极；第七十五晶体管(T75)，栅极与第1级连接关系中的所述主反相器的第一节点(Q(1))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于恒压低电位(DCL)；第七十六晶体管(T76)，栅极与最后一级连接关系中的所述主反相器的第一节点(Q(P))电性连接，漏极电性连接于所述恒压低电位(DCL)，源极电性连接所述第三节点(K)；所述上拉部分包括：第二十一晶体管(T21)，栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(n))，源极电性连接于输出端(G(N))；
所述下传部分包括：第二十二晶体管(T22)，栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(M))，源极电性连接于驱动输出端(ST( N))；其中，在所述扫描驱动电路的第一级联关系中的所述第一节点(Q(1))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(P))的信号输出第二波形均呈“凸”字形，并根据所述第一波形和第二波形交叠部分对应的信号控制所述辅助反相器。
本发明采用的第二种技术方案是提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路，所述电路包括级联的P个GOA单元，每个GOA单元包括上拉控制部分、上拉部分、下传部分、第一下拉部分、自举电容部分和主反相器部分；所述电路还包括辅助反相器，每级连接关系中的所述主反相器部分与所述辅助反相器连接形成对应的所述GOA单元的下拉维持部分；设定P、N均为正整数，且N≤P；其中，第N级连接关系中，所述主反相器部分包括：第五十一晶体管(T51)，栅极与漏极均电性连接于恒压高电位(DCH)，源极电性连接于第四节点(S(N))；第五十二晶体管(T52)，栅极电性连接于第一节点(Q(N))，漏极电性连接于所述第四节点(S(N))，源极电性连接于第一负电位(VSS1)；第五十三晶体管(T53)，栅极电性连接于所述第四节点(S(N))，漏极电性连接于所述恒压高电位(DCH)，源极电性连接于第二节点(P(N))；第五十四晶体管(T54)，栅极电性连接于所述第一节点(Q(N))，漏极电性连接于所述第二节点(P(N))，源极电性连接于第三节点(K)；所述辅助反相器包括：第七十三晶体管(T73)，栅极与第1级连接关系中的所述主反相器的第四节点(S(1))电性连接，漏极电性连接于恒压高电位(DCH)；第七十四晶体管(T74)，栅极与最后一级连接关系中的所述主反相器的第四节点(S(P))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于所述第七十三晶体管(T73)的源极；第七十五晶体管(T75)，栅极与第1级连接关系中的所述主反相器的第一节点(Q(1))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于恒压低电位(DCL)；第七十六晶体管(T76)，栅极与最后一级连接关系中的所述主反相器的第一节点(Q(P))电性连接，漏极电性连接于所述恒压低电位(DCL)，源极电性连接所述第三节点(K)。
其中，第N级连接关系中，所述上拉部分包括第二十一晶体管(T21)，所述第二十一晶体管(T21)的栅极电性连接于第一节点(Q(N))，漏极电性连接于 时钟信号(CK(n))，源极电性连接于输出端(G(N))；所述下传部分包括第二十二晶体管(T22)，所述第二十二晶体管(T22)的栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(M))，源极电性连接于驱动输出端(ST(N))；所述自举电容部分包括一电容(Cb)，所述电容(Cb)的一端电性连接于第一节点(Q(N))，另一端电性连接于输出端(G(N))。
其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
其中，所述时钟信号(CK(M))的波形占空比不大于25/75。
其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
其中，所述时钟信号(CK(M))的波形占空比等于25/75。
其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
其中，在所述扫描驱动电路的第一级联关系中的所述第一节点(Q(1))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(P))的信号输出第二波形均呈“凸”字形，并根据所述第一波形和第二波形交叠部分对应的信号控制所述辅助反相器。
其中，所述扫描驱动电路采用的级传方式是第N-2级传给第N级。
其中，所述扫描驱动电路的第一级连接关系中，第十一晶体管(T11)的栅极和漏极电性连接于电路的启动信号端(STV)。
其中，所述扫描驱动电路的最后一级连接关系中，第四十一晶体管(T41)的栅极电性连接于电路的启动信号端(STV)。
本发明的有益效果是：本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路，该用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路部分具有主反相器，还包括一个公共的辅助反相器，该辅助反相器能够与每个主反相器连接形成对应的下拉维持电路部分，能够实现多级GOA电路的下拉维持电路的共享，从而减少TFT元件的数量，以减少GOA版图空间和降低电路功耗。
【附图说明】
图1为现有技术中用于氧化物半导体薄膜晶体管的扫描驱动电路第N级GOA单元的电路图；
图2为本发明第一实施方式中的用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路的电路图；
图3为具有图2所示的下拉维持电路的用于氧化物半导体薄膜晶体管的扫描驱动电路的波形设置和关键节点的输出波形图；
图4为本发明第二实施方式中的用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路的电路图；
图5为具有图4所示的下拉维持电路的用于氧化物半导体薄膜晶体管的扫描驱动电路的波形设置和关键节点的输出波形图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细说明。
请参阅图1，为现有技术中用于氧化物半导体薄膜晶体管的扫描驱动电路第N级 GOA单元的电路图。该GOA单元10包括上拉控制部分100、上拉部分200、下传部分300、第一下拉部分400、自举电容部分500和下拉维持电路部分600。
上述各部分的组成以及具体的连接方式如下：
该上拉控制部分100包括第十一晶体管T11，该第十一晶体管T11的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端ST(N-2)，漏级电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端G(N-2)，源极电性连接于第一节点Q(N)。
该上拉部分200包括第二十一晶体管T21，该第二十一晶体管T21的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(P)，源极电性连接于输出端G(N)。
该下传部分300包括第二十二晶体管T22，该第二十二晶体管T22的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(P)，源极电性连接于驱动输出端ST(N)。
该第一下拉部分400包括一第四十一晶体管T41，该第四十一晶体管T41的栅极电性连接于该第N级GOA单元的下两级GOA单元第N+2级GOA单元的输出端G(N+2)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2。
该自举电容部分500包括一电容Cb，该电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)。
该下拉维持部分600包括第五十一晶体管T51，该第五十一晶体管T51的栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第四节点S(N)。
第五十二晶体管T52，该第五十二晶体管T52的栅极电性连接于第一节点Q(N)，漏极电性连接于第四节点S(N)，源极电性连接于第一负电位VSS1。
第五十三晶体管T53，该第五十三晶体管T53的栅极电性连接于第四节点S(N)，漏极电性连接于恒压高电位DCH，源极电性连接于第二节点P(N)。
第五十四晶体管T54，该第五十四晶体管T54的栅极电性连接于第一节点Q(N)，漏极电性连接于第二节点P(N)，源极电性连接第三节点K(N)。
第七十一晶体管T71，该第七十一晶体管T71的栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第七十三晶体管T73的栅极。
第七十二晶体管T72，该第七十二晶体管T72的栅极电性连接于第一节点Q(N)，漏极电性连接于第七十三晶体管T73的栅极，源极电性连接于恒压低电位DCL。
第七十三晶体管T73，该第七十三晶体管T73的栅极电性连接于第七十一晶体管T71的源极，漏极电性连接于恒压高电位DCH，源极电性连接于第三节点K(N)。第七十四晶体管T74，该第七十四晶体管T74的栅极电性连接于第一节点Q(N)，漏极电性连接于第三节点K(N)，源极电性连接于恒压低电位DCL。
第四十二晶体管T42，该第四十二晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2。
第三十二晶体管T32，该第三十二晶体管T32的栅极电性连接于第二节点P(N)，漏极电性连接于输出端G(N)，源极电性连接于第一负电位VSS1。
请参阅图2，为本发明第一实施方式中的用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路的电路图，其中，该用于氧化物半导体薄膜晶体管的扫描驱动电路为铟镓锌氧化物(IndiuP GalliuP Zinc Oxide，IGZO)薄膜晶体管的扫描驱动电路，包括级联的P个GOA单元。设P、N为正整数，且N≤P，则第N级GOA单元包括上拉控制部分100、上拉部分200、下传部分300、第一下拉部分400、自举电容部分500和下拉维持电路部分600。
上述各部分的组成以及具体的连接方式如下：
该上拉控制部分100包括第十一晶体管T11，该第十一晶体管T11的栅极电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的驱动输出端ST(N-2)，漏级电性连接于该第N级GOA单元的前两级GOA单元第N-2级GOA单元的输出端G(N-2)，源极电性连接于第一节点Q(N)。
该上拉部分200包括第二十一晶体管T21，该第二十一晶体管T21的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(P)，源极电性连接于输出端G(N)。
该下传部分300包括第二十二晶体管T22，该第二十二晶体管T22的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(P)，源极电性连接于驱动输出端ST(N)。
该第一下拉部分400包括一第四十一晶体管T41，该第四十一晶体管T41的栅极电性连接于该第N级GOA单元的下两级GOA单元第N+2级GOA单元的输出端G(N+2)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2。
该自举电容部分500包括一电容Cb，该电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)。
该下拉维持部分600包括主反相器600a、第三十二晶体管T32以及第四十二晶体管T42。其中，该主反相器600a包括：
第五十一晶体管(T51)，栅极与漏极均电性连接于恒压高电位(DCH)，源极电性连接于第四节点(S(N))。
第五十二晶体管(T52)，栅极电性连接于第一节点(Q(N))，漏极电性连接于所述第四节点(S(N))，源极电性连接于第一负电位(VSS1)。
第五十三晶体管(T53)，栅极电性连接于所述第四节点(S(N))，漏极电性连接于所述恒压高电位(DCH)，源极电性连接于第二节点(P(N))。
第五十四晶体管(T54)，栅极电性连接于所述第一节点(Q(N))，漏极电性连接于所述第二节点(P(N))，源极电性连接于第三节点(K)。
第四十二晶体管T42，该第四十二晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2；
第三十二晶体管T32，该第三十二晶体管T32的栅极电性连接于第二节点P(N)，漏极电性连接于输出端G(N)，源极电性连接于第一负电位VSS1。
进一步地，GOA单元还包括辅助反相器700，每级连接关系中的主反相器部分600a与该辅助反相器700连接形成对应的GOA单元的下拉维持部分600。即，多级的GOA单元的下拉维持部分600共用同一个辅助反相器700。
具体地，该辅助反相器700包括：
第七十三晶体管(T73)，栅极与第1级连接关系中的该主反相器的第四节点(S(1))电性连接，漏极电性连接于恒压高电位(DCH)。
第七十四晶体管(T74)，栅极与最后一级连接关系中的该主反相器的第四节点(S(P))电性连接，漏极电性连接于该第三节点(K)，源极电性连接于该第七十三晶体管(T73)的源极。
第七十五晶体管(T75)，栅极与第1级连接关系中的该主反相器的第一节点(Q(1))电性连接，漏极电性连接于该第三节点(K)，源极电性连接于恒压低电位(DCL)。
第七十六晶体管(T76)，栅极与最后一级连接关系中的该主反相器的第一节点(Q(P))电性连接，漏极电性连接于该恒压低电位(DCL)，源极电性连接该第三节点(K)。
其中，该第一负电位VSS1、二负电位VSS2与恒压低电位DCL的关系为：恒压低电位DCL＜第二负电位VSS2＜第一负电位VSS1。
该扫描驱动电路采用的级传方式是第N-2级传给第N级。
该扫描驱动电路的第一级连接关系中，第十一晶体管T11的栅极与漏极电性连接于电路的启动信号端STV。
该扫描驱动电路的第二级连接关系中，第十一晶体管T11的栅极与漏极均电性连接于电路的启动信号端STV。
该扫描驱动电路的倒数第二级连接关系中，第四十一晶体管T41的栅极电性连接于电路的启动信号端STV。
该扫描驱动电路的最后一级连接关系中，第四十一晶体管T41的栅极电性连接于电路的启动信号端STV。
在本实施方式中，P＝3，即，三级GOA单元连接。在每一级连接关系中，同级别的主反相器600a与辅助反相器700连接共同形成对应的下拉维持电路600，且在三级连接关系中，形成三级的下拉维持电路共需要晶体管的数量为22个。但是，如图1所示的现有技术中的用于氧化物半导体薄膜晶体管的扫描驱动电路，其每一级连接关系中的下拉维持电路600均相同，都具有8个晶体管，则形成三级的下拉维持电路共需要晶体管的数量为24个。因此，通过本发明实施方式，在形成三级连接关系时，相应地减少了2个晶体管。
进一步地，在本实施方式中，第一下拉部分400只有第四十一晶体管T41负责下拉第一节点Q(N)，且第四十一晶体管T41的栅极电性连接于第N+2级GOA单元的输出端G(N+2)，T41的源极电性连接于第二负电位VSS2。该时钟信号CK(M)包含四组时钟信号：第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK( 3)、第四时钟信号CK(4)，而且时钟信号CK(M)的占空比设置需要不大于25/75，以确保第一节点Q(N)呈“凸”字形，优选的，该时钟信号CK(P)的波形占空比为25/75。
上述驱动扫描电路的工作原理如下：
该下拉维持电路部分600中，第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53、第五十四晶体管T54四个晶体管构成的主反相器600a，作用是控制第三十二晶体管T32和第四十二晶体管T42两个晶体管。该辅助反相器700的作用是在作用期间提供给主反相器600a低电位，在非作用期间提供给主反相器600a一个适当的高电位来降低第五十四晶体管T54的漏电，以确保主反相器600a在非作用期间能够产生较高的电位。
具体地，在该辅助反相器700的作用期间，辅助反相器700经恒压高电位DCH与恒压低电位DCL高/低电压驱动后，第五十二晶体管T52被下拉至第一负电位VSS1，第七十四晶体管T74、第七十二晶体管T72在第一节点Q(N)为高电位时开启并下拉恒压高电位DCH，导致第三节点K(N)为更低电位，第二节点P(N)也被下拉到一更低电位，即辅助反相器700在作用期间给主反相器600a提供了低电位，因而可以杜绝第三十二晶体管T32、第四十二晶体管T42因阈值电压较低或趋近于0V的物理特性所引发的漏电情况发生，确保该下拉维持电路部分600能够在作用期间正常拉低。
在该辅助反相器700的非作用期间，第五十二晶体管T52、第五十四晶体管T54、第七十二晶体管T72、第七十四晶体管T74均截止关闭。由于第五十四晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第三节点K(N)，该第五十四晶体管T54的栅极为负电位，源极为正电位，这样Vgs是一个相对来说非常负值的电位，可以将第五十四晶体管T54关闭得很好，减少它的漏电，即辅助反相器在非作用期间给主反相器提供了一个适当的高电位来降低第五十四晶体管T54的漏电，确保该下拉维持电路部分600在非作用期间处于较高的电位，有效维持第一节点Q(N)和输出端G(N)处于低电位。此外，在第三节点K(N)为高电位时，
还存在电阻分压的功能，可以将第二节点P(N)的电位推得更高，因而可以稳定第二节点P(N)的电位。
请同时参阅图3，为本发明第一实施方式的用于氧化物半导体薄膜晶体管的扫描驱动电路的波形设置和关键节点的输出波形图。其中，STV是电路的启动信号；CK(1)-CK(4)是电路的时钟信号，可以看出这里示意的时钟信号波形的占空比为25/75，可以确保第一节点的Q(N)的信号输出波形呈“凸”字形。其它为电路关键节点产生的输出信号波形。由图可知：在扫描驱动电路的第一级联关系中的第一节点(Q(N))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(N+2))的信号输出第二波形均呈“凸”字形，并且第一波形和第二波形交叠部分的对应的输出端G(N)正常输出。在非作用期间，第一级联关系中的第一节点(Q(N))的信号输出第一波形处于低电位，最后一级的级联关系中的所述第一节点(Q(N+2))的信号输出第二波形也处于低电位，此时，输出端G(N)处于低电位。
请参阅图4，为本发明第二实施方式中的用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路的电路图，在本实施方式中，P＝5，即，五级GOA单元连接。在每一级连接关系中，同级别的主反相器600a与辅助反相器700连接共同形成对应的下拉维持电路600，且在三级连接关系中，形成三级的下拉维持电路共需要晶体管的数量为34个。但是，如图1所示的现有技术中的用于氧化物半导体薄膜晶体管的扫描驱动电路，其每一级连接关系中的下拉维持电路600均相同，都具有8个晶体管，则形成三级的下拉维持电路共需要晶体管的数量为40个。因此，通过本发明实施方式，在形成三级连接关系时，相应地减少了6个晶体管。
进一步地，该时钟信号CK(M)包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。同样地，时钟信号CK(M)的占空比设置需要不大于25/75，以确保第一节点Q(N)呈“凸”字形，优选的，该时钟信号CK(P)的波形占空比为25/75。除此之外，图4与图2中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
请同时参阅图5，为本发明第一实施方式的用于氧化物半导体薄膜晶体管的扫 描驱动电路的波形设置和关键节点的输出波形图。其中，STV是电路的启动信号；CK(1)-CK(4)是电路的时钟信号，可以看出这里示意的时钟信号波形的占空比为25/75，可以确保第一节点的Q(N)的信号输出波形呈“凸”字形。其它为电路关键节点产生的输出信号波形。由图可知：在扫描驱动电路的第一级联关系中的第一节点(Q(N))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(N+2))的信号输出第二波形均呈“凸”字形，并且第一波形和第二波形交叠部分的对应的输出端G(N)正常输出。在非作用期间，第一级联关系中的第一节点(Q(N))的信号输出第一波形处于低电位，最后一级的级联关系中的所述第一节点(Q(N+4))的信号输出第二波形也处于低电位，此时，输出端G(N)处于低电位。
本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路，该用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路部分具有主反相器，还包括一个公共的辅助反相器，该辅助反相器能够与每个主反相器连接形成对应的下拉维持电路部分，能够实现多级GOA电路的下拉维持电路的共享，从而减少TFT元件的数量，以减少GOA版图空间和降低电路功耗。
在上述实施例中，仅对本发明进行了示范性描述，但是本领域技术人员在阅读本专利申请后可以在不脱离本发明的精神和范围的情况下对本发明进行各种修改。

Claims (15)

  1. 一种用于氧化物半导体薄膜晶体管的扫描驱动电路，所述电路包括级联的P个GOA单元，每个GOA单元包括上拉控制部分、上拉部分、下传部分、第一下拉部分、自举电容部分和主反相器部分；其中，所述电路还包括辅助反相器，每级连接关系中的所述主反相器部分与所述辅助反相器连接形成对应的所述GOA单元的下拉维持部分；设定P、N均为正整数，且N≤P；其中，第N级连接关系中，所述主反相器部分包括：
    第五十一晶体管(T51)，栅极与漏极均电性连接于恒压高电位(DCH)，源极电性连接于第四节点(S(N))；
    第五十二晶体管(T52)，栅极电性连接于第一节点(Q(N))，漏极电性连接于所述第四节点(S(N))，源极电性连接于第一负电位(VSS1)；
    第五十三晶体管(T53)，栅极电性连接于所述第四节点(S(N))，漏极电性连接于所述恒压高电位(DCH)，源极电性连接于第二节点(P(N))；
    第五十四晶体管(T54)，栅极电性连接于所述第一节点(Q(N))，漏极电性连接于所述第二节点(P(N))，源极电性连接于第三节点(K)；
    所述辅助反相器包括：
    第七十三晶体管(T73)，栅极与第1级连接关系中的所述主反相器的第四节点(S(1))电性连接，漏极电性连接于恒压高电位(D CH)；
    第七十四晶体管(T74)，栅极与最后一级连接关系中的所述主反相器的第四节点(S(P))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于所述第七十三晶体管(T73)的源极；第七十五晶体管(T75)，栅极与第1级连接关系中的所述主反相器的第一节点(Q(1))电性连接，漏极电性连接于所述第三节点 (K)，源极电性连接于恒压低电位(DCL)；
    第七十六晶体管(T76)，栅极与最后一级连接关系中的所述主反相器的第一节点(Q(P))电性连接，漏极电性连接于所述恒压低电位(DCL)，源极电性连接所述第三节点(K)；
    所述上拉部分包括：
    第二十一晶体管(T21)，栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(n))，源极电性连接于输出端(G(N))；
    所述下传部分包括：
    第二十二晶体管(T22)，栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(M))，源极电性连接于驱动输出端(ST(N))；
    其中，在所述扫描驱动电路的第一级联关系中的所述第一节点(Q(1))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(P))的信号输出第二波形均呈“凸”字形，并根据所述第一波形和第二波形交叠部分对应的信号控制所述辅助反相器。
  2. 一种用于氧化物半导体薄膜晶体管的扫描驱动电路，所述电路包括级联的P个GOA单元，每个GOA单元包括上拉控制部分、上拉部分、下传部分、第一下拉部分、自举电容部分和主反相器部分；其中，所述电路还包括辅助反相器，每级连接关系中的所述主反相器部分与所述辅助反相器连接形成对应的所述GOA单元的下拉维持部分；设定P、N均为正整数，且N≤P；其中，第N级连接关系中，所述主反相器部分包括：
    第五十一晶体管(T51)，栅极与漏极均电性连接于恒压高电位(DCH)，源极电性连接于第四节点(S(N))；
    第五十二晶体管(T52)，栅极电性连接于第一节点(Q(N))，漏极电性连接于所述第四节点(S(N))，源极电性连接于第一负电 位(VSS1)；
    第五十三晶体管(T53)，栅极电性连接于所述第四节点(S(N))，漏极电性连接于所述恒压高电位(DCH)，源极电性连接于第二节点(P(N))；
    第五十四晶体管(T54)，栅极电性连接于所述第一节点(Q(N))，漏极电性连接于所述第二节点(P(N))，源极电性连接于第三节点(K)；
    所述辅助反相器包括：
    第七十三晶体管(T73)，栅极与第1级连接关系中的所述主反相器的第四节点(S(1))电性连接，漏极电性连接于恒压高电位(D CH)；
    第七十四晶体管(T74)，栅极与最后一级连接关系中的所述主反相器的第四节点(S(P))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于所述第七十三晶体管(T73)的源极；
    第七十五晶体管(T75)，栅极与第1级连接关系中的所述主反相器的第一节点(Q(1))电性连接，漏极电性连接于所述第三节点(K)，源极电性连接于恒压低电位(DCL)；
    第七十六晶体管(T76)，栅极与最后一级连接关系中的所述主反相器的第一节点(Q(P))电性连接，漏极电性连接于所述恒压低电位(DCL)，源极电性连接所述第三节点(K)。
  3. 根据权利要求2所述用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，第N级连接关系中，所述上拉部分包括第二十一晶体管(T21)，所述第二十一晶体管(T21)的栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(n))，源极电性连接于输出端(G(N))；
    所述下传部分包括第二十二晶体管(T22)，所述第二十二晶体管(T22)的栅极电性连接于第一节点(Q(N))，漏极电性连接于时钟信号(CK(M))，源极电性连接于驱动输出端(ST(N))； 所述自举电容部分包括一电容(Cb)，所述电容(Cb)的一端电性连接于第一节点(Q(N))，另一端电性连接于输出端(G(N))。
  4. 如权利要求3所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
  5. 如权利要求3所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
  6. 如权利要求3所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号(CK(M))的波形占空比不大于25/75。
  7. 如权利要求6所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
  8. 如权利要求6所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
  9. 如权利要求3所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号(CK(M))的波形占空比等于25/75。
  10. 如权利要求9所述的用于氧化物半导体薄膜晶体管的扫描驱动电路 ，其中，当P＝3时，所述时钟信号(CK(M))包含四组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))。
  11. 如权利要求9所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，当P＝5时，所述时钟信号(CK(M))包含八组时钟信号：第一时钟信号(CK(1))、第二时钟信号(CK(2))、第三时钟信号(CK(3))、第四时钟信号(CK(4))、第五时钟信号(CK(5))、第六时钟信号(CK(6))、第七时钟信号(CK(7))、第八时钟信号(CK(8))。
  12. 如权利要求2所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，在所述扫描驱动电路的第一级联关系中的所述第一节点(Q(1))的信号输出第一波形呈“凸”字形，最后一级的级联关系中的所述第一节点(Q(P))的信号输出第二波形均呈“凸”字形，并根据所述第一波形和第二波形交叠部分对应的信号控制所述辅助反相器。
  13. 根据权利要求2所述用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述扫描驱动电路采用的级传方式是第N-2级传给第N级。
  14. 根据权利要求2所述用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述扫描驱动电路的第一级连接关系中，第十一晶体管(T11)的栅极和漏极电性连接于电路的启动信号端(STV)。
  15. 如权利要求2所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述扫描驱动电路的最后一级连接关系中，第四十一晶体管(T41)的栅极电性连接于电路的启动信号端(STV)。
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