200841347 九、發明說明： 【發明所屬之技術領域】 本發明係關於移位暫存 飞卄甩路，且尤指其適用 最低可能功率消耗之移位暫存器設計。 κ 【先前技術】 第1圖係說明斜斟μ错 对對於早級靜態移位暫存器之一種習用 的設計。如同關於体打从必 证白川 、4何的移位暫存器，此電路〗〇 一訊號輸入in ' —時脈於 /、/、 ^才脈輪入仏、與於此架構之互補輸出OUt /、〇u “电路係由二個軌線電壓與v 一供應電壓所供電。 ^徒供的 此特定電路係運用一輸入訊號的緩衝電晶體MP1，其 饋接一對的交叉耦接式雷曰 八 能。 大私曰曰體踏與MP3，以儲存該輸入 ^ 至MP1之輸出的反相器INV1與iNV2係 作為以緩衝輸出電壓與電流位準。時脈開關電晶體卜 MN2、MN3肖MN4係接通該移位暫存器以接受諸如自前 一級的一數位輸入訊號。 針對於該移位暫存器以運作，開關Mm姻4係必須 為完全接通或關斷’因此需要於其閑極端子之全軌線至軌 ㈣M_(swing)°即使外部的低電壓時脈訊號係施 加，位準移位器與時脈緩衝器（未顯示於第！圖）係必須為 ，用以使得閘極控制電壓成為全軌線電塵擺幅。不幸的 疋於此等時脈緩衝器之功率消耗係等於v2c f ,其中， =電源供應電麗差異（VDD_vss)，&係連接^°時脈缓衝 為勒出之總寄生電容，1 fc係時脈頻率。藉著高電壓供應 5 200841347 率大者第)、i多:串聯的移位暫存器、長的連接線、 將因此為消耗大量的功;之運用級電路的一種移位暫存器係 弟2圖係說明另_種習知的移位暫存器級電路⑼，盆 某個程度為改良於第彳闰+ ^ 適以摔作移位暫存器級電路係 輯電=二電塵擺幅的時脈訊號而非高電塵擺幅的邏 能為1〇二：？卿與VSS之間的電壓範圍係可 二係可二*以提供高速。然而，來自時脈輸入ck之電壓 二::、較小許多(於3伏特左右之規模)以降低功率 針對於第2圖之雷敗0A认^ t χ 私路20的輸入與輸出訊號係如後： ck 0與0* r vgp pc 具有自VEE至VDD的峰對峰電壓 之時脈訊號（VEE>VSS) 自先前的移位暫存器級之互補輸出 分別為暫存器輸出與其互補輪出 針對於個別的移位暫存器之重設訊號 類比偏壓電壓 預充電訊號，以在起始之前而初始化 所有的移位暫存器至低 電路2 0係構成，俾使一内邱銘 平便内邛即點a係作為針對於輸入 訊號狀態及針對於驅動輸出緩衝器ΙΝνι之一隽合點。 此，狀態電晶體之數目係已經減少至其配置於串級㈣C。： 6 200841347 串聯之僅為二者，MP2肖MP1。該&訊號輸人係饋送至 MP2之源極。VDD供應電壓係饋送以偏壓電晶體Mp2之 本體。MP2之閘極係自前一個移位暫存器級之互補的輸出 所饋入。 MP1之閘極係由其為一類比偏壓電壓之，所控制。 MP1係偏壓’俾使當其源極電壓係相較於為大於一量 p而導通其中，Vtp係Μρι之臨限電磨。一預充電輪 入Pe與-重設輸人r係饋人刪之汲極，其亦設定於節 點a之電壓。 於作業時，電壓vgp係因此設定為使得vEE_vgp<v印， 其中，Vtp係電晶體剛之臨限電塵。當&係低（㈣）， 綱係關斷(。ff)且節點a係保持為於其先前值；當吐係 南（VDD)且前級輸出e係高（其意指：H(VSS))，節點 過電晶體MP!與MP2而充電為達到__高電壓 第2圖之電路2〇係因此為相較於第工圖之電路⑺而 提供降低的功率消耗。然而，於諸如此舉之設計，夢著由 —低電壓擺幅的輸入時脈所驅動/ I 利心禋阿電壓擺幅的移位 暫存益，内邛或外部的位準移位器 赍 了胍綾衡态係因此經 吊馬必要。 【發明内容】 本發明係-種針對於高電壓移位暫存器之改良 其直接接受低電壓時脈訊號輸 又 特別而丄 ^ /貝運用時脈緩衝器。 5，一種移位暫存器級電路係適以操作於_低電壓 7 200841347 擺幅時脈訊號，該級電路係具有單一個輸入電晶體所直接 驅動之單一個狀悲節點a。此配置係允許降低的功率消耗。 本發明係亦提供改良的速度。該移位暫存器級之速度 係主要為由其連接至單一節點a之寄生電容、與其自一時 脈訊號ck至節點a之一小訊號電阻所決定。寄生電容係包 括接線電容、於其連接至節點a之電晶體的電容。200841347 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to shifting temporary storage, and in particular to shift register design for the lowest possible power consumption. κ [Prior Art] Fig. 1 illustrates a conventional design of a skew 斟 错 对于 for an early stage static shift register. As with the shift register of the body, the circuit is 〇 讯 讯 讯 in 讯 讯 讯 讯 讯 讯 — — — — — — — — — — — — — — — 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此〇u "The circuit is powered by two rail voltages and a supply voltage. ^ This particular circuit is a buffered transistor MP1 that uses an input signal that feeds a pair of cross-coupled thunders. Eight can. Large private body step with MP3, to store the input ^ to the output of MP1 inverter INV1 and iNV2 as the buffer output voltage and current level. Clock switch transistor MN2, MN3 Xiao MN4 The shift register is turned on to accept a digital input signal such as from the previous stage. For the shift register to operate, the switch Mm system must be fully turned on or off 'so it needs to be idle The entire rail of the pole is rail-to-rail (4) M_(swing)° Even if the external low-voltage clock signal is applied, the level shifter and the clock buffer (not shown in the figure!) must be used to make the gate The pole control voltage becomes the full-rail electric dust swing. Unfortunately, these clocks are slow. The power consumption of the punch is equal to v2c f , where = power supply difference (VDD_vss), & connection ^° clock buffer is the total parasitic capacitance of the pull out, 1 fc is the clock frequency. Voltage supply 5 200841347 The rate is greater), i is more: series shift register, long connection line, will therefore consume a lot of work; a shift register of the application level circuit Explain another kind of conventional shift register stage circuit (9). The degree of the basin is improved to the third level. ^ ^ Suitable for shifting the register stage circuit circuit series electricity = two electric dust swing The logic of the pulse signal instead of the high dust swing is 1〇2: The voltage range between the qing and VSS can be two to provide high speed. However, the voltage from the clock input ck is two::, A much smaller (on a scale of around 3 volts) to reduce power for the 2nd picture of the 0A recognition ^ t χ private circuit 20 input and output signals as follows: ck 0 and 0* r vgp pc with VEE The peak-to-peak voltage signal to VDD (VEE>VSS) The complementary outputs from the previous shift register stage are the register outputs and their complementary rounds. Resetting the signal analog bias voltage pre-charge signal for the individual shift register to initialize all the shift register to the low circuit 20 before starting, so that one inside Qiu Ming Ping The point a is used as a coupling point for the input signal state and for the drive output buffer 。νι. Thus, the number of state transistors has been reduced to its configuration at the cascade (four) C.: 6 200841347 Both, MP2 Xiao MP1. The & signal input system is fed to the source of MP2. The VDD supply voltage is fed to bias the body of the transistor Mp2. The gate of MP2 is fed from the complementary output of the previous shift register stage. The gate of MP1 is controlled by an analog bias voltage. The MP1 is biased so that its source voltage is turned on when it is greater than an amount p, and the Vtp is 临ρι. A pre-charge wheel enters the Pe and resets the input r-switched drain, which is also set to the voltage at node a. During operation, the voltage vgp is thus set such that vEE_vgp <vprint, wherein the Vtp-based transistor is just the limit of electric dust. When & is low ((4)), the system is turned off (.ff) and node a is kept at its previous value; when spitting south (VDD) and the pre-output e is high (which means: H(VSS) )), the node over-charges MP! and MP2 are charged to reach the __high voltage circuit 2 of Figure 2, thus providing reduced power consumption compared to the circuit (7) of the first drawing. However, in designs such as this, dreams are driven by the input clock of the low voltage swing / I have a shift in the temporary swing of the voltage swing, internal or external level shifter赍It is necessary to hang the horse. SUMMARY OF THE INVENTION The present invention is directed to an improvement of a high voltage shift register that directly accepts a low voltage clock signal and in particular uses a clock buffer. 5. A shift register stage circuit is adapted to operate at a low voltage 7 200841347 swing clock signal, the stage circuit having a single sad node a directly driven by a single input transistor. This configuration allows for reduced power consumption. The present invention also provides improved speed. The speed of the shift register stage is mainly determined by the parasitic capacitance connected to a single node a, and from the small signal resistance of one of the clock signals ck to the node a. The parasitic capacitance includes the capacitance of the wiring and the capacitance of the transistor connected to node a.
多個應用係可利用造成的低功率消耗與高速。此等者 係包括：設計以運用根據本發明之-種移位暫存器的顯示 器；執行於電池之可攜式裝置，諸如視訊眼戴件（eyewear); 用於攝錄影機（camcorder)與數位相機之電子式探視哭 (viewfinder);軍事系統，諸如熱武器晦準器與夜視二防二 鏡；及，其他的最終用途。 【實施方式】 本發明之貫施例的說明係如後。 第3圖係說明其改良於第i與2圖之配置的一種電路 3〇。在此，時脈訊號輸入ck亦驅動一級電晶體Μρι。然 而，MP1之閘極係饋送自一對的串級（casc〇de)電晶體mm 與MP3，其設定於節點a之狀態為如由輸人e*與㈣所決 定。自前級之反相輸入0係饋送至反相器INV3之輸入端 子’以控制電晶體MP3之間極。MP3汲極端子係控制電晶 體MP1之閘極。電晶體MP2之源極端子係自電壓而 饋電。 一意圖的預充電輸入P0係連同一重設訊號r*為饋送 通過單一個NAND閘〇單一個NAND閘之於山办貝 J I翻出係驅動訊號 8 200841347 緩衝電晶體MN1之閘極端子 相器INV2係分別提供反相 out 〇 。第一反相器INV1與第二反 的輪出out*與非反相的輸出 2路3〇之作業係類似於第2圖之電路20。然而，連 接至節點&之電晶體的數目係減少。此外，透過反相器INV1 與INV2 ’節點a係屝辭太 屏蔽為開外部接線與由移位暫存器級 3〇所驅動的裝置。自Ck至節點a之電阻係亦自一對的串Multiple applications can take advantage of the low power consumption and high speed. These include: displays designed to utilize a shift register in accordance with the present invention; portable devices implemented in batteries, such as eyewear; for camcorder Electronic viewfinder with digital cameras; military systems such as thermal weapons and night vision; and other end uses. [Embodiment] The description of the embodiments of the present invention is as follows. Fig. 3 is a diagram showing a circuit 3' modified in the configuration of the first and second figures. Here, the clock signal input ck also drives the primary transistor Μρι. However, the gate of MP1 is fed from a pair of cascades of transistors mm and MP3, the state of which is set at node a as determined by the inputs e* and (d). The inverting input 0 from the previous stage is fed to the input terminal of the inverter INV3 to control the pole between the transistors MP3. The MP3汲 extreme subsystem controls the gate of the transistor MP1. The source terminal of transistor MP2 is fed from voltage. An intended pre-charge input P0 is connected to the same reset signal r* for feeding through a single NAND gate and a single NAND gate is applied to the Yamaha JI flip-up drive signal 8 200841347 snubber terminal INV2 of the buffer transistor MN1 The system provides the inverse out 〇 respectively. The operation of the first inverter INV1 and the second reverse wheel out* and the non-inverted output 2 channel 3 is similar to the circuit 20 of Fig. 2. However, the number of transistors connected to the nodes & In addition, the inverters INV1 and INV2' node a are shielded from the external wiring and the device driven by the shift register stage 3A. The resistance from Ck to node a is also from a pair of strings
級電晶體者而減少至單-個電晶體者。 就第2圖之電路2ft 20而吕，vgp係設定為vEE-vgp<Vtp， 其中’ Vtp係電晶體Μρι之臨限電壓。第4a目之例圖係 可助於視見化此情況’纟中，Vsw係電晶體Μ"之切換臨 限且Vtp係MP1ip通道臨限電壓。 第4B圖係更為特定說明低電壓時脈訊號ck之情況， 其二’ $遽值係變化自—高軌線t壓VDD而僅為降低至 私壓VEE，VEE係相較於低軌線電壓vss為較大許多。 $ VEE與VDD之間的擺幅係可例如為僅3 3伏特而臨限 壓Vth係設定為稍高於vee。 第3圖之移位暫存器級3〇的速度係因此為主要由連接 =節點a之寄生電容、與自時脈輸人ek至節點a之小訊號 ★電阻所決定。此寄生電容係包括接線電容、與其為連接至 節點a之彼等電晶體的電容。 電晶體MP1係接著偏壓為俾使其當充電節點&而幾乎 未接通。由於此切換作業係將已經為相當緩慢（即··其為由 具有低電壓擺幅之一時脈訊號所控制），故於其為避免引入 9 200841347 額外的電阻。 由輸出驅動器反相器INV1與IN V2所提出的輸出負載 係進一步降低，由於節點a係僅需要驅動對於反相器INV1 之單一個輸入而無直接外部輸出。反相器INV1與INV2係 因此亦提供自輸出out與out*之隔離，而提供電路3〇具有 自其將為由外部電路所提出的阻抗之進一步隔離。The level of the transistor is reduced to a single transistor. For the circuit 2ft 20 of Fig. 2, the vgp system is set to vEE-vgp < Vtp, where 'Vtp is the threshold voltage of the transistor Μρι. The case diagram of the 4th item can help to visualize this situation. In the middle, the Vsw-type transistor Μ" is switched and the Vtp is the MP1ip channel threshold voltage. Figure 4B is a more specific description of the low-voltage clock signal ck, the second '$遽 value changes from the high-rail t voltage VDD and only to the private pressure VEE, VEE compared to the low-trajectory The voltage vss is much larger. The swing between $VEE and VDD can be, for example, only 3 3 volts and the threshold voltage Vth is set slightly higher than vee. The speed of the shift register stage 3 of Fig. 3 is therefore mainly determined by the parasitic capacitance of the connection = node a and the small signal from the clock input ek to the node a. This parasitic capacitance includes the capacitance of the wiring, which is the capacitance of the transistors connected to node a. The transistor MP1 is then biased to 俾 such that it is almost not turned on as the charging node & Since this switching operation will already be quite slow (ie, it is controlled by one of the clock signals with a low voltage swing), it is used to avoid the introduction of 9 200841347 additional resistance. The output load proposed by the output driver inverters INV1 and IN V2 is further reduced since node a only needs to drive a single input to inverter INV1 without direct external output. Inverters INV1 and INV2 thus also provide isolation from output out and out*, while supply circuit 3 has further isolation from the impedance that it will be proposed by the external circuit.
反相器INV1與INV2係可包含快速丨〇伏特擺幅的閘， 其依據功率消耗之觀點而相較於由低電壓擺幅時脈訊號所 驅動的内部移位暫存器20電路之其餘者為較少關係。此 種配置係#由僅具有單一連接而亦降低於節點&之電容負 載0The inverters INV1 and INV2 may comprise gates of fast volts swing, which are based on power consumption compared to the rest of the internal shift register 20 circuit driven by the low voltage swing clock signal For less relationship. This configuration is caused by a single connection and also reduced to the capacitance of the node &
第3圖之電路3G係@此允許節點^僅為由—低電壓 擺幅時脈訊號ck所驅動而擺動自VDD至vss (擺動自〇_3 伏特之-較低許多的電壓範圍），而且使得電阻負載與電容 負載為最小。f 3圖之電路3G係因此提供其優於第i圖 之電路10及/或第2圖之電路2〇的優點，理由如後： 1 ·藉由結合小的！**盘DC*於 版 v、P輸入僅有一個電晶體（MN1) 係運用以提供預充電或重設節點a。 2.藉由在其施加至該級電路前而結合輸入，與e*， 僅有另一個電晶體（Mp 1)得雲| ^ )係而要以驅動郎點a。此種配置係 牛低其提供自時脈輪入$銘魁； ^ 叛入至即點a之電阻，因此電阻相乘電 各（RC)延遲係亦為降低。 out與 。：提離輸出訊號 10 200841347 第5A與5B圖係說明多個第3圖之個別級3〇為可如 何、、且δ以提供一種管線式的移位暫存器$ 〇。在此，至少三 個個別的級30係需要以饋送一邏輯位元1為自輸入至輸 出此串聯連接（管線式）的級30-1、30-2、與30-3係各者 ’:有反相的輪出訊?虎。*，其饋入下個接續的反相輪入訊號 =。一對的偏移時脈訊號ck〇與ckl係饋入個別級。一給 疋級30·3之輸出係饋入初始級之重設輸入。&電路係因此 提供循環移位暫存器之—種型式，其中，-位it值係可移 位自輸入至輸出。 …弟5B圖之時序圖係說明的是：舉例而言，於預充電y 訊號之上升緣，所有的狀態(〇〇、〇1、〇2、〇3、等等)俜重 丫零邏輯狀態。…下—個上升緣，輸= G 1)係將切換至-㊉邏輯值狀態。於時脈訊號山 :下一個上升緣，類似的變化係發生於第二級30_2的 輸出)之狀態。於時脈訊號ck〇之下一個上升緣，輸出。2 糸亦將接者達到一高電壓狀態。自第三級糾的輸出 =到^級3CM之反饋連接係將接著致使第—級則的 輸出狀態〇0為返回至一低邏輯值。 _視該移位暫存器之期望長度而定，自-級30-4 (未顯 示）的輸出〇3之反館却辨在乂 、 反饋°凡唬係類似控制於-串之該等諸級的 第一級30-2、等等。 第6圖係高階圖，說明諸如第5A圖所示之一種管線 工移位暫存态為可如何配一 存器6〇。諸如管線…之—者#配^㈣向式移位暫 者係配置以移位為自左至右， 200841347 連接至各個輸出位 係允許選擇所運用之 且一第二管線50-2係移位為自右至左 兀之多工器51-1、…、5!^、51_n 方向。Circuit 3G of Figure 3 allows the node to swing from VDD to vss (swings from 〇3 volts - a much lower voltage range) driven by the low voltage swing clock signal ck, and This minimizes resistive and capacitive loads. The circuit 3G of the f 3 diagram thus provides advantages over the circuit 10 of the i-th diagram and/or the circuit 2 of the second diagram for the following reasons: 1 · By combining small! **Disc DC* in version v, P input only one transistor (MN1) is used to provide pre-charging or reset node a. 2. By combining the input before it is applied to the stage circuit, and e*, there is only another transistor (Mp 1) to get the cloud | ^) to drive the point a. This configuration is low because it provides the clock from the clock to the wheel; ^ betrayed to the point a, so the resistance phase multiplied (RC) delay system is also reduced. Out with . : Lifting off the output signal 10 200841347 Figures 5A and 5B illustrate how the individual stages 3 of the plurality of figures 3 can be, and δ to provide a pipelined shift register $ 〇. Here, at least three individual stages 30 are required to feed a logic bit 1 from the input to the output of the series connection (inline) stages 30-1, 30-2, and 30-3 each: There is a reverse round of the news? Tiger. *, which feeds the next reversed round-in signal =. A pair of offset clock signals ck〇 and ckl are fed into individual stages. The output of the 30 stage 30·3 is fed into the reset input of the initial stage. The & circuit thus provides a type of cyclic shift register in which the -bit value is shiftable from input to output. The timing diagram of the 5B diagram shows that, for example, in the rising edge of the pre-charged y signal, all states (〇〇, 〇 1, 〇 2, 〇 3, etc.) 俜 zero logic state . ...lower - rising edge, lose = G 1) will switch to the -10 logic value state. In the clock signal mountain: the next rising edge, a similar change occurs in the state of the output of the second stage 30_2). At the rising edge of the clock signal ck〇, the output. 2 糸 also reaches the receiver to a high voltage state. The output from the third stage of correction = to the level 3CM feedback connection will then cause the output stage 第0 of the first stage to return to a low logic value. _Depending on the expected length of the shift register, the output of the self-level 30-4 (not shown) 〇3 is identified in the 馆, feedback ° 唬 类似 类似 类似 类似 类似 类似 类似 类似 类似The first level of the level 30-2, and so on. Figure 6 is a high-order diagram showing how a pipeline shifting temporary state, such as shown in Figure 5A, can be configured with a buffer. For example, the pipeline...the #配^(4) directional shifting system is configured to shift from left to right, and 200841347 is connected to each output bit system to allow selection of a second pipeline 50-2 to be shifted. It is the direction of the multiplexers 51-1, ..., 5!^, 51_n from right to left.
根據本發明之移位暫存器係可運用於諸多不同應用。 作為僅為-個實例，描述於西元2〇〇7年…曰所提出 之共同中請中的美國專财請案第1 1/784,215號（以參照 式内入於本文）之型式的顯示器係包括一陣列之畫素 (P1Xel)7〇件。如為習知於此技藝，彼等晝素元件係由列選 擇線與行㈣線所㈣。此㈣料料料自其為實施 如本文所述之個別的移位暫存器5{>。該種型式之顯示器係 可相繼為運用於數位相機、數位單鏡頭（SLR，Single Lens )相冑冑視型顯不器、手持式視訊遊戲機、行動電 話、㈣眼戴式（eyew叫裝置、與其他的類似產品。 > I g本發明係已㈣定顯示及描述為關於其實施例， 熟悉此技藝之人士係將瞭解的是：^形式與細節之種種的 變化係可作成於其而未脫離由隨附申請專利範圍所涵蓋之 本發明的範轉。 【圖式簡單說明】 前文係由如伴隨圖式所+ 式所不之本發明實施例的上述較為 特定說明而顯明，其中，如円Μ A & T 相同的茶考符號係指於不同視圖 之中的相同部分。圖式係1强& ^， 恭無々為依比例所繪製，而是強調 在於說明本發明之實施例。 第1圖係說明其順庫供恭网 、應低毛壓擺幅時脈訊號輸入之一種 先前技藝的移位暫存器級。 12 200841347 弟2圖係說明另一種先前技藝的移位暫存器級。 第3圖係說明本發明之一個實施例。 弟4 A與4B圖係更為詳細說明時脈訊號。 弟5 A與5B圖係顯示第3圖之多級為如 一個時序圖。 4合且顯示 弟6圖種雙向移位暫存器的高 【主要元件符號說明】 ° • 10 第1圖之電路 20 第2圖之電路 3〇 第3圖之電路 3〇-1、30-2、3(M 級 50第5A圖之移位暫存器 5(M、50-2 管線 51-1 、…、51-n»l 、 51-n 多工器 60第6圖之移位暫存器 鲁 a 節點 ck ' ckO ' ckl 時脈輸入 e*自前級的互補輸出 in 訊號輸入 〇 ' 〆、〇〇、〇1、〇2、〇3 輸出 out、out* 輸出 pc、pc* 預充電訊號 r、r* 重設訊號 INV1、INV2、INV3 反相器 13 200841347The shift register according to the present invention can be used in many different applications. As an example only, it is described in the type of display system of the United States, which is proposed in the United States in the 2nd and 7th year of the United States. Includes an array of Pixel (P1Xel) 7 pieces. As is known in the art, these elemental elements are selected by column (4) and (4). This (four) feed material is from which it is implemented as an individual shift register 5{> as described herein. This type of display can be used for digital cameras, digital single-lens (SLR, Single Lens), visual display consoles, mobile video games, mobile phones, (4) eye-worn devices. And other similar products. The present invention has been shown and described with respect to its embodiments, and those skilled in the art will understand that various changes in form and detail can be made therein. The present invention is not limited by the above-described specific description of the embodiments of the present invention, which is accompanied by the accompanying drawings, wherein The same tea test symbol as 円Μ A & T refers to the same part in different views. The schema is 1 strong & ^, is not drawn to scale, but is emphasized to illustrate the implementation of the present invention The first figure shows a prior art shift register stage for the input of the pulse signal input of the low-pressure swing. 12 200841347 The second picture shows the shift of another prior art. Register level. 3rd The figure illustrates one embodiment of the present invention. The brothers 4 A and 4B are more detailed in explaining the clock signal. The brothers 5 A and 5B are shown in Fig. 3 as a sequence diagram. 6 Figure 2 High-level shift register high [Main component symbol description] ° • 10 Circuit 1 of Figure 1 Circuit 2 of Figure 2〇 Circuit of Figure 3 3〇-1, 30-2, 3 (M Stage 50 5A shift register 5 (M, 50-2 pipeline 51-1, ..., 51-n»l, 51-n multiplexer 60 Figure 6 shift register Lu a node Ck ' ckO ' ckl clock input e* complementary output from the previous stage in signal input 〇 ' 〆, 〇〇, 〇 1, 〇 2, 〇 3 output out, out* output pc, pc* pre-charge signal r, r* Reset signal INV1, INV2, INV3 inverter 13 200841347
MN1-MN4 電晶體 MP1、MP2、MP3 電晶體 Vgp 偏壓電壓 Vth 臨限電壓 VDD、VSS 執線電壓 VEE 時脈電壓 14MN1-MN4 transistor MP1, MP2, MP3 transistor Vgp bias voltage Vth threshold voltage VDD, VSS line voltage VEE clock voltage 14