WO2016127464A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2016127464A1
WO2016127464A1 PCT/CN2015/073925 CN2015073925W WO2016127464A1 WO 2016127464 A1 WO2016127464 A1 WO 2016127464A1 CN 2015073925 W CN2015073925 W CN 2015073925W WO 2016127464 A1 WO2016127464 A1 WO 2016127464A1
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Prior art keywords
line
metal
layer
holes
disposed
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Ceased
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PCT/CN2015/073925
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English (en)
French (fr)
Inventor
付延峰
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to GB1712779.6A priority Critical patent/GB2550762B/en
Priority to EA201791625A priority patent/EA032903B1/ru
Priority to KR1020177025517A priority patent/KR101907079B1/ko
Priority to JP2017541845A priority patent/JP6539743B2/ja
Priority to US14/766,757 priority patent/US9618810B2/en
Publication of WO2016127464A1 publication Critical patent/WO2016127464A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • TFT Thin Film In the case of a side peripheral sector line of a Transistor (thin film transistor)
  • a double metal design is adopted for reducing the impedance, that is, the first metal line is connected in parallel with the second metal line to reduce the impedance, and the first metal line is located in the first metal layer in the non-display area.
  • the second metal line is located on the second metal layer in the non-display area, thereby reducing the degree of influence of the signal due to the delay distortion of the resistor and capacitor.
  • this double metal design when one layer of metal breaks, but because the other layer of metal does not break, this line is not completely broken.
  • the problem cannot be detected, and when the LED is leaked to the Mod display, a lower voltage can be input, and the impedance difference exhibits a light line phenomenon at a low gray level and a low voltage. Affects the display quality of the product.
  • An object of the present invention is to provide an array substrate and a liquid crystal display panel, which can effectively improve the vertical and horizontal light lines of the drain module.
  • An array substrate wherein the array substrate comprises:
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position.
  • the metal line is connected to the second metal line of the corresponding second through hole through the conductive line; the first through hole penetrates the second insulating layer and the second metal in the non-display area
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position. a second through hole for exposing the first metal line; the second through hole for exposing the second metal line; the first one of the first through holes The metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first through hole penetrates through the second insulating layer, the second metal layer, and the first insulating layer in the non-display area; the second through hole runs through On the second insulating layer in the non-display area.
  • the first through holes correspond to the two second through holes, and the second through holes are disposed on both sides of the first through holes.
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes through the The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • a liquid crystal display panel comprising an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate;
  • the array substrate includes:
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position. a second through hole for exposing the first metal line; the second through hole for exposing the second metal line; the first one of the first through holes The metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first via holes are sequentially disposed on the second insulating layer, the second metal layer, and the first insulating layer in the non-display region; the second via hole Provided on the second insulating layer in the non-display area.
  • the first through holes correspond to the two second through holes, and the second through holes are disposed on both sides of the first through holes.
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the array substrate and the liquid crystal display panel provided by the present invention are provided with a plurality of first through holes and a plurality of second through holes at a position of a connecting line of the non-display area, wherein the first through holes are used for bare a first metal line is disposed such that a conductive line in the pixel electrode layer is electrically connected to the first metal line; and the second through hole is used to expose the second metal line so that the pixel electrode layer is The conductive line is electrically connected to the second metal line; the first metal line and the second metal line are electrically connected through the conductive line.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.
  • FIG. 1 is a schematic structural diagram of an array substrate in a non-display area according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention.
  • the display panel of the present invention may be, for example, a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel), AMOLED (Active Matrix Organic Light Emitting) Diode, active matrix OLED panel) and other display panels.
  • TFT-LCD Thin Film Transistor Liquid
  • AMOLED Active Matrix Organic Light Emitting Diode
  • active matrix OLED panel active matrix OLED panel
  • a plurality of first via holes and a plurality of second via holes are disposed on the non-display area, wherein the first through holes are used to expose the first metal lines to guide the pixel electrode layers
  • the through line is electrically connected to the first metal line;
  • the second through hole is used to expose the second metal line, so that the conductive line in the pixel electrode layer is electrically connected to the second metal line
  • the first metal line and the second metal line are electrically connected through the conductive line.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal layer 101 is deposited on the surface of the substrate 100, and then the pattern of the first metal layer 101 is formed by using a yellow light and an etching process, wherein the pattern of the first metal layer 101 includes the display region. a gate and a scan line of the thin film transistor, and a first metal line in the non-display area.
  • the first metal wire includes a plurality of strips.
  • the second metal layer 103 is sputter deposited, and then the pattern of the second metal layer 103 is formed by using a yellow light and an etching process, wherein the pattern of the second metal layer 103 includes the display region.
  • the second metal wire includes a plurality of strips, and the first metal wire has a one-to-one correspondence with the number of the second metal wires.
  • the pattern of the pixel electrode layer 105 is formed by using a yellow light and an etching process, wherein the pattern of the pixel electrode layer 105 includes the display region.
  • a pixel electrode and a conductive line in the non-display area the conductive line includes a plurality of strips, and the number of the first metal lines, the second metal lines, and the conductive lines are in one-to-one correspondence.
  • the first metal line, the second metal line, and the conductive line are overlapped together as a connection line, wherein the plurality of connection lines are electrically connected to the corresponding scan lines and data respectively. line.
  • the first through holes 106 for exposing the first metal lines to make the pixels a conductive line in the electrode layer is electrically connected to the first metal line; the second through hole 107 is used to expose the second metal line, so that the conductive line in the pixel electrode layer
  • the second metal line is electrically connected; the first metal line in the first through hole and the second metal line in the corresponding second through hole are connected through the conductive line.
  • the pixel electrode layer 105 is made of ITO (Indium Tin). Oxide, tin-doped indium oxide) or indium zinc oxide IZO or the like; the first insulating layer 102 may be made of G-Sinx material; the second insulating layer 104 may be made of P-Sinx material .
  • ITO Indium Tin
  • the first insulating layer 102 may be made of G-Sinx material
  • the second insulating layer 104 may be made of P-Sinx material .
  • etching that is, the second insulating layer 104, the second metal layer 103, and the first insulating layer in the non-display region are sequentially performed.
  • a first via hole 106 is disposed on the layer 102, the first via hole penetrating the second insulating layer 104, the second metal layer 103, and the first insulating layer 102 in the non-display region to expose the first through hole a metal line such that a conductive line in the pixel electrode layer is electrically connected to the first metal line.
  • the second via hole 107 is disposed on the second insulating layer 104 in the non-display region. And exposing the second metal line to electrically connect the conductive line in the pixel electrode layer to the second metal line.
  • the step of etching the via of the second via hole may be performed after the first via hole is completed. That is, via etching is performed on the second insulating layer 104 in the non-display region to obtain a second via hole, thereby exposing the second metal line so that the conductive line in the pixel electrode layer The second metal wire is electrically connected.
  • a pixel electrode layer 105 is then sputter deposited to form a pixel electrode and a non-display area in the display region.
  • the conduction line in the middle.
  • a conduction line in the pixel electrode layer is electrically connected to the first metal line, and a guide in the pixel electrode layer
  • the through line is electrically connected to the second metal line.
  • the first through holes 106 correspond to the two second through holes 107, and the second through holes 107 are disposed on both sides of the first through holes 106.
  • the number of the first through holes and the second through holes can be set according to actual needs.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the first through hole is spaced apart from the second through hole, and the separation distance can be set according to actual needs.
  • the array substrate further includes a scan driving chip 110 and a data driving chip 109.
  • the scan driving chip 110 is electrically connected to the scan line through the connecting line 108.
  • the data driving chip 109 is electrically connected to the data line through the connection line 108.
  • a plurality of first through holes and a plurality of second through holes are disposed at the position of the connection line of the non-display area, the first through holes for exposing the first metal lines to enable the pixel electrodes a conductive line in the layer is electrically connected to the first metal line; the second through hole is used to expose the second metal line, so that the conductive line in the pixel electrode layer and the second metal The wire is electrically connected; the first metal wire and the second metal wire are electrically connected through the conductive wire.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.
  • an embodiment of the present invention further provides a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal line, the second metal line and the conductive line are overlapped together as a connecting line, and a plurality of first through holes 106 are disposed at the connecting line position.
  • a corresponding plurality of second via holes 107 for exposing the first metal lines to electrically connect the conduction lines in the pixel electrode layer and the first metal lines a second via 107 for exposing the second metal line to electrically connect the conductive line in the pixel electrode layer to the second metal line;
  • the first metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first through holes 106 are sequentially disposed on the second insulating layer, the second metal layer, and the first insulating layer in the non-display area; the second through holes 107 are disposed in On the second insulating layer in the non-display area.
  • the first through holes 106 correspond to the two second through holes 107, and the second through holes 107 are disposed on both sides of the first through holes 106.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the first through hole 106 is spaced apart from the second through hole 107, and the separation distance can be set according to actual needs.
  • the array substrate further includes a scan driving chip 110 and a data driving chip 109.
  • the scan driving chip 110 is electrically connected to the scan line through the connecting line 108, and the data driving chip 109
  • the data line is electrically connected through the connection line 108.
  • the number of the first through holes and the second through holes is set according to actual needs.
  • the array substrate and the liquid crystal display panel provided by the embodiments of the present invention provide a plurality of first through holes and a plurality of second through holes at the position of the connecting line of the non-display area, and the first through holes are used for the first through holes.
  • the conductive line in the layer is electrically connected to the second metal line; the first metal line and the second metal line are electrically connected through the conductive line.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Geometry (AREA)

Abstract

一种阵列基板包括基板（100），以及依次设置于基板（100）表面上的第一金属层（101）、第一绝缘层（102）、第二金属层（103）、第二绝缘层（104）以及像素电极层（105）；在连接线位置处设置有多个第一通孔（106）和多个第二通孔（107），以裸露出第一金属线和第二金属线，第一金属线与第二金属线通过像素电极层（105）中的导通线电性连接。该基板有效改善漏放模组垂直和水平淡线问题。

Description

一种阵列基板及液晶显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及液晶显示面板。
 背景技术
在现有技术中，在设计TFT（Thin Film Transistor，薄膜晶体管）侧外围扇形线路时，为降低阻抗采用双重金属设计，即将第一金属线与第二金属线并联以降低阻抗，所述第一金属线位于非显示区域中的第一金属层上，所述第二金属线位于非显示区域中的第二金属层上，因此可降低信号因电阻电容延迟失真的影响程度。
然而，采用双重金属设计由此带来一个问题：当第一金属线发生断裂时，那么通过未断裂的第二金属线来进行导通，然而这样导致该线路的阻抗会变大，因此，在模组点灯时易出现垂直淡线或水平淡线，从而降低了TFT LCD（Thin Film Transistor Liquid Crystal Display，超薄膜晶体管液晶显示器）产品的显示品质。
综上所述，这种双重金属设计，在其中一层金属发生断裂时，但由于另一层金属并没有断裂，因此这一条线路并未完全断裂。然而，在Array阵列基板和Cell液晶盒的测试中是无法检测出问题，漏放至Mod显示时可输入较低电压，这种阻抗差异在低灰阶低电压下则会呈现淡线的现象，影响了产品的显示品质。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种阵列基板及液晶显示面板，其能有效改善漏放模组垂直和水平淡线的问题。
 技术解决方案
一种阵列基板，其中所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接；所述第一通孔贯穿在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔贯穿在非显示区域中的所述第二绝缘层上；所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
优选的，在所述阵列基板中，其中所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
优选的，在所述阵列基板中，其中在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
一种阵列基板，所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
优选的，在所述阵列基板中，所述第一通孔贯穿在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔贯穿在非显示区域中的所述第二绝缘层上。
优选的，在所述阵列基板中，所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
优选的，在所述阵列基板中，所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
优选的，在所述阵列基板中，在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；
所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
优选的，在所述液晶显示面板中，所述第一通孔依次设置在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔设置在非显示区域中的所述第二绝缘层上。
优选的，在所述液晶显示面板中，所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
优选的，在所述液晶显示面板中，所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
优选的，在所述液晶显示面板中，在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
 有益效果
相对现有技术，本发明提供的阵列基板和液晶显示面板，由于在非显示区域的连接线位置处设置多个第一通孔和多个第二通孔，所述第一通孔用于裸露出第一金属线，以使像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔用于裸露出第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一金属线与所述第二金属线通过所述导通线电性连接。这种设计带来的好处是：在同一线路上增加了多个连接点以使第一金属线与第二金属线导通。因此，当非显示区域上的其中一层金属发生断裂时，仅仅影响其中一小段线路不能导通，而不会导致整条断裂层金属线无法导通，因此，有效改善漏放模组垂直和水平淡线的问题。
 附图说明
图1为本发明实施例提供的非显示区域中的阵列基板的结构示意图；
图2为本发明实施例提供的液晶显示面板的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
本发明的显示面板可以是诸如TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、AMOLED（Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管面板）等显示面板。
在本发明实施例中，在非显示区域上设置多个第一通孔和多个第二通孔，所述第一通孔用于裸露出第一金属线，以使像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔用于裸露出第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一金属线与所述第二金属线通过所述导通线电性连接。这种设计带来的好处是：在同一线路上增加了多个连接点以使第一金属线与第二金属线导通。因此，当非显示区域上的其中一层金属发生断裂时，仅仅影响其中一小段线路不能导通，而不会导致整条断裂层金属线无法导通，因此，有效改善漏放模组垂直和水平淡线的问题。
为了说明本发明所述的技术方案，下面通过具体实施例来进行说明。
请参阅图1，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括：一基板100，一第一金属层101、一第一绝缘层102、一第二金属层103、一第二绝缘层104、以及一像素电极层105。其中，所述第一金属层101设置于所述基板100表面上；所述第一绝缘层102设置于所述第一金属层101上；所述第二金属层103设置于所述第一绝缘层102上；所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104设置于所述第二金属层103上；所述像素电极层105设置于所述第二绝缘层104上；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
在本发明实施例中，在基板100表面上沉积第一金属层101，并接着利用黄光及蚀刻工艺形成第一金属层101的图样，其中该第一金属层101的图样包括显示区域中的薄膜晶体管的栅极和扫描线、以及非显示区域中的第一金属线。然而，可以理解的是，所述第一金属线包括多条。
在本发明实施例中，溅射沉积第二金属层103后，并接着利用黄光及蚀刻工艺形成第二金属层103的图样，其中，所述第二金属层103的图样包括显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极以及数据线、和非显示区域中的第二金属线。然而，可以理解的是，所述第二金属线包括多条，第一金属线与第二金属线的条数一一对应。
在本发明实施例中，溅射沉积一像素电极层105后，并接着利用黄光及蚀刻工艺形成所述像素电极层105的图样，其中，所述像素电极层105的图样包括显示区域中的像素电极和非显示区域中的导通线。然而，可以理解的是，所述导通线包括多条，所述第一金属线、所述第二金属线以及所述导通线的条数一一对应。
在本发明实施例中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，其中，多条连接线分别电性连接对应的扫描线和数据线。在所述连接线位置处设置有多个第一通孔106和相应的多个第二通孔107，所述第一通孔106用于裸露出所述第一金属线，以使所述像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔107用于裸露出所述第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
在本发明实施例中，所述像素电极层105采用ITO（Indium Tin Oxide，掺锡氧化铟）或铟锌氧化物IZO等等材料制成；所述第一绝缘层102可采用G-Sinx材料制成；所述第二绝缘层104可采用P-Sinx材料制成。然而，可以理解的是，并不限于上述材料，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
在本发明实施例中，在形成所述第二绝缘层104之后，然后进行过孔蚀刻，即依次在非显示区域中的所述第二绝缘层104、第二金属层103、以及第一绝缘层102上均设置第一通孔106，该第一通孔贯穿非显示区域中的所述第二绝缘层104、第二金属层103、以及第一绝缘层102，以裸露出所述第一金属线，以使所述像素电极层中的导通线与所述第一金属线电性连接。
然而，可以理解的是，在形成所述第二绝缘层104之后，在设置第一通孔的同一道工序中，在非显示区域中的所述第二绝缘层104上设置第二通孔107，以裸露出所述第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接。
然而，可以理解的是，可以在完成了第一通孔后，再进行第二通孔的过孔蚀刻的工序。即在非显示区域中的所述第二绝缘层104上进行过孔蚀刻，得到第二通孔，从而裸露出所述第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接。
在本发明实施例中，在设置完所述第一通孔106和所述第二通孔107后，然后在溅射沉积一像素电极层105，以形成显示区域中的像素电极和非显示区域中的导通线。此时，由于具有所述第一通孔和所述第二通孔，因此，所述像素电极层中的导通线与所述第一金属线电性连接，所述像素电极层中的导通线与所述第二金属线电性连接。
作为本发明一优选实施例，所述第一通孔106对应二个所述第二通孔107，其中，所述第二通孔107设置于所述第一通孔106两侧。然而，可以理解的是，所述第一通孔和所述第二通孔的个数可根据实际需求进行设置。在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。所述第一通孔与所述第二通孔间隔设置，间隔距离可根据实际需求进行设置。
在本发明实施例中，请参阅图2，所述阵列基板还包括扫描驱动芯片110和数据驱动芯片109，所述扫描驱动芯片110通过所述连接线108与所述扫描线电性连接，所述数据驱动芯片109通过所述连接线108与所述数据线电性连接。
由上可知，本实施例在非显示区域的连接线位置处设置多个第一通孔和多个第二通孔，所述第一通孔用于裸露出第一金属线，以使像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔用于裸露出第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一金属线与所述第二金属线通过所述导通线电性连接。这种设计带来的好处是：在同一线路上增加了多个连接点以使第一金属线与第二金属线导通。因此，当非显示区域上的其中一层金属发生断裂时，仅仅影响其中一小段线路不能导通，而不会导致整条断裂层金属线无法导通，因此，有效改善漏放模组垂直和水平淡线的问题。
请一并参阅图1和图2，本发明实施例还提供了一种液晶显示面板。为了便于说明，仅示出了与本发明实施例相关的部分。所述液晶显示面板包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒。
所述阵列基板包括：一基板100，一第一金属层101、一第一绝缘层102、一第二金属层103、一第二绝缘层104、以及一像素电极层105。其中，所述第一金属层101设置于所述基板100表面上；所述第一绝缘层102设置于所述第一金属层101上；所述第二金属层103设置于所述第一绝缘层102上；所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104设置于所述第二金属层103上；所述像素电极层105设置于所述第二绝缘层104上；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
在本发明实施例中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔106和相应的多个第二通孔107，所述第一通孔106用于裸露出所述第一金属线，以使所述像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔107用于裸露出所述第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
在本发明实施例中，所述第一通孔106依次设置在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔107设置在非显示区域中的所述第二绝缘层上。
作为本发明一优选实施例，所述第一通孔106对应二个所述第二通孔107，其中，所述第二通孔107设置于所述第一通孔106两侧。在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。所述第一通孔106与所述第二通孔107间隔设置，间隔距离可根据实际需求进行设置。
在本发明实施例中，所述阵列基板还包括扫描驱动芯片110和数据驱动芯片109，所述扫描驱动芯片110通过所述连接线108与所述扫描线电性连接，所述数据驱动芯片109通过所述连接线108与所述数据线电性连接。
然而，可以理解的是，所述第一通孔和所述第二通孔的个数根据实际需求进行设置。
综上所述，本发明实施例提供的阵列基板和液晶显示面板，由于在非显示区域的连接线位置处设置多个第一通孔和多个第二通孔，所述第一通孔用于裸露出第一金属线，以使像素电极层中的导通线与所述第一金属线电性连接；所述第二通孔用于裸露出第二金属线，以使所述像素电极层中的导通线与所述第二金属线电性连接；所述第一金属线与所述第二金属线通过所述导通线电性连接。这种设计带来的好处是：在同一线路上增加了多个连接点以使第一金属线与第二金属线导通。因此，当非显示区域上的其中一层金属发生断裂时，仅仅影响其中一小段线路不能导通，而不会导致整条断裂层金属线无法导通，因此，有效改善漏放模组垂直和水平淡线的问题。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种阵列基板，其中所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
    其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接；所述第一通孔贯穿在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔贯穿在非显示区域中的所述第二绝缘层上；所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
  2. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
  3. 根据权利要求1所述的阵列基板，其中在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
  4. 一种阵列基板，其中所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
    其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
  5. 根据权利要求4所述的阵列基板，其中所述第一通孔贯穿在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔贯穿在非显示区域中的所述第二绝缘层上。
  6. 根据权利要求4所述的阵列基板，其中所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
  7. 根据权利要求4所述的阵列基板，其中所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
  8. 根据权利要求4所述的阵列基板，其中在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
  9. 一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；其中
    所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层形成有显示区域中的薄膜晶体管的栅极、扫描线以及非显示区域中的第一金属线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层形成有显示区域中的薄膜晶体管的源极、薄膜晶体管的漏极、数据线以及非显示区域中的第二金属线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括显示区域中的像素电极和非显示区域中的导通线；
    其中，所述第一金属线、所述第二金属线和所述导通线均重叠在一起作为连接线，在所述连接线位置处设置有多个第一通孔和相应的多个第二通孔，所述第一通孔用于裸露出所述第一金属线；所述第二通孔用于裸露出所述第二金属线；所述第一通孔中的所述第一金属线与相应的所述第二通孔中的所述第二金属线通过所述导通线连接。
  10. 根据权利要求9所述的液晶显示面板，其中所述第一通孔贯穿在非显示区域中的所述第二绝缘层、第二金属层、以及第一绝缘层上；所述第二通孔贯穿在非显示区域中的所述第二绝缘层上。
  11. 根据权利要求9所述的液晶显示面板，其中所述第一通孔对应二个所述第二通孔，其中，所述第二通孔设置于所述第一通孔两侧。
  12. 根据权利要求9所述的液晶显示面板，其中所述阵列基板还包括扫描驱动芯片和数据驱动芯片，所述扫描驱动芯片通过所述连接线与所述扫描线电性连接，所述数据驱动芯片通过所述连接线与所述数据线电性连接。
  13. 根据权利要求9所述的液晶显示面板，其中在所述连接线上均匀设置有多个所述第一通孔和相应的所述第二通孔。
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CN102819995A (zh) * 2011-06-10 2012-12-12 乐金显示有限公司 平板显示装置及其制造方法
CN203275842U (zh) * 2013-06-09 2013-11-06 合肥京东方光电科技有限公司 一种阵列基板及显示装置

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