WO2016127464A1 - Substrat de réseau et panneau d'affichage à cristaux liquides - Google Patents

Substrat de réseau et panneau d'affichage à cristaux liquides Download PDF

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Publication number
WO2016127464A1
WO2016127464A1 PCT/CN2015/073925 CN2015073925W WO2016127464A1 WO 2016127464 A1 WO2016127464 A1 WO 2016127464A1 CN 2015073925 W CN2015073925 W CN 2015073925W WO 2016127464 A1 WO2016127464 A1 WO 2016127464A1
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Prior art keywords
line
metal
layer
holes
disposed
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PCT/CN2015/073925
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English (en)
Chinese (zh)
Inventor
付延峰
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深圳市华星光电技术有限公司
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Priority to GB1712779.6A priority Critical patent/GB2550762B/en
Priority to KR1020177025517A priority patent/KR101907079B1/ko
Priority to US14/766,757 priority patent/US9618810B2/en
Priority to JP2017541845A priority patent/JP6539743B2/ja
Priority to EA201791625A priority patent/EA032903B1/ru
Publication of WO2016127464A1 publication Critical patent/WO2016127464A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • TFT Thin Film In the case of a side peripheral sector line of a Transistor (thin film transistor)
  • a double metal design is adopted for reducing the impedance, that is, the first metal line is connected in parallel with the second metal line to reduce the impedance, and the first metal line is located in the first metal layer in the non-display area.
  • the second metal line is located on the second metal layer in the non-display area, thereby reducing the degree of influence of the signal due to the delay distortion of the resistor and capacitor.
  • this double metal design when one layer of metal breaks, but because the other layer of metal does not break, this line is not completely broken.
  • the problem cannot be detected, and when the LED is leaked to the Mod display, a lower voltage can be input, and the impedance difference exhibits a light line phenomenon at a low gray level and a low voltage. Affects the display quality of the product.
  • An object of the present invention is to provide an array substrate and a liquid crystal display panel, which can effectively improve the vertical and horizontal light lines of the drain module.
  • An array substrate wherein the array substrate comprises:
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position.
  • the metal line is connected to the second metal line of the corresponding second through hole through the conductive line; the first through hole penetrates the second insulating layer and the second metal in the non-display area
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position. a second through hole for exposing the first metal line; the second through hole for exposing the second metal line; the first one of the first through holes The metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first through hole penetrates through the second insulating layer, the second metal layer, and the first insulating layer in the non-display area; the second through hole runs through On the second insulating layer in the non-display area.
  • the first through holes correspond to the two second through holes, and the second through holes are disposed on both sides of the first through holes.
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes through the The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • a liquid crystal display panel comprising an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate;
  • the array substrate includes:
  • first metal layer disposed on the surface of the substrate; the first metal layer being formed with a gate of the thin film transistor in the display region, a scan line, and a first metal line in the non-display area ;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer; the second metal layer is formed with a source of the thin film transistor in the display region, a drain of the thin film transistor, and a data line And a second metal line in the non-display area;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode in the display region and a conductive line in the non-display region;
  • the first metal line, the second metal line, and the conductive line are all overlapped together as a connecting line, and a plurality of first through holes and corresponding plurality of first holes are disposed at the connecting line position. a second through hole for exposing the first metal line; the second through hole for exposing the second metal line; the first one of the first through holes The metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first via holes are sequentially disposed on the second insulating layer, the second metal layer, and the first insulating layer in the non-display region; the second via hole Provided on the second insulating layer in the non-display area.
  • the first through holes correspond to the two second through holes, and the second through holes are disposed on both sides of the first through holes.
  • the array substrate further includes a scan driving chip and a data driving chip, wherein the scan driving chip is electrically connected to the scan line through the connecting line, and the data driving chip passes The connecting line is electrically connected to the data line.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the array substrate and the liquid crystal display panel provided by the present invention are provided with a plurality of first through holes and a plurality of second through holes at a position of a connecting line of the non-display area, wherein the first through holes are used for bare a first metal line is disposed such that a conductive line in the pixel electrode layer is electrically connected to the first metal line; and the second through hole is used to expose the second metal line so that the pixel electrode layer is The conductive line is electrically connected to the second metal line; the first metal line and the second metal line are electrically connected through the conductive line.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.
  • FIG. 1 is a schematic structural diagram of an array substrate in a non-display area according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention.
  • the display panel of the present invention may be, for example, a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel), AMOLED (Active Matrix Organic Light Emitting) Diode, active matrix OLED panel) and other display panels.
  • TFT-LCD Thin Film Transistor Liquid
  • AMOLED Active Matrix Organic Light Emitting Diode
  • active matrix OLED panel active matrix OLED panel
  • a plurality of first via holes and a plurality of second via holes are disposed on the non-display area, wherein the first through holes are used to expose the first metal lines to guide the pixel electrode layers
  • the through line is electrically connected to the first metal line;
  • the second through hole is used to expose the second metal line, so that the conductive line in the pixel electrode layer is electrically connected to the second metal line
  • the first metal line and the second metal line are electrically connected through the conductive line.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal layer 101 is deposited on the surface of the substrate 100, and then the pattern of the first metal layer 101 is formed by using a yellow light and an etching process, wherein the pattern of the first metal layer 101 includes the display region. a gate and a scan line of the thin film transistor, and a first metal line in the non-display area.
  • the first metal wire includes a plurality of strips.
  • the second metal layer 103 is sputter deposited, and then the pattern of the second metal layer 103 is formed by using a yellow light and an etching process, wherein the pattern of the second metal layer 103 includes the display region.
  • the second metal wire includes a plurality of strips, and the first metal wire has a one-to-one correspondence with the number of the second metal wires.
  • the pattern of the pixel electrode layer 105 is formed by using a yellow light and an etching process, wherein the pattern of the pixel electrode layer 105 includes the display region.
  • a pixel electrode and a conductive line in the non-display area the conductive line includes a plurality of strips, and the number of the first metal lines, the second metal lines, and the conductive lines are in one-to-one correspondence.
  • the first metal line, the second metal line, and the conductive line are overlapped together as a connection line, wherein the plurality of connection lines are electrically connected to the corresponding scan lines and data respectively. line.
  • the first through holes 106 for exposing the first metal lines to make the pixels a conductive line in the electrode layer is electrically connected to the first metal line; the second through hole 107 is used to expose the second metal line, so that the conductive line in the pixel electrode layer
  • the second metal line is electrically connected; the first metal line in the first through hole and the second metal line in the corresponding second through hole are connected through the conductive line.
  • the pixel electrode layer 105 is made of ITO (Indium Tin). Oxide, tin-doped indium oxide) or indium zinc oxide IZO or the like; the first insulating layer 102 may be made of G-Sinx material; the second insulating layer 104 may be made of P-Sinx material .
  • ITO Indium Tin
  • the first insulating layer 102 may be made of G-Sinx material
  • the second insulating layer 104 may be made of P-Sinx material .
  • etching that is, the second insulating layer 104, the second metal layer 103, and the first insulating layer in the non-display region are sequentially performed.
  • a first via hole 106 is disposed on the layer 102, the first via hole penetrating the second insulating layer 104, the second metal layer 103, and the first insulating layer 102 in the non-display region to expose the first through hole a metal line such that a conductive line in the pixel electrode layer is electrically connected to the first metal line.
  • the second via hole 107 is disposed on the second insulating layer 104 in the non-display region. And exposing the second metal line to electrically connect the conductive line in the pixel electrode layer to the second metal line.
  • the step of etching the via of the second via hole may be performed after the first via hole is completed. That is, via etching is performed on the second insulating layer 104 in the non-display region to obtain a second via hole, thereby exposing the second metal line so that the conductive line in the pixel electrode layer The second metal wire is electrically connected.
  • a pixel electrode layer 105 is then sputter deposited to form a pixel electrode and a non-display area in the display region.
  • the conduction line in the middle.
  • a conduction line in the pixel electrode layer is electrically connected to the first metal line, and a guide in the pixel electrode layer
  • the through line is electrically connected to the second metal line.
  • the first through holes 106 correspond to the two second through holes 107, and the second through holes 107 are disposed on both sides of the first through holes 106.
  • the number of the first through holes and the second through holes can be set according to actual needs.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the first through hole is spaced apart from the second through hole, and the separation distance can be set according to actual needs.
  • the array substrate further includes a scan driving chip 110 and a data driving chip 109.
  • the scan driving chip 110 is electrically connected to the scan line through the connecting line 108.
  • the data driving chip 109 is electrically connected to the data line through the connection line 108.
  • a plurality of first through holes and a plurality of second through holes are disposed at the position of the connection line of the non-display area, the first through holes for exposing the first metal lines to enable the pixel electrodes a conductive line in the layer is electrically connected to the first metal line; the second through hole is used to expose the second metal line, so that the conductive line in the pixel electrode layer and the second metal The wire is electrically connected; the first metal wire and the second metal wire are electrically connected through the conductive wire.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.
  • an embodiment of the present invention further provides a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal line, the second metal line and the conductive line are overlapped together as a connecting line, and a plurality of first through holes 106 are disposed at the connecting line position.
  • a corresponding plurality of second via holes 107 for exposing the first metal lines to electrically connect the conduction lines in the pixel electrode layer and the first metal lines a second via 107 for exposing the second metal line to electrically connect the conductive line in the pixel electrode layer to the second metal line;
  • the first metal line is connected to the second metal line of the corresponding second through hole through the conductive line.
  • the first through holes 106 are sequentially disposed on the second insulating layer, the second metal layer, and the first insulating layer in the non-display area; the second through holes 107 are disposed in On the second insulating layer in the non-display area.
  • the first through holes 106 correspond to the two second through holes 107, and the second through holes 107 are disposed on both sides of the first through holes 106.
  • a plurality of the first through holes and the corresponding second through holes are uniformly disposed on the connecting line.
  • the first through hole 106 is spaced apart from the second through hole 107, and the separation distance can be set according to actual needs.
  • the array substrate further includes a scan driving chip 110 and a data driving chip 109.
  • the scan driving chip 110 is electrically connected to the scan line through the connecting line 108, and the data driving chip 109
  • the data line is electrically connected through the connection line 108.
  • the number of the first through holes and the second through holes is set according to actual needs.
  • the array substrate and the liquid crystal display panel provided by the embodiments of the present invention provide a plurality of first through holes and a plurality of second through holes at the position of the connecting line of the non-display area, and the first through holes are used for the first through holes.
  • the conductive line in the layer is electrically connected to the second metal line; the first metal line and the second metal line are electrically connected through the conductive line.
  • the benefit of this design is that multiple connection points are added to the same line to make the first metal line and the second metal line conductive.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Geometry (AREA)

Abstract

La présente invention concerne un substrat de réseau comprenant : un substrat (100), et une première couche métallique (101), une première couche d'isolation (102), une deuxième couche métallique (103), une deuxième couche d'isolation (104) et une couche d'électrodes de pixel (105) disposées séquentiellement sur la surface du substrat (100). À une position du fil de connexion, des premiers trous traversants multiples (106) et des deuxièmes trous traversant multiples (107) sont disposés, de manière à exposer un premier film métallique et un deuxième fil métallique, électriquement connectés par l'intermédiaire d'un fil conducteur de la couche d'électrodes de pixel (105). Le substrat évite efficacement le problème de drainage de module vertical ou de défauts de ligne horizontale.
PCT/CN2015/073925 2015-02-11 2015-03-10 Substrat de réseau et panneau d'affichage à cristaux liquides WO2016127464A1 (fr)

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GB1712779.6A GB2550762B (en) 2015-02-11 2015-03-10 Array substrate and liquid crystal display panel
KR1020177025517A KR101907079B1 (ko) 2015-02-11 2015-03-10 어레이 기판 및 액정 디스플레이 패널
US14/766,757 US9618810B2 (en) 2015-02-11 2015-03-10 Array substrate and liquid crystal display panel
JP2017541845A JP6539743B2 (ja) 2015-02-11 2015-03-10 アレイ基板及び液晶表示パネル
EA201791625A EA032903B1 (ru) 2015-02-11 2015-03-10 Подложка матрицы и жидкокристаллическая дисплейная панель

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CN201510072465.2A CN104656327B (zh) 2015-02-11 2015-02-11 一种阵列基板及液晶显示面板

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CN105785677B (zh) * 2016-05-11 2019-06-07 深圳市华星光电技术有限公司 显示装置及其显示面板、显示面板的制造方法
TWI656461B (zh) * 2016-07-31 2019-04-11 矽創電子股份有限公司 觸控顯示裝置
CN106324934A (zh) * 2016-11-08 2017-01-11 深圳市华星光电技术有限公司 短路棒结构及阵列基板
CN109100896A (zh) * 2018-10-08 2018-12-28 深圳市华星光电技术有限公司 阵列基板、显示面板及其显示面板的垂直淡线修复方法
CN109143709A (zh) * 2018-11-09 2019-01-04 信利半导体有限公司 Tft基板及液晶显示装置
CN109872632A (zh) * 2019-03-20 2019-06-11 武汉华星光电技术有限公司 阵列基板
CN111090201B (zh) * 2020-03-22 2020-06-23 深圳市华星光电半导体显示技术有限公司 显示面板及电子装置
CN115830995B (zh) * 2022-12-29 2024-06-11 Tcl华星光电技术有限公司 显示面板

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CN104656327A (zh) 2015-05-27
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KR20170109676A (ko) 2017-09-29
EA032903B1 (ru) 2019-07-31
GB201712779D0 (en) 2017-09-20
GB2550762A (en) 2017-11-29
JP2018506075A (ja) 2018-03-01
GB2550762B (en) 2018-11-21
EA201791625A1 (ru) 2017-11-30
KR101907079B1 (ko) 2018-12-05

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