WO2016106813A1 - 低温多晶硅薄膜晶体管及其制造方法 - Google Patents

低温多晶硅薄膜晶体管及其制造方法 Download PDF

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Publication number
WO2016106813A1
WO2016106813A1 PCT/CN2015/070419 CN2015070419W WO2016106813A1 WO 2016106813 A1 WO2016106813 A1 WO 2016106813A1 CN 2015070419 W CN2015070419 W CN 2015070419W WO 2016106813 A1 WO2016106813 A1 WO 2016106813A1
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interlayer dielectric
dielectric layer
area
layer
recessed
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French (fr)
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卢昶鸣
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/437,822 priority Critical patent/US9905698B2/en
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Priority to US15/845,220 priority patent/US10361316B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • the invention belongs to the technical field of thin film transistors, in particular to a low temperature polysilicon thin film transistor, and to a method for manufacturing the low temperature polysilicon thin film transistor.
  • FIG. 1 is a prior art LTPS-TFT (Low Temperature).
  • Poly-Silicon-Thin Film Transistor a schematic diagram of the structure of a low temperature polysilicon thin film transistor.
  • the prior art LTPS-TFT includes a Substrate layer, a SiNx (silicon nitride) layer, a substrate layer of a SiOx (silicon oxide) layer, and an a-Si (amorphous silicon) layer.
  • the source metal layer and the drain metal layer correspond to the ILD shown in FIG.
  • the via hole indicated by the Via Hole arrow is connected to the doped region.
  • the vertical hole arrangement of the existing recessed region channel has a great influence on the source metal layer and the drain metal layer.
  • the thickness of the ILD interlayer dielectric layer
  • the line width of the source and drain metal layers becomes narrower, and the hidden troubles in the process will gradually emerge, especially in the super-resolution LTPS and final products, the source and the drain.
  • Metal layer is placed in the recessed area channel
  • ILD via Hole such as the edge of the ILD via Hole of the recessed channel
  • the source and drain metal layers may not completely fill the recessed channel ILD via Hole, which forms part of the gap, etc., is liable to cause the reliability of the product to be lowered, and the yield rate of the product cannot be guaranteed.
  • the embodiments of the present invention provide a low-temperature polysilicon thin film transistor and a manufacturing method thereof to solve the technical problem that the source and drain metal layers are easily broken and the product reliability is low in the prior art.
  • an embodiment of the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, wherein the manufacturing method includes: forming an interlayer dielectric layer on a gate metal layer by using a material including silicon oxide and silicon nitride.
  • the method further includes: The photoresist layer performs a plurality of photo-resistances to sequentially expose the interlayer dielectric layers of the plurality of areas, and sequentially etches the interlayer dielectric layers of the plurality of areas to form a multi-step recessed-area channel.
  • the method further includes: forming a source metal layer or a drain metal layer correspondingly on the recessed via channel.
  • the photo-resistance dry etching and plasma are used, and the photoresist is processed for 10 to 500 seconds under the condition of RF power of 200-3000 KHz.
  • the process gas used in the plasma mode is oxygen, carbon tetrafluoride or nitrogen oxide
  • the radio frequency power is 1000-2000 KHz
  • the processing time is 200-300 seconds.
  • etching is performed using a high selective ratio etching process of polysilicon and silicon oxide or silicon nitride film to form the recessed region channel.
  • etching is performed by buffering a hydrofluoric acid BHF etching solution or a hydrofluoric acid HF etching solution to form the recessed region channel.
  • an embodiment of the present invention further provides a low temperature polysilicon thin film transistor, wherein the low temperature polysilicon thin film transistor includes an interlayer dielectric layer, a source metal layer and a drain metal layer, and the interlayer dielectric layer is used. Formed by forming a silicon oxide and a silicon nitride material, the interlayer dielectric layer is formed with a stepped recessed via, and the source metal layer and the drain metal layer are formed in the stepped recessed via .
  • the recessed area channel is at least three steps.
  • the recessed area channel is a four-layer step type.
  • the beneficial effects of the embodiments of the present invention are: the embodiment of the present invention can avoid the step of forming a stepped recessed region channel in the interlayer dielectric layer, so that when the source and drain metal layers are fabricated in the recessed region channel, The angular contact of the channel in the recessed area causes the problem of disconnection, and the technical problem that the source and the drain metal cannot fill the recessed passage to form a void and lead to low reliability of the product can be avoided. Further, the problem of disconnection caused by thickening of the interlayer dielectric layer is avoided, and the reliability, yield and yield of the product are improved.
  • FIG. 1 is a schematic structural view of a prior art LTPS-TFT
  • FIG. 2 is a schematic flow chart of an embodiment of a method for fabricating a low temperature polysilicon thin film transistor of the present invention
  • FIG. 3A to 3E are schematic views showing the effect when the manufacturing method shown in Fig. 2 is employed;
  • FIG. 4 is a schematic structural view of an embodiment of a low temperature polysilicon thin film transistor of the present invention.
  • FIG. 2 is a schematic flow chart of an embodiment of a method for manufacturing a low-temperature polysilicon thin film transistor according to the present invention
  • FIGS. 3A to 3E are schematic diagrams showing the effect of the manufacturing method shown in FIG.
  • the manufacturing method of the polysilicon thin film transistor includes, but is not limited to, the following steps.
  • step S200 an interlayer dielectric layer is formed on the gate metal layer by using a material including silicon oxide and silicon nitride.
  • step S200 the silicon oxide chemical formula is SiOx, the silicon nitride chemical formula is SiNx, and the interlayer dielectric layer is the interlayer dielectric layer ILD shown in FIG. 3A.
  • Step S201 forming a photoresist layer on the interlayer dielectric layer, and performing a first photo-resistance on the photoresist layer to expose the interlayer dielectric layer of the first area.
  • the photoresist layer is the photoresist layer PR shown in FIG. 3A, wherein FIG. 3A can graphically process the photoresist to form an etching channel between the plurality of PRs, wherein the first area and the etching are performed.
  • the cross-sectional area of the channel is the same.
  • Step S202 etching the interlayer dielectric layer of the first area to form a first recessed region.
  • step S202 as shown in FIG. 3B, after etching, a first recessed region is formed on the interlayer dielectric layer, wherein the area of the first recessed region is the same as the first area.
  • Step S203 performing a second photo-resistance on the photoresist layer to expose the interlayer dielectric layer of the second area, wherein the first recessed region is located in the interlayer dielectric layer of the second area.
  • step S203 as shown in FIG. 3C, by performing a second photo-resistance on the PR, the interlayer dielectric layer of the second area covered by the north PR in the original FIG. 3B is exposed, wherein the first area and the second area are The sum is the same as the cross-sectional area of the etching channel formed at this time.
  • Step S204 etching the interlayer dielectric layer and the first recess region of the second area, so that the periphery of the first recess region forms a stepped second recess region.
  • step S204 as shown in FIG. 3D, since the original first recessed region and the exposed second-area interlayer dielectric layer are simultaneously etched, the thickness of the etched layer is substantially the same, and the height is relatively close to uniform. Ladder.
  • the embodiment of the present invention further includes a photo-resistance process to obtain a structure as shown in FIG. 3E.
  • the photoresist layer may be further disposed in this embodiment.
  • the photo-resistance is performed a plurality of times to expose the interlayer dielectric layers of the plurality of areas in sequence, and the interlayer dielectric layers of the plurality of areas are sequentially etched to form a multi-step recessed-area channel.
  • the embodiment of the present invention can form a recessed region channel including three steps, four steps or more by repeatedly performing the above steps, and specifically, the number of steps can be set according to the thickness of the interlayer dielectric layer ILD.
  • the embodiment may further include a process of respectively forming a source metal layer or a drain metal layer on the recessed via channel, as shown in FIG. 3E in the recessed via channel.
  • the present embodiment uses a dry etching and a plasma method and processes the photo-resistance for 10 to 500 seconds under the condition of an RF power of 200 to 3000 KHz (kilohertz).
  • the plasma process may be a process gas of oxygen, carbon tetrafluoride or nitrogen oxide, a radio frequency power of 1000 to 2000 KHz, a processing time of 200 to 300 seconds, etc., which are easily understood by those skilled in the art. , no restrictions.
  • 1800 can be used
  • the RF power of KHz is processed for 250 seconds for cyclic retreating.
  • the present invention can be etched using a high selective ratio etching process of polysilicon and silicon oxide or silicon nitride film, such as when the photoresist is removed by full dry etching and oxygen plasma. A recessed area channel is formed.
  • the invention may be etched using a buffered hydrofluoric acid BHF etchant or a hydrofluoric acid HF etchant to form a recessed via when dry and wet etch combined with photo-resistance.
  • embodiments of the present invention may also pass a half tone mask or gray.
  • the tone (gray tone) process is used for pattern processing, and in the corresponding photo-resistance process, the full-dry etching and oxygen plasma method can also be used to cycle the photoresist.
  • the problem of disconnection caused by the angular contact of the recessed-area channel can be avoided. It can avoid the technical problem that the source and drain metals cannot fill the recessed channel and form a void, resulting in low product reliability. Further, the problem of disconnection caused by thickening of the interlayer dielectric layer is avoided, and the reliability, yield and yield of the product are improved.
  • FIG. 4 is a schematic structural diagram of an embodiment of a low temperature polysilicon thin film transistor of the present invention.
  • the low temperature polysilicon thin film transistor of the present embodiment includes an interlayer dielectric layer 41, and source and drain metal layers 42 and 43.
  • the interlayer dielectric layer is formed by using a silicon oxide and a silicon nitride material, and the interlayer dielectric layer is formed with a stepped recessed via, and the source and drain metal layers 42 and 43 are respectively formed in the stepped recessed via.
  • the recessed area channel of the embodiment has at least three steps, and preferably, the recessed area has a four-layered step.
  • the low temperature polysilicon thin film transistor of the embodiment may further include a gate metal layer GE, a doped region doping, a clear doped region LDD, and a substrate layer including a silicon nitride and a silicon oxide material. It will not be described in detail within the scope that will be easily understood by those skilled in the art.
  • the low-temperature polysilicon thin film transistor of the present embodiment is preferably produced by the manufacturing method of the previous embodiment, which is not limited herein.
  • the angular contact of the recessed region channel can be avoided to cause disconnection.
  • the problem can also avoid the technical problem that the source and drain metals 42, 43 cannot fill the recessed channel and form a void, resulting in low product reliability. Further, the problem of disconnection caused by the thickening of the interlayer dielectric layer 41 is avoided, and the reliability, yield, and yield of the product are improved.

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  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种低温多晶硅薄膜晶体管及其制造方法，方法包括：在栅极金属层上制作形成层间介质层（S200）；在层间介质层上形成光阻层，并对光阻层进行第一次退光阻以露出第一面积的层间介质层(S201)；对第一面积的层间介质层进行蚀刻以形成第一凹陷区(S202)，对光阻层进行第二次退光阻以露出第二面积的层间介质层(S203)；对第二面积的层间介质层和第一凹陷区进行蚀刻，使得第一凹陷区的周边形成阶梯式的第二凹陷区(S204)。通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角碰触造成的断线问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。

Description

低温多晶硅薄膜晶体管及其制造方法
【技术领域】
本发明属于薄膜晶体管技术领域，具体涉及一种低温多晶硅薄膜晶体管，还涉及一种该低温多晶硅薄膜晶体管的制造方法。
【背景技术】
请参阅图1，图1为现有技术的LTPS-TFT（Low Temperature Poly-Silicon-Thin Film Transistor，低温多晶硅薄膜晶体管）的结构示意图。
如图1所示，现有技术LTPS-TFT依序包括Substrate（基底）层、SiNx（氮化硅）层、SiOx（氧化硅）层的基材层、a-Si（非晶硅）层、doping（掺杂）不同剂量的P31（相对分子质量为31的磷）的掺杂区域、及GE（栅极金属）层、Source（源极金属）层和Drain（漏极金属）层等。其中，源极金属层和漏极金属层对应设于图1所示的ILD Via Hole箭头所指的凹陷区通道内并与掺杂区域相连接。
从图1不难看出，现有凹陷区通道的垂直孔设置方式，对源极金属层和漏极金属层影响较大。譬如随著 ILD（层间介质层）膜厚变厚，和源极、漏极金属层的线宽变窄，制程上的隐忧会逐渐浮现，尤其在超解析度LTPS和最终产品中，源极、漏极金属层设置在凹陷区通道 ILD via Hole中会有断线的可能性，譬如与凹陷区通道ILD via Hole的棱角触碰；其次，源极、漏极金属层可能无法完全填满凹陷区通道ILD via Hole，形成部分空隙等，而易造成产品的可靠度降低，成品率合格率无法得到保证。
【发明内容】
有鉴于此，本发明实施例提供一种低温多晶硅薄膜晶体管及其制造方法，以解决现有技术中源极、漏极金属层容易断线、产品可靠度低的技术问题。
为解决上述技术问题，本发明实施例提供一种低温多晶硅薄膜晶体管的制造方法，其中，所述制造方法包括：在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层；在所述层间介质层上形成光阻层，并对所述光阻层进行第一次退光阻以露出第一面积的层间介质层；对所述第一面积的层间介质层进行蚀刻以形成第一凹陷区；对所述光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，所述第一凹陷区位于所述第二面积的层间介质层中；对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区。
其中，在对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区的步骤之后，还包括：对所述光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。
其中，在形成多阶梯式的凹陷区通道的步骤之后，还包括：在所述凹陷区通道上分别对应形成源极金属层或漏极金属层。
其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200~3000KHz的条件下加工10~500秒进行退光阻。
其中，所述电浆方式所采用的制程气体为氧气、四氟化碳或氧化氮，所述射频功率为1000~2000KHz，加工时间为200~300秒。
其中，在采用全干式蚀刻和氧气电浆方式进行退光阻时，使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成所述凹陷区通道。
其中，在采用干式和湿式蚀刻组合退光阻时，采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成所述凹陷区通道。
为解决上述技术问题，本发明实施例还提供一种低温多晶硅薄膜晶体管，其中，所述低温多晶硅薄膜晶体管包括层间介质层、源极金属层和漏极金属层，所述层间介质层采用包括氧化硅和氮化硅材料制作形成，所述层间介质层形成有阶梯式的凹陷区通道，所述源极金属层和所述漏极金属层形成于所述阶梯式的凹陷区通道内。
其中，所述凹陷区通道至少为三层阶梯式。
其中，所述凹陷区通道为四层阶梯式。
通过上述技术方案，本发明实施例的有益效果是：本发明实施例通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的LTPS-TFT的结构示意图；
图2是本发明低温多晶硅薄膜晶体管的制造方法一实施例的流程示意图；
图3A至图3E是采用图2所示制造方法时的效果示意图；
图4是本发明低温多晶硅薄膜晶体管一实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图2~图3E，图2是本发明低温多晶硅薄膜晶体管的制造方法一实施例的流程示意图，图3A至图3E是采用图2所示制造方法时的效果示意图，本实施例的低温多晶硅薄膜晶体管的制造方法包括但不限于以下步骤。
步骤S200，在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层。
在步骤S200中，氧化硅化学式为SiOx，氮化硅化学式为SiNx，层间介质层为图3A所示的层间介质层ILD。
步骤S201，在层间介质层上形成光阻层，并对光阻层进行第一次退光阻以露出第一面积的层间介质层。
在步骤S201中，光阻层为图3A所示的光阻层PR，其中，图3A可以采用图形化处理退光阻，以形成多个PR之间的蚀刻通道，其中，第一面积与蚀刻通道的横截面面积相同。
步骤S202，对第一面积的层间介质层进行蚀刻以形成第一凹陷区。
在步骤S202中，如图3B所示，进行蚀刻后，在层间介质层上形成第一凹陷区，其中，第一凹陷区的面积与第一面积相同。
步骤S203，对光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，第一凹陷区位于第二面积的层间介质层中。
在步骤S203中，如图3C所示，通过对PR进行第二次退光阻，露出了原图3B中北PR覆盖的第二面积的层间介质层，其中，第一面积和第二面积的和与此时形成的蚀刻通道的横截面积相同。
步骤S204，对第二面积的层间介质层和第一凹陷区进行蚀刻，以使得第一凹陷区的周边形成阶梯式的第二凹陷区。
在步骤S204中，如图3D所示，由于原第一凹陷区与露出的第二面积的层间介质层进行同步蚀刻，因此，其所蚀刻的厚度基本上相同，而形成了高度比较接近均匀的阶梯。
其中，在步骤S204之后，本发明实施例还包括退光阻过程，制得如图3E所示的结构。
需要说明的是，在对第二面积的层间介质层和第一凹陷区进行蚀刻，以使得第一凹陷区的周边形成阶梯式的第二凹陷区之后，本实施例还可以对光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。换而言之，本发明实施例可以通过反复执行上述步骤，而形成包括三层阶梯、四层阶梯或以上的凹陷区通道，其具体可以根据层间介质层ILD的厚度而设置阶梯的数目。
此外，在形成多阶梯式的凹陷区通道之后，本实施例还可以包括在凹陷区通道上分别对应形成源极金属层或漏极金属层等过程，如图3E所示在上述凹陷区通道内形成的沉积状结构。
需要指出的是，在进行退光阻时，本实施例采用干式蚀刻和电浆方式并在射频功率为200~3000KHz（千赫兹）的条件下加工10~500秒进行退光阻。具体来说，电浆方式可以所采用的制程气体为氧气、四氟化碳或氧化氮，射频功率为1000~2000KHz，加工时间为200~300秒等，在本技术领域人员容易理解的范围内，不作限定。在优选的实施例中，可以采用1800 KHz的射频功率并加工250秒进行循环退光阻处理。
当然，在其他实施例中，如在采用全干式蚀刻和氧气电浆方式进行退光阻时，本发明则可以使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成凹陷区通道。
在其他实施例中，在采用干式和湿式蚀刻组合退光阻时，本发明可以采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成凹陷区通道。
值得注意的是，本发明的实施例还可以通过half tone（半调式）掩膜或gray tone（灰调式）制程进行图形处理，则在对应的退光阻过程中，也可以采用全干式蚀刻和氧气电浆方式进行循环退光阻。
本发明实施例通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
请参阅图4，图4是本发明低温多晶硅薄膜晶体管一实施例的结构示意图，本实施例低温多晶硅薄膜晶体管包括层间介质层41、源极、漏极金属层42、43。
层间介质层采用包括氧化硅和氮化硅材料制作形成，层间介质层形成有阶梯式的凹陷区通道，源极、漏极金属层42、43分别形成于阶梯式的凹陷区通道内。
需要说明的是，本实施例凹陷区通道至少为三层阶梯式，优选地，凹陷区通道为四层阶梯式。
此外，从图4不难看出，本实施例低温多晶硅薄膜晶体管还可以包括栅极金属层GE、掺杂区域doping、清掺杂区域LDD以及包括氮化硅和氧化硅材料形成的基材层等，在本技术领域人员容易理解的范围内，不作细述。
值得注意的是，本实施例低温多晶硅薄膜晶体管优选地采用前面实施例所涉及的制造方法制得，在此不作限定。
本发明实施例通过在层间介质层41设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层42、43时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属42、43无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层41膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管的制造方法，其中，所述制造方法包括：
    在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层；
    在所述层间介质层上形成光阻层，并对所述光阻层进行第一次退光阻以露出第一面积的层间介质层；
    对所述第一面积的层间介质层进行蚀刻以形成第一凹陷区；
    对所述光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，所述第一凹陷区位于所述第二面积的层间介质层中；
    对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区；对所述光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道，其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200~3000KHz的条件下加工10~500秒进行退光阻。
  2. 一种低温多晶硅薄膜晶体管的制造方法，其中，所述制造方法包括：
    在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层；
    在所述层间介质层上形成光阻层，并对所述光阻层进行第一次退光阻以露出第一面积的层间介质层；
    对所述第一面积的层间介质层进行蚀刻以形成第一凹陷区；
    对所述光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，所述第一凹陷区位于所述第二面积的层间介质层中；
    对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区。
  3. 根据权利要求2所述的制造方法，其中，在对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区的步骤之后，还包括：
    对所述光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。
  4. 根据权利要求3所述的制造方法，其中，在形成多阶梯式的凹陷区通道的步骤之后，还包括：
    在所述凹陷区通道上分别对应形成源极金属层或漏极金属层。
  5. 根据权利要求2任一项所述的制造方法，其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200~3000KHz的条件下加工10~500秒进行退光阻。
  6. 根据权利要求3任一项所述的制造方法，其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200~3000KHz的条件下加工10~500秒进行退光阻。
  7. 根据权利要求4任一项所述的制造方法，其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200~3000KHz的条件下加工10~500秒进行退光阻。
  8. 根据权利要求7所述的制造方法，其中，所述电浆方式所采用的制程气体为氧气、四氟化碳或氧化氮，所述射频功率为1000~2000KHz，加工时间为200~300秒。
  9. 根据权利要求7所述的制造方法，其中，在采用全干式蚀刻和氧气电浆方式进行退光阻时，使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成所述凹陷区通道。
  10. 根据权利要求7所述的制造方法，其中，在采用干式和湿式蚀刻组合退光阻时，采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成所述凹陷区通道。
  11. 一种低温多晶硅薄膜晶体管，其中，所述低温多晶硅薄膜晶体管包括层间介质层、源极金属层和漏极金属层，所述层间介质层采用包括氧化硅和氮化硅材料制作形成，所述层间介质层形成有阶梯式的凹陷区通道，所述源极金属层和所述漏极金属层形成于所述阶梯式的凹陷区通道内。
  12. 根据权利要求11所述的低温多晶硅薄膜晶体管，其中，所述凹陷区通道至少为三层阶梯式。
  13. 根据权利要求12所述的低温多晶硅薄膜晶体管，其中，所述凹陷区通道为四层阶梯式。
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CN104617132A (zh) 2015-05-13

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