CN104617132A - 低温多晶硅薄膜晶体管及其制造方法 - Google Patents

低温多晶硅薄膜晶体管及其制造方法 Download PDF

Info

Publication number
CN104617132A
CN104617132A CN201410856397.4A CN201410856397A CN104617132A CN 104617132 A CN104617132 A CN 104617132A CN 201410856397 A CN201410856397 A CN 201410856397A CN 104617132 A CN104617132 A CN 104617132A
Authority
CN
China
Prior art keywords
depressed area
interlayer dielectric
dielectric layer
area
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410856397.4A
Other languages
English (en)
Other versions
CN104617132B (zh
Inventor
卢昶鸣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201410856397.4A priority Critical patent/CN104617132B/zh
Priority to PCT/CN2015/070419 priority patent/WO2016106813A1/zh
Priority to US14/437,822 priority patent/US9905698B2/en
Publication of CN104617132A publication Critical patent/CN104617132A/zh
Application granted granted Critical
Publication of CN104617132B publication Critical patent/CN104617132B/zh
Priority to US15/845,220 priority patent/US10361316B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明实施例提供一种低温多晶硅薄膜晶体管及其制造方法，方法包括：在栅极金属层上制作形成层间介质层；在层间介质层上形成光阻层，并对光阻层进行第一次退光阻以露出第一面积的层间介质层；对第一面积的层间介质层进行蚀刻以形成第一凹陷区；对光阻层进行第二次退光阻以露出第二面积的层间介质层；对第二面积的层间介质层和第一凹陷区进行蚀刻，以使得第一凹陷区的周边形成阶梯式的第二凹陷区。本发明实施例通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。

Description

低温多晶硅薄膜晶体管及其制造方法
技术领域
本发明属于薄膜晶体管技术领域，具体涉及一种低温多晶硅薄膜晶体管，还涉及一种该低温多晶硅薄膜晶体管的制造方法。
背景技术
请参阅图1，图1为现有技术的LTPS-TFT(Low Temperature Poly-Silicon-Thin Film Transistor，低温多晶硅薄膜晶体管)的结构示意图。
如图1所示，现有技术LTPS-TFT依序包括Substrate(基底)层、SiNx(氮化硅)层、SiOx(氧化硅)层的基材层、a-Si(非晶硅)层、doping(掺杂)不同剂量的P31(相对分子质量为31的磷)的掺杂区域、及GE(栅极金属)层、Source(源极金属)层和Drain(漏极金属)层等。其中，源极金属层和漏极金属层对应设于图1所示的ILD Via Hole箭头所指的凹陷区通道内并与掺杂区域相连接。
从图1不难看出，现有凹陷区通道的垂直孔设置方式，对源极金属层和漏极金属层影响较大。譬如随著ILD(层间介质层)膜厚变厚，和源极、漏极金属层的线宽变窄，制程上的隐忧会逐渐浮现，尤其在超解析度LTPS和最终产品中，源极、漏极金属层设置在凹陷区通道ILD via Hole中会有断线的可能性，譬如与凹陷区通道ILD via Hole的棱角触碰；其次，源极、漏极金属层可能无法完全填满凹陷区通道ILD via Hole，形成部分空隙等，而易造成产品的可靠度降低，成品率合格率无法得到保证。
发明内容
有鉴于此，本发明实施例提供一种低温多晶硅薄膜晶体管及其制造 方法，以解决现有技术中源极、漏极金属层容易断线、产品可靠度低的技术问题。
为解决上述技术问题，本发明实施例提供一种低温多晶硅薄膜晶体管的制造方法，其中，所述制造方法包括：在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层；在所述层间介质层上形成光阻层，并对所述光阻层进行第一次退光阻以露出第一面积的层间介质层；对所述第一面积的层间介质层进行蚀刻以形成第一凹陷区；对所述光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，所述第一凹陷区位于所述第二面积的层间介质层中；对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区。
其中，在对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区的步骤之后，还包括：对所述光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。
其中，在形成多阶梯式的凹陷区通道的步骤之后，还包括：在所述凹陷区通道上分别对应形成源极金属层或漏极金属层。
其中，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200～3000KHz的条件下加工10～500秒进行退光阻。
其中，所述电浆方式所采用的制程气体为氧气、四氟化碳或氧化氮，所述射频功率为1000～2000KHz，加工时间为200～300秒。
其中，在采用全干式蚀刻和氧气电浆方式进行退光阻时，使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成所述凹陷区通道。
其中，在采用干式和湿式蚀刻组合退光阻时，采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成所述凹陷区通道。
为解决上述技术问题，本发明实施例还提供一种低温多晶硅薄膜晶体管，其中，所述低温多晶硅薄膜晶体管包括层间介质层、源极金属层 和漏极金属层，所述层间介质层采用包括氧化硅和氮化硅材料制作形成，所述层间介质层形成有阶梯式的凹陷区通道，所述源极金属层和所述漏极金属层形成于所述阶梯式的凹陷区通道内。
其中，所述凹陷区通道至少为三层阶梯式。
其中，所述凹陷区通道为四层阶梯式。
通过上述技术方案，本发明实施例的有益效果是：本发明实施例通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
附图说明
图1为现有技术的LTPS-TFT的结构示意图；
图2是本发明低温多晶硅薄膜晶体管的制造方法一实施例的流程示意图；
图3A至图3E是采用图2所示制造方法时的效果示意图；
图4是本发明低温多晶硅薄膜晶体管一实施例的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图2～图3E，图2是本发明低温多晶硅薄膜晶体管的制造方法一实施例的流程示意图，图3A至图3E是采用图2所示制造方法时的效果示意图，本实施例的低温多晶硅薄膜晶体管的制造方法包括但不限于以下步骤。
步骤S200，在栅极金属层上采用包括氧化硅和氮化硅材料制作形成 层间介质层。
在步骤S200中，氧化硅化学式为SiOx，氮化硅化学式为SiNx，层间介质层为图3A所示的层间介质层ILD。
步骤S201，在层间介质层上形成光阻层，并对光阻层进行第一次退光阻以露出第一面积的层间介质层。
在步骤S201中，光阻层为图3A所示的光阻层PR，其中，图3A可以采用图形化处理退光阻，以形成多个PR之间的蚀刻通道，其中，第一面积与蚀刻通道的横截面面积相同。
步骤S202，对第一面积的层间介质层进行蚀刻以形成第一凹陷区。
在步骤S202中，如图3B所示，进行蚀刻后，在层间介质层上形成第一凹陷区，其中，第一凹陷区的面积与第一面积相同。
步骤S203，对光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，第一凹陷区位于第二面积的层间介质层中。
在步骤S203中，如图3C所示，通过对PR进行第二次退光阻，露出了原图3B中北PR覆盖的第二面积的层间介质层，其中，第一面积和第二面积的和与此时形成的蚀刻通道的横截面积相同。
步骤S204，对第二面积的层间介质层和第一凹陷区进行蚀刻，以使得第一凹陷区的周边形成阶梯式的第二凹陷区。
在步骤S204中，如图3D所示，由于原第一凹陷区与露出的第二面积的层间介质层进行同步蚀刻，因此，其所蚀刻的厚度基本上相同，而形成了高度比较接近均匀的阶梯。
其中，在步骤S204之后，本发明实施例还包括退光阻过程，制得如图3E所示的结构。 
需要说明的是，在对第二面积的层间介质层和第一凹陷区进行蚀刻，以使得第一凹陷区的周边形成阶梯式的第二凹陷区之后，本实施例还可以对光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。换而言之，本发明实施例可以通过反复执行上述步骤，而形成包括三层阶梯、四层阶梯或以上的凹陷区通道，其具体可以根据层间介质 层ILD的厚度而设置阶梯的数目。
此外，在形成多阶梯式的凹陷区通道之后，本实施例还可以包括在凹陷区通道上分别对应形成源极金属层或漏极金属层等过程，如图3E所示在上述凹陷区通道内形成的沉积状结构。
需要指出的是，在进行退光阻时，本实施例采用干式蚀刻和电浆方式并在射频功率为200～3000KHz(千赫兹)的条件下加工10～500秒进行退光阻。具体来说，电浆方式可以所采用的制程气体为氧气、四氟化碳或氧化氮，射频功率为1000～2000KHz，加工时间为200～300秒等，在本技术领域人员容易理解的范围内，不作限定。在优选的实施例中，可以采用1800KHz的射频功率并加工250秒进行循环退光阻处理。
当然，在其他实施例中，如在采用全干式蚀刻和氧气电浆方式进行退光阻时，本发明则可以使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成凹陷区通道。
在其他实施例中，在采用干式和湿式蚀刻组合退光阻时，本发明可以采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成凹陷区通道。
值得注意的是，本发明的实施例还可以通过half tone(半调式)掩膜或gray tone(灰调式)制程进行图形处理，则在对应的退光阻过程中，也可以采用全干式蚀刻和氧气电浆方式进行循环退光阻。
本发明实施例通过在层间介质层设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
请参阅图4，图4是本发明低温多晶硅薄膜晶体管一实施例的结构示意图，本实施例低温多晶硅薄膜晶体管包括层间介质层41、源极、漏极金属层42、43。
层间介质层采用包括氧化硅和氮化硅材料制作形成，层间介质层形 成有阶梯式的凹陷区通道，源极、漏极金属层42、43分别形成于阶梯式的凹陷区通道内。
需要说明的是，本实施例凹陷区通道至少为三层阶梯式，优选地，凹陷区通道为四层阶梯式。
此外，从图4不难看出，本实施例低温多晶硅薄膜晶体管还可以包括栅极金属层GE、掺杂区域doping、清掺杂区域LDD以及包括氮化硅和氧化硅材料形成的基材层等，在本技术领域人员容易理解的范围内，不作细述。
值得注意的是，本实施例低温多晶硅薄膜晶体管优选地采用前面实施例所涉及的制造方法制得，在此不作限定。
本发明实施例通过在层间介质层41设置阶梯式的凹陷区通道，使得在凹陷区通道内制作源极、漏极金属层42、43时，可以避免凹陷区通道的棱角触碰造成断线的问题，也可以避免源极、漏极金属42、43无法填满凹陷区通道而形成空隙、导致产品可靠度低的技术问题。进一步而言，避免了层间介质层41膜厚变厚所引起的断线问题，同时提高了产品的可靠度、成品率和合格率。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种低温多晶硅薄膜晶体管的制造方法，其特征在于，所述制造方法包括：
在栅极金属层上采用包括氧化硅和氮化硅材料制作形成层间介质层；
在所述层间介质层上形成光阻层，并对所述光阻层进行第一次退光阻以露出第一面积的层间介质层；
对所述第一面积的层间介质层进行蚀刻以形成第一凹陷区；
对所述光阻层进行第二次退光阻以露出第二面积的层间介质层，其中，所述第一凹陷区位于所述第二面积的层间介质层中；
对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区。
2.根据权利要求1所述的制造方法，其特征在于，在对所述第二面积的层间介质层和所述第一凹陷区进行蚀刻，以使得所述第一凹陷区的周边形成阶梯式的第二凹陷区的步骤之后，还包括：
对所述光阻层进行多次退光阻以依次露出多个面积的层间介质层，并对多个面积的层间介质层依序进行相应蚀刻，以形成多阶梯式的凹陷区通道。
3.根据权利要求2所述的制造方法，其特征在于，在形成多阶梯式的凹陷区通道的步骤之后，还包括：
在所述凹陷区通道上分别对应形成源极金属层或漏极金属层。
4.根据权利要求1-3任一项所述的制造方法，其特征在于，在进行退光阻时，采用干式蚀刻和电浆方式并在射频功率为200～3000KHz的条件下加工10～500秒进行退光阻。
5.根据权利要求4所述的制造方法，其特征在于，所述电浆方式所采用的制程气体为氧气、四氟化碳或氧化氮，所述射频功率为1000～2000KHz，加工时间为200～300秒。
6.根据权利要求4所述的制造方法，其特征在于，在采用全干式蚀刻和氧气电浆方式进行退光阻时，使用多晶硅与氧化硅或氮化硅薄膜高选择比的蚀刻配方进行蚀刻，以形成所述凹陷区通道。
7.根据权利要求4所述的制造方法，其特征在于，在采用干式和湿式蚀刻组合退光阻时，采用缓冲氢氟酸BHF蚀刻液或氢氟酸HF蚀刻液进行蚀刻，以形成所述凹陷区通道。
8.一种低温多晶硅薄膜晶体管，其特征在于，所述低温多晶硅薄膜晶体管包括层间介质层、源极金属层和漏极金属层，所述层间介质层采用包括氧化硅和氮化硅材料制作形成，所述层间介质层形成有阶梯式的凹陷区通道，所述源极金属层和所述漏极金属层形成于所述阶梯式的凹陷区通道内。
9.根据权利要求8所述的低温多晶硅薄膜晶体管，其特征在于，所述凹陷区通道至少为三层阶梯式。
10.根据权利要求9所述的低温多晶硅薄膜晶体管，其特征在于，所述凹陷区通道为四层阶梯式。
CN201410856397.4A 2014-12-31 2014-12-31 低温多晶硅薄膜晶体管及其制造方法 Active CN104617132B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201410856397.4A CN104617132B (zh) 2014-12-31 2014-12-31 低温多晶硅薄膜晶体管及其制造方法
PCT/CN2015/070419 WO2016106813A1 (zh) 2014-12-31 2015-01-09 低温多晶硅薄膜晶体管及其制造方法
US14/437,822 US9905698B2 (en) 2014-12-31 2015-01-09 Low temperature poly-silicon thin film transistor and method for manufacturing the same
US15/845,220 US10361316B2 (en) 2014-12-31 2017-12-18 Low temperature poly-silicon thin film transistor and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410856397.4A CN104617132B (zh) 2014-12-31 2014-12-31 低温多晶硅薄膜晶体管及其制造方法

Publications (2)

Publication Number Publication Date
CN104617132A true CN104617132A (zh) 2015-05-13
CN104617132B CN104617132B (zh) 2017-05-10

Family

ID=53151497

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410856397.4A Active CN104617132B (zh) 2014-12-31 2014-12-31 低温多晶硅薄膜晶体管及其制造方法

Country Status (3)

Country Link
US (2) US9905698B2 (zh)
CN (1) CN104617132B (zh)
WO (1) WO2016106813A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105551967B (zh) * 2016-02-14 2019-04-30 武汉华星光电技术有限公司 N型薄膜晶体管的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093707A (ja) * 2001-07-19 2002-03-29 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2004170724A (ja) * 2002-11-20 2004-06-17 Sharp Corp 液晶表示装置の製造方法
KR20060074215A (ko) * 2004-12-27 2006-07-03 전자부품연구원 박막 트랜지스터 및 제조 방법
CN101626034A (zh) * 2008-07-08 2010-01-13 乐金显示有限公司 薄膜晶体管及其制造方法
CN102496625A (zh) * 2011-08-15 2012-06-13 友达光电股份有限公司 薄膜晶体管、画素结构及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064021B2 (en) * 2003-07-02 2006-06-20 Au Optronics Corp. Method for fomring a self-aligned LTPS TFT
CN1567550A (zh) * 2003-07-04 2005-01-19 统宝光电股份有限公司 低温多晶硅薄膜晶体管的制作方法
US20050059191A1 (en) * 2003-09-17 2005-03-17 Hui-Chu Lin Method of fabricating low temperature polysilicon thin film transistor
KR100585410B1 (ko) * 2003-11-11 2006-06-07 엘지.필립스 엘시디 주식회사 구동회로 일체형 액정표시장치의 스위칭 소자 및 구동소자및 그 제조방법
US7598512B2 (en) * 2005-06-17 2009-10-06 Macronix International Co., Ltd. Thin film fuse phase change cell with thermal isolation layer and manufacturing method
KR101353269B1 (ko) * 2006-12-11 2014-01-20 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
KR101575750B1 (ko) * 2009-06-03 2015-12-09 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101248005B1 (ko) * 2009-11-17 2013-03-27 엘지디스플레이 주식회사 어레이 기판 및 그의 제조방법
KR20110084760A (ko) * 2010-01-18 2011-07-26 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
US9029825B2 (en) * 2010-06-16 2015-05-12 Nec Corporation Semiconductor device and manufacturing method for semiconductor device
CN102437196B (zh) * 2011-12-15 2013-04-03 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法
JP6013084B2 (ja) * 2012-08-24 2016-10-25 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
CN102890378B (zh) * 2012-09-17 2015-01-21 京东方科技集团股份有限公司 一种阵列基板及其制造方法
US9385195B1 (en) * 2015-03-31 2016-07-05 Stmicroelectronics, Inc. Vertical gate-all-around TFET

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093707A (ja) * 2001-07-19 2002-03-29 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2004170724A (ja) * 2002-11-20 2004-06-17 Sharp Corp 液晶表示装置の製造方法
KR20060074215A (ko) * 2004-12-27 2006-07-03 전자부품연구원 박막 트랜지스터 및 제조 방법
CN101626034A (zh) * 2008-07-08 2010-01-13 乐金显示有限公司 薄膜晶体管及其制造方法
CN102496625A (zh) * 2011-08-15 2012-06-13 友达光电股份有限公司 薄膜晶体管、画素结构及其制造方法

Also Published As

Publication number Publication date
US20160343875A1 (en) 2016-11-24
CN104617132B (zh) 2017-05-10
US20180108784A1 (en) 2018-04-19
US9905698B2 (en) 2018-02-27
WO2016106813A1 (zh) 2016-07-07
US10361316B2 (en) 2019-07-23

Similar Documents

Publication Publication Date Title
CN100463143C (zh) 具有氧化物间隔层的应变源漏cmos的集成方法
US8450167B2 (en) Method of fabricating semiconductor devices
CN103594370B (zh) 一种半导体器件的制造方法
CN103839783A (zh) 自对准双重图形的形成方法
CN105118807A (zh) 一种低温多晶硅薄膜晶体管及其制造方法
CN104425494B (zh) 用于替换栅极流程的内部l间隔件
CN102646603A (zh) 沟槽型mos的形成方法
US9478665B2 (en) Thin film transistor, method of manufacturing the same, display substrate and display apparatus
CN102005372A (zh) 制作半导体器件的方法
CN104538354B (zh) 一种ltps tft像素单元及其制造方法
CN104617132A (zh) 低温多晶硅薄膜晶体管及其制造方法
CN103681501B (zh) 一种半导体器件的制造方法
CN105552035A (zh) 低温多晶硅tft阵列基板的制作方法及其结构
CN102738243A (zh) 晶体管、阵列基板及其制造方法、液晶面板和显示装置
CN103377928A (zh) 半导体结构的形成方法、晶体管的形成方法
CN102361007A (zh) 沟槽刻蚀方法以及半导体器件
US20100258808A1 (en) Thin film transistor and manufacturing method thereof
CN103151264B (zh) 一种半导体器件的制造方法
CN104576387B (zh) 低温多晶硅薄膜晶体管制造方法
CN105789052A (zh) 一种低温多晶硅薄膜晶体管的制备方法及产品
CN102569180B (zh) 功率mos接触孔的制造方法
CN104779273B (zh) Cmos器件的栅极结构及其制造方法
CN103943509A (zh) 薄膜晶体管的制程方法
CN103258731B (zh) 避免硅衬底表面损伤的方法
CN102832129B (zh) 一种半导体器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant