Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/411—Insulated-gate bipolar transistors [IGBT]
  • H10D12/441—Vertical IGBTs
  • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
  • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
  • H10D62/126—Top-view geometrical layouts of the regions or the junctions
  • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/152—Source regions of DMOS transistors
  • H10D62/154—Dispositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/60—Impurity distributions or concentrations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
  • H10D84/151—LDMOS having built-in components
  • H10D84/153—LDMOS having built-in components the built-in component being PN junction diodes
  • H10D84/154—LDMOS having built-in components the built-in component being PN junction diodes in antiparallel diode configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
  • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices

Definitions

• the invention relates to the field of power electronics and more particularly to a reverse-conducting MOS device according to the preamble of claim 1 .
• RC-IGBT reverse-conducting insulated gate bipolar transistor
• BIGT Bi-mode Insulated Gate Transistor
• FIG 1 shows a prior art reverse-conducting insulated gate bipolar transistor (RC-IGBT) in form of a Bi-mode Insulated Gate Transistor (BIGT) 160
• BIGT Bi-mode Insulated Gate Transistor
• FIG 1 shows a prior art reverse-conducting insulated gate bipolar transistor (RC-IGBT) in form of a Bi-mode Insulated Gate Transistor (BIGT) 160
• IGBT insulated gate bipolar transistor
• the RC-IGBT comprises an anode side 27 (second main side) and a cathode side 20 (first main side), whereas the anode side 27 is arranged opposite of the cathode side 20 of the chip.
• the drift layer thickness 53 is the maximum vertical distance between the anode and cathode side 27 and 20 of that part of the chip with the drift layer doping concentration.
• the reverse-conducting semiconductor device comprises an active cell region 10, which is an area in the chip, which includes and is arranged below any of the source region 3, base layer 4 or gate layer 62.
• an n doped first layer 50 of higher doping concentration than the drift layer doping concentration of the drift layer and a p doped anode layer 55 are alternately arranged on the anode side 27.
• the first layer 50 comprises at least one or a plurality of n doped first regions 51 , wherein each first region has a first region width 52. Each first region width 52 is smaller than the drift layer thickness 53.
• the anode layer 55 comprises at least one or a plurality of p doped second regions 56 and at least one or a plurality of p doped pilot regions 58, wherein each second region 56 has a second region width 57 and each pilot region 58 has a pilot region width 59 (FIG 3).
• the at least one second region 56 is that part of the anode layer 55, which is not the at least one pilot region 58 (which will be defined in the following).
• a mixed region comprises the at least one first and second regions 51 , 56.
• the mixed region is arranged between the pilot region 58 and the active region border and has a width of at least once the base layer thickness 53.
• FIG 2 shows a cut through the line A' - A' of FIG 1 showing such a mixed region.
• Any region has a region width and a region area, which is surrounded by a region border.
• a shortest distance shall be the minimum length between a point within said region area and a point on said region border.
• Each region width is defined as two times the maximum value of all (i.e. any possible) shortest distances within said region.
• Each pilot region area is a p doped area, in which any two first regions 51 , which are arranged on the border of the pilot region 58, have a distance between two neighboured first regions 51 on the pilot region border smaller than two times the drift layer thickness 53.
• the pilot region width 59 is at least two times the drift layer thickness 53.
• the drift layer thickness 53 is at least 100 ⁇ (for a device of about 1200 V), at least 300 ⁇ (for a device of about 2500 V) and at least 500 um (for a device of about 4500 V).
• the pilot region width is at least 200 ⁇ , at least 600 ⁇ or at least 1000 ⁇ .
• the total area of the at least one pilot region 58 is between 10 % and 30 % of the area of the active region.
• the pilot region 58 is laterally surrounded on the pilot region border by first regions 51 , which have a distance from each other of less than two times the drift layer thickness 53, exemplarily smaller than once the drift layer thickness 53.
• No n doped region 51 is enclosed in this p doped pilot region 58. That means that the at least one first region 51 surrounds the at least one pilot region 58 in a plane parallel to the anode side 27 such that an n doped area (i.e. first region(s)), which has at least one opening (i.e.
• the first region 51 is a continuous region surrounding the pilot region 58 in a plane parallel to the anode side 27 or by having a first region 51 formed as an open ring having an opening smaller than two times the drift layer thickness 53.
• p doped areas have a width of less than two times the drift layer thickness 53 (and thus form second regions 56) are arranged.
• each pilot region area has a width larger than 2.5, in particular 3 times or 4 times the drift layer thickness 53.
• the pilot region has a pilot region area such that a circle (p doped area) having a diameter of at least two times the drift layer thickness 53 can be laid into the pilot region over the whole region area in a plane parallel to the anode side 27.
• the at least one pilot region 58 is arranged in the central part of the active region 10 in such a way that there is a minimum distance between the pilot region border to the active region border 580 of at least one time the drift layer thickness 53 (FIG 3).
• the pilot region 58 represents a pilot IGBT region, which is surrounded by shorted regions with alternating first and second doped regions 51 , 56 (mixed region).
• the at least one pilot region 58 is arranged in the central part of the device such that the mixed region laterally surrounds the at least one pilot region 58.
• the p-type pilot region 58 ensures snap-back free operation of the BIGT.
• the pilot region 58 can also be used to give more freedom to determine the IGBT to diode area ratio and decouple this design aspect from the standard approach involving the small second regions 56 only.
• the pilot region 58 represents a pilot IGBT region, which eliminates snap-back effects at low currents.
• the snap-back effect of a BIGT depends on the resistance of the drift layer, which in turn depends on the resistivity and thickness of the drift layer 53. For devices having a greater drift layer thickness 53, the voltage drop across the drift layer is larger. Therefore, also the total on-state voltage drop is higher for such devices, and snap-back effect occurs at higher voltages.
• pilot region a sufficiently large p doped region
• a minimum distance between this pilot region 58 and the border of the active region is essential for good thermal performance and improvement of the device SOA since the pilot IGBT does not include transition parts of the chip such as those from active to termination regions. Furthermore, by using a pilot region 58, snap-back behaviour is improved compared to distributed smaller pilot regions.
• the first and second regions 51 , 56 form the main shorted region in which the silicon area included is utilized in both IGBT and diode mode.
• the n doped anode shorts (first layer) conduct electron current during the turn-off and give rise to the FCE effect which greatly improves turn-off softness of the BIGT device.
• a prior art reverse conducting (RC)-IGBT or BIGT device the p-base layers of the MOS cells are utilized as anode regions of the internal freewheeling PIN diode.
• the MOS cells are terminated at the termination region with deeper and higher doped p-bars, which also act as additional diode anode regions. These additional p-bars are not shorted by the MOS channel and are therefore essential for achieving snap-back free diode mode characteristics, as is described in the patent application US 2013/0099279 A1 .
• the SOA of the freewheeling diode is affected strongly by the design of the p-bars contact with the termination region in the areas around the active area of the BIGT/RC-IGBT.
• the standard design of the RC IGBT and BIGT uses the additional p-bars which are diffused deeper and are higher doped compared to the p-base layer of the MOS cell. They contact the p base layer in an area, in which no MOS channel is formable.
• the p-bars and termination act as anode regions and inject holes into the n-drift layer.
• the electrical field maximum is near the deep and highly doped p-bars, and as a result the reverse current becomes concentrated in these areas.
• a current filament in which holes are highly concentrated in a small area, is created at the curvature of the p-bar.
• a locally high temperature is created in the filament which might lead to device destruction and therefore lowers the diode mode SOA as shown by Prior art curve in the thermodynamic simulation (FIG 4).
• WO 2014/054319 A1 shows an IGBT, which comprises on the first main side p doped diffused regions, which have increased distance to each other with increasing distance from the active cell region.
• the inner p regions close to the active cell region are connected to the cathode electrode, whereas in the outer region the p regions are separated from each other by the drift layer, so that they function as field rings.
• the inventive reverse-conducting MOS device has a first main electrode on a first main side and a second main electrode on a second main side opposite to the first main side.
• the device has an active cell region and a termination region laterally surrounding the active cell region up to an edge of the device.
• the active cell region comprises a plurality of MOS cells, each of which comprises between the first main and second main side a source layer of a first conductivity type, a base layer of a second conductivity type, which is different from the first conductivity type, a drift layer of the first conductivity type and a first layer of the first conductivity type, which is higher doped than the drift layer.
• a gate electrode is arranged on the first main side.
• a bar of the second conductivity type which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region and encloses the active cell region in a plane parallel to the first main side.
• the bar is electrically connected to the first main electrode via the base layer of the second conductivity type or by direct contact.
• variable-lateral-doping layer of the second conductivity type On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged, in which for all depths in the variable- lateral-doping layer the doping concentration decreases towards the edge of the device.
• the variable-lateral-doping layer is connected to the bar so that avalanche can start at the bar and spread then towards a protection layer through the variable-lateral-doping layer.
• a protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.
• the VLD layer is used for reducing the electric field in the termination region.
• the VLD layer is connected to the bar and as the protection layer is embedded in the VLD layer, the electric field is reduced in a small distance, i.e. the need to have a wide field ring structure.
• the holes are directed not into a small spot area at the interface between the bar and the variable-lateral doping-layer, but they are spread more widely within the protection layer and an additional resistance is introduced into the filament path which reduces the filament current.
• This effect can further be enhanced by having a protection layer with a plurality of protection regions, exemplarily by having ring-shaped regions (protection rings) surrounding the active cell region , each of which encloses the active cell region and which separated from each other by the lower doped VLD layer.
• the protection regions which are farer away from the bar region, enclose the protection regions, which are nearer to the bar region, in a plane parallel to the first main side.
• the protection regions being embedded in the VLD layer, in planes parallel to the first main side, a modulated doping profile (of the second conductivity type) is achieved, in which at the protection regions a higher doping concentration is present than at the VLD layer in-between such protection regions.
• the device has up to 5 protection rings or between 3 and 5 protection rings as protection regions.
• Inventive RC-IGBT1 contains five protection regions with decreasing widths and Inventive RC-IGBT2 contains two protection regions with constant widths.
• the hole current is spread out and does not focus into a narrow filament.
• peak temperature in the device is reduced which in turn provides much better turn-off capability of the diode and much better SOA performance in diode mode is achievable.
• the invention combines the advantage of keeping the temperature low in the device with a small termination width (i.e. having a small width in a direction of increasing distance from the active cell region).
• the invention can be applied to reverse conducting MOS devices, i.e. to devices having a MOS cell and enabling reverse conducting mode. That means for a MOS with an n- MOS channel an n doped first layer is arranged on the second main side and for a p- MOS a p doped first layer is arranged on the second main side.
• Such an inventive RC MOS device can be a MOSFET or a RC-IGBT.
• the RC- IGBT may also be designed as a BIGT.
• FIG 1 shows a cross sectional view on a prior art reverse-conducting IGBT
• FIG 2 shows a plan view of the structures of first and second regions of a prior art reverse-conducting IGBT
• FIG 3 shows a plan view of the structures of first and second regions of another prior art reverse-conducting IGBT
• FIG 4 Time dependence of the temperature in the filament of a prior art device and an inventive devices during diode mode turn-off
• FIG 5 shows a cross sectional view on an inventive reverse-conducting
• MOSFET having three protection regions
• FIG 6 shows a cross sectional view on an inventive reverse-conducting IGBT having one protection region
• FIG 7 shows a cross sectional view on an inventive reverse-conducting IGBT having three protection regions
• FIG 8 shows a cross sectional view on an inventive reverse-conducting IGBT having a buffer layer
• FIG 9 shows a cross sectional view on an inventive reverse-conducting IGBT having protection regions with decreasing widths
• FIG 10 shows a cross sectional view on an inventive reverse-conducting IGBT having protection regions with increasing distance between neighbored protection regions
• FIG 1 1 shows a top view on an inventive reverse-conducting IGBT having three protection regions
• FIG 12 shows a top view on an inventive reverse-conducting IGBT having a perforated ring of protection zones
• FIG 13 shows a cross sectional view on an inventive MOSFET having a direct contact between the bar 9 and the first main electrode 2;
• FIG 14 shows a view in a plane parallel to the first main side 20 indicating a line
• FIG 5 a first embodiment of an inventive reverse-conducting (RC) MOS (metal oxide semiconductor) device 1 in form of a metal-oxide-semiconductor field-effect transistor (MOSFET) 100 is shown.
• the MOSFET 100 comprises a first main electrode 2, which is a source electrode for a MOSFET, on a first main side 20 and a second main electrode 25, which is a drain electrode for the MOSFET 100, on a second main side 27 opposite to the first main side 20.
• the device has an active cell region 10 (central region, which shall be a MOS cell region, i.e. such region, in which the MOS cells 1 1 are arranged) and a termination region 12 laterally surrounding the active cell region 10 up to an edge 14 of the device.
• the edge is arranged as the surface of the device between the first and second main side 20, 27 of the device.
• the first main side 20 shall be the surface of the doped layers on the side towards the first main electrode 2. It shall be a plain plane farthest away from the second main electrode 25.
• the active cell region 10 comprises a plurality of MOS cells 1 1 , each of which comprises between the first main and second main side 20, 27 an n doped source layer 3, a p doped base layer 4, an (n-) doped drift layer 5 and an n doped first layer 50, which is higher doped than the drift layer (5).
• the first layer is a drain layer for the MOSFET 100.
• the at least one source region 3, the gate layer 5 and the insulating layer 6 are arranged such that an opening is available above the base layer 4, at which opening the base and source layer 4, 3 contact a source electrode 2.
• the opening is surrounded by the at least one source layer 3, the gate layer 5 and the insulating layer.
• the active cell region 10 is the area in which the device conducts current during on-state, in the case of a RC-IGBT or a MOSFET, this is the MOS cell(s) 1 1 .
• the device may comprise one or more MOS cells 1 1 .
• a gate electrode 6 is arranged on the first main side 20.
• the MOS cell shall be an area having a MOS structure on the first main side with a gate electrode 6 and a source layer 3 and a base layer 4, at which layers a MOS channel is created during device operation (MOS channel, in which electrons flow from the source layer 3, through the base layer 4 to the drift layer 5).
• the active cell region 10 is that area within the device, which includes the source region 3 and base layer 4 and the area, which is arranged below (in projection to) the source layer 3, base layer 4 and gate layer 62.
• the area is meant which is arranged in the device 1 between the first main side 20 and the second main side 27, in which area any of the source layer 3, base layer 4 or gate layer 62 are arranged.
• the gate electrode 6 comprises an electrically conductive gate layer 62 and an insulating layer, which electrically insulates the gate layer 62 from the at least one base layer 4, the source layer 3 and the drift layer 5.
• the gate layer 5 is embedded and completely covered by the insulating layer.
• the insulating layer comprises a first electrically insulating layer 64, preferably made of a silicon dioxide, and a second electrically insulating layer 66, preferably also made of a silicon dioxide,.
• the second electrically insulating layer 66 covers the first electrically insulating layer 64.
• the first electrically insulating layer 64 is arranged on top of the first main side 20.
• the gate layer 62 is embedded, exemplarily it is completely embedded.
• the gate layer 62 is separated from the drift layer 5, the source layer 3 and the base layer 4 by the first electrically insulated layer 64.
• the gate layer 62 is exemplarily made of a heavily doped poly- silicon or a metal like aluminum.
• the gate electrode 6 may also be designed as a trench gate electrode.
• the trench gate electrode comprises an electrically conductive layer 62 and a first electrically insulating layer 64, which surrounds and thus separates the electrically conductive layer 62 from the drift layer 5, the base layer 4 and the source layer 3.
• a second insulating layer 66 is arranged between the electrically conductive layer 62 and the first main electrode 2.
• the trench gate electrode is arranged lateral to the base layer 4 in a plane parallel to the first main side 20.
• the trench gate electrode extends from the first main side 20 up to a trench gate electrode depth.
• the first and second insulating layers 64, 66 may be made of an insulating material, wherein also a dielectric like a metal oxide, exemplarily Silicon dioxide, shall be considered as an insulating layer.
• the covering second insulating layer 66 can also be made as a stack of different insulating layers.
• the insulating layer being a metal oxide layer
• MOS channel metal oxide semiconductor
• MIS channel metal insulator semiconductor
• MOS devices metal insulator semiconductor
• any appropriate electrically conductive material like a metal or poly-silicon may be used.
• the drift layer 5 is an (n-) doped layer of low doping concentration.
• the drift layer 5 has a constantly low doping concentration.
• substantially constant doping concentration of the drift layer 5 shall mean that the doping concentration is substantially homogeneous throughout the drift layer 5, however without excluding that fluctuations in the doping concentration within the drift layer being in the order of a factor of one to five may be possibly present due to e.g. a fluctuations.
• the final drift layer thickness and doping concentration is chosen due to the application needs.
• An exemplary doping concentration of the drift layer 5 is between 5 * 10 12 cm 3 and 5 * 10 14 cm 3 .
• a first main electrode 2 which is a source electrode for a MOSFET 100, is arranged on the first main side 20 within the opening so that it is in direct electrical contact to the base layer 4 and the source layer 3.
• This source electrode exemplarily also covers the insulating layer 64, 66, but is separated and thus electrically insulated from the gate layer 62 by the second electrically insulating layer 66.
• the base layer 4 comprises a base region 41 and a contact layer 40, which is higher doped than the base region 41 .
• the contact layer 40 contacts the source electrode 2 and improves the contact properties and maximum turn-off current capability, whereas the base region 41 separates the source layer 3 form the drift layer 5. It is arranged below the contact layer 40 and laterally surrounds the contact layer 40.
• the contact layer 40 is shown in the figures as a dashed line to indicate that this layer is an exemplary embodiment.
• a p+ highly doped bar 8 which has a higher maximum doping concentration than the base layer 4, is arranged between the active cell region 10 and the termination region 12.
• the bar 8 is a ring shaped such that it encloses the active cell region 10 laterally, i.e. in a plane parallel to the first main side 20.
• the ring shaped bar 8 (bar 8 closed-in-itself and laterally, i.e. in a plane parallel to the first main side 20, enclosing the active cell region 10) can exemplarily have a design of a rectangle with rounded corners.
• the bar 8 is electrically connected to the first main electrode 2 via the base layer 4 or directly.
• FIGs 5 to 10 show a connection of the p bar 98 via the base layer 4 and to the first main electrode 2 and FIG 13 shows a direct connection from the bar 8 to the first main electrode 2.
• FIG 13 shows a direct connection from the bar 8 to the first main electrode 2.
• the bar 8 is connected to the base layer 4 and also directly connected to the first main electrode 2 or any other connection, by which the bar 8 is connected to the first main electrode 2 shall be covered by the invention.
• FIG 14 shows another exemplary embodiment, in which the MOS cells 1 1 are indicated by the p base layer 4.
• FIG 14 is a cut in a plane parallel to the first main side 20 in a depth, in which the p base layer 4, p+ bar 8, VLD layer 7 and protection layer 9 as three protection rings 90 are arranged (see also the line A - A in FIG 5, which line is also shown in FIG 14).
• the VLD layer is shown by the dotted area, the lighter dotted regions indicating the decreasing doping concentration towards the lateral sides (edges) of the device.
• the overlap of the base layer 4 and bar 8 shall indicate the connection of these two layers, by which the bar is connected to the first main electrode 2.
• the bar 8 may have a width between 10 to 200 ⁇ . Width shall correspond to a maximum diameter of a circle, which can be laid into the bar in a plane parallel to the first main side 20.
• the bar 8 can be designed to be partially floating (by contacting the bar 8 to first main electrode 2 via the base layer 4; see FIG.s 5 to 10) or non-floating (the bar 8 directly contacting the first main electrode 2; see FIG 13) depending on the optimum injection from the additional p-bar region desired or both connections are realized in the same device.
• the bar 8 may contact the first main electrode 2 at a bar contact area, which is at most 10 % of the bar area at the first main side surface.
• connection area is the area, in which said bar 8 adjoins the base layer 4.
• the base layer 4 contact the bar 8 in a connection area, which is less than 1 % said base layer surface area. If a bar 8 is electrically connected to the first main electrode 2 directly by placing the first main electrode 2 on the bar 8, the connection area can be adjusted.
• the first main electrode 2 may contact the bar 8 in the area which is less than 10 % or even less than 1 % of said bar surface area.
• VLD variable-lateral- doping
• the doping concentration decreases laterally (i.e. in a plane parallel to the first main side 20) towards the edge 14 of the device (notwithstanding local doping fluctuations which might occur due to the production method).
• the lateral decrease of doping concentration is available for all depths of the VLD layer 7.
• the VLD layer is connected to the bar 8.
• the VLD layer 7 has a thickness of up to 15 ⁇ .
• the VLD layer 7 is a contiguous layer surrounding the MOS cell region 10 and being contiguous in a direction of increasing distance from the MOS cell region 10, so that all areas of the VLD layer 7, and thereby also of the protection layer 9 are weakly connected to the first main electrode via the VLD layer 7 contacting the bar 8.
• the VLD layer 7 is a diffused layer, for which the doping concentration (doping profile, which shall be the doping concentration of the layer in depth direction, i.e. in a direction perpendicular to the first main side 20) decreases from a local maximum doping concentration continuously for greater depths from the first main side 20. Furthermore, the local maximum doping concentration of the VLD layer 7 (of such a doping profile) decreases with increasing distance, i.e. laterally, from the active cell region 10. Exemplarily also the thickness of the VLD layer varies such that for increasing distance from the active cell region 10 the thickness decreases.
• the doping concentration doping profile, which shall be the doping concentration of the layer in depth direction, i.e. in a direction perpendicular to the first main side 20
• the local maximum doping concentration of the VLD layer 7 decreases with increasing distance, i.e. laterally, from the active cell region 10.
• the thickness of the VLD layer varies such that for increasing distance from the active cell region 10 the thickness decreases
• the VLD layer 7 has local maximum doping concentrations, which shall be the maximum doping concentration of a doping profile at any place in the VLD layer 7, and a maximum doping concentration, which shall be the maximum value of all doping concentrations in the VLD layer 7, i.e. also the maximum value of all local maximum doping concentrations.
• a p+ doped protection layer 9 is arranged in the termination region 12 and within the variable-lateral-doping layer 7.
• the protection layer 9 has a higher maximum doping concentration than the (local) maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer 9.
• the protection layer 9 has a higher maximum doping concentration than all local maximum doping concentrations of the VLD layer 7.
• the protection layer 9 may have a maximum doping concentration, which it at least 10 times, 100 times or 1000 times higher than the local maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer 9 or at least 10 times, 100 times or 1000 times higher than the maximum doping concentration of the variable-lateral-doping layer, which is the absolute) maximum doping concentration.
• the doping profile of the p dopant is modulated by the introduction of the protection layer 9.
• a protection layer 9 having ring-shaped protection regions 90 this leads to a modulation of the doping concentration, i.e. higher doping concentration (protection ring 90) and lower doping concentration (VLD layer 7) alternate in a direction of increasing distance from the MOS cell region 10, overlaid with the decreasing doping concentration of the VLD layer with increasing distance from the MOS cell region 10.
• An inventive device with up to 5 protection rings or between 3 and 5 protection rings as protection regions already efficiently reduces the electric field in the termination region 12.
• the bar 8 and the protection layer 9 have the same maximum doping concentration or the same thickness or the same maximum doping concentration and the same thickness.
• the protection layer 9 may have a maximum doping concentration of at most 5 * 10 18 cm 3 or 5 * 10 16 cm 3 or even below 5 * 10 15 cm 3 .
• the thickness of the protection layer 9 may be between 6 to 20 ⁇ , exemplarily up to 9 ⁇ .
• the width of the protection layer 9 may be at most 20 ⁇ .
• the protection layer 9 has a thickness, which is shallower than the thickness of the VLD layer 7.
• the thickness of the protection layer may be up to 9 ⁇ and the thickness of the VLD layer 7 up to 15 ⁇ .
• the inventive device 1 may also be a reverse-conducting insulated gate bipolar transistor (RC-IGBT) 150, which differs from the MOSFET 100 disclosed above in that the RC-IGBT 150 comprises on the second main side 27 a second layer 55, which forms a collector layer for the IGBT.
• the first main electrode 2 forms an emitter electrode for the RC-IGBT.
• the RC-IGBT 150 may also be designed as a Bi-mode Insulated Gate Transistor (BIGT) (i.e. comprises p doped pilot regions) as described above for the prior art BIGTs, but having the inventive structure in and at the termination region 12 of bar 8, VLD layer 7 and protection layer 9.
• BIGT Bi-mode Insulated Gate Transistor
• the RC-IGBT 150 may further comprise an n type buffer layer 54, which is arranged between the drift layer 5 and the first and second layer respectively, and which buffer layer 54 has a higher doping concentration than the drift layer 5.
• the buffer layer 54 has preferably a maximum doping concentration of at most 1 * 10 17 cm 3 .
• the protection layer 9 may comprise at least one ring-shaped region 90 (FIG 1 1 ), i.e. a region forming a ring (in a plane parallel to the first main side 20) around the active cell region 10.
• the ring shall be a shape closed-in-itself, which surrounds the active cell region 10 in a plane parallel to the first min side 20.
• the ring encloses the active cell region 10 in a constant distance.
• the device may also comprise a plurality of such rings, wherein all subsequent rings have a greater distance to the active cell region 10 (see also FIG 7) and are separated from each other by a VLD layer 7.
• the protection layer 9 may comprise a plurality of protection zones 92, which surround the active cell region 10.
• Such protection zones may have in an exemplary embodiment a distance between two neighboured protection zones 92 of at most 50 ⁇ or at most 20 ⁇ (FIG 12).
• such protection zones 92 could be placed only at positions, at which high filament current may be expected, e.g. in the corners of a device for a device having e.g. a rectangular/square shape.
• the protection zones 92 surrounding the active cell region 10 form a perforated ring having opening between neighboured protection zones 92 wherein the openings have a distance of at most 50 ⁇ or at most 20 ⁇ .
• the protection zones 92 of such a perforated ring may be arranged in the constant distance to the active cell region 10.
• the width of neighboured protection region 90 or perforated rings of protection zones 92 may be constant or varying. In an exemplary embodiment, the width of successively following protection regions 90/perforated rings of protection zones 92 decreases in a direction towards the edge 14 of the device (FIG 9). For a device comprising at least two rings (protection regions 90) or perforated rings, the width of each ring may be at most 20 ⁇ .
• the distance between two neighboured protection regions 90 or perforated rings of protection zones 92 may be between 1 to 30 ⁇ . This distance may be constant for all neighboured protection regions 90.
• the distance between two rings i.e. the borders of the rings facing each other
• the protection layer may also be a VLD layer as defined before such that the local maximum doping concentration decreases with increasing distance from the active cell region 10, i.e. towards the edge 14 of the device.
• a VLD layer as defined before such that the local maximum doping concentration decreases with increasing distance from the active cell region 10, i.e. towards the edge 14 of the device.
• such a device comprises two VLD layers 7 and 9, wherein the VLD layer 7 encloses the VLD protection layer 9.
• a passivation layer 69 can be provided over the termination region of the substrate to equalize charge distribution across the termination region and to avoid local accumulations of charge which could cause zones of increased recombination or distort the local doping characteristics of the substrate and therefore also the local electric field gradients.
• SIPOS semi-insulating polysilicon
• European patent application EP 0651435 describes a field plate made from a thin resistive film of semi-insulating polycrystalline silicon (SIPOS, also known as Polydox) deposited on the silicon substrate or sandwiched between two oxide layers in order to reduce thermo-mechanical stresses.
• SIPOS is an example of a semi-insulating material.
• the term "semi-insulating" material is used in this application to refer to undoped semiconductor materials having a very high resistivity (typically greater than 107 ⁇ cm) and a very low intrinsic carrier concentration (relatively wide energy gap).
• SIPOS is an oxygen-containing polycrystalline silicon film with an extremely high (but finite) resistivity, but which nevertheless has a small conductivity which allows the flow of a leakage current. Since the resistivity of a SIPOS layer 69 is the same in every lateral direction, the small leakage current makes the field at the silicon surface more uniform, thus relieving the surface electric field and providing a field- shield effect for the passivated surfaces. SIPOS films have the added advantage that they are electrically almost neutral (typically little or no doping), and therefore do not modify the space-charge regions of any adjacent junctions.
• the SIPOS layer 69 may be covered by a further insulating layer 68, which may exemplarily be made of Silicon nitride. However, it is also possible to cover the termination region by a third insulating layer 67.
• an n doped enhancement layer is arranged between the base layer 4 and the drift layer 5 for having lower on-state losses.
• the enhancement layer separates the base layer 4 from the drift layer 5 and it has higher doping concentration than the drift layer 5.
• the enhancement layer 41 can be present in planar gate designs as well as in trench gate designs.
• the conductivity types of the layers are switched, i.e. all layers of the first conductivity type are p type (e.g. the drift layer 5) and all layers of the second conductivity type are n type (e.g. the base layer 4).
• the inventive reverse-conducting MOS device 1 can for example be used in a converter.

Landscapes

• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Thyristors (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Related Child Applications (1)

Publications (1)

Family

ID=52231999

Family Applications (1)

Country Status (5)

Cited By (3)

Families Citing this family (12)

Citations (6)

Family Cites Families (12)

• 2015
  • 2015-12-22 JP JP2017533808A patent/JP7030515B2/ja active Active
  • 2015-12-22 EP EP15819822.6A patent/EP3238260B1/en active Active
  • 2015-12-22 WO PCT/EP2015/080947 patent/WO2016102549A1/en not_active Ceased
  • 2015-12-22 CN CN201580070745.8A patent/CN107112353B/zh active Active
• 2017
  • 2017-06-22 US US15/630,491 patent/US10109725B2/en active Active

Patent Citations (7)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events