WO2016078400A1 - 一种肖特基二极管及其制作方法 - Google Patents

一种肖特基二极管及其制作方法 Download PDF

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WO2016078400A1
WO2016078400A1 PCT/CN2015/081501 CN2015081501W WO2016078400A1 WO 2016078400 A1 WO2016078400 A1 WO 2016078400A1 CN 2015081501 W CN2015081501 W CN 2015081501W WO 2016078400 A1 WO2016078400 A1 WO 2016078400A1
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anode
trench
field plate
semiconductor layer
layer
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PCT/CN2015/081501
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English (en)
French (fr)
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陈洪维
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苏州捷芯威半导体有限公司
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Priority to JP2017500024A priority Critical patent/JP6474881B2/ja
Publication of WO2016078400A1 publication Critical patent/WO2016078400A1/zh
Priority to US15/382,562 priority patent/US9985143B2/en
Priority to US15/967,257 priority patent/US10367101B2/en

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    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a Schottky diode and a method of fabricating the same.
  • the diode In the field of high voltage switch applications, it is desirable for the diode to have a small reverse leakage, a large reverse voltage, and a small forward voltage drop.
  • gallium nitride materials are mainly epitaxially grown on heterogeneous materials, and the defect density of gallium nitride materials is still at a relatively high level (generally 10 8 cm -3 ), so the vertical structure of gallium nitride Schottky The diode still does not achieve the desired performance.
  • high electron mobility devices HEMTs
  • HEMTs high electron mobility devices based on two-dimensional electron gas channels with high electron mobility in the horizontal direction formed by aluminum gallium nitride/gallium nitride heterostructures have been widely used in radio frequency and power. The field of electronics.
  • GaN is a wide bandgap semiconductor material
  • the material has a critical breakdown electric field about 10 times larger than the silicon material and a corresponding high withstand voltage characteristic.
  • it is due to the two-dimensional electron gas channel.
  • the channel provides very small on-resistance, which reduces the power loss of the switching device. Therefore, horizontal diodes based on aluminum gallium nitride/gallium nitride heterostructures have gradually become important research objects in the industry.
  • the thickness of the aluminum gallium nitride barrier layer between the Schottky metal and the two-dimensional electron gas is generally Up to about 20 nm, so a relatively large Schottky barrier thickness is formed, and a high surface state density of the aluminum gallium nitride barrier layer forms a Fermi level pinning effect, so that the Schottky barrier height is relatively large, thereby The Schottky forward turn-on voltage is large (>1V), which is not conducive to reducing the conduction loss of the diode.
  • an anode trench structure is proposed to remove the aluminum gallium nitride barrier layer and a portion of the gallium nitride channel layer by etching in the anode region, and then deposit an anode metal to make the anode
  • the metal forms a gold half contact with the two-dimensional electron gas channel from the sidewall, thereby eliminating the thickness of the Schottky barrier formed by the 20 nm thick aluminum gallium nitride barrier layer, and reducing the forward turn-on voltage of the diode ( ⁇ 0.7).
  • the high electron mobility two-dimensional electron gas channel provides a very low on-resistance, resulting in a high performance Schottky diode with low turn-on voltage and low on-resistance.
  • the hole concentration in the two-dimensional electron gas channel is very low, and thus has a very small reverse recovery time.
  • existing GaN Schottky diodes still have deficiencies. For example, a field-induced electron emission or electron tunneling effect at a high electric field causes an increase in reverse leakage, resulting in a decrease in withstand voltage characteristics of the device.
  • the anode 21 employs a two-layer composite dielectric layer structure in which a layer 22 The stepped field plate structure is formed in the middle layer, and the other layer 23 is a passivation layer, which serves to reduce the peak electric field and increase the breakdown voltage.
  • the bottom metal of the anode 31 trench forms a Schottky contact with the semiconductor material 32 to form an anode structure.
  • the field plate Under the applied reverse bias voltage, the field plate can reduce the reverse leakage of the Schottky diode by reducing the electric field strength at the position of the Schottky junction. Increase the breakdown voltage of the Schottky diode in the off state.
  • the reverse bias voltage applied across the anode will be completely applied to the reverse bias Schottky before depleting the two-dimensional electron gas of the lower channel. Above the knot.
  • the thickness of the passivation dielectric layer generally needs to reach a thickness of about 100 nm, compared to the thickness of the aluminum gallium nitride barrier layer (generally 20 nm).
  • silicon nitride is generally used as a passivation dielectric layer, and its dielectric constant is lower than that of aluminum gallium nitride, so that the voltage required to deplete the two-dimensional electron gas is large, which means that Before the two-dimensional electron gas channel is depleted and the field plate acts to moderate the electric field, the Schottky junction has been subjected to a large reverse bias, and the field-induced electron emission and tunneling effects cause reverse leakage. Increased, so the reverse leakage is still at a relatively high level.
  • the present invention has been made to solve the above-mentioned deficiencies in the prior art, and an object of the present invention is to provide a Schottky diode and a method of fabricating the same.
  • the Schottky diode can solve the problem that the metal/two-dimensional electron gas Schottky junction in the prior art gallium nitride heterostructure has a large leakage under the anode reverse bias voltage.
  • the present invention employs the following technical solutions:
  • the present invention provides a Schottky diode comprising:
  • a second semiconductor layer is disposed on the first semiconductor layer, and a two-dimensional electron gas is formed at an interface between the first semiconductor layer and the second semiconductor layer;
  • a cathode located above the second semiconductor layer, wherein the cathode forms an ohmic contact with the second semiconductor layer;
  • An anode trench the anode trench being located within the first passivation dielectric layer and the second semiconductor layer, and a bottom of the anode trench extending to an area where the two-dimensional electron gas is located or passing through The two-dimensional The area where the electron gas is located;
  • the field plate trench is located in the first passivation dielectric layer between the anode trench and the cathode, and a bottom of the field plate trench is located in the first passivation dielectric layer Internally extending to the upper surface of the second semiconductor layer or extending into the second semiconductor layer;
  • An anode the anode covering the anode trench, the field plate trench, and a first passivation dielectric layer between the anode trench and the field plate trench, an anode in the anode trench
  • the second semiconductor layer forms a Schottky contact, and the field plate trench and the anode on the first passivation dielectric layer constitute an anode field plate.
  • a field plate trench dielectric layer the field plate trench dielectric layer being over the first passivation dielectric layer outside the field plate trench and over the field plate trench.
  • the anode also covers a portion of the first passivation dielectric layer outside the trench of the field plate.
  • a second passivation medium layer is deposited on the anode, and a second anode field plate is deposited on the second passivation medium layer, and the second anode field plate is electrically connected to the anode.
  • a third passivation dielectric layer is deposited on the second anode field plate, and a third anode field plate is deposited on the third passivation dielectric layer, and the third anode field plate and the anode are electrically connection.
  • the second semiconductor layer includes a first barrier layer and a second barrier layer.
  • a barrier layer is deposited between the first barrier layer and the second barrier layer.
  • first barrier layer and the second barrier layer material are aluminum gallium nitride; the first barrier layer has an aluminum component of 10-15%, and the first barrier layer has a thickness of 5 -15 nm; the second barrier layer has an aluminum component of 20-45%, and the second barrier layer has a thickness of 15-50 nm.
  • the barrier layer material is aluminum nitride.
  • any one side of the anode trench is a combination of any one or at least two of a straight line, a broken line or an arc, and any one side of the anode groove and the bottom of the anode groove
  • the angle is a right angle, an obtuse angle or an acute angle.
  • a cross-sectional shape of any one side surface of the field plate trench is a combination of any one or at least two of a straight line, a broken line or an arc, and any one side of the field plate groove and the field plate groove
  • the angle between the bottom of the groove is a right angle, an obtuse angle or an acute angle.
  • a combination of any one or at least two of a nucleation layer, a buffer layer or a back barrier layer is sequentially deposited between the substrate and the first semiconductor layer.
  • the nucleation layer material is aluminum nitride, gallium nitride or other III-V nitride;
  • the buffer layer material is undoped aluminum nitride, gallium nitride, aluminum gallium nitride or other III a group V nitride;
  • the back barrier layer material is aluminum gallium nitride, and the back barrier layer has an aluminum component of 5-8%.
  • the substrate material is silicon carbide, silicon, sapphire, aluminum nitride, gallium nitride or other substrate material capable of growing a group III-V nitride;
  • the first semiconductor layer material is undoped nitrogen a gallium layer;
  • the second semiconductor layer material is aluminum gallium nitride or other III-V nitride.
  • the present invention provides a method of fabricating a Schottky diode, comprising:
  • An anode trench is formed in the first passivation dielectric layer and the second semiconductor layer between the cathodes, and a bottom of the anode trench extends to a region where the two-dimensional electron gas is located or passes through the two-dimensional The area where the electron gas is located;
  • An anode is formed on a passivation dielectric layer.
  • anode trench or field plate trench is prepared by a dry etching and/or a wet etching process.
  • the Schottky diode of the present invention can solve the problem that the metal/two-dimensional electron gas Schottky junction in the prior art gallium nitride heterostructure has a large leakage under the anode reverse bias voltage, and also retains the nitridation.
  • the forward voltage of the gallium diode is small and the forward conduction resistance is low.
  • 1 to 3 are schematic cross-sectional views of a Schottky diode in the prior art.
  • FIG. 4 is a cross-sectional view of a Schottky diode according to Embodiment 1 of the present invention.
  • 5A and 5B are graphs comparing the electrical characteristics of the Schottky diode of the prior art shown in Fig. 1 with the electrical characteristics of the Schottky diode provided in the first embodiment of the present invention.
  • FIG. 6A and FIG. 6B are respectively an electron concentration distribution diagram of a Schottky diode according to Embodiment 1 of the present invention when the same reverse bias voltage is applied to the anode, and an electron concentration distribution of the Schottky diode in the prior art shown in FIG. Figure.
  • FIG. 7A and FIG. 7B are respectively an electric field distribution diagram of the Schottky diode provided in Embodiment 1 of the present invention and an electric field distribution diagram of the Schottky diode in the prior art shown in FIG. 1 when the same reverse bias voltage is applied to the anode.
  • FIG. 8 is a cross-sectional view of a Schottky diode according to a second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view of a Schottky diode according to a third embodiment of the present invention.
  • Figure 10 is a cross-sectional view showing a Schottky diode according to a fourth embodiment of the present invention.
  • Figure 11 is a cross-sectional view showing a Schottky diode according to a fifth embodiment of the present invention.
  • Figure 12 is a cross-sectional view showing a Schottky diode according to a sixth embodiment of the present invention.
  • Figure 13 is a cross-sectional view showing a Schottky diode according to a seventh embodiment of the present invention.
  • Figure 14 is a cross-sectional view showing a Schottky diode according to Embodiment 8 of the present invention.
  • Figure 15 is a cross-sectional view showing a Schottky diode according to a ninth embodiment of the present invention.
  • Figure 16 is a cross-sectional view showing a Schottky diode according to a tenth embodiment of the present invention.
  • Figure 17 is a cross-sectional view showing a Schottky diode according to an eleventh embodiment of the present invention.
  • Figure 18 is a flow chart showing a method of fabricating a Schottky diode according to a twelfth embodiment of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the Schottky diode includes:
  • the substrate 1 wherein the material of the substrate 1 may be gallium nitride, silicon, sapphire, silicon nitride, aluminum nitride, SOI or other substrate material capable of epitaxially growing a group III-V nitride.
  • the material of the nucleation layer 2 may be aluminum nitride or gallium nitride
  • the material of the buffer layer 3 may be a graded layer of aluminum gallium nitride or a superlattice material
  • the material of the first semiconductor layer 4 may be gallium nitride.
  • the material of the second semiconductor layer 6 may be aluminum gallium nitride, and a two-dimensional electron gas 7 is formed at the interface of the first semiconductor layer 4 and the second semiconductor layer 6.
  • a cathode 5 is formed on the second semiconductor layer 6, wherein the material of the cathode 5 is a metal, and the cathode 5 forms an ohmic contact with the second semiconductor layer 6.
  • a first passivation dielectric layer 8 is deposited on the second semiconductor layer 6 between the cathodes 5, wherein the first passivation dielectric layer 8 can function to suppress the current collapse effect caused by the surface state of the aluminum gallium nitride.
  • the material of the first passivation dielectric layer 8 may be any one or a combination of at least two of silicon nitride, silicon dioxide, silicon oxynitride, fluoride or aluminum oxide.
  • An anode trench structure is formed in the first passivation dielectric layer 8 and the second semiconductor layer 6 between the cathodes 5.
  • a field plate trench structure formed in the first passivation dielectric layer 8 between the anode trench and the cathode metal.
  • the dry etching method can be used, and the different etching rates in the longitudinal direction and the lateral direction can be controlled to obtain the trench structure of different shapes, or can be formed by a wet etching process.
  • the angle between the side and the bottom of the groove is a right angle, an obtuse angle or Any one of the acute angles or a combination of the two, the specific dimensions of the grooves may be determined according to design requirements.
  • the bottom of the anode trench structure may reach or pass through the two-dimensional electron gas 7 and extend into the second semiconductor layer 6.
  • the bottom of the field plate trench structure may reach or exceed the upper surface of the second semiconductor layer 6 to extend to the second Inside the semiconductor layer 6.
  • An anode 9 is formed on the first passivation dielectric layer 8 between the anode trench and the field plate trench, on the field plate trench, and on the first passivation dielectric layer 8 extending over the edge of the field plate trench.
  • the two semiconductor layers 6, the two-dimensional electron gas 7, and the first semiconductor layer 4 form a Schottky contact.
  • the anode metal in the anode trench is directly in contact with the two-dimensional electron gas 7, which can reduce the barrier height and the barrier width of the Schottky junction, thereby reducing the forward voltage of the diode;
  • the field plate trench structure makes the field The plate metal is closer to the two-dimensional electron gas channel, so the two-dimensional electron gas under the trench can be depleted under the action of a small anode reverse bias voltage to isolate the conductive channel of the Schottky junction and the cathode. Therefore, the reverse bias voltage of the Schottky junction formed by the metal/two-dimensional electron gas is greatly reduced, thereby reducing the leakage in the case of the Schottky junction reverse bias and improving the withstand voltage characteristics.
  • the electrical characteristics of Schottky diodes such as forward turn-on voltage, on-resistance, reverse withstand voltage, and reverse leakage, all affect their application.
  • the Schottky diode is required to have a small forward turn-on voltage, a small on-resistance, a high reverse withstand voltage, and a small reverse leakage.
  • 5A and 5B are graphs showing a comparison of the reverse electrical characteristics of the Schottky diode of the prior art shown in Fig. 1 with the reverse electrical characteristics of the Schottky diode provided in the first embodiment of the present invention.
  • the broken line a1 is the reverse electrical characteristic of the Schottky diode in the prior art
  • the solid line b1 is the reverse electrical characteristic of the Schottky diode provided in the first embodiment of the present invention. It can be seen from FIG. 5A that the reverse bias current of the Schottky diode provided by the first embodiment of the present invention is significantly lower than that of the prior art Schottky diode under the same reverse bias voltage. . If the withstand voltage characteristic of the diode is defined by the same leakage level, the withstand voltage characteristic of the Schottky diode having the field plate trench structure proposed by the present invention is remarkably improved.
  • the current unit of the ordinate is the absolute unit
  • au is the abbreviation of absolute unit.
  • the broken line a2 is the forward electrical characteristic of the Schottky diode in the prior art
  • the solid line b2 is the forward electrical characteristic of the Schottky diode provided in the first embodiment of the present invention.
  • the forward voltage of the Schottky diode provided in the first embodiment of the present invention The relationship with the forward current is basically unchanged from the relationship between the forward voltage and the forward current of the Schottky diode in the prior art, that is, the influence of the trench structure of the field plate on the forward characteristics of the Schottky diode.
  • the current unit of the ordinate is the absolute unit
  • au is the abbreviation of absolute unit.
  • the Schottky diode provided in the first embodiment of the present invention has the advantages of small reverse leakage, and also has the advantages of low forward turn-on voltage and small on-resistance.
  • FIG. 6A and FIG. 6B respectively show the electron concentration distribution of the Schottky diode provided in the first embodiment of the present invention when the anode is applied with the same reverse bias voltage (-20 V) and the Schottky in the prior art shown in FIG. The electron concentration distribution of the diode.
  • the Schottky diode provided in the first embodiment of the present invention has a second trench corresponding channel under the anode field plate under the condition that the anode is applied with the same reverse bias voltage (-20 V).
  • the electrons in the region are basically depleted, and the two-dimensional electron gas concentration is only 2.4 ⁇ 10 -6 /cm 3 ; while the channel below the anode field plate of the Schottky diode in the prior art is not depleted, the two-dimensional electron gas concentration Up to 1.7 ⁇ 10 12 /cm 3 .
  • FIG. 7A and 7B respectively show the electric field distribution of the Schottky diode provided in Embodiment 1 of the present invention and the electric field distribution of the Schottky diode in the prior art shown in FIG. 1 when the same reverse bias voltage is applied to the anode. .
  • the electric field intensity of the first trench side of the anode of the Schottky diode provided in the first embodiment of the present invention is 2.6 ⁇ 10 6 V/cm under the condition that the anode is applied with the same reverse bias voltage.
  • the axial electric field strength of the anode trench of the Schottky diode in the prior art is 3.1 ⁇ 10 6 V/cm.
  • the first trench side electric field intensity in the anode of the Schottky diode provided by the first embodiment of the present invention is about 83 of the anode electric field strength of the prior art Schottky diode.
  • the reverse leakage caused by the field-induced electron emission and tunneling effects are exponentially related to the electric field strength, so the electric field strength under the condition of the reverse bias reduction can effectively reduce the inverse Leakage.
  • the comparison of the channel electron concentration in FIGS. 6A and 6B and the comparison of the electric field strengths in FIGS. 7A and 7B further demonstrate that the anode structure of the Schottky diode provided in the first embodiment of the present invention can be depleted at a small reverse bias voltage.
  • the field plate lower plate trench corresponds to the two-dimensional electron gas in the channel region, so that the electric field strength on the Schottky junction formed by the metal/two-dimensional electron gas is reduced.
  • the Schottky diode provided in Embodiment 1 of the present invention combines an anode trench structure and a field plate trench junction
  • the structure can effectively reduce the forward conduction voltage and suppress the reverse leakage current.
  • the anode trench allows direct contact of the Schottky metal of the anode with the two-dimensional electron gas channel, such that the barrier height and barrier width of the Schottky are greatly reduced compared to the non-trench structure, thus A lower forward conduction voltage can be obtained.
  • the field plate trench structure allows the two-dimensional electron gas channel under the field plate trench to be depleted under a small anode reverse bias voltage, thereby reducing the reverse bias voltage experienced by the Schottky junction, ie
  • the reverse bias electric field strength of the Schottky junction can be reduced, thereby reducing the reverse leakage current caused by the field thermoelectron emission or tunneling effect, thereby achieving the effect of reducing reverse leakage.
  • a passivation technique is used to deposit a first passivation dielectric layer of a certain thickness on the aluminum gallium nitride barrier layer (usually a silicon nitride dielectric layer of about 100 nm is used), and the first passivation dielectric layer mainly acts to suppress aluminum gallium nitride.
  • an anodic trench structure and a field plate trench structure are realized by an etching process, wherein the bottom of the anode trench structure reaches or passes through the two-dimensional electron gas, the field plate trench The bottom of the structure reaches or passes through the surface of the second semiconductor layer and extends into the second semiconductor layer.
  • the anode metal is deposited, and the anode metal in the anode trench structure is in direct contact with the two-dimensional electron gas channel to reduce the Schottky barrier height and the barrier width, thereby reducing the forward turn-on voltage of the diode.
  • the anode metal in the field plate trench structure forms a Schottky contact with the surface of the second semiconductor layer. Due to the presence of the field plate trench structure, the field plate metal is closer to the two-dimensional electron gas channel. Therefore, under the action of a smaller reverse bias voltage, the two-dimensional electron gas channel below the trench region can be depleted. Therefore, the reverse bias voltage on the Schottky junction formed by the metal/two-dimensional electron gas is greatly reduced, thereby reducing the leakage under the reverse bias of the Schottky junction.
  • the field plate may be deposited simultaneously with the anode metal and extending over a portion of the first passivation dielectric layer between the trench and the cathode of the field plate, the extension modulating a strong field of the field plate trench near the cathode edge such that The electric field spike at the point is flattened, thereby reducing the peak electric field and improving the withstand voltage characteristics.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 8 is a cross-sectional view showing a Schottky diode according to Embodiment 2 of the present invention.
  • the field plate trench of the Schottky diode provided in the second embodiment extends into the second semiconductor layer 6, but does not extend beyond the second semiconductor layer 6.
  • the second semiconductor layer is After etching and thinning, the concentration of the two-dimensional electron gas under it will decrease, causing an increase in on-resistance. If the etching depth is too deep, the two-dimensional electron gas will be depleted, and the forward voltage of the diode will be Will increase. Therefore, the etching depth of the field plate trench needs to be controlled within a reasonable range. Generally, the distance from the bottom of the trench to the two-dimensional electron gas channel needs to be greater than 5 nm to ensure the concentration of the two-dimensional electron gas that can be normally turned on.
  • the Schottky diode provided by the second embodiment of the present invention makes the field plate closer to the two-dimensional electron gas channel, and thus can be operated under a smaller reverse bias voltage.
  • the two-dimensional electron gas below the trench field plate is depleted.
  • the reverse bias voltage on the Schottky junction formed by the metal/two-dimensional electron gas is further reduced, thereby reducing the leakage of the Schottky junction at the reverse bias voltage.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 9 is a cross-sectional view showing a Schottky diode according to Embodiment 3 of the present invention.
  • the Schottky diode provided in the third embodiment further includes:
  • the field plate trench dielectric layer 10 is located over the passivation dielectric layer 8 and over the field plate trenches.
  • the material of the field plate trench dielectric layer 10 may be any one of silicon nitride, silicon dioxide, silicon oxynitride or aluminum oxide or a combination of at least two.
  • the anode structure of the Schottky diode provided in the third embodiment of the present invention adds a trench dielectric layer between the field plate trench and the anode, which can be further reduced.
  • the leakage of the Schottky junction flowing through the trench region of the field plate is small under the reverse bias voltage.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 10 is a cross-sectional view showing a Schottky diode according to Embodiment 4 of the present invention.
  • the Schottky diode mid-field trench structure provided in the fourth embodiment is subjected to a dry etching process in the trench etching process. Control is performed to retain a portion of the passivation dielectric layer to form a field plate trench dielectric layer.
  • the anode structure of the Schottky diode provided by the fourth embodiment of the present invention simplifies the step of depositing the trench dielectric of the field plate.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • Figure 11 is a cross-sectional view showing a Schottky diode according to a fifth embodiment of the present invention.
  • the back barrier layer 11 is inserted under the first semiconductor layer 4.
  • the material of the back barrier layer 11 may be aluminum gallium nitride having an aluminum composition of 5 to 15%, and the aluminum component of the back barrier layer being lower than the aluminum component of the second semiconductor layer.
  • Aluminum gallium nitride has a larger band gap than gallium nitride, and the introduction of the back barrier layer can better limit the two-dimensional electron gas channel in the first semiconductor layer. Under the action of a reverse bias voltage, electrons leak from the anode through the buffer layer to the cathode, thereby increasing the reverse leakage of the Schottky diode. By introducing a low aluminum component aluminum gallium nitride back barrier layer, electrons can be restricted from entering the buffer layer, thereby reducing reverse leakage current leakage through the buffer layer.
  • the semiconductor structure of the Schottky diode provided in the fifth embodiment of the present invention incorporates a back barrier layer of a lower aluminum component to suppress the flow through the buffer layer. The role of reverse leakage.
  • Figure 12 is a cross-sectional view showing a Schottky diode according to a sixth embodiment of the present invention.
  • the second semiconductor layer of the Schottky diode provided by the sixth embodiment of the present invention is composed of a first barrier layer 6a and a second barrier layer 6b.
  • the material of the first barrier layer 6a may be aluminum gallium nitride, the aluminum component may be 10-15%, the thickness may be 5-15 nm, the material of the second barrier layer 6b may be aluminum gallium nitride, and the second barrier
  • the aluminum component of the layer 6b is higher than the first barrier layer 6a, and the aluminum component may be 25-45% and the thickness may be 15-50 nm.
  • a field plate trench is formed in the first passivation dielectric layer and the high aluminum composition barrier layer by a field plate trench etch process, the bottom of the trench reaching or passing through the surface of the first barrier layer.
  • the first barrier layer under the field plate trench has a lower aluminum composition and a thinner thickness. Therefore, compared to the first embodiment, the two-dimensional electron gas concentration under the field plate trench is lower, and a negative bias is applied to the anode. The pressure is more easily depleted, so that the metal/two-dimensional electron gas Schottky junction is subjected to a lower reverse bias voltage, thereby further reducing the reverse leakage caused by field-induced electron emission and tunneling effects. Electricity.
  • the high aluminum component of the second barrier layer can have a relatively high concentration of the two-dimensional electron gas underneath, thereby making the Schottky diode have a relatively small on-resistance and reduced Positive conduction voltage.
  • the Schottky diode provided in the sixth embodiment can also insert a back barrier layer under the first semiconductor layer to suppress reverse leakage flowing through the buffer layer.
  • the material of the back barrier layer can be aluminum gallium nitride. Since the back barrier layer further depletes the two-dimensional electron gas, the on-resistance becomes large, and the forward conduction voltage increases. Therefore, it is necessary to limit the aluminum component of the aluminum gallium nitride to 5-8%, that is, the back barrier layer.
  • the aluminum component is lower than the aluminum component of the first barrier layer, thereby ensuring that the two-dimensional electron gas under the trench of the field plate still has a certain concentration and is not completely depleted, thereby making the structure under the structure
  • the forward conduction voltage of the special diode remains low.
  • Figure 13 is a cross-sectional view showing a Schottky diode provided in Embodiment 7 of the present invention.
  • the Schottky diode provided in the seventh embodiment of the present invention further includes:
  • the barrier layer 6c is located between the first barrier layer 6a and the second barrier layer 6b, and the material of the barrier layer 6c may be aluminum nitride.
  • the second semiconductor layer of the Schottky diode provided in Embodiment 7 of the present invention has a barrier layer interposed between the second barrier layer and the first barrier layer.
  • Figure 14 is a cross-sectional view showing a Schottky diode provided in Embodiment 8 of the present invention.
  • the structure of the Schottky diode provided in the eighth embodiment of the present invention is further different from the first embodiment, and further includes:
  • a second passivation dielectric layer 12 is deposited on the anode 9 with a second passivation dielectric layer 12.
  • the second anode field plate 13 has a second anode field plate 13 deposited on the second passivation dielectric layer 12, the second anode field plate being interconnected with the anode 9.
  • the material of the second passivation dielectric layer 12 may be any one of silicon nitride, silicon dioxide, silicon oxynitride or aluminum oxide or a combination of at least two.
  • a second passivation dielectric layer is deposited on the anode, and a second passivation dielectric layer is deposited on the second passivation dielectric layer.
  • a second anode field plate interconnected with the anode.
  • Figure 15 is a cross-sectional view showing a Schottky diode provided in Embodiment 9 of the present invention.
  • the Schottky diode provided in Embodiment 9 of the present invention further includes:
  • a third passivation dielectric layer 14 is deposited on the second passivation dielectric layer 12 and the second anode field plate 13;
  • the third anode field plate 15 has a third anode field plate 15 deposited on the third passivation dielectric layer 14, and the third anode field plate is interconnected with the anode 9 and the second anode field plate 13.
  • the material of the third passivation dielectric layer 14 may be any one of silicon nitride, silicon dioxide, silicon oxynitride or aluminum oxide or a combination of at least two.
  • a third passivation is deposited on the second passivation dielectric layer and the second anode field plate, compared to the Schottky diode provided in Embodiment 8 of the present invention.
  • a dielectric layer and a third anode field plate interconnected with the anode By adding the third anode field plate, the peak electric field of the anode edge between the anode and the cathode electrodes can be further reduced on the basis of the eighth embodiment, and the withstand voltage characteristic is improved.
  • Figure 16 is a cross-sectional view showing a Schottky diode provided in Embodiment 10 of the present invention.
  • the Schottky diode provided in the tenth embodiment of the present invention is shown.
  • the first semiconductor layer 4 is deposited on the upper surface of the second semiconductor layer 6, the cathode 5 forms an ohmic contact with the surface of the first semiconductor layer 4, and the anode 9 forms a Schottky contact with the surface of the first semiconductor layer 4.
  • the forbidden band width of the first semiconductor layer 4 is smaller than the forbidden band width of the second semiconductor layer 6, the first semiconductor layer 4 and the cathode 5 are more likely to form an ohmic contact.
  • the Schottky diode provided in Embodiment 10 of the present invention can also realize the electrical characteristics of small reverse leakage and low forward turn-on voltage.
  • Figure 17 is a cross-sectional view showing a Schottky diode according to Embodiment 11 of the present invention.
  • the Schottky diode provided in the eleventh embodiment of the present invention also has the advantages of small reverse leakage and low forward turn-on voltage, and the manufacturing process of the diode is further improved. simple.
  • FIG. 18 shows a method of fabricating a Schottky diode according to Embodiment 12 of the present invention. As shown in Figure 18, the following steps are included:
  • Step S1 sequentially depositing a first semiconductor layer, a second semiconductor layer, and a first passivation dielectric layer on the substrate, and forming a two-dimensional electron gas at an interface between the first semiconductor layer and the second semiconductor layer;
  • Step S2 forming a cathode on the second semiconductor layer
  • Step S3 forming an anode trench in the first passivation dielectric layer and the second semiconductor layer between the cathodes, wherein a bottom of the anode trench extends to a region where the two-dimensional electron gas is located or passes through the two-dimensional electron The area where the gas is located;
  • Step S4 forming a field plate trench in the first passivation dielectric layer between the anode trench and the cathode, wherein a bottom of the field plate trench is located in the first passivation dielectric layer or extends to the second An upper surface of the semiconductor layer or extending into the second semiconductor layer;
  • Step S5 the first blunt on the anode trench and the field plate trench and between the anode trench and the field plate trench An anode is formed on the first dielectric layer on the dielectric layer and/or on the first passivation dielectric layer outside the trench of the field plate.
  • the anode trench or the field plate trench can be prepared by a dry etching and/or a wet etching process.

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Abstract

一种肖特基二极管及其制造方法，该肖特基二极管包括：衬底（1）；位于衬底（1）上的第一半导体层（4）；位于第一半导体层（4）上的第二半导体层（6）；在第一半导体层（4）和第二半导体层（6）的交界面处形成有二维电子气（7）；位于第二半导体层（6）上的阴极（5）；位于第二半导体层（6）上的第一钝化介质层（8）；位于第一钝化介质层（8）和第二半导体层（6）之内的阳极沟槽；位于阳极沟槽与阴极（5）之间的第一钝化介质层（8）内的场板沟槽；覆盖阳极沟槽、场板沟槽以及阳极沟槽和场板沟槽之间的第一钝化介质层（8）的阳极（9）。该肖特基二极管具有正向导通电压低、反向漏电小和耐压高的特性。

Description

一种肖特基二极管及其制作方法
本专利申请要求于2014年11月19日提交的，申请号为201410663922.0，申请人为苏州捷芯威半导体有限公司，发明名称为“一种肖特基二极管及其制作方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种肖特基二极管及其制作方法。
背景技术
在高压开关应用领域中，希望二极管具有反向漏电小、反向耐压大和正向导通压降小的特性。基于宽禁带半导体材料，特别是氮化镓材料的功率电子器件具有优越的特性。因此，氮化镓肖特基二极管近年来逐渐成为研究的热点。在氮化镓衬底上同质外延氮化镓的技术尚处于小尺寸、高成本的阶段，虽然可以获得质量较高的外延材料和较理想的器件性能，但是基于成本的考虑尚未被广泛的采用。目前氮化镓材料主要是在异质材料上外延生长而得，氮化镓材料的缺陷密度仍处于较高的水平(一般为108cm-3)，因而垂直结构的氮化镓肖特基二极管仍不能获得理想的性能。但是基于铝镓氮/氮化镓异质结构所形成的水平方向上高电子迁移率的二维电子气沟道而制作出的高电子迁移率器件(HEMT)已经被广泛的应用于射频和电力电子领域。一方面，是因为氮化镓是宽禁带半导体材料的，该材料具有比硅材料大10倍左右临界击穿电场以及相应的高耐压的特性，另一方面，是由于二维电子气沟道能够提供非常小的导通电阻，从而减少开关器件的功率损耗。因此，基于铝镓氮/氮化镓异质结构的水平二极管逐渐成为业界的重要研究对象。对于在铝镓氮/氮化镓异质结构上直接沉积肖特基金属所形成的肖特基二极管而言，由于肖特基金属与二维电子气之间的铝镓氮势垒层厚度一般达到20nm左右，所以会形成比较大的肖特基势垒厚度，并且在铝镓氮势垒层的表面态密度较大会形成费米能级钉扎效应使得肖特 基势垒高度比较大，从而使得肖特基的正向开启电压较大(＞1V)，不利于减小二极管的导通损耗。为了减小肖特基二极管的正向导通电压，阳极沟槽结构被提出来，通过在阳极区域刻蚀去除铝镓氮势垒层和部分氮化镓沟道层，然后沉积阳极金属，使得阳极金属从侧壁与二维电子气沟道形成金半接触，从而消除了20nm厚的铝镓氮势垒层所形成的肖特基势垒厚度，减小了二极管的正向开启电压(＜0.7V)，同时高电子迁移率的二维电子气沟道提供了很低的导通电阻，从而形成具有低导通电压和低导通电阻的高性能肖特基二极管。并且由于氮化镓材料的宽禁带特性，其二维电子气沟道中的空穴浓度非常低，因而具有非常小的反向恢复时间。但现有的氮化镓肖特基二极管仍然存在不足之处。例如，在高电场下场致热电子发射或电子隧穿效应会使得反向漏电增大，导致器件的耐压特性降低。
现在，也有很多的文献和专利中提出了不同结构的肖特基二极管，以改善其肖特基二极管的性能。例如，
文献“Fast Switching GaN Based Lateral power Schottky Barrier Diode with Low Onset Voltage and Strong Reverse Blocking”提出了将肖特基二极管的阳极11设计为沟槽形加场板结构，场板下的介质为氮化硅层12，沟槽中阳极11金属直接与二维电子气13接触，如图1所示，此文献提出通过增加场板结构和增大阳极和阴极的距离，能够提高肖特基二极管的耐压。
Yuvaraj Dora等人发明的专利号为US8772842B2的专利“Semiconductor Diodes With Low Reverse Bias Currents”提出了如图2所示的肖特基二极管：阳极21采用了两层复合介质层结构，在其中一层22中形成阶梯状的场板结构，另一层23为钝化层，起到降低峰值电场、提高击穿电压的作用。
Yifeng Wu等人发明的专利号为US7898004B2的专利“Semiconductor Heterostucture Diodes”也提出多阶梯结构的肖特基二极管：如图3所示，采用单层介质层来形成阳极阶梯式场板结构，起到降低峰值电场的作用。阳极31沟槽底部金属与半导体材料32形成肖特基接触，构成阳极结构。
在上述解决方案中，都提到了增加场板的方式，在外加反偏电压下，场板可以通过降低肖特基结所在位置的电场强度来减小肖特基二极管的反向漏电， 提高肖特基二极管在关断状态下的击穿电压。然而，在实际应用中，由于场板下的钝化介质层的存在，因此阳极上施加的反偏电压在耗尽其下沟道的二维电子气之前将被完全施加于反偏肖特基结之上。而为了达到理想的钝化效果和较优化的场板缓和电场的效果，钝化介质层的厚度一般需要达到100nm左右的厚度，相比于铝镓氮势垒层的厚度(一般为20nm)是比较大的，并且目前一般使用氮化硅作为钝化介质层，其介电常数也比铝镓氮要低，因此会导致耗尽二维电子气所需的电压较大，也就意味着在二维电子气沟道被耗尽并且场板起到缓和电场的作用之前，肖特基结上已经承受了较大的反向偏压，场致热电子发射和隧穿效应都使得反向漏电增大，因此反向漏电仍处于比较高的水平。
因此，如何进一步减小氮化镓肖特基二极管反偏下的漏电，提高耐压特性，成为一个亟待解决的技术难题。
发明内容
本发明是为了解决现有技术中的上述不足而完成的，本发明的目的在于提出一种肖特基二极管及其制作方法。该肖特基二极管能够解决现有技术中氮化镓异质结构中金属/二维电子气肖特基结在阳极反偏电压下漏电较大的问题。为达此目的，本发明采用以下技术方案：
第一方面，本发明提供了一种肖特基二极管，包括：
衬底；
第一半导体层，位于所述衬底之上；
第二半导体层，位于所述第一半导体层之上，所述第一半导体层与所述第二半导体层的交界面处形成有二维电子气；
阴极，所述阴极位于所述第二半导体层之上，其中，所述阴极与所述第二半导体层形成欧姆接触；
第一钝化介质层，所述第一钝化介质层位于所述第二半导体层之上；
阳极沟槽，所述阳极沟槽位于所述第一钝化介质层和所述第二半导体层之内，且所述阳极沟槽的底部延伸至所述二维电子气所在的区域或穿过所述二维 电子气所在的区域；
场板沟槽，所述场板沟槽位于所述阳极沟槽与所述阴极之间的第一钝化介质层内，且所述场板沟槽的底部位于所述第一钝化介质层内或延伸至所述第二半导体层上表面或延伸至所述第二半导体层内；
阳极，所述阳极覆盖所述阳极沟槽、所述场板沟槽以及所述阳极沟槽和所述场板沟槽之间的第一钝化介质层，所述阳极沟槽内的阳极和所述第二半导体层形成肖特基接触，所述场板沟槽和所述第一钝化介质层上的阳极构成阳极场板。
进一步地，还包括：
场板沟槽介质层，所述场板沟槽介质层位于所述场板沟槽之外的第一钝化介质层之上和所述场板沟槽之上。
进一步地，所述阳极还覆盖所述场板沟槽之外的部分第一钝化介质层。
进一步地，所述阳极上沉积有第二钝化介质层，所述第二钝化介质层上沉积有第二阳极场板，所述第二阳极场板与所述阳极电性连接。
进一步地，所述第二阳极场板上沉积有第三钝化介质层，所述第三钝化介质层上沉积有第三阳极场板，所述第三阳极场板与所述阳极电性连接。
进一步地，所述第二半导体层包括第一势垒层和第二势垒层。
进一步地，所述第一势垒层和第二势垒层之间沉积有阻挡层。
进一步地，所述第一势垒层和第二势垒层材料为铝镓氮；所述第一势垒层的铝组分为10-15％，所述第一势垒层的厚度为5-15nm；所述第二势垒层的铝组分为20-45％，所述第二势垒层的厚度为15-50nm。
进一步地，所述阻挡层材料为氮化铝。
进一步地，所述阳极沟槽的任一个侧面的截面形状为直线、折线或弧形中的任一个或至少两个的组合，所述阳极沟槽的任一个侧面与所述阳极沟槽的底部的夹角为直角、钝角或锐角。
进一步地，所述场板沟槽的任一个侧面的截面形状为直线、折线或弧线中的任一个或至少两个的组合，所述场板沟槽的任一个侧面与所述场板沟槽的底部的夹角为直角、钝角或锐角。
进一步地，所述衬底与所述第一半导体层之间依次沉积有成核层、缓冲层或背势垒层中的任一个或至少两个的组合。
进一步地，所述成核层材料为氮化铝、氮化镓或其它III-V族氮化物；所述缓冲层材料为非掺杂的氮化铝、氮化镓、铝镓氮或其它III-V族氮化物；所述背势垒层材料为铝镓氮，所述背势垒层的铝组分为5-8％。
进一步地，所述衬底材料为碳化硅、硅、蓝宝石、氮化铝、氮化镓或其它能够生长III-V族氮化物的衬底材料；所述第一半导体层材料为非掺杂氮化镓层；所述第二半导体层材料为铝镓氮或其它III-V族氮化物。
第二方面，本发明提供了一种肖特基二极管的制作方法，包括：
在所述衬底上依次沉积第一半导体层、第二半导体层和第一钝化介质层，所述第一半导体层与所述第二半导体层的交界面处形成有二维电子气；
在所述第二半导体层上形成阴极；
在所述阴极之间的第一钝化介质层和第二半导体层内形成阳极沟槽，且所述阳极沟槽的底部延伸至所述二维电子气所在的区域或穿过所述二维电子气所在的区域；
在所述阳极沟槽与所述阴极之间的第一钝化介质层内形成场板沟槽，且所述场板沟槽的底部位于所述第一钝化介质层内或延伸至所述第二半导体层上表面或延伸至所述第二半导体层内；
在所述阳极沟槽和所述场板沟槽上以及所述阳极沟槽和所述场板沟槽之间的第一钝化介质层上和/或所述场板沟槽之外的第一钝化介质层上形成阳极。
进一步地，所述阳极沟槽或场板沟槽是通过干法刻蚀和/或湿法腐蚀工艺制备而成的。
本发明所述的肖特基二极管能够解决现有技术中氮化镓异质结构中金属/二维电子气肖特基结在阳极反偏电压下漏电较大的问题，同时也保留了氮化镓二极管正向开启电压小和正向导通电阻低的优点。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本发明所要描述的一部分实施例的附图，而不是全部的附图，对于本领域普通技术人员，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1-图3是现有技术中的肖特基二极管的剖面示意图。
图4是本发明实施例一提供的肖特基二极管的剖面示意图。
图5A和图5B是图1所示的现有技术中的肖特基二极管的电特性与本发明实施例一提供的肖特基二极管的电特性的比较曲线图。
图6A和图6B分别是阳极施加相同反偏电压时，本发明实施例一提供的肖特基二极管的电子浓度分布图和图1所示的现有技术中的肖特基二极管的电子浓度分布图。
图7A和图7B分别是阳极施加相同反偏电压时，本发明实施例一提供的肖特基二极管的电场分布图和图1所示的现有技术中的肖特基二极管的电场分布图。
图8是本发明实施例二提供的肖特基二极管的剖面示意图。
图9是本发明实施例三提供的肖特基二极管的剖面示意图。
图10是本发明实施例四提供的肖特基二极管的剖面示意图。
图11是本发明实施例五提供的肖特基二极管的剖面示意图。
图12是本发明实施例六提供的肖特基二极管的剖面示意图。
图13是本发明实施例七提供的肖特基二极管的剖面示意图。
图14是本发明实施例八提供的肖特基二极管的剖面示意图。
图15是本发明实施例九提供的肖特基二极管的剖面示意图。
图16是本发明实施例十提供的肖特基二极管的剖面示意图。
图17是本发明实施例十一提供的肖特基二极管的剖面示意图。
图18是本发明实施例十二提供的肖特基二极管的制造方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下将结合本发明实施例中的附图，通过具体实施方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例，基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下获得的所有其他实施例，均落入本发明的保护范围之内。
实施例一：
图4给出了本发明实施例一提供的肖特基二极管的剖面示意图。如图4所示，该肖特基二极管包括：
衬底1，其中，衬底1的材料可以是氮化镓、硅、蓝宝石、氮化硅、氮化铝、SOI或其它可以外延生长III-V族氮化物的衬底材料。
在衬底1上依次生长的成核层2、缓冲层3、第一半导体层4和第二半导体层6，其中，第一半导体层4的禁带宽度小于第二半导体层6的禁带宽度，成核层2的材料可以是氮化铝或氮化镓，缓冲层3的材料可以是铝镓氮的缓变层或超晶格材料，第一半导体层4的材料可以是氮化镓，第二半导体层6的材料可以是铝镓氮，在第一半导体层4和第二半导体层6的交界面处形成有二维电子气7。
在第二半导体层6上形成的阴极5，其中，阴极5的材料为金属，阴极5与第二半导体层6形成欧姆接触。
在位于阴极5之间的第二半导体层6上沉积有第一钝化介质层8，其中，该第一钝化介质层8能够起到抑制铝镓氮表面态引起的电流崩塌效应的作用。该第一钝化介质层8的材料可以是氮化硅、二氧化硅、氮氧化硅，氟化物或氧化铝中的任意一种或至少两种的组合。
在位于阴极5之间的第一钝化介质层8和第二半导体层6内形成的阳极沟槽结构。在阳极沟槽和阴极金属之间的第一钝化介质层8内形成的场板沟槽结构。其中，在制作阳极沟槽或场板沟槽时，可以通过干法刻蚀手段，并且控制纵向和横向的不同刻蚀速率以获得不同形状的沟槽结构，也可以通过湿法腐蚀工艺形成，或者是通过其他工艺形成，沟槽侧面与底面的夹角为直角、钝角或 锐角中任意一种或其中两种的组合，沟槽的具体尺寸可以按照设计要求而定。阳极沟槽结构的底部可以达到或穿过二维电子气7而延伸至第二半导体层6内，场板沟槽结构的底部可以达到或超过第二半导体层6的上表面而延伸至第二半导体层6内。
在阳极沟槽与场板沟槽之间的第一钝化介质层8上、场板沟槽上以及在场板沟槽边缘延伸的第一钝化介质层8上形成阳极9，阳极9与第二半导体层6、二维电子气7以及第一半导体层4形成肖特基接触。阳极沟槽中阳极金属直接与二维电子气7接触，可以减小该肖特基结的势垒高度和势垒宽度，进而减小二极管正向的导通电压；场板沟槽结构使得场板金属更加接近二维电子气沟道，因此可以在较小的阳极反偏电压的作用下将沟槽下方的二维电子气耗尽，以隔离肖特基结与阴极的导电通道。从而，使得金属/二维电子气形成的肖特基结所承受的反偏电压被大大减小，进而减小在肖特基结反偏情况下的漏电，提高耐压特性。
在实际应用中，肖特基二极管的电特性参数，例如，正向开启电压、导通电阻、反向耐压以及反向漏电，都会影响其应用效果。为了有更好的应用效果，需要肖特基二极管具有正向开启电压小、导通电阻小、反向耐压高以及反向漏电小的特性。
图5A和图5B给出了图1所示的现有技术中的肖特基二极管的反向电特性与本发明实施例一提供的肖特基二极管的反向电特性的比较曲线图。
图5A中，虚线a1为现有技术中的肖特基二极管的反向电特性，实线b1为本发明实施例一提供的肖特基二极管的反向电特性。从图5A中可以看出：在相同的反偏电压条件下，本发明实施例一提供的肖特基二极管的反偏电流比现有技术中的肖特基二极管的反偏电流有明显的降低。如果以同样的漏电水平来定义二极管的耐压特性，则采用本发明所提出的具有场板沟槽结构的肖特基二极管的耐压特性得到了显著的提高。其中，纵坐标的电流单位采用的是绝对单位，au是absolute unit(绝对单位)的缩写。图5B中，虚线a2为现有技术中的肖特基二极管的正向电特性，实线b2为本发明实施例一提供的肖特基二极管的正向电特性。从图5B中可以看出：本发明实施例一提供的肖特基二极管的正向电压 和正向电流的关系与现有技术中的肖特基二极管的正向电压和正向电流的关系相比基本保持不变，亦即采用场板沟槽结构后对肖特基二极管的正向特性影响很小。其中，纵坐标的电流单位采用的是绝对单位，au是absolute unit(绝对单位)的缩写。
根据上述电特性的比较，进一步证明了本发明实施例一提供的肖特基二极管具有反向漏电小的优点，同时也保留了正向开启电压低、导通电阻小的优点。
图6A和图6B分别给出了阳极施加相同反偏电压(-20V)时，本发明实施例一提供的肖特基二极管的电子浓度分布和图1所示的现有技术中的肖特基二极管的电子浓度分布。
从图6A和6B中可以看出，在阳极施加相同的反偏电压的条件(-20V)下，本发明实施例一提供的肖特基二极管，其阳极场板下第二沟槽对应沟道区域的电子基本被耗尽，二维电子气浓度只有2.4×10-6/cm3；而现有技术中的肖特基二极管的阳极场板下方沟道没有被耗尽，二维电子气浓度高达1.7×1012/cm3。
图7A和图7B分别给出了在阳极施加相同反偏电压时，本发明实施例一提供的肖特基二极管的电场分布和图1所示的现有技术中的肖特基二极管的电场分布。
从图7A和7B中可以看出，在阳极施加相同的反偏电压条件下，本发明实施例一提供的肖特基二极管的阳极中第一沟槽侧面电场强度为2.6×106V/cm，而现有技术中的肖特基二极管的阳极沟槽侧面电场强度为3.1×106V/cm。和现有技术中的肖特基二极管相比，本发明实施例一提供的肖特基二极管的阳极中的第一沟槽侧面电场强度约为现有技术肖特基二极管的阳极电场强度的83％；在肖特基结中，场致热电子发射和隧穿效应引起的反向漏电都与电场强度呈指数相关特性，因此在反向偏压降低条件下的电场强度可以有效的减小反向漏电。
通过图6A、6B中沟道电子浓度的比较以及图7A、7B中电场强度的比较，进一步证明了本发明实施例一提供的肖特基二极管的阳极结构可以在小的反偏电压下耗尽场板下场板沟槽对应沟道区域的二维电子气，从而使得金属/二维电子气所形成的肖特基结上所承担的电场强度减小了。
本发明实施例一提供的肖特基二极管，结合了阳极沟槽结构和场板沟槽结 构，能够有效的降低正向导通电压并抑制反向漏电流。阳极沟槽使得阳极的肖特基金属与二维电子气沟道形成直接的接触，使得肖特基的势垒高度和势垒宽度相比于非沟槽结构得到了极大的减小，因此能获得较低的正向导通电压。而场板沟槽结构则使得场板沟槽下方的二维电子气沟道能够在较小的阳极反偏电压下被耗尽，因此减小了肖特基结所承受的反偏电压，即能够减小肖特基结的反偏电场强度，进而减小场致热电子发射或隧穿效应引起的反向漏电流，从而达到减小反向漏电的效果。
应用钝化技术在铝镓氮势垒层上沉积一定厚度的第一钝化介质层(通常使用的是100nm左右的氮化硅介质层)，第一钝化介质层主要起到抑制铝镓氮材料的表面态的充放电引起的电流崩塌效应的作用。在位于阴极之间的半导体结构以及介质层中，采用刻蚀工艺实现阳极沟槽结构和场板沟槽结构，其中阳极沟槽结构的底部会达到或穿过二维电子气，场板沟槽结构的底部达到或穿过第二半导体层的表面而延伸至第二半导体层内。
沉积阳极金属，阳极沟槽结构中阳极金属与二维电子气沟道直接接触，用于减小肖特基势垒高度和势垒宽度，从而降低二极管的正向开启电压。
场板沟槽结构中阳极金属与第二半导体层的表面形成肖特基接触。由于场板沟槽结构的存在，使得场板金属更加接近二维电子气沟道。因此，在更小反偏电压的作用下，就可以将沟槽区域下方的二维电子气沟道耗尽。从而使得金属/二维电子气所形成的肖特基结上所承受的反偏电压被大大减小，进而减小该肖特基结反偏下的漏电。
场板可以与阳极金属同时沉积，并且延伸覆盖位于场板沟槽与阴极之间的部分第一钝化介质层，该延伸部分可以对场板沟槽靠近阴极边缘的强场进行调制，使得该处的电场尖峰被拉平，从而减小峰值电场，提高耐压特性。
实施例二：
图8给出了本发明实施例二提供的肖特基二极管的剖面示意图。
如图8所示，与实施例一不同的是，本实施例二提供的肖特基二极管的场板沟槽延伸至第二半导体层6内，但不会超出第二半导体层6。第二半导体层被 刻蚀减薄后会导致其下的二维电子气浓度减小，引起导通电阻的增大，如果刻蚀深度过深，将导致二维电子气被耗尽，则二极管的正向导通电压会增大。因此场板沟槽的刻蚀深度需要控制在合理的范围内，一般而言沟槽底部距离二维电子气沟道的距离需要大于5nm以保证具有可正常导通的二维电子气的浓度。
与本发明实施例一提供的肖特基二极管相比，本发明实施例二提供的肖特基二极管使得场板更加接近二维电子气沟道，因此可以在更小的反偏电压的作用下将沟槽区域场板下方的二维电子气耗尽。从而使得在金属/二维电子气所形成的肖特基结上承担的反偏电压被进一步减小，进而减小该肖特基结在反偏电压下的漏电。
实施例三：
图9给出了本发明实施例三提供的肖特基二极管的剖面示意图。
如图9所示，与实施例一不同的是，本实施例三提供的肖特基二极管还包括：
场板沟槽介质层10，位于钝化介质层8之上和场板沟槽之上。
本实施例中，场板沟槽介质层10的材料可以是氮化硅、二氧化硅、氧氮化硅或氧化铝中的任意一种或至少两种的组合。
与本发明实施例一提供的肖特基二极管相比，本发明实施例三提供的肖特基二极管的阳极结构，在场板沟槽与阳极之间增加了场板沟槽介质层，可以进一步减小在反偏电压下流过场板沟槽区域肖特基结的漏电。
实施例四：
图10给出了本发明实施例四提供的肖特基二极管的剖面示意图。
如图10所示，与实施例三不同的是，本实施例四提供的肖特基二极管中场板沟槽结构，在沟槽刻蚀工艺中，采用干法刻蚀工艺，对刻蚀时间进行控制，保留部分的钝化介质层以形成场板沟槽介质层。
与本发明实施例三提供的肖特基二极管相比，本发明实施例四提供的肖特基二极管的阳极结构简化了场板沟槽介质沉积的步骤。
实施例五：
图11给出了本发明实施例五提供的肖特基二极管的剖面示意图。
如图11所示，与实施例一不同的是，在本发明实施例五提供的肖特基二极管的半导体结构中，在第一半导体层4下面插入背势垒层11。
背势垒层11的材料可以是铝镓氮，其铝组分为5～15％，且背势垒层的铝组分低于第二半导体层的铝组分。
铝镓氮具有比氮化镓更大的禁带宽度，引入背势垒层可以对第一半导体层中的二维电子气沟道起到更好的限制作用。在外加反偏电压的作用下，电子会从阳极通过缓冲层泄漏到阴极，从而增大肖特基二极管的反向漏电。通过引入低铝组分铝镓氮背势垒层可以限制电子进入缓冲层，从而降低通过缓冲层泄漏的反向漏电流。
与本发明实施例一提供的肖特基二极管相比，本发明实施例五提供的肖特基二极管的半导体结构中加入了较低铝组分的背势垒层，起到了抑制流过缓冲层的反向漏电的作用。
实施例六：
图12给出了本发明实施例六提供的肖特基二极管的剖面示意图。
如图12所示，与实施例一不同的是，本发明实施例六提供的肖特基二极管的第二半导体层由第一势垒层6a和第二势垒层6b组成。
第一势垒层6a的材料可以是铝镓氮，铝组分可以为10-15％，厚度可以为5-15nm，第二势垒层6b的材料可以是铝镓氮，且第二势垒层6b的铝组分要高于第一势垒层6a，其铝组分可以为25-45％，厚度可以为15-50nm。
利用场板沟槽刻蚀工艺在第一钝化介质层和高铝组分势垒层中形成场板沟槽，沟槽底部达到或穿过第一势垒层的表面。场板沟槽下方的第一势垒层的铝组分较低并且厚度也较薄，因此相比于实施例一，场板沟槽下的二维电子气浓度更低，在阳极施加负偏压时更易耗尽，使得金属/二维电子气肖特基结所承受的反偏电压更低，从而进一步减小场致热电子发射和隧穿效应引起的反向漏 电。在场板沟槽与阴极之间，第二势垒层的高铝组分可以使得其下的二维电子气具有比较高的浓度，因此使得肖特基二极管具有比较小的导通电阻并降低了正向导通电压。
本实施例六提供的肖特基二极管还可以在第一半导体层下面插入背势垒层，起到抑制流过缓冲层的反向漏电的作用，背势垒层的材料可以是铝镓氮。由于背势垒层会进一步耗尽二维电子气，使得导通电阻变大，正向导通电压增加，因此，需要将铝镓氮的铝组分限定为5-8％，即背势垒层的铝组分低于第一势垒层的铝组分，由此可以保证在场板沟槽下方的二维电子气仍具有一定的浓度，不会被完全耗尽，从而使得该结构下的肖特基二极管的正向导通电压仍保持较低。
实施例七：
图13给出了本发明实施例七提供的肖特基二极管的剖面示意图。
如图13所示，与实施例六不同的是，本发明实施例七提供的肖特基二极管还包括：
阻挡层6c，位于第一势垒层6a和第二势垒层6b之间，阻挡层6c的材料可以是氮化铝。
与本发明实施例六提供的肖特基二极管相比，本发明实施例七提供的肖特基二极管的第二半导体层，在第二势垒层和第一势垒层之间插入了阻挡层，通过引入阻挡层氮化铝，在干法刻蚀时氮化铝与铝镓氮之间的刻蚀选择比比较大，使得刻蚀的沟槽界面具有比较精确的停止位置，从而提高肖特基二极管开启电压的均匀性。
实施例八：
图14给出了本发明实施例八提供的肖特基二极管的剖面示意图。
如图14所示，与实施例一不同的是，本发明实施例八提供的肖特基二极管的结构中，还包括：
第二钝化介质层12，在阳极9上沉积有第二钝化介质层12。
第二阳极场板13，在第二钝化介质层12上沉积有第二阳极场板13，第二阳极场板与阳极9互连。
本实施例中，第二钝化介质层12的材料可以是氮化硅、二氧化硅、氧氮化硅或氧化铝中的任意一种或至少两种的组合。
与本发明实施例一提供的肖特基二极管相比，发明实施例八提供的肖特基二极管结构中，在阳极上沉积有第二钝化介质层，在第二钝化介质层上沉积有第二阳极场板，该第二阳极场板与阳极互连。通过增加第二阳极场板，可以进一步降低阴阳电极间阳极边缘的峰值电场，提高耐压特性。
实施例九：
图15给出了本发明实施例九提供的肖特基二极管的剖面示意图。
如图15所示，与实施例八不同的是，本发明实施例九提供的肖特基二极管还包括：
第三钝化介质层14，在第二钝化介质层12上和第二阳极场板13上沉积有第三钝化介质层14；
第三阳极场板15，在第三钝化介质层14上沉积有第三阳极场板15，第三阳极场板与阳极9以及第二阳极场板13互连。
本实施例中，第三钝化介质层14的材料可以是氮化硅、二氧化硅、氧氮化硅或氧化铝中的任意一种或至少两种的组合。
与本发明实施例八提供的肖特基二极管相比，在本发明实施例九提供的肖特基二极管结构中，在第二钝化介质层以及第二阳极场板上沉积有第三钝化介质层和第三阳极场板，该第三阳极场板与阳极互连。通过增加第三阳极场板，可以在实施例八的基础上，进一步降低阴阳电极间阳极边缘的峰值电场，提高耐压特性。
实施例十：
图16给出了本发明实施例十提供的肖特基二极管的剖面示意图。
如图16所示，与实施例一不同的是，在本发明实施例十提供的肖特基二极 管的结构中，第一半导体层4沉积在了第二半导体层6的上表面，阴极5与第一半导体层4表面形成欧姆接触，阳极9与第一半导体层4表面形成肖特基接触。由于第一半导体层4的禁带宽度比第二半导体层6的禁带宽度小，所以第一半导体层4与阴极5更容易形成欧姆接触。与本发明实施例一提供的肖特基二极管相比，本发明实施例十提供的肖特基二极管同样可以实现小反向漏电，低正向开启电压的电特性。
实施例十一：
图17给出了本发明实施例十一提供的肖特基二极管的剖面示意图。
如图17所示，与实施例一不同的是，在本发明实施例十一提供的肖特基二极管的结构中，只有一个阴极和一个场板沟槽。
与本发明实施例一提供的肖特基二极管相比，本发明实施例十一提供的肖特基二极管同样具有小反向漏电、低正向开启电压的优点，同时，该二极管的制造工艺更加简单。
实施例十二：
图18给出了本发明实施例十二提供的肖特基二极管的制作方法。如图18所示，包括以下步骤：
步骤S1、在衬底上依次沉积第一半导体层、第二半导体层和第一钝化介质层，第一半导体层与第二半导体层的交界面处形成有二维电子气；
步骤S2、在第二半导体层上形成阴极；
步骤S3、在阴极之间的第一钝化介质层和第二半导体层内形成阳极沟槽，其中阳极沟槽的底部延伸至所述二维电子气所在的区域或穿过所述二维电子气所在的区域；
步骤S4、在阳极沟槽与述阴极之间的第一钝化介质层内形成场板沟槽，其中场板沟槽的底部位于所述第一钝化介质层内或延伸至所述第二半导体层上表面或延伸至所述第二半导体层内；
步骤S5、在阳极沟槽和场板沟槽上以及阳极沟槽和场板沟槽之间的第一钝 化介质层上和/或场板沟槽之外的第一钝化介质层上形成阳极。
其中，阳极沟槽或场板沟槽可以通过干法刻蚀和/或湿法腐蚀工艺制备而成的。
上述仅为本发明的较佳实施例及所运用的技术原理。本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行的各种明显变化、重新调整及替代均不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由权利要求的范围决定。

Claims (16)

  1. 一种肖特基二极管，其特征在于，包括：
    衬底；
    第一半导体层，位于所述衬底之上；
    第二半导体层，位于所述第一半导体层之上，所述第一半导体层与所述第二半导体层的交界面处形成有二维电子气；
    阴极，所述阴极位于所述第二半导体层之上，其中，所述阴极与所述第二半导体层形成欧姆接触；
    第一钝化介质层，所述第一钝化介质层位于所述第二半导体层之上；
    阳极沟槽，所述阳极沟槽位于所述第一钝化介质层和所述第二半导体层之内，且所述阳极沟槽的底部延伸至所述二维电子气所在的区域或穿过所述二维电子气所在的区域；
    场板沟槽，所述场板沟槽位于所述阳极沟槽与所述阴极之间的第一钝化介质层内，且所述场板沟槽的底部位于所述第一钝化介质层内或延伸至所述第二半导体层上表面或延伸至所述第二半导体层内；
    阳极，所述阳极覆盖所述阳极沟槽、所述场板沟槽以及所述阳极沟槽和所述场板沟槽之间的第一钝化介质层，所述阳极沟槽内的阳极和所述第二半导体层形成肖特基接触，所述场板沟槽和所述第一钝化介质层上的阳极构成阳极场板。
  2. 根据权利要求1所述的肖特基二极管，其特征在于，还包括：
    场板沟槽介质层，所述场板沟槽介质层位于所述场板沟槽之外的第一钝化介质层之上和所述场板沟槽之上。
  3. 根据权利要求1所述的肖特基二极管，其特征在于，所述阳极还覆盖所述场板沟槽之外的部分第一钝化介质层。
  4. 根据权利要求1所述的肖特基二极管，其特征在于，所述阳极上沉积有第二钝化介质层，所述第二钝化介质层上沉积有第二阳极场板，所述第二阳极场板与所述阳极电性连接。
  5. 根据权利要求4所述的肖特基二极管，其特征在于，所述第二阳极场板上沉积有第三钝化介质层，所述第三钝化介质层上沉积有第三阳极场板，所述 第三阳极场板与所述阳极电性连接。
  6. 根据权利要求1所述的肖特基二极管，其特征在于，所述第二半导体层包括第一势垒层和第二势垒层。
  7. 根据权利要求6所述的肖特基二极管，其特征在于，在所述第一势垒层和第二势垒层之间沉积有阻挡层。
  8. 根据权利要求6所述的肖特基二极管，其特征在于，所述第一势垒层和第二势垒层材料为铝镓氮；所述第一势垒层的铝组分为10-15％，所述第一势垒层的厚度为5-15nm；所述第二势垒层的铝组分为20-45％，所述第二势垒层的厚度为15-50nm。
  9. 根据权利要求7所述的肖特基二极管，其特征在于，所述阻挡层材料为氮化铝。
  10. 根据权利要求1-9任一所述的肖特基二极管，其特征在于，所述阳极沟槽的任一个侧面的截面形状为直线、折线或弧形中的任一个或至少两个的组合，所述阳极沟槽的任一个侧面与所述阳极沟槽的底部的夹角为直角、钝角或锐角。
  11. 根据权利要求1-9任一所述的肖特基二极管，其特征在于，所述场板沟槽的任一个侧面的截面形状为直线、折线或弧线中的任一个或至少两个的组合，所述场板沟槽的任一个侧面与所述场板沟槽的底部的夹角为直角、钝角或锐角。
  12. 根据权利要求1-9任一所述的肖特基二极管，其特征在于，所述衬底与所述第一半导体层之间依次沉积有成核层、缓冲层或背势垒层中的任一个或至少两个的组合。
  13. 根据权利要求12所述的肖特基二极管，其特征在于，所述成核层材料为氮化铝、氮化镓或其它III-V族氮化物；所述缓冲层材料为非掺杂的氮化铝、氮化镓、铝镓氮或其它III-V族氮化物；所述背势垒层材料为铝镓氮，所述背势垒层的铝组分为5-8％。
  14. 根据权利要求1-9任一所述的肖特基二极管，其特征在于，所述衬底材料为碳化硅、硅、蓝宝石、氮化铝、氮化镓或其它能够生长III-V族氮化物的衬底材料；所述第一半导体层材料为非掺杂氮化镓层；所述第二半导体层材料为铝镓氮或其它III-V族氮化物。
  15. 一种肖特基二极管的制作方法，其特征在于，包括：
    在所述衬底上依次沉积第一半导体层、第二半导体层和第一钝化介质层，所述第一半导体层与所述第二半导体层的交界面处形成有二维电子气；
    在所述第二半导体层上形成阴极；
    在所述阴极之间的第一钝化介质层和第二半导体层内形成阳极沟槽，且所述阳极沟槽的底部延伸至所述二维电子气所在的区域或穿过二维电子气所在的区域；
    在所述阳极沟槽与所述阴极之间的第一钝化介质层内形成场板沟槽，且所述场板沟槽的底部位于所述第一钝化介质层内或延伸至所述第二半导体层上表面或延伸至所述第二半导体层内；
    在所述阳极沟槽和所述场板沟槽上以及在所述阳极沟槽和所述场板沟槽之间的第一钝化介质层上和/或所述场板沟槽之外的第一钝化介质层上形成阳极。
  16. 根据权利要求15所述的肖特基二极管的制作方法，其特征在于，所述阳极沟槽或场板沟槽是通过干法刻蚀和/或湿法腐蚀工艺制备而成的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110521005A (zh) * 2018-12-28 2019-11-29 香港应用科技研究院有限公司 高压碳化硅肖特基二极管倒装芯片阵列

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465795B (zh) * 2014-11-19 2017-11-03 苏州捷芯威半导体有限公司 一种肖特基二极管及其制作方法
CN106611776A (zh) * 2015-10-22 2017-05-03 南京励盛半导体科技有限公司 一种n型碳化硅肖特基二极管结构
CN107104040A (zh) * 2016-02-23 2017-08-29 北京大学 氮化镓肖特基二极管的阳极制作方法
JP6558385B2 (ja) * 2017-02-23 2019-08-14 トヨタ自動車株式会社 半導体装置の製造方法
US20180331235A1 (en) * 2017-05-12 2018-11-15 Gpower Semiconductor, Inc. Schottky diode and manufacturing method thereof
TW201911583A (zh) * 2017-07-26 2019-03-16 新唐科技股份有限公司 異質接面蕭特基二極體元件
DE112018007055B4 (de) * 2018-02-09 2024-02-01 Mitsubishi Electric Corporation Leistungshalbleitereinheit
CN109786453B (zh) * 2018-04-25 2022-05-17 苏州捷芯威半导体有限公司 半导体器件及其制作方法
CN110718589B (zh) * 2018-07-12 2024-04-16 纳姆实验有限责任公司 具有半导体器件的电子电路的异质结构
CN111755510B (zh) * 2019-03-26 2024-04-12 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
CN112420850B (zh) * 2019-08-23 2024-04-12 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
CN111370483B (zh) * 2020-02-27 2023-05-26 常熟理工学院 一种具有多场板结构的氮化镓功率器件及其制备方法
CN111477678B (zh) * 2020-04-02 2021-07-09 西安电子科技大学 一种基于叉指结构的横向肖特基二极管及其制备方法
CN111952366A (zh) * 2020-08-19 2020-11-17 深圳方正微电子有限公司 场效应晶体管及其制备方法
WO2023013431A1 (ja) * 2021-08-03 2023-02-09 ヌヴォトンテクノロジージャパン株式会社 可変容量素子
CN115084231B (zh) * 2022-07-19 2023-03-03 浙江大学 一种二极管及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540343A (zh) * 2009-04-14 2009-09-23 西安电子科技大学 偏移场板结构的4H-SiC PiN/肖特基二极管及其制作方法
CN102598275A (zh) * 2009-08-28 2012-07-18 特兰斯夫公司 具有场板的半导体器件
US20130336033A1 (en) * 2012-06-14 2013-12-19 Infineon Technologies Austria Ag Integrated Power Semiconductor Component, Production Method and Chopper Circuit Comprising Integrated Semiconductor Component
CN104465795A (zh) * 2014-11-19 2015-03-25 苏州捷芯威半导体有限公司 一种肖特基二极管及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5065595B2 (ja) * 2005-12-28 2012-11-07 株式会社東芝 窒化物系半導体装置
JP4761319B2 (ja) * 2008-02-19 2011-08-31 シャープ株式会社 窒化物半導体装置とそれを含む電力変換装置
CN101604704B (zh) * 2008-06-13 2012-09-05 西安能讯微电子有限公司 Hemt器件及其制造方法
JP2010010412A (ja) * 2008-06-27 2010-01-14 Furukawa Electric Co Ltd:The 半導体素子及びその製造方法
US7898004B2 (en) * 2008-12-10 2011-03-01 Transphorm Inc. Semiconductor heterostructure diodes
JP2010219117A (ja) * 2009-03-13 2010-09-30 Toshiba Corp 半導体装置
JP5589329B2 (ja) * 2009-09-24 2014-09-17 豊田合成株式会社 Ｉｉｉ族窒化物半導体からなる半導体装置、電力変換装置
WO2011118098A1 (ja) * 2010-03-26 2011-09-29 日本電気株式会社 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置
JP5056883B2 (ja) * 2010-03-26 2012-10-24 サンケン電気株式会社 半導体装置
US8772842B2 (en) * 2011-03-04 2014-07-08 Transphorm, Inc. Semiconductor diodes with low reverse bias currents
US8772901B2 (en) * 2011-11-11 2014-07-08 Alpha And Omega Semiconductor Incorporated Termination structure for gallium nitride schottky diode
JP2013232578A (ja) * 2012-05-01 2013-11-14 Advanced Power Device Research Association ショットキーバリアダイオード
KR101927408B1 (ko) * 2012-07-20 2019-03-07 삼성전자주식회사 고전자 이동도 트랜지스터 및 그 제조방법
JP5777586B2 (ja) * 2012-09-20 2015-09-09 株式会社東芝 半導体装置及びその製造方法
JP2014090037A (ja) * 2012-10-29 2014-05-15 Advanced Power Device Research Association 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101540343A (zh) * 2009-04-14 2009-09-23 西安电子科技大学 偏移场板结构的4H-SiC PiN/肖特基二极管及其制作方法
CN102598275A (zh) * 2009-08-28 2012-07-18 特兰斯夫公司 具有场板的半导体器件
US20130336033A1 (en) * 2012-06-14 2013-12-19 Infineon Technologies Austria Ag Integrated Power Semiconductor Component, Production Method and Chopper Circuit Comprising Integrated Semiconductor Component
CN104465795A (zh) * 2014-11-19 2015-03-25 苏州捷芯威半导体有限公司 一种肖特基二极管及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110521005A (zh) * 2018-12-28 2019-11-29 香港应用科技研究院有限公司 高压碳化硅肖特基二极管倒装芯片阵列
CN110521005B (zh) * 2018-12-28 2022-03-18 香港应用科技研究院有限公司 碳化硅肖特基二极管及其制作方法

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