WO2015186223A1 - バースト信号受信回路 - Google Patents
バースト信号受信回路 Download PDFInfo
- Publication number
- WO2015186223A1 WO2015186223A1 PCT/JP2014/064985 JP2014064985W WO2015186223A1 WO 2015186223 A1 WO2015186223 A1 WO 2015186223A1 JP 2014064985 W JP2014064985 W JP 2014064985W WO 2015186223 A1 WO2015186223 A1 WO 2015186223A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- average value
- value detection
- differential
- burst signal
- detection circuit
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
- H03F3/45596—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction
- H03F3/45609—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by offset reduction by using a feedforward circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
- H04B10/6933—Offset control of the differential preamplifier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/695—Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
Definitions
- the present invention relates to a burst signal receiving circuit.
- a one-to-many optical communication system to which time division multiplexing is applied, in an upstream signal from one or a plurality of slave station devices to a master station device, packets from each slave station device are burst signals that are spaced apart from each other. It becomes.
- a photo detector Photo Detector: PD
- Transimpedance amplifier Transimpedance
- the signal detection circuit in the conventional burst signal receiving circuit uses DC coupling to connect to the TIA in order to avoid the occurrence of a bit error at the head of the burst received signal due to the AC transient response (for example, Patent Document 1 below)
- DC coupling to connect to the TIA in order to avoid the occurrence of a bit error at the head of the burst received signal due to the AC transient response
- processing such as filling a non-signal section with an idle signal is performed so that an AC transient response does not occur (for example, Non-Patent Document 1 below).
- the single-phase output of the TIA output circuit is branched into two, one is directly input to the LIA, the other is input to the average value detection circuit, and a differential signal is generated from the average value detection circuit. Average voltage is obtained.
- the output voltage of the average value detection circuit reaches almost the average value of the differential signal, since the differential signal cannot be reproduced in the LIA corresponding to the burst mode located in the subsequent stage, data loss occurs at the head of the burst signal. Will occur.
- Patent Document 1 in order to solve this problem, a high-speed time constant average value detection circuit that operates at a high speed but has a weak continuous sign strength, and a low-speed time constant that operates at a low speed but has a strong continuous sign resistance.
- the circuit configuration is such that the data loss amount at the head of the burst signal is minimized.
- Non-Patent Document 1 in order to avoid DC voltage drift in a non-signal section, a signal having a high speed and a low frequency cut-off frequency (for example, PRBS (Pseudo Random Binary Sequence) 7) in the non-signal section. Signal) is extrapolated.
- PRBS Physical Random Binary Sequence
- the DC voltage after AC coupling is always the same as when a burst signal is received, so even if AC coupling is performed with a capacitor having a large capacity (for example, 0.1 uF), DC voltage drift does not occur, and the burst signal It is supposed that the preamble length at the head can be shortened.
- between input / output circuits when the connection between the TIA and the LIA or between the LIA and the CDR circuit (hereinafter referred to as “between input / output circuits”) is DC coupled, the voltage level must be matched between the input / output circuits. Circuits that handle digital signals after the CDR circuit tend to decrease the power supply voltage in conjunction with recent advances in CMOS miniaturization technology, while the power supply voltage of the receiver circuit up to the LIA has a high speed, high gain, and low noise. Since it is required, it has stopped lowering, and there is a mismatch in the power supply voltage between circuits. Therefore, in recent trends, a situation where DC coupling is physically difficult has occurred.
- the single-phase output of the TIA output circuit is branched into two, one is directly input to the LIA, and the other is input to the average value detection circuit, from which the differential signal generation is generated. It is characterized by obtaining an average voltage.
- the assumed signal speed is about 1.25 Gbps, and for high-speed signals of 10 Gbps or more, the impedance between the input and output circuits. Since the resistance to matching and noise is reduced, there is a problem that it is difficult to use for high-speed signals.
- Non-Patent Document 1 processing for filling a no-signal section with an idle signal is performed in order to perform AC coupling between the LIA and the CDR circuit, but in order to perform this processing, before AC coupling, idle processing is performed. It is necessary to perform processing for combining the signal and the main signal.
- the burst signal receiving circuit up to the LIA is mounted in the transceiver housing, but after the CDR circuit, the LSI is integrated with the media access control (MAC) processing unit.
- MAC media access control
- the interface with the transceiver is also standardized. Therefore, there arises a problem that the transceiver has to receive an uncommon idle signal from the outside and match it with the main signal.
- the present invention has been made in view of the above, and eliminates data loss at the head of a burst signal or makes it extremely small even when input-output circuits cannot be DC-coupled and AC coupling is required.
- An object of the present invention is to provide a burst signal receiving circuit capable of performing the above.
- the present invention provides a burst signal receiving circuit that receives a differential signal of a burst signal input via a preamplifier, and the differential signal is received by a capacitor.
- a differential amplifier that inputs the differential input signal to the differential amplifier, an average value detection circuit that detects an average value of the differential input signal to the differential amplifier, and a DC of the differential input signal based on an output signal of the average value detection circuit
- a differential offset cancellation circuit that operates to cancel the voltage level difference, and the average value detection speed of the average value detection circuit is configured to be switched depending on whether or not a burst signal is received, and the burst signal It is characterized in that it is switched to the high speed side at the head portion of the, and is switched to the low speed side other than the head portion.
- FIG. 1 is a diagram illustrating a configuration example of a burst signal receiver including a burst signal receiving circuit according to the first embodiment.
- FIG. 2 is a diagram illustrating a configuration example of the burst signal receiving circuit according to the first embodiment.
- FIG. 3 is a diagram illustrating a configuration example of the average value detection circuit according to the first embodiment.
- FIG. 4 is a diagram showing an outline of a main waveform for explaining the operation of the burst signal receiving circuit according to the first embodiment.
- FIG. 5 is a diagram illustrating a configuration example of the average value detection circuit according to the second embodiment.
- FIG. 6 is a diagram illustrating a configuration example of an average value detection circuit according to the third embodiment.
- FIG. 1 is a diagram illustrating a configuration example of a burst signal receiver including a burst signal receiving circuit according to the first embodiment.
- the burst signal receiving circuit 3 converts the current signal flowing through the PD 1 into a voltage signal by the preamplifier 2 (TIA is illustrated in FIG. 1), and is included in the voltage signal.
- TIA is illustrated in FIG. 1
- This is a circuit that detects the transmitted signal component and transmits it as an output signal to the subsequent circuit.
- FIG. 2 is a diagram illustrating a configuration example of the burst signal receiving circuit according to the first embodiment.
- the burst signal receiving circuit 3 inputs a differential input signal from the differential signal input terminals 15a and 15b via capacitors 11a and 11b that perform AC coupling.
- Amplifier 4 positive phase input average value detection circuit 8a and negative phase input average value detection circuit 8b, positive phase input average value detection circuit 8a and negative phase input for detecting the average value of differential input signals
- a differential offset cancel circuit 5 for canceling the DC voltage level difference of the differential input signal based on each output signal of the average value detection circuit 8b.
- the differential amplifier 4 includes input termination resistors 21 and 22, first-stage differential pair transistors 31 and 32, first-stage differential pair load resistors 41 and 42, and a first-stage differential pair current source 45.
- the differential offset cancel circuit 5 includes an offset cancel differential pair 61 and 62 and an offset cancel differential pair current source 55.
- first stage is attached to the head of the differential amplifier 4 for convenience.
- the term “for offset cancellation” is attached to the head.
- the first-stage differential pair load resistors 41 and 42 are shown only in the differential amplifier 4 in FIG. 2, but can also be provided in the differential offset cancel circuit 5. However, as shown in FIG.
- the collector terminals of the first-stage differential pair transistor 31 and the offset canceling differential pair 61 and the collector terminals of the first-stage differential pair transistor 32 and the offset canceling differential pair 62 are connected to each other so that a differential signal output terminal 16a and 16b, and the outputs of the differential signal output terminals 16a and 16b are output signals of the burst signal receiving circuit 3.
- the normal phase input average value detection circuit 8a and the negative phase input average value detection circuit 8b have the same circuit configuration, and FIG. 3 shows only the circuit configuration. Henceforth, a common circuit part is named the average value detection circuit 8 generically.
- the average value detection circuit 8 includes average value detection circuit resistors 81 and 82, an average value detection circuit capacitor 83, an average value detection speed switching MOS switch 84, and an average value detection circuit operational amplifier 85.
- the In FIG. 3, the average value detection circuit 8 is configured as a primary LPF using an operational amplifier. However, the average value detection circuit 8 may be configured as an LPF having a second order or higher order, and does not use an operational amplifier. You may comprise as.
- the differential amplifier 4 has a linear amplifier configuration in which an output signal can be obtained even when the DC levels of the differential input signals do not match. Therefore, a configuration in which a resistor is inserted between the emitters of the first-stage differential pair transistors 31 and 32 may be employed. Further, although an NPN transistor is shown in FIG. 2, it may be an NMOS transistor. In this embodiment, since high-speed signals such as 10 Gbps are exchanged, the output terminal is terminated with the same resistance as the input termination resistors 21 and 22 as in the CML (Current Mode Logic) level before AC coupling. It is assumed that the buffer is connected.
- CML Current Mode Logic
- FIG. 4 is a diagram showing a main part waveform in the burst signal receiving circuit according to the first embodiment, and shows a waveform when a signal is inputted after a long no-signal section.
- the circuit configuration is such that the time constant is switched using the average value detection circuit 8 and the differential offset cancel circuit 5. Specifically, it is as follows.
- a LOS (Loss of Signal) signal is input to the average value detection circuit 8 from the outside through the reset input terminal 18.
- the LOS signal is input to an average value detection speed switching MOS switch 84 provided in the average value detection circuit 8, and the time constant is switched by turning on the MOS switch 84. That is, the MOS switch 84 that operates according to the LOS signal indicating whether or not the burst signal is received operates as the switching circuit 9 for switching the average value detection speed of the average value detection circuit 8.
- the resistance value is reduced by short-circuiting the MOS switch 84. That is, in the no-signal section, the time constant of the average value detection circuit 8 is set to a high speed and is rapidly converged from several bits to several tens of bits at the head of the burst signal (see FIG. 3).
- the resistance value is increased by opening the MOS switch 84. That is, after the burst signal can be identified, the time constant of the average value detection circuit 8 is lowered to reduce the speed. At that time, the speed is set to a speed that can follow the AC response time constant determined by the AC coupling and the input / output termination resistance (for example, 10 times the speed). With such a setting, it is possible to have sufficient resistance even for signals that require continuous resistance of the same sign, such as a CID (Consequential Identification Digit) signal, while following the AC transient response.
- a CID Consequential Identification Digit
- the LOS signal can respond within about 100 ns or less within the LIA, so that the signal can be used on the CDR circuit side.
- the presence / absence of a signal can be identified by reading the current value of PD and the amplitude value inside TIA. Can be used.
- the output voltage of the average value detection circuit 8 generated by switching the time constant is input to the differential pair of the differential offset cancel circuit 5, that is, the bases of the offset cancel differential pairs 61 and 62, respectively.
- the offset level of the differential output voltage of the differential amplifier 4 can be adjusted. For example, when the positive phase of the DC voltage level of the differential input signal (for example, the voltage on the differential signal input terminal 15a side) is high, the current value on the positive phase output side of the differential amplifier 4 (first-stage differential versus load resistance 41). The amount of drop voltage at the first-stage differential pair load resistor 41 is increased by increasing the value of the current flowing in the differential signal output terminals 16a and 16b.
- the average value detection circuit detects the average value of the differential input signal to the differential amplifier input through the capacitor
- the dynamic offset cancel circuit operates to cancel the DC voltage level difference of the differential input signal based on the output signal of the average value detection circuit, and determines the average value detection speed of the average value detection circuit depending on whether or not the burst signal is received, Since the first part of the burst signal is switched to the high speed side and the other part is switched to the low speed side, the preamble at the head of the burst signal can be used even when DC coupling is not possible between the input and output circuits and AC coupling is required. It is possible to reproduce the signal on the receiving side in time and eliminate the data loss at the beginning of the burst signal or make it extremely small That.
- the burst signal receiving circuit according to the first embodiment it is possible to create a new circuit in the previous circuit in the case of AC coupling (for example, in the case of AC coupling between the LIA and the CDR circuit). Since a high-speed burst reception can be realized by adding a new circuit only to the subsequent circuit side that requires AC coupling, there is an effect that even if the previous circuit is already completed, the previous circuit is not affected. .
- Embodiment 2 FIG.
- the average value detection circuit resistor 81 is arranged in parallel with the MOS switch 84 for switching the average value detection speed, and the time constant is changed by changing the resistance value.
- the time constant is changed (switched) by changing the capacitance value of the capacitor instead of changing the resistance value.
- the configuration of the burst signal receiving circuit is the same as or equivalent to that of the first embodiment, except for the configuration of the positive phase input average value detection circuit 8a and the negative phase input average value detection circuit 8b.
- the same reference numerals are given to the parts, and duplicate descriptions are omitted.
- FIG. 5 is a diagram illustrating a configuration example of the average value detection circuit according to the second embodiment.
- the average value detection circuit 8 according to the second embodiment includes an average value detection circuit resistor 82, average value detection circuit capacitors 83 and 86, an average value detection speed switching MOS switch 87, and an average value detection circuit operational amplifier 85. Is done.
- This average value detection circuit 8 is applied as a positive phase input average value detection circuit 8a and a negative phase input average value detection circuit 8b shown in FIG.
- the average value detection circuit 8 is in the form of a primary LPF using an operational amplifier, but may be an LPF having a second order or higher order, and does not use an operational amplifier. Form may be sufficient.
- the operation in the second embodiment is almost the same as that in the first embodiment, but there are also differences. Specifically, in the second embodiment, the combined capacity is increased by short-circuiting the MOS switch 87 in the non-signal period, while the capacity is decreased by opening the MOS switch 87 in the signal reception period. The point is to change the time constant. With this configuration, it is possible to further reduce the amount of bit loss at the beginning of the packet, and to maintain the same code consecutive strength in the data area of the burst signal.
- Embodiment 3 In the first and second embodiments described above, a resistor or capacitor is connected in parallel with the MOS switch 84 for switching the average value detection speed as shown in FIG. 3 or FIG.
- the time constant was changed by changing it.
- the third embodiment an embodiment in which the time constant is changed (switched) by changing both the resistance value and the capacitance value will be described.
- the configuration of the burst signal receiving circuit is the same as or equivalent to that of the first embodiment (or the second embodiment) except for the configurations of the positive phase input average value detection circuit 8a and the negative phase input average value detection circuit 8b. Yes, the same or equivalent components are denoted by the same reference numerals, and redundant description is omitted.
- FIG. 6 is a diagram illustrating a configuration example of an average value detection circuit according to the third embodiment.
- the average value detection circuit 8 according to the third embodiment includes average value detection circuit resistors 81 and 82, average value detection circuit capacitors 83 and 86, average value detection speed switching MOS switches 84 and 87, and an average value detection circuit operational amplifier 85. It is configured with.
- This average value detection circuit 8 is applied as a positive phase input average value detection circuit 8a and a negative phase input average value detection circuit 8b shown in FIG.
- the average value detection circuit 8 is in the form of a primary LPF using an operational amplifier, but it may be an LPF having a second order or higher order, and does not use an operational amplifier. Form may be sufficient.
- the operation in the third embodiment is almost the same as that in the first or second embodiment, but there are also differences. More specifically, in the third embodiment, in the no-signal section, the resistance value is reduced by short-circuiting the MOS switch 84, and the combined capacitance is increased by short-circuiting the MOS switch 87. On the other hand, after the burst signal can be identified, the MOS switch 84 is opened to increase the resistance value, and the MOS switch 87 is opened to reduce the capacitance and change the time constant. With this configuration, the difference between the high-speed time constant and the low-speed time constant can be made larger than in the first and second embodiments, and a more optimal time constant can be set.
- Embodiments 1 to 3 above are examples of the configuration of the present invention, and can be combined with other known techniques, and can be combined within the scope of the present invention. Needless to say, the configuration may be modified by omitting the unit.
- the present invention provides a burst signal receiving circuit capable of eliminating or extremely reducing data loss at the head of a burst signal even when the input / output circuits cannot be DC coupled and AC coupling is required. Useful as.
- 1 PD photo detector
- 2 preamplifier 3 burst signal receiving circuit
- 4 differential amplifier 5 differential offset cancel circuit
- 8 average value detection circuit 8a positive phase input average value detection circuit
- 8b for reverse phase input Average value detection circuit 9 switching circuit, 11a, 11b capacitor, 15a, 15b differential signal input end, 16a, 16b differential signal output end, 18 reset input end, 21, 22 input termination resistance, 31, 32 first stage differential Transistor, 41, 42 First stage differential pair load resistance, 45 First stage differential pair current source, 55 Offset cancellation differential pair current source, 61, 62 Offset cancellation differential pair, 81, 82 Average value detection circuit resistance, 83,86 Average value detection circuit capacitor, 84,87 MOS switch, 85 Average value detection circuit ope Flop.
Abstract
Description
図1は、実施の形態1に係るバースト信号受信回路を含むバースト信号受信器の一構成例を示す図である。実施の形態1に係るバースト信号受信回路3は、図1に示すように、PD1に流れる電流信号を前置増幅器2(図1ではTIAを例示)が電圧信号に変換し、その電圧信号に含まれる信号成分を検出して後段の回路に出力信号として伝達する回路である。
上述した実施の形態1では、図3に示したように平均値検出速度切り替え用のMOSスイッチ84と並列に、平均値検出回路抵抗81を配置し、抵抗値を変更することで時定数を変更していた。一方、実施の形態2では、抵抗値の変更ではなく、コンデンサの容量値を変更することで時定数の変更(切り替え)を行う実施の形態について説明する。なお、バースト信号受信回路の構成は、正相入力用平均値検出回路8aおよび逆相入力用平均値検出回路8bの構成を除き、実施の形態1と同一または同等であり、同一または同等の構成部には同一の符号を付して重複する説明は省略する。
上述した実施の形態1,2では、図3または図5に示したように平均値検出速度切り替え用のMOSスイッチ84と並列に、抵抗またはコンデンサを接続し、抵抗値または容量値の何れかを変更することで時定数を変更していた。一方、実施の形態3では、抵抗値および容量値の双方を変更することで時定数の変更(切り替え)を行う実施の形態について説明する。なお、バースト信号受信回路の構成は、正相入力用平均値検出回路8aおよび逆相入力用平均値検出回路8bの構成を除き、実施の形態1(もしくは実施の形態2)と同一または同等であり、同一または同等の構成部には同一の符号を付して重複する説明は省略する。
Claims (6)
- 前置増幅器を介して入力されるバースト信号の差動信号を受信するバースト信号受信回路であって、
前記差動信号をコンデンサを介して入力する差動増幅器と、
前記差動増幅器への差動入力信号の平均値を検出する平均値検出回路と、
前記平均値検出回路の出力信号に基づいて前記差動入力信号のDC電圧レベル差をキャンセルするように動作する差動オフセットキャンセル回路と、
を備え、
前記平均値検出回路の平均値検出速度は、バースト信号受信の有無によって切り替えられるように構成されており、
前記バースト信号の先頭部分では高速側に切り替えられ、当該先頭部分以外ではより低速側に切り替えられる
ことを特徴とするバースト信号受信回路。 - 前記差動オフセットキャンセル回路は、初段差動差動器と負荷抵抗を同一とする差動増幅器であることを特徴とする請求項1に記載のバースト信号受信回路。
- 前記平均値検出回路は、抵抗、コンデンサおよびオペアンプを用いたLPFであることを特徴とする請求項1または2に記載のバースト信号受信回路。
- 前記平均値検出回路の平均値検出速度は、抵抗値の切り替えによって変更されることを特徴とする請求項1から3の何れか1項に記載のバースト信号受信回路。
- 前記平均値検出回路の平均値検出速度は、容量値の切り替えによって変更されることを特徴とする請求項1から3の何れか1項に記載のバースト信号受信回路。
- 前記平均値検出回路の平均値検出速度は、抵抗値および容量値の双方の切り替えによって変更されることを特徴とする請求項1から3の何れか1項に記載のバースト信号受信回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201480078176.7A CN106233644B (zh) | 2014-06-05 | 2014-06-05 | 突发信号接收电路 |
US15/124,520 US9628194B2 (en) | 2014-06-05 | 2014-06-05 | Burst-signal reception circuit |
JP2016513564A JP5951160B2 (ja) | 2014-06-05 | 2014-06-05 | バースト信号受信回路 |
PCT/JP2014/064985 WO2015186223A1 (ja) | 2014-06-05 | 2014-06-05 | バースト信号受信回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2014/064985 WO2015186223A1 (ja) | 2014-06-05 | 2014-06-05 | バースト信号受信回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015186223A1 true WO2015186223A1 (ja) | 2015-12-10 |
Family
ID=54766319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2014/064985 WO2015186223A1 (ja) | 2014-06-05 | 2014-06-05 | バースト信号受信回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9628194B2 (ja) |
JP (1) | JP5951160B2 (ja) |
CN (1) | CN106233644B (ja) |
WO (1) | WO2015186223A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018198249A1 (ja) * | 2017-04-26 | 2018-11-01 | 三菱電機株式会社 | 振幅制限増幅器、光受信器、光終端装置、および光通信システム |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11725985B2 (en) * | 2018-05-03 | 2023-08-15 | Verity Instruments, Inc. | Signal conversion system for optical sensors |
JP7125820B1 (ja) | 2022-07-01 | 2022-08-25 | 株式会社シェルタージャパン | シェルター扉の断熱構造 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036470A (ja) * | 1999-07-15 | 2001-02-09 | Sharp Corp | バースト伝送対応光受信器 |
JP2009278426A (ja) * | 2008-05-15 | 2009-11-26 | Nippon Telegr & Teleph Corp <Ntt> | 振幅制限増幅回路 |
JP2010278753A (ja) * | 2009-05-28 | 2010-12-09 | Mitsubishi Electric Corp | 差動増幅器および光受信器 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2625347B2 (ja) * | 1993-04-20 | 1997-07-02 | 日本電気株式会社 | ディジタル受信器の自動オフセット制御回路 |
JP3209909B2 (ja) * | 1996-01-30 | 2001-09-17 | 富士通株式会社 | バースト光信号受信機 |
US6826372B1 (en) * | 2000-08-30 | 2004-11-30 | Sycamore Networks, Inc. | Methods and apparatus for dynamic threshold setting for an optically amplified receiver |
JP2005184658A (ja) | 2003-12-22 | 2005-07-07 | Mitsubishi Electric Corp | 光受信回路 |
JP4729454B2 (ja) * | 2006-08-04 | 2011-07-20 | 富士通株式会社 | 光受信回路及びその識別レベル制御方法 |
KR101009806B1 (ko) * | 2006-12-21 | 2011-01-19 | 미쓰비시덴키 가부시키가이샤 | 광 수신기 |
US7920798B2 (en) | 2007-06-18 | 2011-04-05 | Micrel, Inc. | PON burst mode receiver with fast decision threshold setting |
JP5138990B2 (ja) * | 2007-06-28 | 2013-02-06 | ラピスセミコンダクタ株式会社 | 前置増幅器および光受信装置 |
JP5283443B2 (ja) | 2007-10-10 | 2013-09-04 | 株式会社エヌ・ティ・ティ・ドコモ | 複合通信システム、禁止信号送信装置、無線基地局及び方法 |
US20100272448A1 (en) * | 2007-11-19 | 2010-10-28 | Fujikura Ltd. | Optical burst signal receiving device |
JP5176505B2 (ja) * | 2007-12-03 | 2013-04-03 | 富士通オプティカルコンポーネンツ株式会社 | 光受信装置,光局側装置および光ネットワークシステム |
CN102257749B (zh) * | 2009-01-19 | 2014-04-30 | 株式会社日立制作所 | 跨阻抗放大器及pon系统 |
JP5496514B2 (ja) | 2009-01-19 | 2014-05-21 | 株式会社Nttドコモ | 無線通信システム |
JP2010178256A (ja) * | 2009-02-02 | 2010-08-12 | Nippon Telegr & Teleph Corp <Ntt> | 光受信器の増幅器 |
JP5396637B2 (ja) | 2009-05-29 | 2014-01-22 | 独立行政法人情報通信研究機構 | 地上/衛星共用携帯電話システム |
JP4856771B2 (ja) * | 2010-02-15 | 2012-01-18 | 日本電信電話株式会社 | 光信号断検出回路および光受信器 |
JP5494285B2 (ja) * | 2010-06-24 | 2014-05-14 | 住友電気工業株式会社 | 電子回路 |
JP2012085229A (ja) * | 2010-10-14 | 2012-04-26 | Nec Corp | Ponシステムとその局側装置及び光受信器並びに光受信方法 |
CN103229435B (zh) * | 2011-04-05 | 2015-05-06 | 三菱电机株式会社 | 光接收器 |
WO2012144038A1 (ja) * | 2011-04-20 | 2012-10-26 | 富士通オプティカルコンポーネンツ株式会社 | 検出装置、光受信装置、検出方法および光受信方法 |
JP5906818B2 (ja) * | 2012-03-02 | 2016-04-20 | 住友電気工業株式会社 | 差動増幅回路および光受信装置 |
-
2014
- 2014-06-05 CN CN201480078176.7A patent/CN106233644B/zh not_active Expired - Fee Related
- 2014-06-05 JP JP2016513564A patent/JP5951160B2/ja not_active Expired - Fee Related
- 2014-06-05 US US15/124,520 patent/US9628194B2/en not_active Expired - Fee Related
- 2014-06-05 WO PCT/JP2014/064985 patent/WO2015186223A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001036470A (ja) * | 1999-07-15 | 2001-02-09 | Sharp Corp | バースト伝送対応光受信器 |
JP2009278426A (ja) * | 2008-05-15 | 2009-11-26 | Nippon Telegr & Teleph Corp <Ntt> | 振幅制限増幅回路 |
JP2010278753A (ja) * | 2009-05-28 | 2010-12-09 | Mitsubishi Electric Corp | 差動増幅器および光受信器 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018198249A1 (ja) * | 2017-04-26 | 2018-11-01 | 三菱電機株式会社 | 振幅制限増幅器、光受信器、光終端装置、および光通信システム |
Also Published As
Publication number | Publication date |
---|---|
JP5951160B2 (ja) | 2016-07-13 |
US20170019184A1 (en) | 2017-01-19 |
US9628194B2 (en) | 2017-04-18 |
JPWO2015186223A1 (ja) | 2017-04-20 |
CN106233644A (zh) | 2016-12-14 |
CN106233644B (zh) | 2018-01-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2021232861A1 (zh) | 差分信号放大电路、数字隔离器和接收器 | |
JP5238085B2 (ja) | 差動ドライバー回路の高速コモンモードフィードバック制御装置 | |
US8502584B1 (en) | Capacitive isolation receiver circuitry | |
US8451032B2 (en) | Capacitive isolator with schmitt trigger | |
US20080260049A1 (en) | Serializer and deserializer | |
US10700785B2 (en) | Optical transceiver | |
JPH0823354A (ja) | 信号入出力装置 | |
KR20160005431A (ko) | 버퍼 증폭기 및 버퍼 증폭기를 포함하는 트랜스 임피던스 증폭기 | |
WO2015060066A1 (ja) | トランスインピーダンスアンプ回路 | |
US20130002347A1 (en) | Coupling system for data receivers | |
JP5951160B2 (ja) | バースト信号受信回路 | |
JP2008029004A (ja) | チャンネルの相互シンボル干渉を減らし、信号利得損失を補償する受信端 | |
JP2007036329A (ja) | 増幅回路およびトランスインピーダンスアンプ | |
JP2016063345A (ja) | 受信回路 | |
JP2011244093A (ja) | 光受信回路 | |
JP2009038556A (ja) | リミッタアンプ回路 | |
TWI517710B (zh) | 可同時處理差模信號及共模信號的接收電路 | |
US20170034607A1 (en) | Burst-mode receiver | |
JP3577541B2 (ja) | 受信回路 | |
US7212071B2 (en) | Techniques to lower drive impedance and provide reduced DC offset | |
JP2024061131A (ja) | 光受信器、光通信システムおよび車載光通信ネットワークシステム | |
JP3881293B2 (ja) | 瞬時応答増幅回路 | |
JP2012156660A (ja) | 受信回路並びにそれを備えた半導体装置及び情報処理システム | |
JP2004120468A (ja) | インプットイコライザ | |
JP2005136649A (ja) | 瞬時応答振幅制限増幅回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14894157 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2016513564 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15124520 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14894157 Country of ref document: EP Kind code of ref document: A1 |