WO2015060066A1 - トランスインピーダンスアンプ回路 - Google Patents
トランスインピーダンスアンプ回路 Download PDFInfo
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- WO2015060066A1 WO2015060066A1 PCT/JP2014/075634 JP2014075634W WO2015060066A1 WO 2015060066 A1 WO2015060066 A1 WO 2015060066A1 JP 2014075634 W JP2014075634 W JP 2014075634W WO 2015060066 A1 WO2015060066 A1 WO 2015060066A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3084—Automatic control in amplifiers having semiconductor devices in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
- H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
- H03F3/087—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with IC amplifier blocks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
- H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/58—Compensation for non-linear transmitter output
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
- H04B10/6931—Automatic gain control of the preamplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45142—At least one diode being added at the input of a dif amp
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45288—Differential amplifier with circuit arrangements to enhance the transconductance
Definitions
- the present invention relates to a transimpedance amplifier (TIA) circuit, and more particularly to an automatic gain adjustment function of a TIA circuit.
- TIA transimpedance amplifier
- FIG. 9 is a block diagram of a configuration example of a general TIA circuit.
- the TIA circuit 100 is a multistage amplifier circuit including amplifiers 22, 40 and 50.
- the TIA circuit 100 further includes an automatic gain control (AGC) circuit 200 that includes a gain control unit 21 and adjusts the gain of the amplifier 22 in the first stage.
- the gain control unit 21 controls the feedback resistor Rf of the amplifier 22 with the control voltage Vagc, and adjusts the gain of the amplifier 22 so as to keep the amplitude of the signal output from the amplifier 22 at a constant value.
- AGC automatic gain control
- the received light intensity varies depending on the length of the communication distance, and therefore it is required to amplify from a weak (dark) optical signal to a strong (bright) optical signal with low noise and low distortion (distortion).
- the TIA circuit for optical communication often has a function of adjusting the amplification gain according to the magnitude of the input signal intensity, that is, the magnitude of the received light intensity. When the intensity is small, the gain is increased.
- AGC circuits in which such gain adjustment is automatically performed have been put into practical use in various architectures.
- the AGC circuit adjusts the gain with a certain time constant.
- a function for the AGC circuit to determine and control an optimum gain is referred to as an “AGC function”
- a time constant when the AGC circuit adjusts the gain is referred to as an “AGC function time constant”.
- the time constant of the AGC function is determined by the size of the resistor Ragc and the capacitance Cagc of the AGC circuit 200.
- the time constant of the AGC function is too short, it follows the logic change of the input signal, and a desired output may not be obtained.
- the time constant of the AGC function is designed to be a time constant that is long enough to grasp the average input amplitude in consideration of the baud rate of the input data and the encoding method.
- the burst response time is set to within 800 ns in total for the TIA and the limiting amplifier at the subsequent stage, and the TIA circuit responds within about 400 ns.
- the AGC function time constant is set to be relatively short, or different fixed gains are switched for each burst.
- the TIA circuit for continuous optical communication in which the time constant of the AGC function is set to be relatively long cannot respond to burst signals, and burst communication. If a TIA circuit with a relatively short time constant of the AGC function is used for continuous optical communication, the continuous code becomes longer depending on the encoding method, and the BER characteristics particularly in the input optical power in the error-free vicinity region deteriorate. End up. Further, in order to apply a TIA circuit for burst communication to continuous signals, expensive signal processing such as FEC is required, and for example, a system needs to be constructed at low cost such as Ethernet (registered trademark). It is not preferable in the network.
- a method of adjusting a time constant by connecting a capacitive element or a resistive element as an external component outside an IC chip on which a TIA circuit is integrated is conceivable (for example, non-patent document). 2).
- this method if there are multiple locations in the circuit where the capacitance and resistance should be increased or decreased, the same number of terminals (pads) for connecting external elements are required, and there are external terminals in the optical module on which the TIA chip is mounted. It is also necessary to secure a space for mounting the element.
- a problem to be solved by the present invention is that a low-cost and compact circuit combines a time constant of a short AGC function for instantaneously responding to a burst signal and a time constant of a long AGC function for obtaining good BER characteristics in a continuous signal. It is to be compatible with the configuration.
- a transimpedance amplifier circuit includes an amplifier that amplifies a received signal, and an amplification gain of the amplifier is adjusted with a first time constant according to the level of the received signal. And an automatic gain adjustment circuit for selecting the first time constant from a plurality of predetermined values.
- a short time constant for instantaneously responding to a burst signal and a long time constant for obtaining good BER characteristics in a continuous signal can be realized with a low-cost and compact circuit configuration.
- FIG. 1 is a block diagram showing a configuration example of a TIA circuit according to the first embodiment of the present invention.
- FIG. 2 is a block diagram illustrating a configuration example of the TIA circuit according to the first embodiment.
- FIG. 3 is a block diagram showing a modification of the TIA circuit according to the first embodiment.
- FIG. 4 is a block diagram showing a configuration example of a TIA circuit according to the second embodiment of the present invention.
- FIG. 5A is a block diagram illustrating a modification of the TIA circuit according to the second embodiment.
- FIG. 5B is a diagram illustrating a transfer gate circuit.
- FIG. 6 is a block diagram showing a configuration example of a TIA circuit according to the third embodiment of the present invention.
- FIG. 7A is a block diagram illustrating a configuration example of a signal detection circuit provided in the TIA circuit according to the third embodiment.
- FIG. 7B is a block diagram illustrating a configuration example of a signal detection circuit provided in the TIA circuit according to the third embodiment.
- FIG. 8 is a configuration example of a TIA circuit according to the fourth embodiment of the present invention.
- FIG. 9 is a block diagram showing a configuration example of a conventional TIA circuit.
- the present invention in order to realize the time constants of a plurality of AGC functions, for example, at least one of the resistance value of the resistance element and the capacitance value of the capacitance element that determines the value of the time constant of the AGC function based on the control signal is calculated. change.
- the first selection circuit that selects the time constant of the AGC function from a plurality of predetermined values includes a plurality of resistance elements or a plurality of capacitance elements included in the AGC circuit, and the plurality of resistance elements.
- a switch that is connected in series or in parallel with at least a part of the plurality of capacitive elements and changes the resistance value of the resistive element or the capacitance value of the capacitive element that determines the value of the time constant by turning on or off based on a control signal Element.
- a switch is installed in at least a part of a resistor element or a capacitor element of a circuit that determines the time constant of the AGC function, or both elements, and these elements are activated or controlled by on / off control of the switch. By invalidating, the resistance value or the capacitance value is changed.
- a switch when a switch is connected in parallel with a resistive element or a capacitive element, if the switch is on, the terminal of the element is short-circuited, the element is invalidated, and if the switch is off, conversely The short-circuit state changes to the open state, and the element becomes effective.
- a switch may be connected in series with the element, the element may be connected to the circuit when the switch is on, and the element may not be connected to the circuit when the switch is off, or a combination thereof. That is, the resistance element and the capacitive element are enabled or disabled by the switch control inside the circuit, and the time constant in the AGC circuit can be changed discretely.
- a MOS transistor can be used as the switch.
- the control signal is applied to the gate terminal of the MOS transistor.
- the gate terminal of the MOS transistor is the input terminal for the switch control signal
- the switch is turned on and the switch is short-circuited.
- the switch is opened. The reverse is true for a PMOS transistor.
- the control signal of the switch element is a logic signal of 2 bits or more, and the switch element switches the time constant of the AGC function between a plurality of predetermined discrete values according to the value of the logic signal. May be.
- the first selection circuit further includes a reception signal detection circuit that detects a reception signal and outputs a first control signal when a continuous reception time of the reception signal exceeds a predetermined time.
- a longer time constant may be selected from two or more predetermined values of the first time constant based on one control signal.
- the reception signal detection circuit outputs a second control signal when the signal disconnection of the reception signal is detected, and the first selection circuit outputs the first control signal based on the second control signal.
- a shorter time constant may be selected from two or more values determined in advance.
- FIG. 1 is a configuration example of a TIA circuit that controls the time constant of the AGC circuit with one external terminal.
- the TIA circuit 1 is a multistage amplifier circuit including amplifiers 22, 40 and 50.
- the TIA circuit 1 further includes an AGC circuit 2 that includes a gain control unit 21 and adjusts the gain of the first-stage amplifier 22.
- the gain control unit 21 controls the feedback resistor Rf of the amplifier 22 with the control voltage Vagc, and adjusts the gain of the amplifier 22 so as to keep the amplitude of the signal output from the amplifier 22 at a constant value. That is, the AGC circuit 2 controls the gain of the amplifier 22 so that the amplitude of the signal output from the amplifier 22 is maintained at a constant value.
- the AGC circuit 2 further includes a resistor (Ragc, Rs), a capacitor (Cagc, Cs), and switches SW1, SW2.
- the resistor Rs to be added is connected in series with the resistor Ragc, and SW1 is connected in parallel with the resistor Rs.
- An additional capacitor Cs is connected in parallel with the capacitor Cagc, and SW2 is connected in series with the capacitor Cs.
- These switches SW1 and SW2 are turned ON / OFF by a switch control signal Vsw.
- the time constant of the AGC function of the TIA circuit 1 is determined from a plurality of predetermined values obtained by a combination of resistance (Ragc, Rs) and capacitance (Cagc, Cs) by turning on / off the switches SW1 and SW2. You can choose.
- resistors (Ragc, Rs), capacitors (Cagc, Cs), and switches SW1, SW2 form a first selection circuit 25 that selects a time constant of the AGC function from a plurality of predetermined values.
- the polarities of the switches SW1 and SW2 are opposite to each other. For example, when the switch control signal Vsw is High, SW1 is open (OFF) and SW2 is connected (ON). . Needless to say, the reverse logic may be used.
- the switch control signal Vsw may be at the DC level, the switch control signal Vsw may be pulled up to the power supply voltage in the continuous mode and pulled down to the ground level in the burst mode, and the additional external terminal may be a minimum of one pin.
- FIG. 1 the configuration in which the resistance element and the capacitance element are complementarily switched using one control signal has been described.
- the resistance and the capacitance are respectively set according to the value of the time constant to be designed. You may make it control separately.
- the time constant may be switched by controlling only the resistance or the capacitance. With such a configuration, two pins are required for the external terminal, but a value of two or more discrete time constants is determined in advance, and the time change of the received optical signal, for example, an optical signal that is continuously received It is also possible to select a desired time constant depending on whether the optical signal is received in bursts, and more flexible time constant control is possible.
- the additional resistor Rs is connected in series with the resistor Ragc and the additional capacitor Cs is connected in parallel with the capacitor Cagc.
- the circuit configuration of the selection circuit 25a composed of the resistors (Ragc, Rs), the capacitors (Cagc, Cs), and the switches SW1 and SW2 is set so that the additional resistor element Rs is connected in parallel and the additional capacitor element Cs is connected in series. Good.
- the resistance value of the resistance element or the capacitance value of the capacitance element which is a component that determines the time constant, is set in advance so that the time constant can take discrete values, and the switching element SW1.
- the time constant is selectively controlled by turning ON / OFF SW2.
- the value of each element and the connection form may be appropriately selected and determined according to the desired time constant value. The same applies to the embodiments described below.
- the TIA circuit according to the second embodiment of the present invention is a configuration example of a TIA circuit that outputs a differential output.
- a TIA circuit used in high-speed communication desirably has a differential output.
- S2D Single-to-Differential Converter
- the TIA circuit In burst signal reception, since the light intensity between burst signals is not always equal, when a single-phase signal is changed to a differential signal within the TIA circuit, it is necessary to eliminate the DC offset of the differential signal.
- the TIA circuit is provided with an automatic offset adjustment (AOC) circuit that automatically eliminates the DC offset of the differential signal. Similar to the time constant of the AGC function, the time constant of the AOC function by the AOC circuit needs to be shorter than that of the continuous optical signal TIA circuit in burst signal reception.
- AOC automatic offset adjustment
- the time constant of the AOC function in the conventional TIA circuit is fixed. Therefore, when an AOC circuit corresponding to a burst signal is applied to continuous optical communication, the BER characteristic deteriorates depending on the encoding method. In a TIA circuit equipped with an AOC function having a long time constant for continuous optical communication, There was a problem of not being able to respond to the signal.
- the second selection circuit can change at least one of a resistance value of the resistance element that determines a value of the second time constant and a capacitance value of the capacitance element based on the control signal.
- the second selection circuit is connected in series or in parallel to a plurality of resistance elements or a plurality of capacitance elements included in the AOC circuit and at least a part of the plurality of resistance elements or the plurality of capacitance elements, And a second switch element that changes the resistance value of the resistance element or the capacitance value of the capacitance element that determines the value of the second time constant by turning on or off based on a control signal.
- the second switch element is, for example, a MOS transistor, and the control signal is applied to the gate terminal of the MOS transistor.
- control signal of the second switch element is a logic signal of 2 bits or more
- the second switch element is a discrete signal in which the second time constant is predetermined according to the value of the logic signal. It is also possible to switch between multiple values.
- the second selection circuit includes the second selection circuit
- a longer time constant may be selected from two or more predetermined values for the second time constant based on the first control signal.
- the reception signal detection circuit outputs a second control signal when the signal disconnection of the reception signal is detected, and the second selection circuit outputs the second control signal based on the second control signal.
- the time constant may be configured to select a shorter time constant from two or more predetermined values.
- the TIA circuit according to the second embodiment of the present invention is similar to the AGC circuit described above, for example, at least one of the resistance element or the capacitance element of the circuit that determines the time constant of the AOC function, or both elements.
- a switch is installed in the unit, and by enabling or disabling these elements by on / off control of the switch, the resistance value or the capacitance value is changed, and a plurality of time constants of the AOC function are realized.
- FIG. 4 is a block diagram showing a configuration example of the TIA circuit 10 that includes the AGC circuit 20 and the AOC circuit 30 and controls the time constant using a MOS transistor circuit as a switch element.
- the TIA circuit 10 of the present embodiment converts a single-phase input signal input from a photoelectric conversion element such as a photodiode (not shown) into a differential signal and outputs the differential signal. Therefore, the TIA circuit 10 includes a replica amplifier 23 that is the same as the first-stage input amplifier 22 as the first-stage amplifier.
- the aforementioned single-phase input signal is input to the input terminal of the first stage input amplifier 22, and the input terminal of the replica amplifier 23 is released.
- the gain controller 21 of the AGC circuit 20 is shared by these two amplifier circuits.
- the outputs of the input amplifier 22 and the replica amplifier 23 are further differentially amplified by the next stage amplifiers 40 and 50 via the AOC circuit 30.
- the AOC circuit 30 is a circuit in which the outputs of the input amplifier 22 and the replica amplifier 23 in the first stage are AC-coupled by the capacitor Cb, and the DC level is matched by the bias voltage Vbias via the bias resistor Rb. Yes.
- an additional capacitor Cbs is connected in parallel with the capacitor Cb
- an additional resistor Rbs is connected in series with the resistor Rb
- NMOS transistors 33 and 34 are connected in parallel with the resistor Rbs.
- PMOS transistors 31 and 32 are connected to each other.
- the AGC circuit 20 is connected with an additional resistor Rgs in series with a resistor Rg for determining a time constant, and PMOS transistors 24 and 25 are connected in parallel with the resistor Rgs.
- the time constant of the AGC circuit 20 is adjusted only by the resistor, but the capacitance may be controlled in the same manner as the AOC circuit 30.
- the switch control signal Vsw described in the first embodiment is applied to the NMOS transistors 33 and 34 and the PMOS transistors 24, 25, 31, and 32 to control the on / off of the MOS transistors.
- the switch control signal Vsw when the switch control signal Vsw is at a high level, the additional resistor and the additional capacitor are connected to the circuit, so that the time constant increases. Therefore, in the case of an application for receiving a continuous optical signal, the switch control signal Vsw may be fixed at a high level in advance. When the switch control signal Vsw is at the low level, the time constant is reduced by disconnecting the additional resistor and the additional capacitor from the circuit. Therefore, in the case of an application for receiving a burst optical signal, the switch control signal Vsw may be fixed at a low level.
- a plurality of time constant determining elements in a plurality of circuits are enabled or disabled by only one control signal, so that each AGC circuit and AOC circuit are long.
- One of the time constant and the short time constant can be selected, and the time constant can be switched discretely. Even when it is necessary to change the time constant greatly, such as in burst optical communication and continuous optical communication, each resistance value and capacitance value are appropriately designed as desired for the user, and the time constant is easily set to the desired value. can do.
- PMOS and NMOS transistors are used as switching elements.
- the sources and drains of the PMOS and NMOS transistors are connected to each other as shown in FIG.
- a so-called transfer gate (TG) circuit 60 to 66 that inputs and controls various logic signals (X, X to) may be used.
- TG transfer gate
- switches 61 and 62 connected in parallel to the pair of additional resistance elements Rgs of the AGC circuit 20a, and switches 63 and 62 connected in parallel to the pair of additional resistance elements Rbs of the AOC circuit 30a, 64 and the switches 65 and 66 connected in series to the pair of additional capacitance elements Cbs are used as the TG circuit 60, and the control signal input circuit 69 controls the polarities of the control signals A and B to be input to each other.
- FIG. 6 shows an example of the configuration of a TIA circuit 10b that uses a signal detection (SD) circuit 70 to determine the presence or absence of an optical signal input and automatically determine which time constant should be set based on the determination result.
- SD signal detection
- the TIA circuit 10b In continuous optical signal communication, it always receives optical signals of a certain level or higher. On the other hand, in burst optical communication, optical signal input is intermittent. Therefore, the TIA circuit 10b according to the present embodiment is provided with an SD circuit 70 that determines the presence or absence of the optical signal input OPTin and outputs a high or low logic level signal based on the determination result. In the present embodiment, it is assumed that the SD circuit 70 outputs a high level when light reception continues for a predetermined time Tc or longer in accordance with the polarity of Vsw described above.
- the SD circuit 70 when the optical signal reception does not continue for a certain period of time and the SD circuit 70 detects a signal interruption, the SD circuit 70 maintains the low level output, and the received optical signal continues for a certain period Tc or longer. Otherwise, the High level is not output. Therefore, the high level output of the SD circuit 70 represents “with optical signal”, and the low level output represents “no optical signal”. In the default (when the circuit power is turned on), the output of the SD circuit 70 is assumed to be Low. Since these logic polarities are design items, they may be appropriately selected.
- Such a logic circuit can be configured by a counter 72, a reset circuit 73, a latch circuit 74, and the like, as shown in FIG. 7A. That is, while the optical signal is being received, the counter 72 counts the clock signal (CLK), and if the optical signal reception time exceeds a certain count amount, the latch circuit 74 switches the output to the high level and holds it. On the other hand, when the photodetection circuit 71 detects the disconnection of the optical signal, the reset circuit 73 outputs a reset signal based on the low level output of the SD circuit 70, resets the counter 72 and the latch circuit 74, and the switch control signal Vsw. As a low level.
- the counter 72 is not limited to a digital circuit (FIG. 7A) that uses a clock signal, but may be an analog holding circuit 75 that uses charging and discharging of a capacitor as shown in FIG. 7B.
- the fixed time Tc is longer than the maximum value of the burst packet. That is, if Tc is set to be longer than the time length of the longest burst packet, there is no opportunity for the SD circuit to output a high level after power-on, and the SD circuit maintains the low level. If this output is used as Vsw, the time constant of the AGC function and the time constant of the AOC function of the TIA circuit are kept short for burst communication. On the contrary, in the continuous optical signal reception, the SD circuit output becomes High level after a certain time Tc, so that the time constant is set long for continuous communication. It is also possible to provide means for forcibly fixing the value of Vsw to High or Low.
- the continuous light is used to automatically determine whether the input signal is a continuous light signal or a burst light signal. Since it is possible to use the same optical package for the signal and the burst optical signal, it is easy to use and effective in reducing the cost. According to the present embodiment, it is possible to more effectively utilize the feature of the present invention in which the time constant switching is performed by a switch inside the integrated circuit.
- a fourth embodiment of the present invention will be described with reference to FIG.
- at least the time constant is set to a binary value of long or short, and both the AGC function and the AOC function are set collectively.
- control signals of the first switch element of the AGC circuit and the second switch element of the AOC circuit are logic signals of 2 bits or more, and these first and second switch elements Depending on the value of the signal, each of the first time constant, that is, the time constant of the AGC function, and the second time constant, that is, the time constant of the AOC function, is one of a plurality of predetermined discrete values. Switch to. It is also possible to select the time constant value from a plurality of stages of two or more, or to set different values for the AGC function and the AOC function.
- a time constant setting value is written in a register inside the TIA circuit 10 'from a control processor 90 such as a CPU or a microcomputer.
- a control processor 90 such as a CPU or a microcomputer.
- a memory in which a set value is stored in advance may be connected, and the TIA circuit 10 'may download the value stored in the memory and store it in its own register.
- the digital interface control circuit 80 outputs a switch control signal corresponding to the stored value, and sets time constants in the AGC circuit 20 and the AOC circuit 30, respectively.
- SCL serial clock
- SDA serial data
- the present invention includes means for discretely switching the time constants of the AGC circuit and the AOC circuit for determining the response time of the TIA circuit by the control of the switch mounted inside the circuit, so that the short time constant can be reduced.
- a TIA circuit that can handle both necessary burst signal communication and continuous signal communication that requires a long time constant can be realized simply and at low cost.
- a communication topology as represented by a PON ( ⁇ Passive ⁇ Optical Network) system
- a one-to-many branch configuration is frequently used, and there are cases where the required reception response time is different for each node.
- the response time constant of the same integrated circuit can be optimized at each node, so that the same IC chip can be applied to a wide range of applications. Since the cost of the IC chip is substantially inversely proportional to the number of shipments, it is possible to reduce the component cost, the device cost, and further the system cost by applying it to various purposes.
- the present invention can be used for a receiving circuit in an optical communication system that needs to support both burst signal communication in which the intensity and timing of a received optical signal change greatly and continuous signal communication in which an optical signal is continuously received. .
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Abstract
Description
光通信においては、通信距離の長短によって受信する光強度が異なるので、弱い(暗い)光信号から強い(明るい)光信号まで低ノイズかつ低歪(ひず)みで増幅することが求められる。このため、光通信用のTIA回路は、しばしば、入力信号強度の大小、すなわち受信光強度の大小に応じて増幅利得を調節する機能を具備して、受信強度が大きいときは利得を小さく、受信強度が小さい時は利得を大きくする。このような利得調節が自動的に実施されるAGC回路は、様々なアーキテクチャで実用化されている。
図9の構成例では、AGC機能の時定数は、AGC回路200の抵抗Ragcと容量Cagcの大きさによって決定される。ここで、もし、このAGC機能の時定数が短すぎると、入力信号の論理変化に追従してしまうため、所望の出力が得られなくなってしまう場合がある。これは、例えば、入力信号がHighレベルの時に利得を小さく、Lowレベルの時に利得を大きくしてしまうと、Highレベルの時の出力レベルと、Lowレベルの時の出力レベルが略等しくなってしまい、結果的に出力振幅が小さくなってしまうからである。そこで、一般的には、AGC機能の時定数は、入力データのボーレートや符号化方式を考慮して、平均的な入力振幅を把握するために十分な長さの時定数となるように設計される。
例えば、IEEE802.3avで標準化されている10G-EPONの規格では、バースト応答時間はTIAとその後段のリミッティングアンプとの合計で800ns以内とされており、TIA回路としては、約400ns以内に応答することが望ましいが、一般的な連続信号用TIA回路では、数μs~数msと長くなっている。
このため、バースト通信の用途においては、AGC機能の時定数を比較的短く設定したり、異なる固定利得をバースト毎に切り替えることなどにより、増幅回路としての応答速度とダイナミックレンジの両立を図ることとなる(例えば、非特許文献1参照)。
また、上記の受信信号検出回路は、前記受信信号の信号断を検出した場合に第2の制御信号を出力し、前記第1の選択回路は、前記第2の制御信号に基づいて前記第1の時定数を予め定めた2以上の値のうちより短い時定数を選択するようにしてもよい。
TIA回路1は、増幅器22、40、50を備えた多段増幅回路である。TIA回路1は、さらに、利得制御部21を含み、一段目の増幅器22の利得を調節するAGC回路2を備えている。利得制御部21は、制御電圧Vagcによって増幅器22の帰還抵抗Rfを制御して、増幅器22から出力される信号の振幅を一定値に保つように、増幅器22の利得を調節する。すなわち、AGC回路2は、増幅器22から出力される信号の振幅を一定値に保つように、増幅器22の利得を制御する。
AGC回路2は、さらに、抵抗(Ragc、Rs)、容量(Cagc、Cs)、およびスイッチSW1、SW2を備えている。追加する抵抗Rsは抵抗Ragcと直列に接続され、抵抗Rsと並列にSW1が接続されている。容量Cagcと並列に追加容量Csが接続され、容量Csと直列にSW2が接続されている。これらスイッチSW1とSW2は、スイッチ制御信号VswによってON/OFFする。TIA回路1のAGC機能の時定数は、スイッチSW1とSW2とをON/OFFすることによって、抵抗(Ragc、Rs)、容量(Cagc、Cs)の組み合わせによって得られる予め定められた複数の値から選択することができる。
これらの抵抗(Ragc、Rs)、容量(Cagc、Cs)、およびスイッチSW1、SW2は、AGC機能の時定数を予め定められた複数の値から選択する第1の選択回路25を構成している。
本実施の形態においては、これらスイッチSW1とSW2の極性は互いに逆となっており、例えばスイッチ制御信号VswがHighの場合、SW1は開放(OFF)で、SW2は接続(ON)となっている。この逆の論理でもよいことは言うまでもない。
図1では、1つの制御信号を用いて抵抗素子と容量素子を相補的に切り替える構成を説明したが、図2に示すように、設計する時定数の値に応じて、抵抗と容量とをそれぞれ個別に制御するようにしてもよい。さらに、抵抗のみあるいは容量のみをそれぞれ制御して、時定数を切り替えるようにしてもよい。このような構成とすれば、外部端子は2ピン必要になるが、2以上の離散的な時定数の値を予め定めておき、受信光信号の時間変化、例えば、連続的に受信する光信号かバースト的に受信する光信号かに応じて、所望の時定数を選択することも可能となり、より柔軟な時定数の制御が可能となる。
本発明の第2の実施の形態に係るTIA回路は、差動出力を出力するTIA回路の構成例である。
高速通信で用いられるTIA回路においては、多くの場合、その出力が差動出力であることが望ましい。一般的には、1個のフォトダイオードの出力は単相であるため、差動出力を得るためには、TIA回路内部で単相信号を差動信号に変える仕組み(S2D:Single-to-Differential Converter)が必要となる。したがって、本実施の形態は、より具体的なTIA回路での実施の形態である。
また、前記第2の選択回路は、前記AOC回路に含まれる複数の抵抗素子または複数の容量素子と、前記複数の抵抗素子または前記複数の容量素子の少なくとも一部と直列または並列に接続され、制御信号に基づいてオンまたはオフして前記第2の時定数の値を定める抵抗素子の抵抗値又は容量素子の容量値を変更する第2のスイッチ素子とを含むことができる。
前記第2のスイッチ素子は、例えば、MOSトランジスタであり、前記制御信号は、前記MOSトランジスタのゲート端子に印加される。
また、前記受信信号検出回路は、前記受信信号の信号断を検出した場合に第2の制御信号を出力し、前記第2の選択回路は、前記第2の制御信号に基づいて前記第2の時定数を予め定めた2以上の値のうちより短い時定数を選択するように構成してもよい。
図4は、AGC回路20およびAOC回路30を備え、かつ、スイッチ素子としてMOSトランジスタ回路を用いて時定数を制御するTIA回路10の構成例を示すブロック図である。図4に示すように、本実施の形態のTIA回路10は、図示しないフォトダイオード等の光電変換素子から入力される単相入力信号を差動信号に変換して出力する。このため、TIA回路10は、一段目の増幅器として、初段入力アンプ22と同一のレプリカアンプ23を備えている。初段入力アンプ22の入力端子には前述の単相入力信号が入力され、レプリカアンプ23の入力端子は解放されている。AGC回路20の利得制御部21はこれら2つの増幅回路に共有される。入力アンプ22とレプリカアンプ23の出力は、AOC回路30を介して次段アンプ40、50でさらに差動増幅される。
なお、図4のAGC回路20においては、抵抗のみでAGC回路20の時定数を調節しているが、容量についてもAOC回路30と同様に制御するようにしてもよい。
本実施の形態ではスイッチ素子としてPMOSおよびNMOSトランジスタを使用したが、スイッチ素子として、図5Bに示すような、PMOSとNMOSトランジスタそれぞれのソースとドレインを互いに接続して、各トランジスタのゲートに相補的な論理信号(X、X~)を入力して制御する、いわゆるトランスファーゲート(TG: Transfer Gate)回路(60~66)を用いても良い。この場合には、図5Aに示すように、AGC回路20aの一対の追加抵抗素子Rgsにそれぞれ並列接続したスイッチ61、62、ならびにAOC回路30aの一対の追加抵抗素子Rbsに並列接続したスイッチ63、64、および一対の追加容量素子Cbsに直列接続したスイッチ65、66をTG回路60とし、制御信号入力回路69によって、それぞれ入力する制御信号A、Bの極性が互いに逆となるように制御する。
図6、図7A、図7Bを用いて、本発明の第3の実施の形態を説明する。
図6は、信号検出(SD: Signal Detection)回路70を用いて、光信号入力の有無を判定し、判定結果に基づき長短どちらの時定数に設定すべきかを自動判別するTIA回路10bの構成例を示したものである。図7A、図7Bは、SD回路70の構成例である。
なお、カウンタ72はクロック信号を用いるデジタル回路(図7A)に限らず、図7Bに示すように容量の充電と放電を利用したアナログ保持回路75でもよい。
本実施の形態によれば、時定数切り替えを集積回路内部のスイッチによって実施するという本発明の特徴をより効果的に利用することができる。
図8を参照して、本発明の第4の実施の形態について説明する。第2および第3の実施の形態においては、少なくとも時定数の設定を長いか短いかの2値で、かつ、AGC機能とAOC機能の両方を一括で設定した。本実施の形態においては、集積回路内部で集積化されたスイッチを制御することによって、時定数を2値以上の値で、さらに細かく設定することが可能である。すなわち、本実施の形態においては、AGC回路の第1のスイッチ素子とAOC回路の第2のスイッチ素子の制御信号を2bit以上の論理信号とし、これら第1および第2のスイッチ素子は、上記論理信号の値に応じて、それぞれ第1の時定数、すなわち、AGC機能の時定数と、第2の時定数、すなわちAOC機能の時定数を、予め定められた離散的な複数の値のいずれかに切り替える。時定数の値を、2以上の複数の段階の中から選択したり、AGC機能とAOC機能とで異なる値に設定することも可能である。
Claims (14)
- 受信信号を増幅する増幅器と、
前記受信信号のレベルに応じて前記増幅器の増幅利得を第1の時定数で調節する自動利得調節回路と、
前記第1の時定数を予め定められた複数の値から選択する第1の選択回路と
を備えたトランスインピーダンスアンプ回路。 - 前記第1の選択回路は、
制御信号に基づいて前記第1の時定数の値を定める抵抗素子の抵抗値および容量素子の容量値の少なくとも1つを変更すること
を特徴とする請求項1記載のトランスインピーダンスアンプ回路。 - 前記第1の選択回路は、
前記自動利得調節回路に含まれる複数の抵抗素子または複数の容量素子と、
前記複数の抵抗素子または前記複数の容量素子の少なくとも一部と直列または並列に接続され、制御信号に基づいてオンまたはオフして前記第1の時定数の値を定める抵抗素子の抵抗値又は容量素子の容量値を変更する第1のスイッチ素子とを含むこと
を特徴とする請求項1記載のトランスインピーダンスアンプ回路。 - 前記第1のスイッチ素子は、MOSトランジスタであり、
前記制御信号は、前記MOSトランジスタのゲート端子に印加されること
を特徴とする請求項3記載のトランスインピーダンスアンプ回路。 - 前記第1のスイッチ素子の前記制御信号は、2bit以上の論理信号であり、
前記第1のスイッチ素子は、前記論理信号の値に応じて前記第1の時定数を予め定められた離散的な複数の値で切り替えること
を特徴とする請求項3に記載のトランスインピーダンスアンプ回路。 - 前記受信信号を検出し、前記受信信号の連続受信時間が所定の時間を超えた場合に第1の制御信号を出力する受信信号検出回路をさらに備え、
前記第1の選択回路は、前記第1の制御信号に基づいて前記第1の時定数を予め定めた2以上の値のうちより長い時定数を選択すること
を特徴とする請求項1記載のトランスインピーダンスアンプ回路。 - 前記受信信号検出回路は、前記受信信号の信号断を検出した場合に第2の制御信号を出力し、
前記第1の選択回路は、前記第2の制御信号に基づいて前記第1の時定数を予め定めた2以上の値のうちより短い時定数を選択すること
を特徴とする請求項6記載のトランスインピーダンスアンプ回路。 - 前記増幅器の出力に基づいて差動信号を出力し、差動信号のオフセット量を第2の時定数で調節する自動オフセット調節回路と、
前記第2の時定数を予め定めた複数の値から選択する第2の選択回路と
をさらに備えたこと
を特徴とする請求項1記載のトランスインピーダンスアンプ回路。 - 前記第2の選択回路は、
制御信号に基づいて前記第2の時定数の値を定める抵抗素子の抵抗値および容量素子の容量値の少なくとも1つを変更すること
を特徴とする請求項8記載のトランスインピーダンスアンプ回路。 - 前記第2の選択回路は、
前記自動オフセット調節回路に含まれる複数の抵抗素子または複数の容量素子と、
前記複数の抵抗素子または前記複数の容量素子の少なくとも一部と直列または並列に接続され、制御信号に基づいてオンまたはオフして前記第2の時定数の値を定める抵抗素子の抵抗値又は容量素子の容量値を変更する第2のスイッチ素子と
を含むこと
を特徴とする請求項8記載のトランスインピーダンスアンプ回路。 - 前記第2のスイッチ素子は、MOSトランジスタであり、
前記制御信号は、前記MOSトランジスタのゲート端子に印加されること
を特徴とする請求項10記載のトランスインピーダンスアンプ回路。 - 前記第2のスイッチ素子の前記制御信号は、2bit以上の論理信号であり、
前記第2のスイッチ素子は、前記論理信号の値に応じて前記第2の時定数を予め定められた離散的な複数の値で切り替えること
を特徴とする請求項10に記載のトランスインピーダンスアンプ回路。 - 前記受信信号を検出し、前記受信信号の連続受信時間が所定の時間を超えた場合に第1の制御信号を出力する受信信号検出回路をさらに備え、
前記第2の選択回路は、前記第1の制御信号に基づいて前記第2の時定数を予め定めた2以上の値のうちより長い時定数を選択すること
を特徴とする請求項8記載のトランスインピーダンスアンプ回路。 - 前記受信信号検出回路は、前記受信信号の信号断を検出した場合に第2の制御信号を出力し、
前記第2の選択回路は、前記第2の制御信号に基づいて前記第2の時定数を予め定めた2以上の値のうちより短い時定数を選択すること
を特徴とする請求項13記載のトランスインピーダンスアンプ回路。
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CN108173524B (zh) * | 2018-02-08 | 2021-02-19 | 厦门亿芯源半导体科技有限公司 | 适用于高带宽tia的双环路自动增益控制电路 |
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CN105684304A (zh) | 2016-06-15 |
JP5731615B2 (ja) | 2015-06-10 |
KR20160060127A (ko) | 2016-05-27 |
JP2015084474A (ja) | 2015-04-30 |
KR101768470B1 (ko) | 2017-08-17 |
US9853618B2 (en) | 2017-12-26 |
US20160261246A1 (en) | 2016-09-08 |
CN105684304B (zh) | 2018-12-07 |
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