WO2015085841A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2015085841A1
WO2015085841A1 PCT/CN2014/090443 CN2014090443W WO2015085841A1 WO 2015085841 A1 WO2015085841 A1 WO 2015085841A1 CN 2014090443 W CN2014090443 W CN 2014090443W WO 2015085841 A1 WO2015085841 A1 WO 2015085841A1
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Prior art keywords
source
active region
region
source pad
drain
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PCT/CN2014/090443
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English (en)
French (fr)
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张乃千
裴风丽
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苏州能讯高能半导体有限公司
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Priority to EP14868920.1A priority Critical patent/EP3082160A4/en
Priority to JP2016546134A priority patent/JP6338679B2/ja
Priority to US14/741,767 priority patent/US9941400B2/en
Publication of WO2015085841A1 publication Critical patent/WO2015085841A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device having a via structure and a method of fabricating the same.
  • GaN semiconductor materials have significant advantages such as large band gap, high electron saturation drift rate, high breakdown field strength, and high temperature resistance. They are more suitable for fabrication than first-generation semiconductor silicon and second-generation semiconductor gallium arsenide. High-temperature, high-voltage, high-frequency and high-power electronic devices have broad application prospects, and thus have become a hot spot in the semiconductor industry.
  • Gallium Nitride High Electron Mobility Transistor is a GaN device formed by using two-dimensional electron gas at the AlGaN/GaN heterojunction, which can be applied to the fields of high frequency, high voltage and high power. Due to the high mobility and saturation drift rate of the two-dimensional electron gas, the depletion type gallium nitride HEMT device is usually fabricated by utilizing the characteristics of the two-dimensional electron gas channel normally open, and is suitable for high frequency applications such as wireless communication. In the packaging process of a gallium nitride device, in order to increase the device gain and reduce the grounding inductance, a via structure is usually employed.
  • Such a structure is generally introduced by etching from a back surface of a substrate (ground back ground), the through hole penetrating through the substrate and the nitride semiconductor epitaxial layer, up to the source, and then using metal
  • the vias are filled to connect the source to the back side of the grounded substrate to reduce source-to-ground inductance.
  • the source 1 and the drain 21 in the active region 5 are ohmic contact electrodes
  • the drain 22 outside the active region 5 is an interconnect metal of the ohmic contact drain 21
  • the gate 3 is The source 1 and the drain 21 are distributed in an interdigitated manner.
  • the via 4 is in each source 1 in the active region 5, and the area of each source 1 is larger than the area of the opposite drain 21 .
  • the position distribution of the via hole has the advantage that the source in each active region can be directly grounded through the via hole, reducing the source-to-ground distance in the active region, thereby reducing the grounding inductance, and each source
  • the grounding inductance of the pole is the same; the position distribution of the through hole is insufficient as follows: First, the through hole is placed on the source of the active region, and the size of the through hole is limited. The small through hole increases the grounding inductance on the one hand and increases the difficulty of the manufacturing process on the other hand. Second, the heat dissipation of the device is poor.
  • the source 1 is an ohmic contact, and the metal of the ohmic contact is not suitable as an etch barrier. Using the ohmic contact source 1 as an etch barrier can impair the contact performance of the ohmic electrode and also affect the blocking effect of the etch.
  • the source 11 and the drain 21 in the active region 5 are ohmic contact electrodes
  • the drain 22 outside the active region 5 is an interconnection metal of the ohmic contact drain 21
  • the gate 3 is The source 11 and the drain 21 are distributed in an interdigitated manner
  • the source interconnection 12 and the source pad 13 outside the active region 5 are interconnection metals of the source 11, and several sources 11 pass through corresponding sources.
  • Interconnect 12 is connected to the same source pad 13, source The pads 13 are symmetrically distributed on both sides of the gate 3, and the via holes 4 are distributed in each of the source pads 13. The positional distribution of the via hole avoids the disadvantage of placing the via hole on the source of the active region in FIG.
  • the size of the via hole is not limited, and the device is not limited.
  • the heat dissipation is not affected, and the selection of the etch barrier layer is flexible, but there are also disadvantages, as follows: First, the source-to-ground distance in the active region is increased, and the grounding of the source is increased. Inductance; secondly, the source interconnection 12 must cross the gate, and the air bridge is required to cross the gate. On the one hand, the presence of the air bridge makes the device structure more complicated, increasing the difficulty of the process, and on the other hand, the device During the packaging process, the air bridge is easily collapsed, which reduces the reliability of the device.
  • the air bridge introduces a capacitor between the source and the gate, which reduces the high-frequency performance of the device.
  • the source The lengths of the interconnects 12 are different, resulting in different grounding inductances of each of the source electrodes 11, thereby affecting the performance of the device, such as gain.
  • the invention designs a semiconductor device with a novel through-hole structure, which solves the problems caused by the position distribution of the through-hole of the current device (as shown in FIG. 1(a) and FIG. 1(b)), and utilizes at the same time
  • the advantages are that the grounding inductance of the device source is minimized, and the gain and power of the device are improved.
  • FIG. 2 A semiconductor device of the present invention is shown in FIG. 2.
  • the source 11 and the drain 21 in the active region 5 are ohmic contact electrodes, and the drain 22 in the inactive region is the drain of the drain 21 in the active region.
  • the gate 3 is interdigitated between the source and the drain
  • the source pad 13 in the inactive region is the interconnect metal of the source 11
  • the source 11 and the source pad 13 are in one-to-one correspondence.
  • Each source 11 is directly connected to a respective source pad 13
  • the source pad 13 is symmetrically distributed between the gates 3 outside the active region 5
  • the vias 4 are distributed in each source pad In the tray 13.
  • the present invention places the via hole 4 at the source source outside the active region closest to the source.
  • the grounding distance of the two methods is basically the same, and the grounding inductance of each source is the same, but the present invention avoids the problem brought by FIG. 1(a), and the through hole 4 is not directly placed on the active.
  • the source 11 of the region is placed on the source interconnection metal, that is, the source pad 13 outside the active region of the source, thus having the following advantages:
  • the shape and number of the via 4 and the source pad 13 are no longer limited, which is advantageous for reducing the grounding inductance and reducing the manufacturing difficulty of the process;
  • the source and drain sizes in the active region can be the same, which solves the heat dissipation problem caused by different sizes, and is more conducive to improving the output power of the device;
  • the problem caused by the ohmic metal etching barrier is solved.
  • the interconnect metal is outside the active region, and the selection of the interconnect metal is wider, which is more favorable for the via etching process and does not affect the source ohmic.
  • the performance of the contact improves the transconductance and power performance of the device.
  • the design of the semiconductor device of the present invention is the same as that of the prior art semiconductor device in FIG. 1(b). The same point is that the via hole is placed on the interconnect metal outside the active region, the difference is
  • the present invention does not use the source interconnection 12, but directly connects the source 11 and the source pad 13 of the active region directly, thereby solving the problem caused by the use of the source interconnection 12, and has the following advantages:
  • the source 11 and the source pad 13 of the active region are directly connected, thereby reducing the distance between the source and the ground of the active region, and reducing the grounding inductance;
  • the source does not need to cross the gate, and there is no need to use an air bridge across the gate, thereby reducing the process difficulty and improving the reliability and high frequency performance of the device;
  • a semiconductor device comprising:
  • a substrate having a ground electrode disposed on a back surface thereof;
  • the semiconductor layer includes an active region and an inactive region, the active region is in a closed form, and an area outside the active region is an inactive region;
  • a source and a drain on the semiconductor layer, a source and a drain in the active region are ohmic contact electrodes, and the ohmic contact electrodes are plural, each of the ohmic contact electrodes being equal in size and adjacent to each other An interval between two of the ohmic contact electrodes is equal, and a drain in the inactive region is an interconnect metal of a drain in the active region;
  • the gate of the active region is interdigitated between the source and the drain, and the gate in the passive region is a gate in the active region Extremely interconnected metal;
  • the source pad located in the inactive region, the source pad is directly electrically connected to a source in the active region; the source pad is symmetrically distributed between the gates or both sides;
  • Each source in the active region is individually grounded through a source pad and via directly connected thereto.
  • each source in the active region is directly connected to one or more source pads.
  • the source pads are on the same side of the active region, and/or the source pads are on different sides of the active region.
  • each of the source pads is connected to one or more vias.
  • the source pads corresponding to the source regions in the active region have the same cross-sectional shape or different cross-sectional shapes.
  • the source pad has a regular shape or an irregular shape in cross section.
  • the through hole has a regular shape or an irregular shape.
  • the semiconductor layer comprises a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, and indium phosphide.
  • a method of fabricating a semiconductor device comprising the steps of:
  • the semiconductor layer includes an active region and an inactive region, the active region is a closed form, and an area outside the active region is an inactive region;
  • a source is formed on the active region
  • a drain is formed on the active region and the inactive region
  • a source and a drain in the active region are ohmic contact electrodes
  • the ohmic contact electrode is a plurality, each of the ohmic contact electrodes being equal in size and having an equal interval between each adjacent two of the ohmic contact electrodes, and a drain in the inactive region being an interconnect metal of a drain in the active region;
  • the source pad is directly electrically connected to a source in the active region; the source pad is symmetrically distributed between the gate or both sides ;
  • the semiconductor device and the manufacturing method thereof of the invention solve the problems caused by the position distribution of the through holes of the current device, and at the same time utilize the advantages thereof, thereby minimizing the grounding inductance of the device source and improving the gain of the device. Performance.
  • FIG. 1(a) is a schematic structural view showing a position distribution of a through hole of a gallium nitride device in the prior art
  • 1(b) is a schematic structural view showing a position distribution of a through hole of another GaN device in the prior art
  • FIG. 2 is a top plan view showing a semiconductor device in a first embodiment of the present invention
  • FIG. 3 is a top plan view showing a semiconductor device in a second embodiment of the present invention.
  • FIG. 4 is a top plan view showing a semiconductor device in a third embodiment of the present invention.
  • FIG. 5 is a top plan view showing a semiconductor device in a fourth embodiment of the present invention.
  • FIG. 6 is a schematic plan view showing a semiconductor device in a fifth embodiment of the present invention.
  • FIG. 7 is a schematic plan view showing a semiconductor device in a sixth embodiment of the present invention.
  • FIG. 8 is a top plan view showing a semiconductor device in a seventh embodiment of the present invention.
  • FIG. 9 is a schematic plan view showing a semiconductor device in an eighth embodiment of the present invention.
  • the semiconductor device includes:
  • a substrate and a ground electrode is disposed on the back surface of the substrate;
  • the semiconductor layer includes an active region 5 and an inactive region, the active region 5 is in a closed form, and the region outside the active region 5 is an inactive region;
  • the source 11 and the drain 21 in the active region are ohmic contact electrodes, and the ohmic contact electrode is Each of the ohmic contact electrodes is of equal size and the interval between each adjacent two of the ohmic contact electrodes is equal, and the drain 22 in the inactive region is an interconnect metal of the drain 21 in the active region;
  • a gate 3 on the active region 5 and the inactive region a gate 3 on the active region 5 is interdigitated between the source 11 and the drain 21, and a gate 3 in the inactive region
  • a through hole 4 between the ground electrode and the source pad 13 the through hole penetrating through the substrate and the semiconductor layer, straight To the source pad 13, the via hole electrically connects the source pad and the ground electrode of the back surface of the substrate, and each source electrode 11 in the active region 5 passes through the source pad 13 and the via hole 4 directly connected thereto Ground separately.
  • the source pad 13 includes at least one sub-source pad, and the structure of the sub-source pad is the same as that of the source pad.
  • the source pad 13 includes a plurality of sub-source pads, a schematic structural view of the semiconductor device is shown in FIG. 5, and specifically refer to the sixth embodiment.
  • the source pads 13 described above are symmetrically distributed in the middle or both sides of the gate. Specifically, the source pads 13 may be located on the same side of the active region 5, such as Figure 2 shows. It may also be located on different sides of the active area 5, as shown in Figure 3, with particular reference to the second embodiment.
  • the semiconductor layer includes a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, and indium phosphide.
  • the cross section of the source pad 13 is a regular shape or an irregular shape
  • the cross section of the through hole 4 is a regular shape or an irregular shape.
  • the cross-sectional shape of the source pad is a combination of an isosceles trapezoid and a rectangle
  • the cross-sectional shape of the through hole is a circle.
  • the manufacturing method of the above semiconductor device is specifically as follows:
  • the semiconductor layer includes an active region 5 and an inactive region, the active region 5 is in a closed form, and the region outside the active region 5 is an inactive region;
  • S3 forming a source 11 on the active region 5, forming a drain 21 on the active region 5 and the inactive region, and the source 11 and the drain 21 in the active region are ohmic contact electrodes
  • the ohmic contact electrode is plural, each of the ohmic contact electrodes is equal in size and the interval between each adjacent two ohmic contact electrodes is equal, and the drain 22 in the passive region is an active region Interconnect metal of drain 21;
  • the cross-sectional shape of the source pad may be a regular shape or an irregular shape, for example, a combination of an isosceles trapezoid and a rectangle;
  • the ground electrode is electrically connected; each source 11 in the active region 5 is separately grounded through the source pad 13 and the through hole 4 directly connected thereto.
  • the cross-sectional shape of the through hole 4 may be a regular shape, for example Round, which can also be irregular.
  • the present embodiment solves the problems caused by the position distribution of the through holes of the current device, and at the same time utilizes the advantages thereof, minimizes the grounding inductance of the device source, and improves the gain and the like of the device.
  • FIG. 3 is a schematic plan view showing a semiconductor device in a second embodiment of the present invention.
  • the source pad 13 is located on both sides of the active region 5 in the embodiment, wherein one source pad 13 is located on one side of the active region 5, and another source is soldered.
  • the disk 13 is located on the other side of the active region 5.
  • the source pads 13 are symmetrically distributed in the middle or both sides of the gate, and the source pads 13 are directly connected to the source on the active region 5. Electrical connection.
  • This structure increases the flexibility of device layout design.
  • Other structures and manufacturing methods are the same as or similar to the first embodiment, and details are not described herein again. For details, refer to the description of the first embodiment.
  • FIG. 4 is a schematic plan view showing a semiconductor device in a third embodiment of the present invention.
  • the difference from the first embodiment is that there are three through holes 4 connected to each of the source pads 13 in the embodiment, and the cross-sectional shape of the through holes is circular or other shapes, of course, in other embodiments.
  • the hole can also be other than three. This arrangement increases the cross-sectional area of the through hole, which is more conducive to reducing the grounding inductance.
  • Other structures and manufacturing methods are the same as or similar to those of the first embodiment, and are not described herein again.
  • the source pad 13 includes two sub-source pads, and the advantage of this method is that the area of the inactive area can be reasonably used, and the size of the entire device is minimized. It should be noted that the source pad 13 is not limited to including only two sub-source pads, which may include a plurality of sub-source pads. Similarly, the through holes 4 connected to each of the source pads 13 are not limited to one, and a plurality of through holes may be provided in the same manner as in the third embodiment. Other structures and manufacturing methods are the same as or similar to those of the first embodiment, and are not described herein again.
  • FIG. 6 is a schematic plan view showing a semiconductor device in a fifth embodiment of the present invention.
  • the difference from the first embodiment is that in the present embodiment, the shape of the source pad 13 connected to each source in the active region is different, and the shape of the via hole 4 is also different, and the advantage of the mode is that The area of the passive region is reasonably used according to the structure of the gate interconnection, and the size of the entire device is minimized.
  • Other structures and manufacturing methods are the same as or similar to those of the first embodiment, and are not described herein again.
  • FIG. 7 is a schematic plan view showing a semiconductor device in a sixth embodiment of the present invention.
  • the cross-sectional shape of the source pad 13 is circular or elliptical in this embodiment, and the cross-sectional shape of the through hole 4 is also circular or elliptical, and other structures and manufacturing methods are the same.
  • An embodiment is the same or similar and will not be described again here.
  • FIG. 8 is a schematic plan view showing a semiconductor device in a seventh embodiment of the present invention.
  • the difference from the first embodiment is that the cross-sectional shape of the source pad 13 is circular or elliptical in the present embodiment, and the cross-sectional shape of the through hole 4 is rectangular.
  • Other structures and manufacturing methods are the same as the first embodiment. The same or similar, will not be described here.
  • FIG. 9 is a schematic plan view showing a semiconductor device in an eighth embodiment of the present invention.
  • the cross-sectional shape of the source pad 13 in the present embodiment is an irregular shape
  • the cross-sectional shape of the through hole 4 is also an arbitrary irregular shape
  • the advantage of the irregular shape is that The cross-sectional area of the via hole connected to the pad is as large as possible, which increases the cross-sectional area of the via hole, and is more conducive to reducing the grounding inductance.
  • Other structures and manufacturing methods are the same as or similar to those of the first embodiment, and are not described herein again.
  • the present invention places the via hole 4 at the source source outside the active region closest to the source.
  • the grounding distance of the two methods is basically the same, and the grounding inductance of each source is the same, but the present invention avoids the problem brought by FIG. 1(a), and the through hole 4 is not directly placed on the active.
  • the source 11 of the region is placed on the source interconnection metal, that is, the source pad 13 outside the active region of the source, thus having the following advantages:
  • the shape and number of the via 4 and the source pad 13 are no longer limited, which is advantageous for reducing the grounding inductance and reducing the manufacturing difficulty of the process;
  • the source and drain sizes in the active region can be the same, which solves the heat dissipation problem caused by different sizes, and is more conducive to improving the output power of the device;
  • the problem caused by the ohmic metal etching barrier is solved.
  • the interconnect metal is outside the active region, and the selection of the interconnect metal is wider, which is more favorable for the via etching process and does not affect the source ohmic.
  • the performance of the contact improves the transconductance and power performance of the device.
  • the design of the semiconductor device of the present invention is the same as that of the prior art semiconductor device in FIG. 1(b). The same point is that the via hole is placed on the interconnect metal outside the active region, the difference is
  • the present invention does not use the source interconnection 12, but directly connects the source 11 and the source pad 13 of the active region directly, thereby solving the problem caused by the use of the source interconnection 12, and has the following advantages:
  • the source 11 and the source pad 13 of the active region are directly connected, thereby reducing the distance between the source and the ground of the active region, and reducing the grounding inductance;
  • the source does not need to cross the gate, and there is no need to use an air bridge across the gate, thereby reducing the process difficulty and improving the reliability and high frequency performance of the device;
  • the semiconductor device and the manufacturing method thereof of the present invention solve the problems caused by the position distribution of the through holes of the current device, and at the same time utilize the advantages thereof, thereby minimizing the source of the device.
  • Grounding inductance improves the performance of the device.

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Abstract

一种半导体器件及其制造方法，半导体器件包括衬底，衬底背面设有接地电极；位于衬底正面上的半导体层，半导体层包括有源区（5）和无源区，有源区（5）为封闭形式，有源区（5）之外的区域为无源区，位于有源区（5）的源极（11）和位于无源区的源极焊盘（13），源极焊盘（13）与源极（11）直接电连接，有源区内的每个源极（11）通过与其直接连接的源极焊盘（13）和通孔（4）单独接地。解决了目前半导体器件的通孔位置分布带来的问题，同时又利用了其优点，最大程度地减小了器件源极的接地电感，提高了器件的增益和功率等性能。

Description

半导体器件及其制造方法
本申请要求于2013年12月13日提交中国专利局、申请号为201310682785.0、发明名称为“半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，特别是涉及一种具有通孔结构的半导体器件及其制造方法。
背景技术
氮化镓半导体材料具有禁带宽度大、电子饱和漂移速率高、击穿场强高、耐高温等显著优点，与第一代半导体硅和第二代半导体砷化镓相比，更适合于制作高温、高压、高频和大功率的电子器件，具有广阔的应用前景，因此成为目前半导体行业研究的热点。
氮化镓高电子迁移率晶体管(HEMT)是利用AlGaN/GaN异质结处的二维电子气形成的一种氮化镓器件，可以应用于高频、高压和大功率的领域。由于二维电子气具有较高的迁移率和饱和漂移速率，通常利用二维电子气沟道常开的特性来制作耗尽型的氮化镓HEMT器件，适用于无线通信等高频应用领域。在进行氮化镓器件的封装工艺时，为了提高器件增益，减小接地电感，通常采用通孔结构。这种结构一般是通过刻蚀的方式从衬底背面引入通孔(衬底背面接地)，该通孔贯穿衬底和氮化物半导体外延层，直至源极，然后用金属 填充通孔，从而将源极和接地的衬底背面相连，以减少源极到地的电感。
目前氮化镓器件的通孔的位置分布主要有两种形式，示意图参见图1(a)和图1(b)，例如：美国CREE公司采用了图1(a)的形式，美国TriQuint公司采用了图1(b)的形式。
在示意图1(a)中，有源区5内的源极1和漏极21为欧姆接触电极，有源区5外的漏极22为欧姆接触漏极21的互连金属，栅极3在源极1和漏极21间呈叉指状分布，通孔4在有源区5内的每个源极1中，每个源极1的面积大于与之相对的漏极21的面积。该通孔的位置分布优点是每个有源区内的源极可以通过通孔直接接地，减小了有源区内的源极到地的距离，从而减小了接地电感，并且每个源极的接地电感是相同的；该通孔的位置分布不足之处有如下几点：首先，将通孔放在有源区的源极上，通孔的大小受限。小的通孔一方面增加了接地电感，另一方面增加了制作工艺难度。其次，器件的散热较差。一方面，有源区面积一定时，为了增大通孔的直径，需要增大每个源极1的面积，这会导致源极1的面积大，漏极21的面积小，欧姆接触电极的分布不均匀，从而影响了器件的散热；另一方面，有源区5内的源极1中形成通孔后，由于通孔是中空的，影响了器件的散热。第三，源极1为欧姆接触，欧姆接触的金属不适合做刻蚀阻挡层。用欧姆接触的源极1来作为刻蚀阻挡层，会损害欧姆电极的接触性能，也会影响刻蚀的阻挡效果。
在示意图1(b)中，有源区5内的源极11和漏极21为欧姆接触电极，有源区5外的漏极22为欧姆接触漏极21的互连金属，栅极3在源极11和漏极21间呈叉指状分布，有源区5外的源极互连12和源极焊盘13为源极11的互连金属，几个源极11通过相应的源极互连12连接至同一个源极焊盘13，源极 焊盘13对称分布在栅极3两侧，通孔4分布在每个源极焊盘13中。该通孔的位置分布避免了图1(a)中的把通孔放在有源区的源极上的缺点，把通孔放在了有源区外，通孔的大小不受限制，器件的散热不受影响，刻蚀阻挡层的选择比较灵活，但是也存在缺点，有如下几点：首先，增大了有源区内的源极到地的距离，及增大了源极的接地电感；其次，源极互连12必须跨过栅极，而跨过栅极时需要使用空气桥，一方面空气桥的存在会使器件结构更加复杂，增大工艺的难度，另一方面在器件封装工艺过程中，空气桥非常容易被压塌，降低了器件的可靠性，还有就是空气桥会在源极和栅极之间引入电容，降低了器件的高频性能；第三，源极互连12的长度不同，导致每个源极11的接地电感不同，从而影响了器件的增益等性能。
因此，针对上述技术问题，有必要提供一种具有新型通孔结构的半导体器件及其制造方法。
发明内容
本发明设计了一种具有新型通孔结构的半导体器件，解决了目前器件的通孔的位置分布(如图1(a)和图1(b)所示)带来的问题，同时又利用了其优点，最大程度地减小了器件源极的接地电感，提高了器件的增益和功率等性能。
本发明的一种半导体器件如图2所示，有源区5内的源极11和漏极21为欧姆接触电极，无源区内的漏极22为有源区内的漏极21的互连金属，栅极3在源极和漏极间呈叉指状分布，无源区内的源极焊盘13为源极11的互连金属，源极11和源极焊盘13一一对应，每个源极11直接连接至各自的源极焊盘13，源极焊盘13对称分布在有源区5外的栅极3之间，通孔4分布在每个源极焊 盘13中。
本发明半导体器件的设计，与现有技术中半导体器件的通孔位置分布图1(a)相比，本发明将通孔4放在了最接近源极的有源区之外的源极互连金属上，两种方式的接地距离基本相同，每个源极的接地电感也相同，但是本发明避开了图1(a)的带来的问题，没有将通孔4直接放在有源区的源极11上，而是放在了接近源极的有源区之外的源极互连金属即源极焊盘13上，这样一来，具有以下优点：
首先，通孔4和源极焊盘13的形状和数量不再受限，更利于减小接地电感和减小工艺制作难度；
其次，有源区内源极和漏极的大小可以相同，解决了大小不同导致的散热问题，更利于提高器件的输出功率；
第三，解决了欧姆金属做刻蚀阻挡层带来的问题，互连金属在有源区之外，互连金属的选择范围更广，更利于通孔刻蚀工艺，不会影响源极欧姆接触的性能，提高了器件的跨导和功率等性能。
本发明半导体器件的设计，与现有技术中半导体器件的通孔位置分布图1(b)相比，相同点是都把通孔放在了有源区外的互连金属上，不同点是本发明没有使用源极互连12，而是直接将有源区的源极11和源极焊盘13直接相连，从而解决了使用源极互连12带来的问题，具有以下优点：
首先，将有源区的源极11和源极焊盘13直接相连，减小了有源区的源极与地的距离，减小了接地电感；
其次，没有使用源极互连12，源极不需要跨过栅极，也就不需要使用跨过栅极的空气桥，因而降低了工艺难度，提高了器件的可靠性和高频性能；
第三，没有使用源极互连12，就避开了源极互连12长度不同带来的每个源极11接地电感不同的问题，提高了器件的增益等性能。
为了实现上述目的，本发明实施例提供的技术方案如下：
一种半导体器件，所述半导体器件包括：
衬底，所述衬底背面设有接地电极；
位于所述衬底正面上的半导体层，所述半导体层包括有源区和无源区，有源区为封闭形式，有源区之外的区域为无源区；
位于所述半导体层上的源极和漏极，有源区内的源极和漏极为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极之间的间隔相等，无源区内的漏极为有源区内的漏极的互连金属；
位于所述有源区和无源区上的栅极，位于所述有源区的栅极在源极和漏极间呈叉指状分布，无源区内的栅极为有源区内的栅极的互连金属；
位于所述无源区的源极焊盘，所述源极焊盘与有源区内的源极直接电连接；所述源极焊盘对称分布在所述栅极之间或两侧；
位于接地电极和源极焊盘间的通孔，所述通孔贯穿衬底和半导体层，直至源极焊盘，通孔使源极焊盘和衬底背面的接地电极电性连接；
有源区内的每个源极通过与其直接连接的源极焊盘和通孔单独接地。
作为本发明的进一步改进，所述有源区内的每个源极与一个或多个源极焊盘直接连接。
作为本发明的进一步改进，所述源极焊盘位于所述有源区的同一侧，和/或，所述源极焊盘位于所述有源区的不同侧。
作为本发明的进一步改进，所述每个源极焊盘与一个或多个通孔相连。
作为本发明的进一步改进，所述有源区内的源极对应的源极焊盘的截面形状相同或截面形状不同。
作为本发明的进一步改进，所述源极焊盘的截面为规则形状或不规则形状。
作为本发明的进一步改进，所述通孔的截面为规则形状或不规则形状。
作为本发明的进一步改进，所述半导体层包括氮化镓、铝镓氮、铟镓氮、铝铟镓氮、砷化镓、磷化铟中一种或多种的组合。
相应地，一种半导体器件的制造方法，所述方法包括以下步骤：
S1、提供一衬底，在所述衬底背面形成接地电极；
S2、在所述衬底正面上沉积半导体层，所述半导体层包括有源区和无源区，有源区为封闭形式，有源区之外的区域为无源区；
S3、在所述有源区上形成源极，在所述有源区和所述无源区上形成漏极，有源区内的源极和漏极为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极之间的间隔相等，无源区内的漏极为有源区内的漏极的互连金属；
S4、在所述有源区和无源区上形成栅极，形成于所述有源区内的栅极在源极和漏极间呈叉指状分布，位于无源区内的栅极为有源区内的栅极的互连金属；
S5、在所述无源区上形成源极焊盘，所述源极焊盘与有源区内的源极直接电连接；所述源极焊盘对称分布在所述栅极之间或两侧；
S6、在接地电极和源极焊盘间形成电性连接的通孔，所述通孔贯穿衬底和 半导体层，直至源极焊盘，通孔使源极焊盘和衬底背面的接地电极电性连接；有源区内的每个源极通过与其直接连接的源极焊盘和通孔单独接地。
本发明的半导体器件及其制造方法，解决了目前器件的通孔的位置分布带来的问题，同时又利用了其优点，最大程度地减小了器件源极的接地电感，提高了器件的增益等性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1(a)是现有技术中一种氮化镓器件的通孔的位置分布的结构示意图；
图1(b)是现有技术中另一种氮化镓器件的通孔的位置分布的结构示意图；
图2是本发明第一实施方式中半导体器件的俯视结构示意图；
图3是本发明第二实施方式中半导体器件的俯视结构示意图；
图4是本发明第三实施方式中半导体器件的俯视结构示意图；
图5是本发明第四实施方式中半导体器件的俯视结构示意图；
图6是本发明第五实施方式中半导体器件的俯视结构示意图；
图7是本发明第六实施方式中半导体器件的俯视结构示意图；
图8是本发明第七实施方式中半导体器件的俯视结构示意图；
图9是本发明第八实施方式中半导体器件的俯视结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。
第一实施方式
参图2所示，在本发明的第一实施方式中，该半导体器件包括：
衬底，衬底背面设有接地电极；
位于衬底正面上的半导体层，半导体层包括有源区5和无源区，有源区5为封闭形式，有源区5之外的区域为无源区；
位于所述有源区的源极11和漏极21以及位于所述无源区的漏极22，有源区内的源极11和漏极21为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极的间隔相等，无源区内的漏极22为有源区内的漏极21的互连金属；
位于有源区5和无源区上的栅极3，位于所述有源区5上的栅极3在源极11和漏极21间呈叉指状分布，无源区内的栅极3为有源区内的栅极的互连金属；
位于所述无源区的源极焊盘13，所述源极焊盘13与所述有源区5上的源极11直接电连接；所述源极焊盘13对称分布在所述栅极3之间或两侧；
位于接地电极和源极焊盘13间的通孔4，通孔贯穿衬底和半导体层，直 至源极焊盘13，通孔使源极焊盘和衬底背面的接地电极电性连接，有源区5内的每个源极11通过与其直接连接的源极焊盘13和通孔4单独接地。
需要说明的是，所述源极焊盘13包括至少一个子源极焊盘，所述子源极焊盘的结构与所述源极焊盘的结构相同。当源极焊盘13包括多个子源极焊盘时，半导体器件的结构示意图如图5所示，具体参见第六实施方式。
另外，上述所述的所述源极焊盘13对称分布在所述栅极的中间或两侧，可以具体为，所述源极焊盘13可以位于所述有源区5的同一侧，如图2所示。也可以位于所述有源区5的不同侧，如图3所示，具体参见第二实施方式。
进一步地，半导体层包括氮化镓、铝镓氮、铟镓氮、铝铟镓氮、砷化镓、磷化铟中一种或多种的组合。
其中，源极焊盘13的截面为规则形状或不规则形状，通孔4的截面为规则形状或不规则形状。如在本实施方式中源极焊盘的截面形状为等腰梯形和长方形的组合，通孔的截面形状为圆形。
相应地，上述半导体器件的制造方法具体为：
S1、提供一衬底，在衬底背面形成接地电极；
S2、在衬底正面上沉积半导体层，半导体层包括有源区5和无源区，有源区5为封闭形式，有源区5之外的区域为无源区；
S3、在所述有源区5上形成源极11，在所述有源区5和所述无源区上形成漏极21，有源区内的源极11和漏极21为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极之间的间隔相等，无源区内的漏极22为有源区内的漏极21的互连金属；
S4、在所述有源区和无源区上形成栅极3，形成于所述有源区内的栅极3 在源极和漏极间呈叉指状分布，位于无源区内的栅极为有源区内的栅极的互连金属；
S5、在所述无源区上形成源极焊盘13，所述源极焊盘13与有源区5内的源极11直接电连接；所述源极焊盘13对称分布在所述栅极的中间或两侧。其中，源极焊盘的截面形状可以为规则形状，也可以为不规则形状，例如，可以为等腰梯形和长方形的组合；
S6、在接地电极和源极焊盘间形成电性连接的通孔4，通孔4贯穿衬底和半导体层，直至源极焊盘13，通孔4使源极焊盘13和衬底背面的接地电极电性连接；有源区5内的每个源极11通过与其直接连接的源极焊盘13和通孔4单独接地.其中，通孔4的截面形状可以为规则形状，例如为圆形，其也可以为不规则形状。
本实施方式解决了目前器件的通孔的位置分布带来的问题，同时又利用了其优点，最大程度地减小了器件源极的接地电感，提高了器件的增益等性能。
第二实施方式
参图3是本发明第二实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中源极焊盘13位于有源区5的两侧，其中1个源极焊盘13位于有源区5的一侧，另外一个源极焊盘13位于所述有源区5的另一侧。但是，无论是位于有源区的哪一侧，所述源极焊盘13对称分布在所述栅极的中间或两侧，并且，源极焊盘13与有源区5上的源极直接电连接。
此种结构增加了器件布局设计的灵活性。其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述，具体请参见第一实施方式的描述。
第三实施方式
参图4是本发明第三实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中与每个源极焊盘13相连的通孔4有3个，通孔的截面形状为圆形或其它形状，当然在其他实施方式中通孔也可以为3个以外的其他数量，如此设置增加了通孔的截面面积，更利于减小接地电感。其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
第四实施方式
参图5是本发明第四实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中，源极焊盘13包括2个子源极焊盘，该方式的优点是可以合理使用无源区的面积，尽量减小整个器件的尺寸。需要说明的是，源极焊盘13不限于只包括两个子源极焊盘，其可以包括多个子源极焊盘。同样地，与每个源极焊盘13相连的通孔4也不限于一个，可以和第三实施方式中相同设置多个通孔。其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
第五实施方式
参图6是本发明第五实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中，与有源区内每个源极相连的源极焊盘13的形状不同，通孔形状4也对应的不同，该方式的优点是可以根据栅极互连的结构合理使用无源区的面积，尽量减小整个器件的尺寸。其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
第六实施方式
参图7是本发明第六实施方式中半导体器件的俯视结构示意图。与第一实 施方式不同之处在于，本实施方式中源极焊盘13的截面形状均为圆形或椭圆形，通孔4的截面形状也均为圆形或椭圆形，其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
第七实施方式
参图8是本发明第七实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中源极焊盘13的截面形状均为圆形或椭圆形，通孔4的截面形状为矩形，其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
第八实施方式
参图9是本发明第八实施方式中半导体器件的俯视结构示意图。与第一实施方式不同之处在于，本实施方式中源极焊盘13的截面形状为不规则形状，通孔4的截面形状也为任意不规则形状，该不规则形状的优点是在与源极焊盘相连的通孔的截面面积可以尽可能的大，增加了通孔的截面面积，更利于减小接地电感。其它结构和制造方法均与第一实施方式相同或类似，在此不再赘述。
本发明半导体器件的设计，与现有技术中半导体器件的通孔位置分布图1(a)相比，本发明将通孔4放在了最接近源极的有源区之外的源极互连金属上，两种方式的接地距离基本相同，每个源极的接地电感也相同，但是本发明避开了图1(a)的带来的问题，没有将通孔4直接放在有源区的源极11上，而是放在了接近源极的有源区之外的源极互连金属即源极焊盘13上，这样一来，具有以下优点：
首先，通孔4和源极焊盘13的形状和数量不再受限，更利于减小接地电感和减小工艺制作难度；
其次，有源区内源极和漏极的大小可以相同，解决了大小不同导致的散热问题，更利于提高器件的输出功率；
第三，解决了欧姆金属做刻蚀阻挡层带来的问题，互连金属在有源区之外，互连金属的选择范围更广，更利于通孔刻蚀工艺，不会影响源极欧姆接触的性能，提高了器件的跨导和功率等性能。
本发明半导体器件的设计，与现有技术中半导体器件的通孔位置分布图1(b)相比，相同点是都把通孔放在了有源区外的互连金属上，不同点是本发明没有使用源极互连12，而是直接将有源区的源极11和源极焊盘13直接相连，从而解决了使用源极互连12带来的问题，具有以下优点：
首先，将有源区的源极11和源极焊盘13直接相连，减小了有源区的源极与地的距离，减小了接地电感；
其次，没有使用源极互连12，源极不需要跨过栅极，也就不需要使用跨过栅极的空气桥，因而降低了工艺难度，提高了器件的可靠性和高频性能；
第三，没有使用源极互连12，就避开了源极互连12长度不同带来的每个源极11接地电感不同的问题，提高了器件的增益等性能。
由以上实施方式可以看出，本发明的半导体器件及其制造方法，解决了目前器件的通孔的位置分布带来的问题，同时又利用了其优点，最大程度地减小了器件源极的接地电感，提高了器件的增益等性能。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非 限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (9)

  1. 一种半导体器件，其特征在于，所述半导体器件包括：
    衬底，所述衬底背面设有接地电极；
    位于所述衬底正面上的半导体层，所述半导体层包括有源区和无源区，有源区为封闭形式，有源区之外的区域为无源区；
    位于所述有源区的源极和漏极以及位于所述无源区的漏极，有源区内的源极和漏极为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极之间的间隔相等，无源区内的漏极为有源区内的漏极的互连金属；
    位于所述有源区和无源区上的栅极，位于所述有源区的栅极在源极和漏极间呈叉指状分布，无源区内的栅极为有源区内的栅极的互连金属；
    位于所述无源区的源极焊盘，所述源极焊盘与有源区内的源极直接电连接；所述源极焊盘13对称分布在所述栅极的中间或两侧；
    位于接地电极和源极焊盘间的通孔，所述通孔贯穿衬底和半导体层，直至源极焊盘，通孔使源极焊盘和衬底背面的接地电极电性连接；
    有源区内的每个源极通过与其直接连接的源极焊盘和通孔单独接地。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述源极焊盘包括至少一个子源极焊盘。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述源极焊盘位于所述有源区的同一侧，和/或，所述源极焊盘位于所述有源区的不同侧。
  4. 根据权利要求2所述的半导体器件，其特征在于，所述每个子源极焊盘与一个或多个通孔相连。
  5. 根据权利要求1所述的半导体器件，其特征在于，所述有源区内的源极对应的源极焊盘的截面形状相同或截面形状不同。
  6. 根据权利要求1所述的半导体器件，其特征在于，所述源极焊盘的截面为规则形状或不规则形状。
  7. 根据权利要求1所述的半导体器件，其特征在于，所述通孔的截面为规则形状或不规则形状。
  8. 根据权利要求1所述的半导体器件，其特征在于，所述半导体层包括 氮化镓、铝镓氮、铟镓氮、铝铟镓氮、砷化镓、磷化铟中一种或多种的组合。
  9. 一种如权利要求1～8中任一项所述的半导体器件的制造方法，其特征在于，所述方法包括以下步骤：
    S1、提供一衬底，在所述衬底背面形成接地电极；
    S2、在所述衬底正面上沉积半导体层，所述半导体层包括有源区和无源区，有源区为封闭形式，有源区之外的区域为无源区；
    S3、在所述有源区上形成源极，在所述有源区和所述无源区上形成漏极，有源区内的源极和漏极为欧姆接触电极，所述欧姆接触电极为多个，每个所述欧姆接触电极的尺寸相等且每相邻两个所述欧姆接触电极之间的间隔相等，无源区内的漏极为有源区内的漏极的互连金属；
    S4、在所述有源区和无源区上形成栅极，形成于所述有源区内的栅极在源极和漏极间呈叉指状分布，位于无源区内的栅极为有源区内的栅极的互连金属；
    S5、在所述无源区上形成源极焊盘，所述源极焊盘与有源区内的源极直接电连接；所述源极焊盘对称分布在所述栅极的中间或两侧；
    S6、在接地电极和源极焊盘间形成电性连接的通孔，所述通孔贯穿衬底和半导体层，直至源极焊盘，通孔使源极焊盘和衬底背面的接地电极电性连接；有源区内的每个源极通过与其直接连接的源极焊盘和通孔单独接地。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633046B (zh) * 2013-12-13 2017-03-15 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN104201253B (zh) * 2014-07-10 2017-08-25 中航（重庆）微电子有限公司 一种氮化镓器件及其制造方法
CN104617092B (zh) * 2014-11-06 2018-06-22 苏州捷芯威半导体有限公司 一种半导体器件及其制作方法
CN105321993B (zh) * 2015-05-27 2019-03-29 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法
US10128365B2 (en) 2016-03-17 2018-11-13 Cree, Inc. Bypassed gate transistors having improved stability
US9786660B1 (en) * 2016-03-17 2017-10-10 Cree, Inc. Transistor with bypassed gate structure field
US9960127B2 (en) 2016-05-18 2018-05-01 Macom Technology Solutions Holdings, Inc. High-power amplifier package
CN106252310B (zh) * 2016-06-02 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
US10134658B2 (en) * 2016-08-10 2018-11-20 Macom Technology Solutions Holdings, Inc. High power transistors
JP6812764B2 (ja) * 2016-11-29 2021-01-13 日亜化学工業株式会社 電界効果トランジスタ
CN107980171B (zh) * 2016-12-23 2022-06-24 苏州能讯高能半导体有限公司 半导体芯片、半导体晶圆及半导体晶圆的制造方法
CN108630677B (zh) * 2017-03-17 2022-03-08 智瑞佳（苏州）半导体科技有限公司 一种功率器件版图结构及制作方法
CN107195673A (zh) * 2017-05-19 2017-09-22 北京华进创威电子有限公司 一种非均匀栅长GaNHEMT栅极结构及器件
CN107369708B (zh) * 2017-08-29 2020-04-07 成都海威华芯科技有限公司 一种氮化镓高电子迁移率晶体管及其制备和使用方法
CN109671773B (zh) * 2017-10-16 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN109817605A (zh) * 2018-05-29 2019-05-28 苏州能讯高能半导体有限公司 半导体器件及其制备方法
US10629526B1 (en) * 2018-10-11 2020-04-21 Nxp Usa, Inc. Transistor with non-circular via connections in two orientations
CN111354640B (zh) * 2018-12-21 2022-08-12 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法
CN111384163A (zh) * 2018-12-28 2020-07-07 中国科学院半导体研究所 改善GaN HEMT器件散热性能的结构及布局
CN112018175B (zh) * 2019-05-30 2022-04-08 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法、半导体封装结构
US11791388B2 (en) * 2020-02-27 2023-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Source leakage current suppression by source surrounding gate structure
CN112331653B (zh) * 2020-10-29 2021-11-05 长江存储科技有限责任公司 半导体器件、三维存储器及半导体器件制备方法
CN114664725A (zh) * 2020-12-23 2022-06-24 华润微电子（重庆）有限公司 GaN器件互联结构及其制备方法
CN113437051B (zh) * 2021-08-26 2021-11-19 深圳市时代速信科技有限公司 一种半导体器件
CN115346948B (zh) * 2022-10-14 2023-04-07 吉光半导体(绍兴)有限公司 一种半桥模块

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424006B1 (en) * 1995-06-20 2002-07-23 Infineon Technologies Ag Semiconductor component
CN101378079A (zh) * 2007-08-29 2009-03-04 东部高科股份有限公司 半导体器件
CN102013437A (zh) * 2009-09-07 2011-04-13 西安捷威半导体有限公司 半导体器件及其制造方法
US20130228789A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device
US20130228790A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device
CN103633046A (zh) * 2013-12-13 2014-03-12 苏州能讯高能半导体有限公司 半导体器件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0821595B2 (ja) * 1987-07-28 1996-03-04 三菱電機株式会社 半導体装置
JP3156896B2 (ja) * 1994-01-28 2001-04-16 富士通株式会社 半導体装置の製造方法およびかかる製造方法により製造された半導体装置
JP2629643B2 (ja) * 1995-03-31 1997-07-09 日本電気株式会社 電界効果トランジスタ
JP3235476B2 (ja) * 1996-06-28 2001-12-04 株式会社村田製作所 高周波半導体デバイス
US6166436A (en) * 1997-04-16 2000-12-26 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
JP3758876B2 (ja) * 1999-02-02 2006-03-22 Ｎｅｃマイクロシステム株式会社 半導体装置のレイアウト方法
EP2088620B1 (en) * 2006-11-02 2016-03-16 Kabushiki Kaisha Toshiba Semiconductor device
JP5300238B2 (ja) * 2006-12-19 2013-09-25 パナソニック株式会社 窒化物半導体装置
JP5107138B2 (ja) * 2008-05-29 2012-12-26 住友電工デバイス・イノベーション株式会社 半導体装置
JP5535490B2 (ja) * 2009-01-30 2014-07-02 住友電工デバイス・イノベーション株式会社 半導体装置
JP5604855B2 (ja) * 2009-11-17 2014-10-15 富士通株式会社 半導体装置及びその製造方法
JP2012023212A (ja) * 2010-07-14 2012-02-02 Sumitomo Electric Ind Ltd 半導体装置
WO2012147287A1 (ja) * 2011-04-25 2012-11-01 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
KR101928814B1 (ko) * 2012-05-04 2018-12-14 한국전자통신연구원 질화물계 화합물 전력반도체 장치 및 그 제조 방법
US20130313718A1 (en) * 2012-05-24 2013-11-28 Micron Technology, Inc. Substrates Comprising Integrated Circuitry, Methods Of Processing A Substrate Comprising Integrated Circuitry, And Methods Of Back-Side Thinning A Substrate Comprising Integrated Circuitry
US8872190B1 (en) * 2012-09-14 2014-10-28 M/A-Com Technology Solutions Holdings, Inc. Multi-finger HEMT layout providing improved third order intercept point and saturated output power performance

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424006B1 (en) * 1995-06-20 2002-07-23 Infineon Technologies Ag Semiconductor component
CN101378079A (zh) * 2007-08-29 2009-03-04 东部高科股份有限公司 半导体器件
CN102013437A (zh) * 2009-09-07 2011-04-13 西安捷威半导体有限公司 半导体器件及其制造方法
US20130228789A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device
US20130228790A1 (en) * 2012-03-02 2013-09-05 Kabushiki Kaisha Toshiba Semiconductor device
CN103633046A (zh) * 2013-12-13 2014-03-12 苏州能讯高能半导体有限公司 半导体器件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3082160A4 *

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CN103633046B (zh) 2017-03-15
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