WO2012147287A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2012147287A1 WO2012147287A1 PCT/JP2012/002417 JP2012002417W WO2012147287A1 WO 2012147287 A1 WO2012147287 A1 WO 2012147287A1 JP 2012002417 W JP2012002417 W JP 2012002417W WO 2012147287 A1 WO2012147287 A1 WO 2012147287A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- divided
- electrodes
- semiconductor device
- abnormally grown
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000002159 abnormal effect Effects 0.000 claims abstract description 36
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 17
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 description 19
- 238000010586 diagram Methods 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/095—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device in which a semiconductor device including an abnormally grown portion in an operation region can be easily removed by an appearance check.
- field effect transistors As one of field effect transistors (FET) having high breakdown resistance and high speed, there is a field effect transistor using a gallium nitride (GaN) -based semiconductor material having a wide band gap characteristic.
- Field effect transistors using GaN are used in, for example, high-frequency amplifiers, high-power amplifiers, power switching devices, and the like.
- GaN is often epitaxially grown on a SiC substrate, a sapphire substrate, a Si substrate, or the like instead. At this time, an abnormally grown portion may occur on the surface of the GaN epitaxial film depending on the substrate used for the growth of GaN and the growth conditions.
- Possible causes for the formation of the abnormal growth portion 103 include defects (micropipes) in the SiC substrate 101 on which the GaN film 102 is grown and abnormal growth with minute dust adhering during growth as a nucleus.
- the abnormally grown portion can be formed in a GaN film epitaxially grown on a Si substrate or a sapphire substrate or a SiC film epitaxially grown on a SiC substrate.
- Patent Document 1 discloses a technique related to a high power transistor that can reduce the drain-source capacitance by dividing the drain electrode into two.
- Patent Document 2 discloses a technique in which the drain electrode and the source electrode have a lattice shape in order to reduce the parasitic capacitance of the drain electrode and the source electrode.
- FIG. 10 is a diagram for explaining an abnormally grown portion formed in the epitaxial film.
- the upper figure is a top view and the lower figure is a cross-sectional view.
- an abnormally grown portion 103 is formed depending on the growth conditions.
- the size of the abnormal growth portion 103 depends on the growth conditions of the GaN film 102, it is a rounded hexagon, and its diameter is about 40 ⁇ m or more when approximated by a circle.
- the thickness is about 50 to 100 nm from the surface of the GaN film 102. If the growth conditions of the GaN film 102 are the same, abnormally grown portions having substantially the same size are formed on the same wafer and between wafers processed in different batches.
- Non-Patent Documents 1 and 2 When the gate of the FET is formed on the abnormally grown portion when forming the FET, an increase in gate leakage or a pinch-off defect occurs (see Non-Patent Documents 1 and 2). On the other hand, when the gate of the FET is not formed on the abnormally grown portion, there is no abnormality caused by the abnormally grown portion such as an increase in gate leakage or a pinch-off defect. At this time, even if the source electrode and the drain electrode are formed on the abnormally grown portion, there is no abnormality in electrical characteristics such as DC characteristics. However, if the source electrode and drain electrode, which are ohmic contacts, are formed on the abnormally grown portion, there is a risk of affecting long-term reliability. There is a need to. For this reason, it is necessary to remove the FET having an abnormally grown portion in the operation region by an appearance check or the like.
- FIG. 11 is a diagram for explaining the problem of the present invention, and is a top view of an FET in which gate electrodes 103_1 to 103_4, source electrodes 104_1 to 104_3, and drain electrodes 105_1 to 105_2 are formed.
- one gate electrode 103_1 and the source electrode 104_1 and the drain electrode 105_1 sandwiching the gate electrode 103_1 constitute one unit FET, and a plurality of the unit FETs are arranged in parallel.
- a region that operates as an FET is referred to as an operation region 106, and regions other than the operation region 106 are processed so that a semiconductor crystal is broken and current does not flow by ion implantation or the like.
- the drain electrode 105_1 located between the adjacent gate electrodes 103_1 and 103_2 and the source electrode 104_2 located between the adjacent gate electrodes 103_2 and 103_3 are each formed using a continuous electrode film. ing.
- the abnormal growth portion 109 exists under the region where the drain electrode 105_2 is formed, the abnormal growth portion 109 is hidden by the drain electrode 105_2, so the presence of the abnormal growth portion is detected from the appearance. Can not do it. For this reason, there has been a problem that FETs having abnormally grown portions in the operation region 106 cannot be removed by appearance check.
- a semiconductor device includes a substrate, an epitaxial layer formed on the substrate, and a gate electrode, a source electrode, and a drain electrode respectively formed on the epitaxial layer.
- Each of the source electrode and the drain electrode includes at least two first divided electrodes formed so as to extend in parallel with each other in a first direction, and the distance between the electrodes of the first divided electrode is the surface of the epitaxial layer And the width of each of the first divided electrodes is less than or equal to the radius of the abnormally grown portion.
- the distance between the electrodes of the first divided electrodes is not less than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the width of each divided electrode is not more than the radius of the abnormally grown portion. It is said. For this reason, since the abnormally grown portion is exposed to the outside through the gap between the divided electrodes constituting the source electrode and the drain electrode, the abnormally grown portion can be easily detected by the appearance check, and the abnormally grown portion is included in the operation region. The semiconductor device can be easily removed.
- an epitaxial layer is formed on a substrate, a gate electrode, a source electrode, and a drain electrode are formed on the epitaxial layer, and the gate electrode, the source electrode, and the When forming the drain electrodes, at least two first divided electrodes extending in parallel with each other in the first direction are formed on the source electrode and the drain electrode, respectively, and the distance between the electrodes of the first divided electrodes is
- the radius of the abnormally grown portion formed on the surface of the epitaxial layer is set to be equal to or larger than the radius of the abnormally grown portion.
- the distance between the electrodes of the first divided electrodes is not less than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the width of each divided electrode is the abnormally grown portion. Less than the radius. For this reason, since the abnormally grown portion is exposed to the outside through the gap between the divided electrodes constituting the source electrode and the drain electrode, the abnormally grown portion can be easily detected by the appearance check, and the abnormally grown portion is included in the operation region. The semiconductor device can be easily removed.
- the present invention it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device, in which a semiconductor device including an abnormally grown portion in an operation region can be easily removed by an appearance check.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment
- FIG. 3 is a top view showing an arrangement of a gate electrode, a source electrode, and a drain electrode of the semiconductor device according to the first embodiment.
- FIG. 6 is a diagram for explaining an effect of the semiconductor device according to the first embodiment;
- FIG. 6 is a diagram of a comparative example for explaining the effect of the semiconductor device according to the first embodiment.
- FIG. 6 is a diagram for explaining an effect of the semiconductor device according to the first embodiment;
- FIG. 6 is a diagram of a comparative example for explaining the effect of the semiconductor device according to the first embodiment.
- FIG. 6 is a top view showing another arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the first embodiment.
- FIG. 7 is a cross-sectional view showing another example of the semiconductor device according to the first embodiment
- FIG. FIG. 6 is a top view illustrating an arrangement of a gate electrode, a source electrode, and a drain electrode of a semiconductor device according to a second embodiment.
- FIG. 6 is a top view illustrating an arrangement of a gate electrode, a source electrode, and a drain electrode of a semiconductor device according to a second embodiment.
- FIG. 6 is a diagram for explaining an effect of the semiconductor device according to the first embodiment;
- FIG. 6 is a diagram of a comparative example for explaining the effect of the semiconductor device according to the first embodiment.
- FIG. 6 is a top view showing another arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the second embodiment. It is a figure for demonstrating the abnormal growth part formed in an epitaxial film. It is a figure for demonstrating the subject of this invention.
- FIGS. 1A and 1B are diagrams for explaining a semiconductor device according to a first embodiment of the present invention.
- 1A is a cross-sectional view taken along the line IA-IA of FIG. 1B
- FIG. 1B is a top view showing the arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the present embodiment.
- the semiconductor device according to the present embodiment includes a substrate 1, an epitaxial layer 2 formed on the substrate 1, a gate electrode 3 and a source electrode 4 formed on the epitaxial layer 2, respectively. And the drain electrode 5.
- the semiconductor device according to the present embodiment is, for example, a field effect transistor (FET).
- the epitaxial layer 2 is a GaN-based material
- a SiC substrate, a sapphire substrate, a Si substrate, a GaN substrate, a GaAs substrate, or the like can be used as the substrate 1.
- a substrate means a single crystal substrate.
- the substrate 1 can be determined according to the epitaxial layer 2 formed on the substrate 1.
- a SiC substrate is used as the substrate 1 and GaN is formed as the epitaxial layer 2 will be described.
- any material can be used for the substrate 1 and the epitaxial layer 2 as long as the epitaxial layer 2 can be formed on the substrate 1 and an abnormally grown portion is formed on the surface of the epitaxial layer. Can do.
- the abnormally grown portion is an abnormally grown portion formed according to the growth conditions when, for example, the epitaxial layer 2 is grown on the substrate 1.
- the size of the abnormal growth portion 103 depends on the growth conditions of the GaN film 102, it is a rounded hexagon, and its diameter is about 40 ⁇ m or more when approximated by a circle. The thickness is about 50 to 100 nm from the surface of the GaN film 102 (see FIG. 10).
- the radius and diameter of the abnormally grown portion are the radius and diameter when the abnormally grown portion having a hexagonal shape is approximated by a circle. If the growth conditions of the epitaxial layer 2 are the same, abnormally grown portions having substantially the same size are formed on the same wafer and between wafers processed in different batches.
- Possible causes of the formation of the abnormal growth portion 103 include defects (micropipes) in the substrate 1 on which the epitaxial layer 2 is grown and abnormal growth with minute dust adhered during growth as a nucleus.
- the abnormally grown portion can be formed in a GaN film epitaxially grown on a Si substrate or a sapphire substrate or a SiC film epitaxially grown on a SiC substrate.
- the size of the abnormally grown portion is an example, and the present invention can be used even when an abnormally grown portion other than the above size is formed.
- the source electrode 4 and the drain electrode 5 are formed so as to sandwich the gate electrode 3.
- the source electrode 4 is connected to the divided electrodes (first divided electrodes) 4_1 and 4_2 extending in parallel with the longitudinal direction (first direction) of the gate electrode and the divided electrodes 4_1 and 4_2. And an electrode 4_3.
- the interval (pitch) between the divided electrode 4_1 and the divided electrode 4_2 is Ps
- the width of the divided electrode 4_1 is Ws1
- the width of the divided electrode 4_2 is Ws2.
- the drain electrode 5 includes divided electrodes (first divided electrodes) 5_1 and 5_2 extending in parallel with the longitudinal direction of the gate electrode, and a connection electrode 5_3 connecting the divided electrodes 5_1 and 5_2.
- the interval (pitch) between the divided electrode 5_1 and the divided electrode 5_2 is Pd
- the width of the divided electrode 5_1 is Wd1
- the width of the divided electrode 5_2 is Wd2.
- the region that operates as an FET is the operation region 6, and the region other than the operation region 6 is processed so that the semiconductor crystal is destroyed and current does not flow by ion implantation or the like.
- the inter-electrode distance Ps of the divided electrodes 4_1 and 4_2 of the source electrode 4 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer 2, and each of the divided electrodes 4_1 and 4_2.
- the widths Ws1 and Ws2 are set to be equal to or smaller than the radius of the abnormal growth portion.
- the interelectrode distance Pd between the divided electrodes 5_1 and 5_2 of the drain electrode 5 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer 2, and the widths Wd1 and Wd2 of the divided electrodes 5_1 and 5_2 are abnormally grown. Less than the radius of the part.
- the drain electrode 105_1 located between the adjacent gate electrodes 103_1 and 103_2 and the source electrode 104_2 located between the adjacent gate electrodes 103_2 and 103_3 each use a continuous electrode film. Is formed.
- the abnormal growth portion 109 exists under the region where the drain electrode 105_2 is formed, the abnormal growth portion 109 is hidden by the drain electrode 105_2, so the presence of the abnormal growth portion is detected from the appearance. Can not do it. That is, in the appearance check of the abnormal growth unit 109, the contrast of the outer peripheral line of the abnormal growth unit 109 is recognized and detected.
- the abnormally grown portion 109 is formed by raising a 50 to 100 nm GaN layer, the contrast becomes unclear when it is covered with a thick source electrode or drain electrode. For this reason, there has been a problem that an FET having an abnormally grown portion in the operation region cannot be removed by an appearance check.
- the interelectrode distance Ps of the divided electrodes 4_1 and 4_2 of the source electrode 4 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer 2, and the drain electrode
- the inter-electrode distance Pd between the five divided electrodes 5_1 and 5_2 is equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer 2. Accordingly, for example, as shown in FIG. 2A, when the abnormally grown portion 9 having the radius r is formed between the divided electrode 4_1 and the divided electrode 4_2 of the source electrode 4, the divided electrode 4_1 is used in the invention according to the present embodiment. Since the inter-electrode distance Ps of 4_2 is sufficiently wide, a part of the abnormal growth portion 9 is exposed to the outside, and the abnormal growth portion 9 can be easily detected by appearance check.
- the widths Ws1 and Ws2 of the divided electrodes 4_1 and 4_2 are set to be equal to or less than the radius of the abnormally grown portion, and the widths Wd1 and Wd1 of the divided electrodes 5_1 and 5_2, respectively.
- Wd2 is set to be equal to or less than the radius of the abnormally grown portion.
- the abnormally grown portion 9 having the radius r when the abnormally grown portion 9 having the radius r is formed so as to overlap the divided electrode 4_1 when the width Ws1 of the divided electrode 4_1 of the source electrode 4 is wide, The portion of the abnormally grown portion 9 that is exposed is reduced, and it is difficult to check the presence of the abnormally grown portion from the appearance. Therefore, as in the invention according to the present embodiment, by making the widths Ws1 and Ws2 of the divided electrodes 4_1 and 4_2 below the radius of the abnormal growth portion, the abnormal growth portion can be easily detected by the appearance check. become able to. 3A and 3B show the source electrode, the same applies to the drain electrode.
- Patent Document 1 described in the background art discloses a technique related to a high power transistor capable of reducing the drain-source capacitance by dividing the drain electrode into two.
- Patent Document 2 discloses a technique in which the drain electrode and the source electrode have a lattice shape in order to reduce the parasitic capacitance of the drain electrode and the source electrode.
- Patent Document 2 it is difficult to check the presence of abnormally grown portions from the appearance when the lattice spacing is narrow.
- FIG. 4 is a top view showing another arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the present embodiment.
- one gate electrode 13_1 and the source electrode 14_1 and the drain electrode 15_1 sandwiching the gate electrode 13_1 constitute one unit FET, and a plurality of the unit FETs are arranged in parallel.
- the region that operates as the FET is the operation region 16, and the region other than the operation region 16 is processed so that the semiconductor crystal is broken and current does not flow by ion implantation or the like.
- the gate electrode includes electrodes 13_1, 13_2, 13_3, and 13_4, a connection electrode 13_5 that connects these electrodes, and an electrode pad 13_6.
- the source electrode includes divided electrodes 14_1, 14_2, 14_3, 14_4 and an electrode pad 14_6.
- the drain electrode includes divided electrodes 15_1, 15_2, 15_3, and 15_4, a connection electrode 15_5 that connects these divided electrodes, and an electrode pad 15_6.
- the interelectrode distance Ps between the divided electrodes 14_2 and 14_3 of the source electrode is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Ws1 and 14_3 of the divided electrodes 14_2 and 14_3, Ws2 is set to be equal to or less than the radius of the abnormally grown portion.
- the interelectrode distance Pd between the divided electrodes 15_1 and 15_2 of the drain electrode is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Wd1 and Wd2 of the divided electrodes 15_1 and 15_2 are set to the abnormally grown portion. Below the radius. These conditions are the same for other unit FETs.
- the interval between the divided electrodes and the width of each divided electrode can be arbitrarily set for each divided electrode as long as the above conditions are satisfied.
- the inter-electrode distance Ps of the divided electrodes 14_2 and 14_3 of the source electrode is 60 ⁇ m
- the widths Ws1 and Ws2 of the divided electrodes 14_2 and 14_3 are 15 ⁇ m
- the divided electrode 15_1 of the drain electrode , 15_2 has an electrode distance Pd of 60 ⁇ m
- the widths Wd1 and Wd2 of the divided electrodes 15_1 and 15_2 are 15 ⁇ m
- the distance between the gate electrode 13_2 and the divided electrode 15_1 of the drain electrode is 5 ⁇ m
- the distance from 14_2 can be set to 5 ⁇ m. The same applies to other unit FETs.
- the abnormal growth portion included in the operation region can be easily detected by the appearance check.
- FIG. 5 is a cross-sectional view for explaining the HEMT transistor according to the present embodiment.
- the HEMT transistor according to the present embodiment is formed on a silicon substrate 21, a channel layer 22 formed on the silicon substrate 21, a channel layer 22, and an electron on the channel layer 22.
- a two-dimensional electron gas layer (2DEG) 23 formed by a heterojunction of the channel layer 22 and the barrier layer 24, a source electrode 26 and a drain electrode 27 in ohmic contact with the barrier layer 24,
- a gate electrode 25 is formed between the source electrode 26 and the drain electrode 27 and has a barrier layer 24 and a Schottky junction.
- i-GaN (i is intrinsic, that is, an intrinsic semiconductor to which no impurity is added) can be used for the channel layer 22.
- the channel layer 22 may have a multilayer structure including not only i-GaN but also i-Al (Ga) N, i-In (Ga) N, and the like.
- i-AlxGa1-xN 0.1 to 0.4
- n-AlGaN doped with high-concentration Si can be used.
- the barrier layer 24 supplies electrons to the channel layer 22.
- a two-dimensional electron gas layer (2DEG) 23 is formed at the interface between the channel layer 22 and the barrier layer 24.
- the channel layer 22 and the barrier layer 24 are epitaxially grown on the silicon substrate 21.
- a nucleation layer for relaxing crystal dislocation is omitted.
- a source electrode 26 and a drain electrode 27 that are in ohmic contact with the barrier layer 24 are formed on the barrier layer 24, and electrons are transferred from the source electrode 26 to the drain electrode 27 through the two-dimensional electron gas layer 23. Flowing.
- the source electrode 26 and the drain electrode 27 are composed of, for example, an ohmic electrode such as Ti / Al and a wiring electrode such as Ti / Pt / Au.
- a gate electrode 25 that forms a Schottky junction with the barrier layer 24 is formed between the source electrode 26 and the drain electrode 27 on the barrier layer 24.
- the gate electrode 25 can be formed using, for example, Ni / Au.
- an epitaxial layer 2 is formed on a substrate 1, and a gate electrode 3, a source electrode 4, and a drain electrode 5 are formed on the epitaxial layer 2. Then, when forming the gate electrode 3, the source electrode 4, and the drain electrode 5, respectively, at least two divided electrodes 4_1, 4_2, 5_1, 5_2 extending in parallel to each other in the first direction on the source electrode 4 and the drain electrode 5. And the distances Ps and Pd between the divided electrodes are not less than the radius of the abnormally grown portion formed on the surface of the epitaxial layer 2, and the width of each of the divided electrodes is not more than the radius of the abnormally grown portion. To.
- the invention according to the present embodiment it is possible to provide a semiconductor device that can easily remove a semiconductor device including an abnormally grown portion in an operation region by an appearance check, and a method for manufacturing the semiconductor device. It becomes possible.
- Embodiment 2 Next, a second embodiment of the present invention will be described.
- the present embodiment is different from the semiconductor device according to the first embodiment in that the arrangement of the gate electrode, the source electrode, and the drain electrode is a lattice. Since other than this is the same as that of the semiconductor device according to the first embodiment, the redundant description is omitted.
- FIG. 6 is a top view showing the arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the second embodiment.
- the source electrode 34 and the drain electrode 35 are formed so as to sandwich the gate electrode 33.
- the source electrode 34 includes divided electrodes 34_1 and 34_2 extending in parallel with the longitudinal direction (first direction) of the gate electrode 33, and at least two divided portions extending in a direction intersecting with the divided electrodes 34_1 and 34_2 (second direction). Electrodes (second divided electrodes) 34_3 and 34_4 and connection electrodes 34_5 connecting the divided electrodes 34_1 and 34_2 are provided.
- the interval (pitch) between the divided electrode 34_1 and the divided electrode 34_2 is Ps11
- the width of the divided electrode 34_1 is Ws11
- the width of the divided electrode 34_2 is Ws12.
- the interval (pitch) between the divided electrode 34_3 and the divided electrode 34_4 is Ps21
- the width of the divided electrode 34_3 is Ws21
- the width of the divided electrode 34_4 is Ws22.
- the drain electrode 35 includes divided electrodes 35_1 and 35_2 extending in parallel with the longitudinal direction of the gate electrode 33, and at least two divided electrodes (second directions) extending in a direction (second direction) intersecting the divided electrodes 35_1 and 35_2.
- Divided electrodes) 35_3 and 35_4, and connection electrodes 35_5 for connecting the divided electrodes 35_1 and 35_2.
- the interval (pitch) between the divided electrode 35_1 and the divided electrode 35_2 is Pd11
- the width of the divided electrode 35_1 is Wd11
- the width of the divided electrode 35_2 is Wd12.
- the interval (pitch) between the divided electrode 35_3 and the divided electrode 35_4 is Pd21
- the width of the divided electrode 35_3 is Wd21
- the width of the divided electrode 35_4 is Wd22.
- FIG. 6 illustrates the case where the first direction and the second direction are orthogonal, the first direction and the second direction only need to intersect, and the case is orthogonal It is not limited to.
- the source electrode 34 and the drain electrode 35 are formed in a lattice shape. Then, the interelectrode distance Ps11 between the divided electrodes 34_1 and 34_2 of the source electrode 34 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Ws11 and Ws12 of the divided electrodes 34_1 and 34_2 are set as the abnormally grown portion. Less than the radius.
- the inter-electrode distance Ps21 between the divided electrodes 34_3 and 34_4 of the source electrode 34 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Ws21 and Ws22 of the divided electrodes 34_3 and 34_4 are set as the abnormally grown portion. Below the radius. Further, at least one of the inter-electrode distance Ps11 of the divided electrodes 34_1 and 34_2 and the inter-electrode distance Ps21 of the divided electrodes 34_3 and 34_4 is set to be equal to or larger than the diameter of the abnormally grown portion.
- the interelectrode distance Pd11 between the divided electrodes 35_1 and 35_2 of the drain electrode 35 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Wd11 and Wd12 of the divided electrodes 35_1 and 35_2 are set as the abnormally grown portion. Less than the radius.
- the inter-electrode distance Pd21 between the divided electrodes 35_3 and 35_4 of the drain electrode 35 is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the respective widths Wd21 and Wd22 of the divided electrodes 35_3 and 35_4 are set as the abnormally grown portion. Below the radius.
- At least one of the interelectrode distance Pd11 of the divided electrodes 35_1 and 35_2 and the interelectrode distance Pd21 of the divided electrodes 35_3 and 35_4 is set to be equal to or larger than the diameter of the abnormally grown portion.
- the inter-electrode distances Ps21 and Pd21 of the divided electrodes parallel to the second direction are equal to or larger than the diameter of the abnormally grown portion.
- the inter-electrode distances Ps11 and Pd11 of the divided electrodes parallel to the first direction are set to be equal to or larger than the diameter of the abnormally grown portion.
- FIG. 8A shows a case where the interelectrode distance Ps11 of the divided electrodes 34_1 and 34_2 is equal to or larger than the radius of the abnormally grown portion, and the interelectrode distance Ps21 of the divided electrodes 34_3 and 34_4 is equal to or larger than the diameter of the abnormally grown portion. .
- the condition that at least one of the interelectrode distance Ps11 of the divided electrodes 34_1 and 34_2 and the interelectrode distance Ps21 of the divided electrodes 34_3 and 34_4 is equal to or larger than the diameter of the abnormally grown portion is not satisfied.
- the abnormally growing part 39 is covered with the divided electrodes, and therefore the abnormally growing part 39 cannot be detected by the appearance check.
- 8A and 8B show the source electrode, the same applies to the drain electrode.
- FIG. 9 is a top view showing another arrangement of the gate electrode, the source electrode, and the drain electrode of the semiconductor device according to the present embodiment.
- one gate electrode and a source electrode and a drain electrode sandwiching the gate electrode constitute one unit FET, and a plurality of unit FETs are arranged in parallel.
- the region that operates as the FET is the operation region 46, and the region other than the operation region 46 is processed so that the semiconductor crystal is broken and current does not flow by ion implantation or the like.
- the gate electrode includes a plurality of electrodes 43_1, a connection electrode 43_2 that connects these electrodes, and an electrode pad 43_3.
- the source electrode includes divided electrodes 44_1, 44_2, and 44_3, divided electrodes 44_4, 44_5, and 44_6 that are orthogonal to the divided electrodes 44_1, 44_2, and 44_3, and an electrode pad 44_7.
- the drain electrodes are divided electrodes 45_1, 45_2, 45_3, divided electrodes 45_4, 45_5, 45_6 orthogonal to these divided electrodes 45_1, 45_2, 45_3, connection electrodes 45_7 that connect the divided electrodes 45_1, 45_2, 45_3, and electrodes And a pad 45_8.
- the inter-electrode distance Ps11 of the divided electrodes 44_1, 44_2, and 44_3 of the source electrode is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the widths of the divided electrodes 44_1, 44_2, and 44_3 are abnormally grown. It is below the radius of the part.
- the interelectrode distance Ps21 of the divided electrodes 44_4, 44_5, 44_6 of the source electrode is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the width of each of the divided electrodes 44_4, 44_5, 44_6 is Below the radius.
- At least one of the interelectrode distance Ps11 of the divided electrodes 44_1, 44_2, and 44_3 and the interelectrode distance Ps21 of the divided electrodes 44_4, 44_5, and 44_6 is set to be equal to or larger than the diameter of the abnormally grown portion.
- the interelectrode distance Ps21 between the divided electrodes 44_4, 44_5, and 44_6 is equal to or greater than the diameter of the abnormally grown portion.
- the interelectrode distance Pd11 between the divided electrodes 45_1, 45_2, and 45_3 of the drain electrode is set to be not less than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the width of each of the divided electrodes 45_1, 45_2, and 45_3 is the abnormally grown portion. Less than the radius.
- the interelectrode distance Pd21 of the divided electrodes 45_4, 45_5, 45_6 of the drain electrode is set to be equal to or larger than the radius of the abnormally grown portion formed on the surface of the epitaxial layer, and the width of each of the divided electrodes 45_1, 45_2, 45_3 is Below the radius.
- At least one of the interelectrode distance Pd11 of the divided electrodes 45_1, 45_2, and 45_3 and the interelectrode distance Pd21 of the divided electrodes 45_4, 45_5, and 45_6 is set to be equal to or larger than the diameter of the abnormally grown portion.
- the interelectrode distance Pd21 between the divided electrodes 45_4, 45_5, and 45_6 is equal to or greater than the diameter of the abnormally grown portion.
- the interelectrode distance Ps11 of the source electrode divided electrodes 44_1, 44_2, and 44_3 is 25 ⁇ m
- the interelectrode distance Ps21 of the source electrode divided electrodes 44_4, 44_5, and 44_6 is 45 ⁇ m.
- the width of the divided electrodes 44_1 and 44_2 can be 15 ⁇ m
- the width of the divided electrodes 44_3, 44_4, 44_5 and 44_6 can be 10 ⁇ m.
- the inter-electrode distance Pd11 of the drain electrode divided electrodes 45_1, 45_2, 45_3 is 25 ⁇ m
- the inter-electrode distance Pd21 of the drain electrode divided electrodes 45_4, 45_5, 45_6 is 45 ⁇ m
- the width of the divided electrodes 45_1, 45_2 is 15 ⁇ m
- the width of the divided electrodes 45_3, 45_4, 45_5, and 45_6 can be 10 ⁇ m.
- the interval between the divided electrodes and the width of each divided electrode can be arbitrarily set for each divided electrode as long as the above conditions are satisfied.
- the divided electrodes 44_4, 44_5, and 44_6 of the source electrode do not need to be orthogonal to the divided electrodes 44_1, 44_2, and 44_3, and are provided so as to obliquely intersect the divided electrodes 44_1, 44_2, and 44_3 as long as the above conditions are satisfied. It may be.
- the divided electrodes 45_4, 45_5, and 45_6 of the drain electrode do not need to be orthogonal to the divided electrodes 45_1, 45_2, and 45_3, and are provided so as to obliquely intersect the divided electrodes 45_1, 45_2, and 45_3 as long as the above conditions are satisfied. It may be done.
- the abnormal growth portion included in the operation region can be easily detected by the appearance check. Therefore, according to the invention according to the present embodiment, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device, in which a semiconductor device including an abnormally grown portion in an operation region can be easily removed by an appearance check.
- the drain electrode and the source electrode are each divided into a plurality of divided electrodes, the density of the current flowing through one divided electrode is increased, and the electrodes are deteriorated by electromigration. There was a fear.
- the drain electrode and the source electrode are each formed in a lattice shape, whereby the density of current flowing through one divided electrode , And electrode deterioration due to electromigration can be suppressed. Further, it is possible to eliminate the phase shift of the signal between the divided electrodes. Furthermore, in the semiconductor device according to the present embodiment, by forming the source electrode and the drain electrode so as to satisfy the above conditions, the semiconductor device including an abnormally grown portion in the operation region can be easily removed by appearance check. .
- the interelectrode distances Ps, Pd, Ps11, and Pd11 of the first divided electrode are set to be greater than or equal to the radius of the abnormally grown portion.
- the interelectrode distance of the first divided electrode is It is good also as 3/4 or more of a diameter.
- the inter-electrode distances Ps21 and Pd21 of the second divided electrode are set to be equal to or larger than the radius of the abnormally grown portion.
- the interelectrode distance of the second divided electrode is set to 3 / of the diameter of the abnormally grown portion. It is good also as 4 or more.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
以下、図面を参照して本発明の実施の形態について説明する。
図1Aおよび図1Bは、本発明の実施の形態1にかかる半導体装置を説明するための図である。図1Aは図1BのIA-IAにおける断面図であり、図1Bは本実施の形態にかかる半導体装置のゲート電極、ソース電極、およびドレイン電極の配置を示す上面図である。
次に、本発明の実施の形態2について説明する。本実施の形態では、ゲート電極、ソース電極、およびドレイン電極の配置が格子状となっている点が実施の形態1にかかる半導体装置と異なる。これ以外は実施の形態1にかかる半導体装置と同様であるので、重複した説明は省略する。
2 エピタキシャル層
3 ゲート電極
4 ソース電極
5 ドレイン電極
6 動作領域
4_1、4_2 分割電極
4_3 接続電極
5_1、5_2 分割電極
5_3 接続電極
9 異常成長部
Claims (13)
- 基板と、
前記基板上に形成されたエピタキシャル層と、
前記エピタキシャル層の上部にそれぞれ形成されたゲート電極、ソース電極、およびドレイン電極と、を備え、
前記ソース電極およびドレイン電極はそれぞれ、第1の方向に互いに平行に延びるように形成された少なくとも2つの第1の分割電極を備え、当該第1の分割電極の電極間距離は前記エピタキシャル層の表面に形成される異常成長部の半径以上であり、且つ前記第1の分割電極のそれぞれの幅が前記異常成長部の半径以下である、
半導体装置。 - 前記ソース電極およびドレイン電極はそれぞれ、更に前記第1の分割電極と交差する第2の方向に互いに平行に延びるように形成された少なくとも2つの第2の分割電極を備え、当該第2の分割電極の電極間距離は前記異常成長部の半径以上であり、前記第2の分割電極のそれぞれの幅が前記異常成長部の半径以下であり、且つ、前記第1の分割電極の電極間距離および前記第2の分割電極の電極間距離の少なくとも一方は前記異常成長部の直径以上である、
請求項1に記載の半導体装置。 - 前記異常成長部は前記エピタキシャル層の表面において六角形であり、前記異常成長部の半径は前記六角形の形状を円形に近似した際の半径である、請求項1または2に記載の半導体装置。
- 前記エピタキシャル層はGaNを含む、請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記基板は、SiC基板、サファイア基板、Si基板、GaN基板、およびGaAs基板のうちのいずれかである、請求項1乃至4のいずれか一項に記載の半導体装置。
- 前記異常成長部の半径が20μm以上である、請求項1乃至5のいずれか一項に記載の半導体装置。
- 前記ゲート電極と、当該ゲート電極を挟む前記ソース電極およびドレイン電極と、が複数並列に配置されている、請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記第1の分割電極の電極間距離は前記異常成長部の直径の3/4以上である、請求項1乃至7のいずれか一項に記載の半導体装置。
- 前記第2の分割電極の電極間距離は前記異常成長部の直径の3/4以上である、請求項2乃至8のいずれか一項に記載の半導体装置。
- 前記エピタキシャル層は、
チャネル層と、
前記チャネル層上に形成されると共に、前記チャネル層に電子を供給するバリア層と、
前記チャネル層と前記バリア層とのヘテロ接合により形成された2次元電子ガス層と、を含み、
前記ソース電極およびドレイン電極は、前記バリア層とオーミック接触するように形成され、
前記前記ゲート電極は、前記バリア層とショットキー接合するように形成されている、
請求項1乃至9のいずれか一項に記載の半導体装置。 - 前記チャネル層はi-GaNで形成されており、前記バリア層はi-AlxGa1-xN(x=0.1~0.4)で形成されている、請求項10に記載の半導体装置。
- 基板上にエピタキシャル層を形成し、
前記エピタキシャル層の上部にゲート電極、ソース電極、およびドレイン電極をそれぞれ形成し、
前記ゲート電極、前記ソース電極、および前記ドレイン電極をそれぞれ形成する際に、前記ソース電極およびドレイン電極に第1の方向に互いに平行に延びる少なくとも2つの第1の分割電極をそれぞれ形成し、当該第1の分割電極の電極間距離が前記エピタキシャル層の表面に形成される異常成長部の半径以上で、且つ前記第1の分割電極のそれぞれの幅が前記異常成長部の半径以下となるようにする、
半導体装置の製造方法。 - 前記ソース電極およびドレイン電極に、前記第1の分割電極と交差する第2の方向に互いに平行に延びる少なくとも2つの第2の分割電極をそれぞれ形成し、当該第2の分割電極の電極間距離が前記異常成長部の半径以上で、前記第2の分割電極のそれぞれの幅が前記異常成長部の半径以下で、且つ、前記第1の分割電極の電極間距離および前記第2の分割電極の電極間距離の少なくとも一方が前記異常成長部の直径以上となるようにする、
請求項12に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013511901A JP5628416B2 (ja) | 2011-04-25 | 2012-04-06 | 半導体装置および半導体装置の製造方法 |
US14/112,374 US9166009B2 (en) | 2011-04-25 | 2012-04-06 | Semiconductor apparatus and method for making semiconductor apparatus |
US14/854,741 US20160005847A1 (en) | 2011-04-25 | 2015-09-15 | Semiconductor apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011-096929 | 2011-04-25 | ||
JP2011096929 | 2011-04-25 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/112,374 A-371-Of-International US9166009B2 (en) | 2011-04-25 | 2012-04-06 | Semiconductor apparatus and method for making semiconductor apparatus |
US14/854,741 Continuation US20160005847A1 (en) | 2011-04-25 | 2015-09-15 | Semiconductor apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012147287A1 true WO2012147287A1 (ja) | 2012-11-01 |
Family
ID=47071821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/002417 WO2012147287A1 (ja) | 2011-04-25 | 2012-04-06 | 半導体装置および半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9166009B2 (ja) |
JP (1) | JP5628416B2 (ja) |
WO (1) | WO2012147287A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465741A (zh) * | 2013-09-13 | 2015-03-25 | 株式会社东芝 | 半导体装置 |
US20150194517A1 (en) * | 2014-01-03 | 2015-07-09 | Globalfoundries Inc. | Gate stack and contact structure |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103633046B (zh) * | 2013-12-13 | 2017-03-15 | 苏州能讯高能半导体有限公司 | 半导体器件及其制造方法 |
JP6299665B2 (ja) * | 2015-04-30 | 2018-03-28 | 三菱電機株式会社 | 電界効果トランジスタ |
JP6660631B2 (ja) | 2015-08-10 | 2020-03-11 | ローム株式会社 | 窒化物半導体デバイス |
JP6812764B2 (ja) * | 2016-11-29 | 2021-01-13 | 日亜化学工業株式会社 | 電界効果トランジスタ |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62252949A (ja) * | 1986-04-25 | 1987-11-04 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ−群を有する基板の検査法 |
JP2004356454A (ja) * | 2003-05-30 | 2004-12-16 | Sharp Corp | 窒化物半導体発光素子 |
JP2008518462A (ja) * | 2004-10-29 | 2008-05-29 | クリー インコーポレイテッド | トランジスタ用の非対称レイアウト構造及びその製作方法 |
JP2008124262A (ja) * | 2006-11-13 | 2008-05-29 | Oki Electric Ind Co Ltd | 選択再成長を用いたAlGaN/GaN−HEMTの製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4206469A (en) * | 1978-09-15 | 1980-06-03 | Westinghouse Electric Corp. | Power metal-oxide-semiconductor-field-effect-transistor |
JPH05190574A (ja) | 1992-01-17 | 1993-07-30 | Nippon Steel Corp | 電界効果トランジスタ |
US5343071A (en) * | 1993-04-28 | 1994-08-30 | Raytheon Company | Semiconductor structures having dual surface via holes |
JP2004260364A (ja) * | 2003-02-25 | 2004-09-16 | Renesas Technology Corp | 半導体装置及び高出力電力増幅装置並びにパソコンカード |
US7573097B2 (en) * | 2004-11-03 | 2009-08-11 | Agere Systems Inc. | Lateral double diffused MOS transistors |
JP5468286B2 (ja) * | 2009-04-07 | 2014-04-09 | 株式会社東芝 | 半導体装置およびその製造方法 |
US8304812B2 (en) * | 2010-02-24 | 2012-11-06 | Panasonic Corporation | Terahertz wave radiating element |
JP5712516B2 (ja) * | 2010-07-14 | 2015-05-07 | 住友電気工業株式会社 | 半導体装置 |
US8869085B2 (en) * | 2012-10-11 | 2014-10-21 | International Business Machines Corporation | Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages |
-
2012
- 2012-04-06 US US14/112,374 patent/US9166009B2/en not_active Expired - Fee Related
- 2012-04-06 JP JP2013511901A patent/JP5628416B2/ja not_active Expired - Fee Related
- 2012-04-06 WO PCT/JP2012/002417 patent/WO2012147287A1/ja active Application Filing
-
2015
- 2015-09-15 US US14/854,741 patent/US20160005847A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62252949A (ja) * | 1986-04-25 | 1987-11-04 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ−群を有する基板の検査法 |
JP2004356454A (ja) * | 2003-05-30 | 2004-12-16 | Sharp Corp | 窒化物半導体発光素子 |
JP2008518462A (ja) * | 2004-10-29 | 2008-05-29 | クリー インコーポレイテッド | トランジスタ用の非対称レイアウト構造及びその製作方法 |
JP2008124262A (ja) * | 2006-11-13 | 2008-05-29 | Oki Electric Ind Co Ltd | 選択再成長を用いたAlGaN/GaN−HEMTの製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465741A (zh) * | 2013-09-13 | 2015-03-25 | 株式会社东芝 | 半导体装置 |
US20150194517A1 (en) * | 2014-01-03 | 2015-07-09 | Globalfoundries Inc. | Gate stack and contact structure |
US9252273B2 (en) * | 2014-01-03 | 2016-02-02 | Globalfoundries Inc. | Gate stack and contact structure |
US9570615B2 (en) | 2014-01-03 | 2017-02-14 | Globalfoundries Inc. | Gate stack and contact structure |
Also Published As
Publication number | Publication date |
---|---|
JPWO2012147287A1 (ja) | 2014-07-28 |
US20160005847A1 (en) | 2016-01-07 |
US9166009B2 (en) | 2015-10-20 |
JP5628416B2 (ja) | 2014-11-19 |
US20140034971A1 (en) | 2014-02-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109155331B (zh) | 具有旁路栅极结构的晶体管 | |
JP5628416B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US9911843B2 (en) | Semiconductor device | |
KR100933277B1 (ko) | GaN계 캡 세그먼트 상에 게이트 콘택을 구비한AlGaN/GaN HEMT 및 그 제조방법 | |
JP5696083B2 (ja) | 窒化物半導体素子及びその製造方法 | |
JP6381881B2 (ja) | 高電子移動度トランジスタ及びその駆動方法 | |
JP2013004967A (ja) | エンハンスメント型iii−v族高電子移動度トランジスタ(hemt)および製造方法 | |
KR101092467B1 (ko) | 인헨스먼트 노말리 오프 질화물 반도체 소자 및 그 제조방법 | |
JP2008187173A (ja) | Iii族窒化物パワー半導体デバイス | |
JP2012028725A (ja) | エンハンスメントモードの高電子移動度トランジスタ及びその製造方法 | |
JP2009206163A (ja) | ヘテロ接合型電界効果トランジスタ | |
JPWO2020174956A1 (ja) | 窒化物半導体装置 | |
KR20150065005A (ko) | 노멀리 오프 고전자이동도 트랜지스터 | |
JP5948500B2 (ja) | ヘテロ接合電界効果トランジスタ | |
JP2013038239A (ja) | 窒化物半導体装置 | |
JP2013062494A (ja) | 窒化物半導体装置 | |
JP5553997B2 (ja) | トランジスタおよびその製造方法 | |
US11652145B2 (en) | Nitride semiconductor device comprising layered structure of active region and method for manufacturing the same | |
JP2007250727A (ja) | 電界効果トランジスタ | |
JP2013077638A (ja) | 半導体装置 | |
JP2015119028A (ja) | 半導体装置、電界効果トランジスタ、およびダイオード | |
JP2008227432A (ja) | 窒化物化合物半導体素子およびその製造方法 | |
TWI662701B (zh) | 高電子遷移率電晶體結構 | |
JP6575268B2 (ja) | 窒化物半導体装置 | |
KR102135344B1 (ko) | 질화물 반도체 소자 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12776118 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2013511901 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14112374 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12776118 Country of ref document: EP Kind code of ref document: A1 |