WO2015070528A1 - 抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 - Google Patents

抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 Download PDF

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WO2015070528A1
WO2015070528A1 PCT/CN2014/070364 CN2014070364W WO2015070528A1 WO 2015070528 A1 WO2015070528 A1 WO 2015070528A1 CN 2014070364 W CN2014070364 W CN 2014070364W WO 2015070528 A1 WO2015070528 A1 WO 2015070528A1
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source region
tunneling
source
region
insulating layer
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French (fr)
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黄如
黄芊芊
吴春蕾
王佳鑫
王超
王阳元
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Peking University
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Peking University
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
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    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
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    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
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Definitions

  • TECHNICAL FIELD The present invention relates to field effect transistor logic devices and circuits in CMOS Very Large Integrated Circuits (ULSI), and more particularly to a method of suppressing leakage current of a tunneling transistor and a corresponding device and method of fabrication.
  • ULSI Very Large Integrated Circuits
  • TFETs tunneling transistors
  • TFETs have many excellent characteristics such as low leakage current, low subthreshold slope, low operating voltage and low power consumption.
  • TFETs face the problem of small on-state current, which is extremely large. Limits the application of TFET devices.
  • the gate length is less than about 20 nm, the direct-band tunneling current from the source to the drain in the body region is drastically increased, so that the leakage current and the subthreshold slope of the TFET device are seriously degraded.
  • the TFET with ultra-thin SOI substrate can suppress this short-channel effect to a certain extent, but due to the existence of a buried silicon layer under the thin silicon film, the heat dissipation problem will become a major problem, the self-heating effect is serious, affecting device characteristics, and thin silicon
  • the film requirements also increase the process complexity of the device.
  • the tunneling transistor provided by the present invention comprises a high resistance semiconductor substrate (1), a highly doped source region (10), a low doped drain region (11), and a gate dielectric layer ( 3) and a control gate (4).
  • a tunneling junction of the tunneling transistor is formed between the highly doped source region (10) and the channel, the tunneling junction has a thickness h of 5-10 nm, and an insulating layer (7) and an insulating layer are disposed under the tunneling junction ( 7) Between the highly doped source region (10) and the high resistance semiconductor substrate (1), and having a thickness of 50-500 nm.
  • the doping source region and the doping drain region are respectively located on both sides of the control gate, and the doping types are opposite, and the doping concentration is different.
  • the source region is a highly doped P + source region with a doping concentration of 5xl0 19 ⁇ lxl0 21 cm- 3
  • the drain region is a low-doped N-drain region with a doping concentration of lxl0 18 ⁇ lxl0 19 C m - 3
  • the source region is a highly doped N + source region with a doping concentration of 5xl0 19 ⁇ lxl0 21 cm_ 3
  • the drain region is a lower doped P drain region with a doping concentration of lxl0 18 ⁇ lxl0 19 cm_ 3
  • the high-resistance semiconductor substrate is lightly doped, and the doping type and the source region are doped uniformly, and the doping concentration is less than lxl0 17 cm- 3 .
  • the method for preparing the tunneling transistor includes the following steps:
  • the thickness of the thin sidewall wall determines the distance from the source junction to the edge of the control gate, depending on the design ;
  • lithography exposes the source region, with the gate sidewall as the protective layer, anisotropically etches the source region of silicon, and the etching depth is the tunneling junction thickness h; then deposits the oxidation resistant material and lithography again Exposing the source region, anisotropically etching the oxidation resistant material to form a unilateral anti-oxidation sidewall;
  • lithography exposes the source region, using the photoresist and the control gate as a mask, and ion implantation forms a highly doped source region; then lithography exposes the drain region, using the photoresist and the control gate as a mask, the ion Injecting a low doped drain region forming another doping type, and then rapidly high temperature thermal annealing activates source and drain doping impurities;
  • the conventional CMOS subsequent process including depositing a passivation layer, opening a contact hole, and metallization, can be performed to obtain the tunneling field effect transistor, as shown in FIG.
  • the semiconductor substrate material in the step (1) is selected from the group consisting of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV binary or ternary compound semiconductors, Silicon on insulator (SOI) or germanium on insulator (GOI).
  • the gate dielectric layer material in the step (2) is selected from the group consisting of SiO 2 , Si 3 N 4 and high-k gate dielectric materials.
  • the method of growing the gate dielectric layer in the step (2) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition, and physical vapor deposition.
  • the control gate material in the step (2) is selected from the group consisting of doped polysilicon, metallic cobalt, nickel, and other metals or metal silicides.
  • the thin sidewall material in the step (3) is an oxide such as SiO 2 .
  • the oxidation resistant material in the step (4) is a material which is not easily oxidized such as Si 3 N 4 .
  • the source-drain material in the step (6) is selected from the group consisting of polycrystalline silicon, Ge, SiGe, GaAs or other binary or ternary compound semiconductors of the II-VI, III-V and IV-IV groups.
  • the method for suppressing leakage current of the tunneling transistor of the present invention is specifically: an insulating layer is disposed under the tunneling junction of the tunneling transistor, and the insulating layer is located between the source region and the body region below the channel, and the tunneling is suppressed by the insulating layer
  • the leakage current of the source and drain of the transistor directly tunnels.
  • the method of the present invention can effectively reduce the source-to-drain direct band tunneling probability of a small-sized TFET device by introducing an insulating layer under the tunneling junction, thereby suppressing tunneling transistor tunneling. Wear leakage current to obtain a lower off-state current. Moreover, the electric field edge effect of the insulating layer enables a higher electric field than the conventional TFET when the device is banded, thereby improving the subthreshold characteristics of the TFET device.
  • the tunneling transistor prepared by the method of the invention has a high doping source and a low doping drain, and the source region is doped
  • the impurity concentration is 5x l0 19 ⁇ lx l0 21 cm_ 3
  • the doping concentration of the drain region is lx l0 18 ⁇ l > ⁇ 10 19 C m_ 3
  • the doping types of the source and the drain are opposite
  • the substrate is lightly doped and doped.
  • type source region and heteroaryl uniform doping concentration is less than lx l0 17 cm_ 3.
  • the transistor conducts with a band-to-tunneling mechanism at the tunnel junction, breaking through the subthreshold slope of the MOSFET device, resulting in steeper subthreshold characteristics than conventional TFET devices and MOSFET devices.
  • the low concentration of the drain region doping can also effectively reduce the band tunneling probability at the drain junction and suppress the tunneling current at the drain junction, thereby suppressing the bipolar conduction effect of the device.
  • the semiconductor substrate of the tunneling transistor of the present invention is lightly doped and has the same doping type and source, it is a three-terminal device, and the substrate is directly drawn through the source junction, compared to the MOSFET of the four-terminal device. Can achieve smaller layout area and higher integration.
  • the tunneling transistor of the present invention can effectively solve the heat dissipation problem of the SOI structure and suppress the self-heating effect compared to the conventional SOI TFET structure.
  • the method of the present invention The method of fabricating the tunneling transistor is fully compatible with the existing CMOS process.
  • the tunneling junction thickness is determined by the etching process and can alleviate the requirements of the thin film process compared to the SOI TFET structure.
  • the final deposition of the source material layer can conveniently realize the design of the TFET heterojunction, and can accurately control the position of the TFET heterojunction.
  • Heterojunction TFETs have steeper tunneling junctions and smaller tunneling barrier widths than homojunction TFETs, thus enabling higher on-state currents and lower subthreshold slopes.
  • the method of the present invention can effectively suppress the direct tunneling leakage current of the source and drain of the TFET in a small size, and at the same time, can obtain a larger tunneling electric field and improve the subthreshold characteristics of the TFET device.
  • the tunneling transistor prepared by the method can also suppress the bipolar conduction effect of the device, has a smaller layout area and higher integration, and the preparation process is fully compatible with the existing CMOS process, and is expected to be in the field of low power consumption.
  • FIG. 1 is a schematic view showing a process step of forming a shallow trench isolation on a high resistance semiconductor substrate
  • FIG. 2 is a device after growing a gate dielectric layer and forming a control gate and a thin sidewall spacer
  • FIG. 3 is a schematic view of a device in which a thickness of silicon of h is etched in a source region and a single-sided anti-oxidation sidewall is formed
  • FIG. 4 is a process of etching the groove in which the source region is located and oxidizing the "L"-shaped insulating layer.
  • FIG. 5 is a schematic diagram of a device after leaching a source material
  • FIG. 6 is a schematic diagram of a device after lithography exposing a source region and ion implantation to form a high doping concentration source region
  • FIG. 7 is a lithography exposing a drain region and Schematic diagram of a device after ion implantation forms a drain region of a lower doping concentration of another doping type
  • Figure 8 is a schematic illustration of the completion of depositing a passivation layer, opening contact holes, and metallized tunneling transistors.
  • the active region isolation layer 2 is formed by shallow trench isolation technique.
  • the doping concentration of the substrate is lightly doped, as shown in Fig. 1.
  • a gate dielectric layer 3 the gate dielectric layer is Si0 2 , the thickness is l-5nm; depositing the gate electrode layer 4 and the gate hard mask layer 5, the gate electrode layer is doped polysilicon layer, the thickness is 150-300 nm, the hard mask layer is Si0 2 , the thickness is 100-200 nm ; the control gate pattern is lithographically etched, the gate hard mask layer 5 and the gate electrode layer 4 are etched up to the gate dielectric layer 3; deposition by LPCVD A thin layer of Si0 2 is formed to cover the gate structure to a thickness of 30 nm. Thereafter, a gate structure with a thin sidewall protection can be obtained by dry etching, as shown in FIG.
  • the lithography exposes the pattern of the source region, with the gate sidewall as the protective layer, the silicon in the source region of the anisotropic etch, the etching depth is 10 nm, and the photoresist is removed; then the Si 3 N 4 is deposited, and the thickness is 50-100 nm, once again lithographically exposing the source region, anisotropically etching the Si 3 N 4 to form a unilateral anti-oxidation spacer 6 to remove the photoresist, as shown in FIG.
  • Si 3 N 4 further anisotropically etches the silicon in the source region to form a recessed silicon trench structure with an etch depth of 20-100 nm; then oxidizes the exposed silicon to form a Si0 2 layer, ie, an insulating layer 7, the Si0 2 layer
  • the thickness is 50-100 nm, as shown in Figure 4.
  • LPCVD layer of thick polysilicon material 8 as shown in Figure 5.
  • the hard mask at the top of the gate region is used as a stop layer, chemical mechanical polishing (CMP) polysilicon, and polysilicon is over-etched to the surface of the channel to form a polysilicon source structure.
  • CMP chemical mechanical polishing
  • Photolithography exposes the source region, and P + ion implantation is performed by using the photoresist 9 and the gate region as a mask to form a highly doped source region 10, the energy of the ion implantation is 40 keV, and the impurity is BF 2 + , as shown in the figure. 6 is shown.
  • the lithography exposes the drain region, and the N ion implantation is performed by using the photoresist 9 and the gate region as a mask to form a drain region 11 with a lower concentration of doping, the energy of the ion implantation is 50 keV, and the impurity is implanted as As + , such as Figure 7 shows a rapid high temperature anneal to activate source-drain doping impurities.
  • the conventional CMOS process is performed, including depositing a passivation layer 12, opening a contact hole, and metallizing to form a metal layer 13, thereby forming the tunneling transistor, as shown in FIG.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。通过在源区（10）和隧穿结下方的体区之间插入绝缘层（7），而在源区和沟道之间的隧穿结处不插入绝缘层，从而有效抑制了小尺寸TFET器件体内的源漏直接隧穿泄漏电流，并能有效改善亚阈值斜率。相应的器件制备方法与现有的CMOS工艺完全兼容。

Description

抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 相关申请的交叉引用
本申请要求于 2013年 11月 13 日提交的中国专利申请 （201310571563.1 ) 的优 先权， 其全部内容通过引用合并于此。 技术领域 本发明属于 CMOS超大集成电路（ULSI)中的场效应晶体管逻辑器件与电路领 域， 具体涉及一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法。 背景技术
在摩尔定律的驱动下， 传统 MOSFET的特征尺寸不断缩小， 如今已经到进入纳 米尺度， 随之而来， 器件的短沟道效应等负面影响也愈加严重。 漏致势垒降低、 带带 隧穿等效应使得器件关态漏泄电流不断增大， 同时， 传统 MOSFET的亚阈值斜率受 至 IJ热电势的限制无法随着器件尺寸的缩小而同步减小， 由此增加了器件功耗。功耗问 题如今已经成为限制器件等比例缩小的最严峻的问题。 为了能将器件应用在超低压低功耗领域， 采用新型导通机制而获得超陡亚阈值 斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研 究者们提出了一种可能的解决方案， 就是采用隧穿晶体管 （TFET)。 TFET不同于传 统 MOSFET, 其源漏掺杂类型相反， 利用栅极控制反向偏置的 P-I-N结的带带隧穿实 现导通，能突破传统 MOSFET亚阈值斜率 60mV/dec的限制，并且长沟情况下其漏电 流非常小。 TFET具有低漏电流、 低亚阈值斜率、 低工作电压和低功耗等诸多优异特 性， 但由于受源结隧穿几率和隧穿面积的限制， TFET面临着开态电流小的问题， 极 大限制了 TFET器件的应用。另外一方面，对于小尺寸的 TFET,当栅长小于约 20nm， 在体区来自源到漏的直接带带隧穿电流会急剧增大，使得 TFET器件的泄漏电流和亚 阈值斜率严重退化。采用超薄体 SOI衬底的 TFET可以一定程度上抑制这种短沟效应， 但是由于薄硅膜下埋氧层的存在， 散热问题将成为主要问题， 自热效应严重， 影响器 件特性， 同时薄硅膜的要求也增加的器件的工艺复杂度。 发明内容 本发明的目的在于提出一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制 备方法。该方法通过在源区和隧穿结下方的体区之间插入绝缘层， 而在源区和沟道之 间的隧穿结处不插入绝缘层，从而有效抑制了小尺寸 TFET器件体内的源漏直接隧穿 泄漏电流， 并同时能有效改善亚阈值斜率。 相应的器件制备方法与现有的 CMOS工 艺完全兼容。 本发明的技术方案如下： 本发明提供的隧穿晶体管包括一个高阻半导体衬底（1)、一个高掺杂源区（10)、 一个低掺杂漏区（11)， 一个栅介质层（3)和一个控制栅（4)。所述高掺杂源区（10) 和沟道之间构成隧穿晶体管的隧穿结， 隧穿结的厚度 h为 5-10nm， 隧穿结下方设有 绝缘层 （7)， 绝缘层 （7)位于高掺杂源区 （10)和高阻半导体衬底 （1)之间， 且厚 度为 50-500nm。所述掺杂源区和掺杂漏区分别位于控制栅的两侧， 且掺杂类型相反， 掺杂浓度不同。 对于 N 型晶体管， 源区为高掺杂 P+源区， 掺杂浓度为 5xl019~lxl021cm-3, 漏区为低掺杂 N漏区， 掺杂浓度为 lxl018~lxl019 Cm-3。 对于 P 型晶体管， 源区为高掺杂 N+源区， 掺杂浓度为 5xl019~lxl021cm_3， 漏区为较低掺杂 P漏区， 掺杂浓度为 lxl018~lxl019cm_3。 所述高阻半导体衬底为轻掺杂， 掺杂类型和 源区掺杂一致， 掺杂浓度小于 lxl017cm— 3。 上述隧穿晶体管的制备方法， 包括以下步骤：
(1) 在高阻半导体衬底上通过浅槽隔离定义有源区； (2) 生长栅介质层， 淀积控制栅材料和硬掩膜层；
(3) 光刻和刻蚀， 形成控制栅图形， 并利用侧墙工艺， 形成器件的一层薄侧墙保护 结构， 薄侧墙的厚度决定了源结到控制栅边缘的距离， 根据设计决定；
(4) 光刻暴露出源区， 以栅侧墙为保护层， 各向异性刻蚀源区的硅， 刻蚀深度为隧 穿结的厚度 h; 然后淀积抗氧化材料， 再一次光刻暴露出源区， 各向异性刻蚀该抗氧 化材料， 形成单边抗氧化侧墙；
(5) 以抗氧化侧墙为保护， 进一步各向异性刻蚀源区的硅形成凹陷的硅槽结构； 氧 化暴露的硅， 形成绝缘层；
(6) 去掉抗氧化层， 然后淀积源材料， 过刻源材料层直到沟道表面； (7) 光刻暴露出源区， 以光刻胶和控制栅为掩膜， 离子注入形成高掺杂源区； 然后 光刻暴露出漏区， 以光刻胶和控制栅为掩膜， 离子注入形成另一种掺杂类型的低掺杂 漏区， 然后快速高温热退火激活源漏掺杂杂质；
( 8)最后进入常规 CMOS后道工序， 包括淀积钝化层、 开接触孔以及金属化， 即可 制得所述的隧穿场效应晶体管， 如图 8所示。 上述的制备方法中， 所述步骤 （1 ) 中的半导体衬底材料选自 Si、 Ge、 SiGe、 GaAs或其他 II- VI， III-V和 IV-IV族的二元或三元化合物半导体、绝缘体上的硅（ SOI) 或绝缘体上的锗 （GOI)。 上述的制备方法中， 所述步骤 （2) 中的栅介质层材料选自 Si02、 Si3N4和高 K 栅介质材料。 上述的制备方法中，所述步骤（2)中的生长栅介质层的方法选自下列方法之一： 常规热氧化、 掺氮热氧化、 化学气相淀积和物理气相淀积。 上述的制备方法中， 所述步骤 （2) 中的控制栅材料选自掺杂多晶硅、 金属钴， 镍以及其他金属或金属硅化物。 上述的制备方法中， 所述步骤 （3 ) 中的薄侧墙材料为 Si02等氧化物。 上述的制备方法中， 所述步骤 （4) 中的抗氧化材料为 Si3N4等不易被氧化的材 料。
上述的制备方法中， 所述步骤（6)中的源漏材料选自多晶硅、 Ge、 SiGe、 GaAs 或其他 II- VI， III-V和 IV-IV族的二元或三元化合物半导体。 本发明抑制隧穿晶体管泄漏电流的方法具体为， 在隧穿晶体管的的隧穿结处下 方设有绝缘层， 绝缘层位于源区和沟道下方的体区之间，利用绝缘层抑制隧穿晶体管 的源漏直接隧穿的泄漏电流。 本发明的技术效果如下： 一、本发明的方法通过在隧穿结下方引入绝缘层，可以有效地降低小尺寸 TFET 器件的源到漏的直接带带隧穿几率， 从而抑制隧穿晶体管的隧穿泄漏电流， 获得较低 的关态电流。 且绝缘层的电场集边效应使得该器件发生带带隧穿时能获得比传统 TFET更高的电场， 从而提高 TFET器件的亚阈特性。 二、 利用本发明的方法制备的隧穿晶体管具有高掺杂源和较低掺杂漏， 源区掺 杂浓度为 5x l019~l x l021cm_3，漏区掺杂浓度为 l x l018~l >< 1019 Cm_3，且源和漏的掺杂类 型相反， 衬底为轻掺杂且掺杂类型和源区一致， 掺杂浓度小于 l x l017cm_3。 该晶体管 利用隧穿结处的带带隧穿机制导通， 能突破 MOSFET器件的亚阈值斜率的限制， 获 得比常规 TFET器件和 MOSFET器件更陡直的亚阈特性。 低浓度的漏区掺杂也能有 效降低漏结处的带带隧穿几率，抑制漏结处的隧穿电流， 从而抑制器件的双极导通效 应。 另外， 由于本发明的隧穿晶体管的半导体衬底为轻掺杂， 且掺杂类型和源相同， 因此是一种三端器件， 衬底直接通过源结引出了， 相比四端器件的 MOSFET能获得 更小的版图面积和更高的集成度。 再有， 相比常规 SOI TFET结构， 本发明的隧穿晶 体管能有效解决 SOI结构的散热问题， 抑制自热效应。 三、本发明的方法相应的隧穿晶体管的制备方法与现有的 CMOS工艺完全兼容。 隧穿结厚度由刻蚀工艺决定， 相比 SOI TFET结构， 能缓解对薄膜工艺的要求。 且制 备方法中， 最后淀积源材料层可以方便地实现 TFET异质结的设计， 并且可以准确地 控制 TFET异质结所处的位置。 异质结 TFET相比同质结 TFET有更陡的隧穿结， 更 小的隧穿势垒宽度， 因此能实现更高的开态电流和更低的亚阈值斜率。 简而言之， 本发明的方法能有效地抑制小尺寸下 TFET 的源漏直接隧穿泄漏电 流， 另一方面同时也能获得了更大的隧穿电场， 提高了 TFET器件的亚阈特性。 利用 该方法制备的隧穿晶体管还能抑制器件的双极导通效应，拥有更小的版图面积和更高 的集成度， 且制备工艺与现有的 CMOS工艺完全兼容， 有望在低功耗领域得到采用， 有较高的实用价值 附图说明 图 1是在高阻半导体衬底上形成浅槽隔离的工艺步骤示意图； 图 2是生长栅介质层并形成了控制栅和薄侧墙后的器件示意图； 图 3是在源区刻蚀出 h厚度的硅后并形成单边抗氧化侧墙的器件示意图； 图 4是刻蚀出源区所在的凹槽并氧化出 "L"形绝缘层后的器件示意图； 图 5是淀积源材料后的器件示意图； 图 6是光刻暴露出源区并离子注入形成高掺杂浓度源区后的器件示意图； 图 7是光刻暴露出漏区并离子注入形成另一种掺杂类型的较低掺杂浓度的漏区 后的器件示意图； 图 8是完成淀积钝化层、 开接触孔以及金属化的隧穿晶体管的示意图。
¾中：
1 —— - 高阻半导体衬底 2 —— 有源区隔呙层
3 —— -栅介质层 4 —— -控制栅
5 —— -栅硬掩膜层 6 —— -抗氧化侧墙
7 —— -绝缘层 8 —— -源材料
9 —— -光刻胶 10 - 局掺杂源区
11 — -较低掺杂漏区 12 - ―钝化隔离层
13 —— -金属层 具体实施方式 下面通过实例对本发明做进一步说明。 需要注意的是， 公布实施例的目的在于 帮助进一步理解本发明，但是本领域的技术人员可以理解： 在不脱离本发明及所附权 利要求的精神和范围内， 各种替换和修改都是可能的。 因此， 本发明不应局限于实施 例所公开的内容， 本发明要求保护的范围以权利要求书界定的范围为准。 本发明制备方法的一具体实例包括图 1至图 8所示的工艺步骤：
1、 选取晶向为 （100) 的体硅硅片硅衬底 1上采用浅槽隔离技术制作有源区隔 离层 2， 衬底掺杂浓度为轻掺杂， 如图 1所示。
2、 然后热生长一层栅介质层 3， 栅介质层为 Si02， 厚度为 l-5nm; 淀积栅电极 层 4和栅硬掩膜层 5，栅电极层为掺杂多晶硅层，厚度为 150-300nm，硬掩膜层为 Si02， 厚度为 100-200nm; 光刻出控制栅图形， 刻蚀栅硬掩膜层 5和栅电极层 4直到栅介质 层 3 ; 用 LPCVD的方法淀积一层薄 Si02形成对栅结构的覆盖， 厚度为 30nm， 之后， 利用干法刻蚀可出带薄侧墙保护的栅结构， 如图 2所示。
3、 光刻暴露出源区图形， 以栅侧墙为保护层， 各向异性刻蚀源区的硅， 亥 lj蚀深 度为 10nm， 去除光刻胶； 然后淀积 Si3N4， 厚度为 50-100nm， 再一次光刻暴露出源 区， 各向异性刻蚀该 Si3N4， 形成单边抗氧化侧墙 6， 去除光刻胶， 如图 3所示。
4、 以 Si3N4为保护， 进一步各向异性刻蚀源区的硅形成凹陷的硅槽结构， 刻蚀 深度为 20-lOOnm; 然后氧化暴露出来的硅， 形成 Si02层， 即绝缘层 7， 该 Si02层的 厚度为 50-100nm， 如图 4所示。
5、 LPCVD一层厚的多晶硅材料 8， 如图 5所示。 以栅区顶端的硬掩膜为停止 层， 化学机械抛光 （CMP) 多晶硅， 过刻多晶硅直到沟道表面， 形成多晶硅源结构。
6、光刻暴露出源区， 以光刻胶 9和栅区为掩膜进行 P+离子注入， 形成高掺杂源 区 10， 离子注入的能量为 40keV， 注入杂质为 BF2 +， 如图 6所示。
7、光刻暴露出漏区， 以光刻胶 9和栅区为掩膜进行 N离子注入， 形成较低浓度 掺杂的漏区 11， 离子注入的能量为 50keV， 注入杂质为 As+， 如图 7所示； 进行一次 快速高温退火， 激活源漏掺杂的杂质。
8、 最后进入常规 CMOS后道工序， 包括淀积钝化层 12、 开接触孔以及金属化 形成金属层 13， 即可制得所述的隧穿晶体管， 如图 8所示。 虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。 任何熟悉本 领域的技术人员，在不脱离本发明技术方案范围情况下， 都可利用上述揭示的方法和 技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实 施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发明的技术实质对以上实施 例所做的任何简单修改、 等同变化及修饰， 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求
1. 一种隧穿晶体管， 包括一个高阻半导体衬底（1)、一个高掺杂源区（10)、 一个低掺杂漏区 （11)， 一个栅介质层 （3)和一个控制栅 （4)， 所述高掺杂源区
(10) 和沟道之间构成隧穿晶体管的隧穿结， 隧穿结的厚度 h为 5-10nm， 其特 征在于， 隧穿结下方设有绝缘层 （7)， 绝缘层 （7) 位于高掺杂源区 （10) 和高 阻半导体衬底（1)之间， 绝缘层（7)的厚度为 50-500nm， 所述高掺杂源区（10) 和低掺杂漏区 （11) 掺杂类型相反， 对于 N型晶体管， 高掺杂 P+源区的掺杂浓 度为 5xl019~lxl021cm_3，低掺杂 N漏区的掺杂浓度为 lxl018~l><1019 Cm_3 ;对于 P 型晶体管， 高掺杂 N+源区的掺杂浓度为 5xl019~lxl021cm_3， 低掺杂 P漏区的掺 杂浓度为 lxl018~lxl019cm-3。
2. 如权利要求 1所述的隧穿晶体管，其特征在于，所述高阻半导体衬底（1) 为轻掺杂， 掺杂类型和高掺杂源区 （10) 掺杂一致， 掺杂浓度小于 lxl017cm— 3。 3. 一种抑制隧穿晶体管泄漏电流的方法， 隧穿晶体管的源区和沟道的界面 处为隧穿结， 其特征在于， 隧穿结下方设有绝缘层， 绝缘层位于高掺杂源区和高 阻半导体衬底之间， 绝缘层的厚度为 50-500nm， 利用该绝缘层抑制隧穿晶体管 的源漏直接隧穿的泄漏电流。 4. 制备如权利要求 1所述的隧穿晶体管的方法， 包括以下步骤：
(1) 在高阻半导体衬底上通过浅槽隔离定义有源区；
(2) 生长栅介质层， 淀积控制栅材料和硬掩膜层；
(3) 光刻和刻蚀， 形成控制栅图形， 并利用侧墙工艺， 形成器件的一层薄 侧墙保护结构， 薄侧墙的厚度决定了源结到控制栅边缘的距离；
(4) 光刻暴露出源区， 以栅侧墙为保护层， 各向异性刻蚀源区的硅， 刻蚀 深度为隧穿结的厚度 h; 然后淀积抗氧化材料， 再一次光刻暴露出源区， 各向异 性刻蚀该抗氧化材料， 形成单边抗氧化侧墙；
(5) 以抗氧化侧墙为保护， 进一步各向异性刻蚀源区的硅形成凹陷的硅槽 结构； 氧化暴露的硅， 形成绝缘层；
(6) 去掉抗氧化层， 然后淀积源材料， 过刻源材料层直到沟道表面；
(7) 光刻暴露出源区， 以光刻胶和控制栅为掩膜， 离子注入形成高掺杂源 区； 然后光刻暴露出漏区， 以光刻胶和控制栅为掩膜， 离子注入形成另一种掺杂 类型的较低掺杂漏区， 然后快速退火激活源漏掺杂杂质；
( 8)最后进入 CMOS后道工序，即可制得如权利要求 1所述的隧穿晶体管。 5. 如权利要求 4所述的制备方法， 其特征在于， 所述步骤 （1 ) 中的半导体 衬底材料选自 Si、 Ge、 SiGe、 GaAs或其他 II- VI， III-V和 IV-IV族的二元或三 元化合物半导体、 绝缘体上的硅或绝缘体上的锗。
6. 如权利要求 4所述的制备方法， 其特征在于， 所述步骤 （2) 中的栅介质 层材料选自 Si02、 Si3N4和高 K栅介质材料。
7. 如权利要求 4所述的制备方法， 其特征在于， 所述步骤 （2) 中的控制栅 材料选自掺杂多晶硅、 金属钴， 镍以及其他金属或金属硅化物。 8. 如权利要求 4所述的制备方法， 其特征在于， 所述步骤 （6) 中的源漏材 料选自多晶硅、 Ge、 SiGe、 GaAs或其他 II- VI， III-V和 IV-IV族的二元或三元 化合物半导体。
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