WO2015058582A1 - Amoled像素驱动电路及其驱动方法、阵列基板 - Google Patents

Amoled像素驱动电路及其驱动方法、阵列基板 Download PDF

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Publication number
WO2015058582A1
WO2015058582A1 PCT/CN2014/084998 CN2014084998W WO2015058582A1 WO 2015058582 A1 WO2015058582 A1 WO 2015058582A1 CN 2014084998 W CN2014084998 W CN 2014084998W WO 2015058582 A1 WO2015058582 A1 WO 2015058582A1
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Prior art keywords
thin film
film transistor
driving
gate
source
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PCT/CN2014/084998
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English (en)
French (fr)
Inventor
谭文
祁小敬
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US14/436,268 priority Critical patent/US9489893B2/en
Publication of WO2015058582A1 publication Critical patent/WO2015058582A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes

Definitions

  • FIG. 1(a) shows an AMOLED pixel driving circuit composed of an N-type thin film transistor (TFT), including: T1, ⁇ 2 two ⁇ -type TFTs, and a light-emitting diode Dl And the storage capacitor C1;
  • TFT N-type thin film transistor
  • FIG. 1(b) shows an AMOLED pixel driving circuit composed of a P-type TFT, comprising: T1, ⁇ 2 two ⁇ -type TFTs, a light-emitting diode D1 and a storage capacitor C1.
  • the above circuit is suitable for all types of transistors, including depletion mode TFTs.
  • the pixel driving circuit does not have a threshold voltage compensation function, and cannot solve the problem of non-uniformity of the threshold voltage due to process non-uniformity and the non-uniformity of the organic light emitting diode (OLED) driving.
  • Oxide TFTs are the development direction of large-size AMOLEDs. Since the oxide TFT has a depletion type characteristic, the N-type threshold voltage is negative.
  • the depletion mode TFT uses the conventional N-type TFT AMOLED pixel drive circuit design. When the diode connection is used to compensate the threshold voltage, since the threshold voltage is negative, the source-drain voltage is before the TFT enters the sub-saturation saturation cutoff. Zero and early cutoff, thus losing the wide value voltage compensation function.
  • an AMOLED pixel driving circuit, a driving method thereof, and an array substrate are provided, which can realize a sub-wide saturation cutoff and compensate for the purpose of driving a TFT threshold voltage.
  • An embodiment of the present disclosure provides an AMOLED pixel driving circuit, including: a driving thin film transistor, a storage capacitor, and an organic light emitting diode, wherein the method further includes:
  • a gate initial voltage writing module configured to write an initial voltage signal to a gate of the driving thin film transistor, a first end of the storage capacitor, and a second end of the coupling capacitor;
  • a data voltage writing module for writing a data voltage signal to a source of the driving thin film transistor
  • An initialization module configured to initialize a source voltage of the driving thin film transistor
  • a light emission control module configured to control a connection between one end of the organic light emitting diode and a drain of the driving thin film transistor
  • the gate initial voltage writing module includes a second thin film transistor, a source of the second thin film transistor and a first end of the storage capacitor, a second end of the combined capacitor, and the The gate of the driving thin film transistor is connected, the gate of the second thin film transistor is connected to a row of gate signals, and the drain of the second thin film transistor is connected to the initial voltage signal terminal.
  • the data voltage writing module includes a third thin film transistor, a gate of the third thin film transistor is connected to the gate signal of the current row, and a drain of the third thin film transistor is connected to a source of the driving thin film transistor, The source of the three thin film transistor is connected to the data voltage signal terminal.
  • the saturated discharge module includes a fourth thin film transistor, a drain of the fourth thin film transistor is connected to a first end of the combined capacitor, a gate of the fourth thin film transistor and a first control signal A line is connected, and a source of the fourth thin film transistor is connected to a drain of the driving thin film transistor.
  • the initialization module includes a fifth thin film transistor, a source of the fifth thin film transistor is connected to a source of the driving thin film transistor, and a gate of the fifth thin film transistor is connected to a second control signal line.
  • the drain of the fifth thin film transistor and the second end of the storage capacitor are connected in common to the second power source.
  • the illuminating control module includes a sixth thin film transistor, a source of the sixth thin film transistor is connected to a drain of the driving thin film transistor, and a gate of the sixth thin film transistor is connected to a second control signal.
  • the drain of the sixth thin film transistor is connected to the one end of the organic light emitting diode, and the other end of the organic light emitting diode is connected to the first power source.
  • the driving thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are depleted N-type Thin film transistor.
  • the initial voltage signal is a data voltage signal.
  • an array substrate including the pixel driving circuit.
  • a driving method of an AMOLED pixel driving circuit is further provided in an embodiment of the present disclosure,
  • the pixel driving circuit includes: a driving thin film transistor, a gate initial voltage writing module, a data voltage writing module, a saturation discharging module, an initialization module, an emission control module, a storage capacitor, a coupling capacitor, and an organic light emitting diode; and the driving method includes:
  • the gate initial voltage writing module Writing, by the gate initial voltage writing module, an initial voltage signal to a gate of the driving thin film transistor, a first end of the storage capacitor, and a second end of the coupling capacitor; and the data voltage signal terminal is written by the data voltage writing module Disconnecting from a source of the driving thin film transistor; connecting, by the initialization module, a source of the driving transistor to a second power source; charging a second end of the storage capacitor by a second power source;
  • the control module communicates one end of the organic light emitting diode with the drain of the driving thin film transistor; the first end of the combined capacitor is connected to the drain of the driving thin film transistor by the saturated discharge module; a power source charges the first end of the combined capacitor through the organic light emitting diode;
  • the signal end is connected to the source of the driving thin film transistor, and writes a data voltage signal to the source of the driving thin film transistor; the source of the driving thin film transistor is disconnected from the second power source by the initialization module;
  • the light emission control module disconnects the one end of the organic light emitting diode from the drain of the driving thin film transistor; the first end of the combined capacitor and the driving thin film transistor are a drain connection; the storage capacitor and the coupling capacitor are discharged through the driving thin film transistor;
  • the signal end is disconnected from the source of the driving thin film transistor; the source of the driving thin film transistor is connected to the second power source by the initialization module; the one end of the organic light emitting diode is used by the light emitting control module Communicating with a drain of the driving thin film transistor; disconnecting a first end of the combined capacitor from a drain of the driving thin film transistor by the saturated discharge module; the driving transistor is provided for the organic light emitting diode Drive current.
  • the gate initial voltage writing module may include a second thin film transistor; the data voltage writing module may include a third thin film transistor; the saturated discharge module may include a fourth thin film
  • the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor and the sixth thin film transistor are turned on, the third thin film transistor is turned off; the initial voltage signal is written into the gate of the driving thin film transistor, and the storage capacitor is One end, the second end of the coupling capacitor; the second power source charges the second end of the storage capacitor; the first power source charges the first end of the combined capacitor;
  • the third thin film transistor and the fourth thin film transistor are turned on, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off; a data voltage signal is written to a source of the driving thin film transistor; the storage capacitor and the coupling The capacitor is discharged through the driving transistor;
  • the AMOLED pixel driving circuit and the driving method thereof, the array substrate, and the pixel driving circuit provided in the embodiment of the present disclosure include: a driving thin film transistor, a gate initial voltage writing module, a data voltage writing module, a saturation discharging module, an initialization module, a light-emitting control module, a storage capacitor, a coupling capacitor, an organic light-emitting diode; a gate initial voltage writing module for writing an initial voltage signal to a gate of the driving thin film transistor, a first end of the storage capacitor, and a second end of the coupling capacitor;
  • the writing module is configured to write the data voltage signal to the source of the driving thin film transistor;
  • the initialization module is configured to connect or disconnect the source of the driving thin film transistor with the second power source;
  • the light emitting control module is configured to connect one end of the organic light emitting diode with The drain of the driving thin film transistor is connected or disconnected;
  • the saturated discharge module is configured to connect or disconnect the first end of the coupling capacitor to the drain
  • FIG. 1 is a basic pixel driving circuit structure of a conventional AMOLED; 2 is a graph showing Ids-Vgs characteristics of an N-type depleted TFT;
  • Figure 3 (a) is a schematic diagram of a known AMOLED pixel driving circuit structure with wide voltage compensation
  • Figure 3 (b) is a schematic diagram of the threshold voltage compensation principle of the driving TFT shown in Figure 3 (a);
  • Figure 4 (a) is a schematic diagram of the threshold voltage of the circuit-enhanced TFT shown in Figure 3 (a);
  • Figure 4 (b) is a schematic diagram of a threshold voltage compensation circuit of the circuit depletion TFT shown in FIG. 3 (a);
  • FIG. 5 is a structural diagram of an AMOLED pixel driving circuit of the depletion TFT of the first embodiment of the present disclosure;
  • FIG. 6 is a structural diagram of an AMOLED pixel driving circuit of a depletion TFT of a second embodiment of the present disclosure
  • FIG. 7 is an operation timing diagram of an AMOELD pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 8(a) is a working principle diagram of an AMOELD pixel driving circuit in an initialization stage according to an embodiment of the present disclosure
  • FIG. 8(b) is a schematic diagram showing the operation of the AMOELD pixel driving circuit in the threshold voltage compensation and data voltage writing stages according to an embodiment of the present disclosure
  • FIG. 8( c ) is a schematic diagram showing the operation of the AMOELD pixel driving circuit in the OLED lighting stage according to an embodiment of the present disclosure.
  • DETAILED DESCRIPTION OF THE INVENTION Currently, devices of oxide TFTs are mostly characterized by a depletion type. 2 is a graph showing the Ids-Vgs characteristic of an N-type depleted TFT. It can be seen from Fig. 2 that the most characteristic feature of the N-type depletion TFT is that the threshold voltage V TH is less than 0, the abscissa is the voltage, and the ordinate is the current.
  • FIG. 3(a) is a schematic structural diagram of a known AMOLED pixel driving circuit with threshold voltage compensation.
  • Fig. 3(b) is a schematic diagram showing the principle of the threshold voltage compensation of the driving TFT shown in Fig. 3(a).
  • T5 and T6 are turned off, and the connection of the driving TFT T1 to the high level V DD and the low level V ss is cut off, and one end of the storage capacitor C1 is connected to the gate of the driving TFT T1.
  • T2 is turned on, T3 and T4 are turned off, that is, the gate of T1 is charged to the initial voltage signal VINI; then, T2 is turned off, ⁇ 3 and ⁇ 4 are turned on, and the gate and drain of the driving TFT T1 are connected to form a diode connection.
  • Discharge that is, the voltage across the storage capacitor C1 (ie, the gate source of T1) The voltage is discharged to the sub-wide conduction state V DATA + V TH of the driving TFT T1, where V DATA is a data voltage signal.
  • the threshold voltage is positive.
  • the voltage across the storage capacitor C1 ie, the gate-source voltage of T1 can be normally discharged to V DATA + V TH .
  • the threshold voltage V TH is negative, as shown in FIG. 4 (b), when the voltage across the storage capacitor C1 is discharged through the diode-connected driving TFT T1, the source of the driving TFT T1 is driven.
  • the pixel driving circuit loses the threshold voltage compensation function.
  • the basic idea of the embodiment of the present disclosure is to provide a coupling capacitor between the discharge node and the gate of the driving TFT T1, change the pre-charging mode, charge the discharging node to a high level V DD , and drive the TFT T1 gate to charge to V DATA .
  • V INI during the discharge of the discharge node, the gate voltage of the driving TFT T1 is simultaneously reduced by the coupling capacitor, so as to drive the source voltage of the TFT T1, thereby achieving the sub-saturation saturation cutoff, and the threshold voltage of the driving TFT T1 is obtained. make up.
  • G N ⁇ is the gate signal of the previous row
  • G N is the Gate signal of the row
  • S1 is the first control signal
  • S2 is the second control signal
  • V DD is the first power supply
  • V ss is the first Two power supplies.
  • the discharge node of the embodiment of the present disclosure is the point P in FIG.
  • the source of the thin film transistor T2 and the first end of the storage capacitor C1, the coupling capacitor C2 And a gate terminal of a second driving thin film transistor T1 is connected to the gate of the thin film transistor T2 connected to the gate signal line G N, the initial voltage of the drain signal terminal connected to the thin film transistor T2 is connected.
  • the initial voltage signal terminal in the first embodiment of the present disclosure is the data voltage signal terminal V DATA .
  • the gate of the thin film transistor T3 is connected to the gate signal G N of the row, the drain of T3 is connected to the source of the driving thin film transistor T1, and the source of the T3 is connected to the data voltage signal terminal V DATA .
  • the drain of the thin film transistor T4 is connected to the first end of the coupling capacitor C2, the gate of T4 is connected to the first control signal line S1, and the source of T4 is connected to the drain of the driving thin film transistor T1.
  • the source of the thin film transistor T5 is connected to the source of the driving thin film transistor T1, the gate of T5 is connected to the second control signal line S2, and the drain of T5 and the second end of the storage capacitor C1 are commonly connected to the second power thin film transistor T6.
  • the source is connected to the drain of the driving thin film transistor T1, the gate of T6 is connected to the second control signal S2; the drain of T6 is connected to one end of the organic light emitting diode D1, and the other end of the organic light emitting diode D1 is connected to the first power source V DD connection.
  • FIG. 6 is a structural diagram of an AMOLED pixel driving circuit of a depletion TFT according to a second embodiment of the present disclosure. As shown in FIG. 6, the circuit includes: a driving thin film transistor T1, a gate initial voltage writing module, a data voltage writing module, a saturation discharging module, an initialization module, and an emission control module.
  • the gate initial voltage writing module includes a second thin film transistor T2, ⁇ 2 is a gate initial voltage writing TFT, the data voltage writing module includes a third thin film transistor ⁇ 3, and ⁇ 3 is a data voltage writing TFT, saturated
  • the discharge module includes a fourth thin film transistor T4, ⁇ 4 is a saturated discharge TFT, the initialization module includes a fifth thin film transistor T5, ⁇ 5 is an initialization TFT, and the illumination control module includes a sixth thin film transistor T6, and the ⁇ 6 is a light emission control TFT.
  • the driving thin film transistor T1 and the thin film transistor T2 T6 are N-type TFTs having depletion characteristics.
  • the circuit further includes a storage capacitor C1, a coupling capacitor C2, and an organic light emitting diode D1.
  • the embodiment of the present disclosure further provides a driving method of an AMOLED pixel driving circuit
  • the pixel driving circuit includes: a driving thin film transistor, a gate initial voltage writing module, a data voltage writing module, a saturated discharge module, an initialization module, an illumination control module, Storage capacitor, coupling capacitor, organic light emitting diode;
  • the driving method includes the following work process: In the initialization phase:
  • the initial voltage signal terminal is disconnected from the gate of the driving thin film transistor T1, the first end of the storage capacitor C1, and the second end of the coupling capacitor C2 by the gate initial voltage writing module;
  • the data voltage signal terminal is connected by the data voltage writing module electrode driving thin film transistor T1 communication source, the voltage of the data write driver thin film transistor T1 signal source; by the initialization module of the driving thin film transistor T1 and the second power source V ss OFF; by the light-emitting organic light emitting control module
  • One end of the diode D1 is disconnected from the drain of the driving thin film transistor T1;
  • the first end of the coupling capacitor C2 is connected to the drain of the driving thin film transistor T1 by the saturated discharge module;
  • the storage capacitor C1 and the coupling capacitor C2 are discharged through the driving thin film transistor T1 In the lighting phase:
  • the initial voltage signal terminal is disconnected from the gate of the driving thin film transistor T1, the first end of the storage capacitor C1, and the second end of the coupling capacitor C2 by the gate initial voltage writing module; the data voltage signal terminal is connected by the data voltage writing module
  • the source of the driving thin film transistor T1 is disconnected; the source of the driving thin film transistor T1 is connected to the second power source V ss by the initialization module; one end of the organic light emitting diode D1 is connected to the drain of the driving thin film transistor T1 by the light emitting control module;
  • the first end of the coupling capacitor C2 is disconnected from the drain of the driving thin film transistor Ti by the saturated discharge module; the driving transistor supplies a driving current to the organic light emitting diode D1.
  • the gate initial voltage writing module may include a second thin film transistor; the data voltage writing module may include a third thin film transistor; the saturated discharge module may include a fourth thin film transistor; the initialization module may include a fifth thin film transistor; A sixth thin film transistor may be included.
  • the above driving method works as follows:
  • the third thin film transistor and the fourth thin film transistor are turned on, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off; the data voltage signal is written to the source of the driving thin film transistor T1; the storage capacitor and the coupling capacitor are driven The thin film transistor T1 is discharged;
  • FIG. 7 is an operation timing diagram of an AMOELD pixel driving circuit according to an embodiment of the present disclosure, wherein a is an initialization phase, and b is a threshold voltage compensation and data voltage writing phase, and c is an illumination phase.
  • G N-1 , SI and S2 are high level, G N is low level, DATA is data voltage V DATA , and the initial voltage signal is V
  • DATA is VSS ⁇ V D ATA ⁇ V DD , T2, ⁇ 4, ⁇ 5, and ⁇ 6 are turned on, and ⁇ 3 is turned off.
  • the first end of the gate of the storage capacitor C1 connected to T1 is charged to V DATA , and the second end is charged to V SS , then the voltage difference between the storage capacitor C1 is V DATA - V SS , and the first end of the coupling capacitor C2 is V DD , the second terminal is V DATA , the voltage difference between the coupling capacitor C2 is V DD -VDATAO in the threshold voltage compensation and data voltage writing phase b: as shown in Figure 8 (b), G ⁇ o S2 is low Level, S1 and G N are high level, DATA is data voltage V DATA , taking the initial voltage signal as V DATA as an example, V SS ⁇ V DATA ⁇ V DD , T3 and T4 are on, T2, ⁇ 5 and ⁇ 6 are off .
  • the voltage initially stored on C1 and C2 is discharged through T1, that is, from the high level V DD through the discharge T1 drain, and the gate of T1 also drops from V DATA due to the coupling of C2.
  • the voltage change at the T1 gate is [C2/(C1+C2)]*AV.
  • the level of the first end of the storage capacitor C1 connected to the gate of T1 is V DATA + V TH
  • the second terminal level is V ss , that is, the voltage difference between the two ends of the storage capacitor CI is V DATA -V SS +V TH .
  • the leakage current of Tl is independent of the threshold voltage, which can compensate the T1 threshold voltage.
  • k is a current coefficient of the thin film transistor.
  • Tl threshold voltage is similar to the case where the initial voltage signal is V DATA .
  • An embodiment of the present disclosure further provides an array substrate, including: a plurality of data lines arranged along a column, a plurality of first scan lines, second scan lines, and signal control lines extending along a row, arranged in a matrix form A plurality of pixels at a position where the data line and the scan line intersect; the pixel includes the pixel drive circuit described above.
  • Embodiments of the present disclosure also provide a display panel including the array substrate described above.
  • Embodiments of the present disclosure also provide a display device including the display panel described above.
  • the display device may be a display device such as an electronic paper, a mobile phone, or a digital photo frame.

Abstract

一种AMOLED像素驱动电路及其驱动方法、阵列基板，其中，AMOLED像素驱动电路包括：驱动薄膜晶体管（T1）；将初始电压信号写入驱动薄膜晶体管（T1）的栅极、存储电容（C1）第一端、耦合电容（C2）第二端的栅极初始电压写入模块（T2）；将数据电压信号写入驱动薄膜晶体管（T1）的源极的数据电压写入模块（T3）；将耦合电容（C2）的第一端与驱动薄膜晶体管（T1）的漏极连通或断开的饱和放电模块（T4）；将驱动薄膜晶体管（T1）的源极与第二电源（Vss）连通或断开的初始化模块（T5）；将有机发光二极管（D1）的一端与驱动薄膜晶体管（T1）的漏极连通或断开的发光控制模块（T6）；存储电容（C1）；耦合电容（C2）；和有机发光二极管（D1）。该AMOLED像素驱动电路及其驱动方法可实现亚阈饱和截止，补偿驱动薄膜晶体管（T1）阈值电压的目的。

Description

AMOLED像素驱动电路及其驱动方法、 阵列基板 技术领域 本公开涉及一种有源矩阵有机发光二极体（Active Matrix Organic Light Emitting Diode, AMOLED )像素驱动电路及其驱动方法、 阵列基板。 背景技术 传统 AMOLED的基本像素驱动电路结构如图 1所示， 图 1 ( a )表示 N 型薄膜晶体管 （TFT )构成的 AMOLED像素驱动电路， 包括： Tl、 Τ2两个 Ν型 TFT， 发光二极管 Dl和存储电容 C1 ; 图 1 ( b )表示 P型 TFT构成的 AMOLED像素驱动电路， 包括： Tl、 Τ2两个 Ρ型 TFT， 发光二极管 D1和 存储电容 Cl。 上述电路适用于所有类型的晶体管， 包括耗尽型 TFT。 但该像 素驱动电路不具有阔值电压补偿功能， 不能解决由于工艺非均匀性导致的阔 值电压的非均匀性和有机发光二极管 （OLED )驱动发光非均匀性的问题。
氧化物 TFT是大尺寸 AMOLED的发展方向。 由于氧化物 TFT具有耗尽 型的特点，即 N型阔值电压为负。耗尽型 TFT釆用传统 N型 TFT的 AMOLED 像素驱动电路设计， 在釆用二极管连接方式补偿阔值电压时， 由于阔值电压 为负值， 在 TFT进入亚阔饱和截止之前， 源漏电压为零而提前截止， 从而失 去阔值电压补偿功能。 发明内容 有鉴于此， 在此提供一种 AMOLED像素驱动电路及其驱动方法、 阵列 基板， 可实现亚阔饱和截止， 补偿驱动 TFT阔值电压的目的。
本公开的实施例提供了一种 AMOLED像素驱动电路， 包括： 驱动薄膜 晶体管、 存储电容、 有机发光二极管， 其中还包括：
与所述存储电容的第一端连接的耦合电容；
栅极初始电压写入模块， 用于将初始电压信号写入所述驱动薄膜晶体管 的栅极、 存储电容的第一端、 耦合电容的第二端；
数据电压写入模块， 用于将数据电压信号写入所述驱动薄膜晶体管的源 极；
初始化模块， 用于初始化所述驱动薄膜晶体管的源极电压；
发光控制模块， 用于控制所述有机发光二极管的一端与所述驱动薄膜晶 体管漏极的连接；
饱和放电模块， 连接在所述辆合电容的第一端与所述驱动薄膜晶体管的 漏极之间。
示例性地， 所述栅极初始电压写入模块包括第二薄膜晶体管， 所述第二 薄膜晶体管的源极与所述存储电容的第一端、 所述辆合电容的第二端以及所 述驱动薄膜晶体管的栅极相连， 第二薄膜晶体管的栅极接上一行栅极信号， 所述第二薄膜晶体管的漏极与初始电压信号端连接。
示例性地， 所述数据电压写入模块包括第三薄膜晶体管， 第三薄膜晶体 管的栅极连接本行栅极信号， 第三薄膜晶体管的漏极与所述驱动薄膜晶体管 的源极连接， 第三薄膜晶体管的源极与数据电压信号端连接。
示例性地， 所述饱和放电模块包括第四薄膜晶体管， 所述第四薄膜晶体 管的漏极与所述辆合电容的第一端相连， 所述第四薄膜晶体管的栅极与第一 控制信号线连接， 所述第四薄膜晶体管的源极与所述驱动薄膜晶体管的漏极 连接。
示例性地， 所述初始化模块包括第五薄膜晶体管， 所述第五薄膜晶体管 的源极与所述驱动薄膜晶体管的源极连接， 所述第五薄膜晶体管的栅极与第 二控制信号线连接， 所述第五薄膜晶体管的漏极和所述存储电容的第二端共 同连接第二电源。
示例性地， 所述发光控制模块包括第六薄膜晶体管， 所述第六薄膜晶体 管的源极与所述驱动薄膜晶体管的漏极连接， 所述第六薄膜晶体管的栅极与 第二控制信号连接； 所述第六薄膜晶体管的漏极与所述有机发光二极管的所 述一端连接， 所述有机发光二极管的另一端与第一电源连接。
可替换地， 所述驱动薄膜晶体管、 所述第二薄膜晶体管、 所述第三薄膜 晶体管、 所述第四薄膜晶体管、 所述第五薄膜晶体管、 所述第六薄膜晶体管 为耗尽型 N型薄膜晶体管。
可替换地， 所述初始电压信号为数据电压信号。
在本公开的实施例中还提供了一种阵列基板， 包括所述的像素驱动电路。 在本公开的实施例中还提供了 AMOLED像素驱动电路的驱动方法， 该 像素驱动电路包括： 驱动薄膜晶体管、 栅极初始电压写入模块、 数据电压写 入模块、 饱和放电模块、 初始化模块、 发光控制模块、 存储电容、 耦合电容、 有机发光二极管； 所述驱动方法包括：
在初始化阶段：
由所述栅极初始电压写入模块将初始电压信号写入所述驱动薄膜晶体管 的栅极、 存储电容第一端、 耦合电容第二端； 由所述数据电压写入模块将数 据电压信号端与所述驱动薄膜晶体管的源极断开； 由所述初始化模块将所述 驱动晶体管的源极与第二电源连通； 由第二电源对所述存储电容的第二端充 电； 由所述发光控制模块将所述有机发光二极管的一端与所述驱动薄膜晶体 管的漏极连通； 由所述饱和放电模块将所述辆合电容的第一端与所述驱动薄 膜晶体管的漏极连通； 由第一电源通过所述有机发光二极管对所述辆合电容 的第一端充电；
在阔值电压补偿和数据电压写入阶段：
由所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管 的栅极、 存储电容第一端、 耦合电容第二端断开； 由所述数据电压写入模块 将数据电压信号端与所述驱动薄膜晶体管的源极连通， 将数据电压信号写入 所述驱动薄膜晶体管的源极； 由所述初始化模块将所述驱动薄膜晶体管的源 极与第二电源断开； 由所述发光控制模块将所述有机发光二极管的所述一端 与所述驱动薄膜晶体管的漏极断开； 由所述饱和放电模块将所述辆合电容的 第一端与所述驱动薄膜晶体管的漏极连通； 所述存储电容和耦合电容通过所 述驱动薄膜晶体管放电；
在发光阶段：
由所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管 的栅极、 存储电容第一端、 耦合电容第二端断开； 由所述数据电压写入模块 将数据电压信号端与所述驱动薄膜晶体管的源极断开； 由所述初始化模块将 所述驱动薄膜晶体管的源极与第二电源连通； 由所述发光控制模块将所述有 机发光二极管的所述一端与所述驱动薄膜晶体管的漏极连通； 由所述饱和放 电模块将所述辆合电容的第一端与所述驱动薄膜晶体管的漏极断开； 所述驱 动晶体管为所述有机发光二极管提供驱动电流。
示例性地， 所述栅极初始电压写入模块可包括第二薄膜晶体管； 所述数 据电压写入模块可包括第三薄膜晶体管； 所述饱和放电模块可包括第四薄膜 晶体管； 所述初始化模块可包括第五薄膜晶体管； 所述发光控制模块可包括 第六薄膜晶体管； 所述驱动方法包括：
在初始化阶段：
所述第二薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体管和第六薄膜晶 体管导通， 所述第三薄膜晶体管截止； 将初始电压信号写入所述驱动薄膜晶 体管的栅极、 存储电容第一端、 耦合电容第二端； 第二电源对所述存储电容 的第二端充电； 第一电源对所述辆合电容的第一端充电；
在阔值电压补偿和数据电压写入阶段：
第三薄膜晶体管和第四薄膜晶体管导通， 第二薄膜晶体管、 第五薄膜晶 体管和第六薄膜晶体管截止； 将数据电压信号写入到所述驱动薄膜晶体管的 源极； 所述存储电容和耦合电容通过所述驱动晶体管放电；
发光阶段：
第五薄膜晶体管和第六薄膜晶体管导通， 第二薄膜晶体管、 第三薄膜晶 体管和第四薄膜晶体管截止； 所述驱动薄膜晶体管为所述发光二极管提供驱 动电流。
本公开实施例中提供的 AMOLED像素驱动电路及其驱动方法、 阵列基 板， 像素驱动电路， 包括： 驱动薄膜晶体管、 栅极初始电压写入模块、 数据 电压写入模块、 饱和放电模块、 初始化模块、 发光控制模块、 存储电容、 耦 合电容、 有机发光二极管； 栅极初始电压写入模块用于将初始电压信号写入 驱动薄膜晶体管的栅极、 存储电容第一端、 耦合电容第二端； 数据电压写入 模块用于将数据电压信号写入驱动薄膜晶体管的源极； 初始化模块用于将驱 动薄膜晶体管的源极与第二电源连通或断开； 发光控制模块用于将有机发光 二极管的一端与驱动薄膜晶体管的漏极连通或断开； 饱和放电模块用于将耦 合电容的第一端与驱动晶体管的漏极连通或断开。 本公开实施例通过在放电 节点和驱动 TFT的栅极之间设置一个耦合电容， 改变预充电方式， 将放电节 点充电至高电平 VDD， 驱动 TFT栅极充电至 VDATA或 VINI， 放电节点放电过 程中通过辆合电容同时降低驱动 TFT栅极电压，使其低于驱动 TFT源级电压， 从而实现亚阔饱和截止， 驱动 TFT的阔值电压得到补偿。 附图说明 图 1为传统 AMOLED的基本像素驱动电路结构; 图 2为 N型耗尽 TFT的 Ids-Vgs特性曲线图；
图 3 (a) 为已知的具有阔值电压补偿的 AMOLED像素驱动电路结构示 意图；
图 3 (b) 为图 3 (a)所示驱动 TFT的阔值电压补偿原理示意图； 图 4 (a) 为图 3 (a)所示电路增强型 TFT的阔值电压示意图； 图 4 (b) 为图 3 (a) 所示电路耗尽型 TFT的阔值电压补偿失效示意图； 图 5为本公开第一实施例的耗尽型 TFT的 AMOLED像素驱动电路结构 图；
图 6为本公开第二实施例的耗尽型 TFT的 AMOLED像素驱动电路结构 图；
图 7为本公开实施例的 AMOELD像素驱动电路的工作时序图； 图 8 (a) 为本公开实施例的 AMOELD像素驱动电路在初始化阶段的工 作原理图；
图 8 (b) 为本公开实施例的 AMOELD像素驱动电路在阔值电压补偿和 数据电压写入阶段的工作原理图；
图 8 ( c ) 为本公开实施例的 AMOELD像素驱动电路在 OLED发光阶段 的工作原理图。 具体实施方式 目前， 氧化物 TFT的器件大都具有耗尽型的特点。 图 2为 N型耗尽 TFT 的 Ids-Vgs特性曲线图。 由图 2可以看出 N型耗尽 TFT的最大特点是阔值电 压 VTH小于 0， 横坐标为电压， 纵坐标为电流。
下面首先对已知的具有阔值电压补偿的 AMOLED像素驱动电路进行简 单介绍。
图 3 (a) 为一种已知的具有阔值电压补偿的 AMOLED像素驱动电路结 构示意图。 图 3 (b) 为图 3 (a)所示的驱动 TFT的阔值电压补偿原理示意 图。 在电压编程阶段， 如图 3 (b)所示， 首先 T5和 T6截止， 切断驱动 TFT T1与高电平 VDD和低电平 Vss的连接， 存储电容 C1的一端连接驱动 TFTT1 的栅极， T2导通， T3和 T4截止， 即 T1的栅极被充电至初始电压信号 VINI; 然后， 关断 T2， 导通 Τ3和 Τ4， 将驱动 TFT T1的栅极与漏极连接形成二极 管连接方式进行放电， 即， 最终将存储电容 C1两端的电压（即 T1的栅源极 间电压）放电至驱动 TFT T1的亚阔导通状态 VDATA+VTH， 其中 VDATA为数据 电压信号。
当驱动 TFTT1为一般增强型特性时， 阔值电压为正， 如图 4 ( a )所示， 存储电容 C1两端电压（即 T1的栅源极间电压 )可以正常放电至 VDATA+VTH， 实现阔值电压补偿。但是， 当驱动 TFT为耗尽型特性时， 阔值电压 VTH为负， 如图 4 ( b )所示， 存储电容 C1两端电压通过二极管连接的驱动 TFT T1放电 时， 驱动 TFT T1的源漏电压变为零截止时， 依然未放电达到亚阔导通状态， 即存储电容 C1两端电压为 0， 而不是 VTH ( VTH<0 )。 因此， 像素驱动电路失 去阔值电压补偿功能。
本公开实施例的基本思想是：在放电节点和驱动 TFT T1的栅极之间设置 一个耦合电容，改变预充电方式，将放电节点充电至高电平 VDD，驱动 TFT T1 栅极充电至 VDATA或 VINI， 放电节点放电过程中通过耦合电容同时降低驱动 TFT T1的栅极电压， 使其氏于驱动 TFT T1的源级电压， 从而实现亚阔饱和 截止， 使驱动 TFT T1的阔值电压得到补偿。
这里， 所述亚阔饱和截止状态是指： 介于导通和截止之间的临界状态， 即指 VGS=VTH的这个状态， 其中 VGS是驱动 TFT的栅极和源极之间的电压。
下面结合附图对本公开的实施例作进一步详细说明。
图 5为按照本公开的第一实施例的耗尽型 TFT的 AMOLED像素驱动电 路结构图， 如图 5所示， 该 AMOLED像素驱动电路包括： 驱动薄膜晶体管 Tl、 栅极初始电压写入模块、 数据电压写入模块、 饱和放电模块、 初始化模 块、 发光控制模块。 在该示例性实施例中， 栅极初始电压写入模块包括第二 薄膜晶体管 Τ2， Τ2为栅极初始电压写入 TFT， 数据电压写入模块包括第三 薄膜晶体管 Τ3， Τ3 为数据电压写入 TFT， 饱和放电模块包括第四薄膜晶体 管 T4， Τ4为饱和放电 TFT， 初始化模块包括第五薄膜晶体管 T5， Τ5为初始 化 TFT， 发光控制模块包括第六薄膜晶体管 T6， Τ6为发光控制 TFT。 驱动 薄膜晶体管 T1和薄膜晶体管 T2 T6为具有耗尽特性的 N型 TFT。 该电路还 包括存储电容 Cl、 耦合电容 C2， 有机发光二极管 Dl。 图中所示 GN^为上一 行栅极（Gate )信号， GN为本行 Gate信号， S1为第一控制信号， S2为第二 控制信号， VDD为第一电源， Vss为第二电源。 本公开实施例的放电节点即图 5中的 P点。
示例性地，薄膜晶体管 T2的源极与存储电容 C1的第一端、耦合电容 C2 的第二端以及驱动薄膜晶体管 T1的栅极相连， 薄膜晶体管 T2的栅极接上一 行栅极信号 GN ， 薄膜晶体管 T2的漏极与初始电压信号端连接连接。 本公开 的第一实施例中的初始电压信号端为数据电压信号端 VDATA。
薄膜晶体管 T3的栅极连接本行栅极信号 GN， T3的漏极与驱动薄膜晶体 管 T1的源极连接， T3源极与数据电压信号端 VDATA连接。
薄膜晶体管 T4的漏极与耦合电容 C2的第一端相连， T4的栅极与第一控 制信号线 S1连接， T4的源极与驱动薄膜晶体管 T1的漏极连接。
薄膜晶体管 T5的源极与驱动薄膜晶体管 T1的源极连接， T5的栅极与第 二控制信号线 S2连接， T5的漏极和存储电容 C1的第二端共同连接第二电源 薄膜晶体管 T6的源极与驱动薄膜晶体管 T1的漏极连接， T6的栅极与第 二控制信号 S2连接； T6的漏极与有机发光二极管 D1的一端连接，有机发光 二极管 D1的另一端与第一电源 VDD连接。
图 6为本公开第二实施例的耗尽型 TFT的 AM0LED像素驱动电路结构 图。 如图 6所示， 该电路包括： 驱动薄膜晶体管 Tl、栅极初始电压写入模块、 数据电压写入模块、 饱和放电模块、 初始化模块、 发光控制模块。 该实施例 中， 栅极初始电压写入模块包括第二薄膜晶体管 Τ2， Τ2 为栅极初始电压写 入 TFT，数据电压写入模块包括第三薄膜晶体管 Τ3，Τ3为数据电压写入 TFT， 饱和放电模块包括第四薄膜晶体管 T4， Τ4为饱和放电 TFT， 初始化模块包 括第五薄膜晶体管 T5， Τ5为初始化 TFT， 发光控制模块包括第六薄膜晶体 管 T6， Τ6为发光控制 TFT。驱动薄膜晶体管 T1和薄膜晶体管 T2 T6为具有 耗尽特性的 N型 TFT。 该电路还包括存储电容 Cl、 耦合电容 C2， 有机发光 二极管 Dl。 图 6中， 所示 GN-1为上一行栅极（Gate )信号， GN为本行 Gate 信号， S1为第一控制信号， S2为第二控制信号， Vss为第二电源， VDD为第 一电源。 图 6中的所述 P点即为本公开实施例的放电节点。
本实施例与第一实施例的区别仅在于：薄膜晶体管 T2的漏极与初始电压 信号端 VIM连接， 其他部分的连接关系完全相同， 此处不再描述。
本公开实施例还提供了 AMOLED像素驱动电路的驱动方法， 该像素驱 动电路包括： 驱动薄膜晶体管、 栅极初始电压写入模块、 数据电压写入模块、 饱和放电模块、 初始化模块、 发光控制模块、 存储电容、 耦合电容、 有机发 光二极管； 该驱动方法包括以下工作过程： 在初始化阶段中：
由栅极初始电压写入模块将初始电压信号写入驱动薄膜晶体管 T1 的栅 极、 存储电容 C1第一端、 耦合电容 C2第二端； 由数据电压写入模块将数据 电压信号端与驱动薄膜晶体管 T1 的源极断开； 由初始化模块将驱动晶体管 T1 的源极与第二电源连通 Vss; 由第二电源对存储电容 C1 的第二端充电； 由发光控制模块将有机发光二极管 D1的一端与驱动薄膜晶体管 T1的漏极连 通； 由饱和放电模块将耦合电容 C2的第一端与驱动薄膜晶体管 T1的漏极连 通； 第一电源 VDD通过有机发光二极管 D1对所述辆合电容的第一端充电； 在阔值电压补偿和数据电压写入阶段中：
由栅极初始电压写入模块将初始电压信号端与驱动薄膜晶体管 T1 的栅 极、 存储电容 C1第一端、 耦合电容 C2第二端断开； 由数据电压写入模块将 数据电压信号端与驱动薄膜晶体管 T1的源极连通，将数据电压信号写入驱动 薄膜晶体管 T1的源极； 由初始化模块将驱动薄膜晶体管 T1的源极与第二电 源 Vss断开；由发光控制模块将有机发光二极管 D1的一端与驱动薄膜晶体管 T1的漏极断开； 由饱和放电模块将耦合电容 C2的第一端与驱动薄膜晶体管 T1的漏极连通； 存储电容 C1和耦合电容 C2通过驱动薄膜晶体管 T1放电； 在发光阶段中：
由栅极初始电压写入模块将初始电压信号端与驱动薄膜晶体管 T1 的栅 极、 存储电容 C1第一端、 耦合电容 C2第二端断开； 由数据电压写入模块将 数据电压信号端与驱动薄膜晶体管 T1的源极断开；由初始化模块将驱动薄膜 晶体管 T1 的源极与第二电源 Vss连通； 由发光控制模块将有机发光二极管 D1的一端与驱动薄膜晶体管 T1的漏极连通； 由饱和放电模块将耦合电容 C2 的第一端与驱动薄膜晶体管 Ti 的漏极断开； 驱动晶体管为有机发光二极管 D1提供驱动电流。
例如， 栅极初始电压写入模块可包括第二薄膜晶体管； 数据电压写入模 块可包括第三薄膜晶体管； 饱和放电模块可包括第四薄膜晶体管； 初始化模 块可包括第五薄膜晶体管； 发光控制模块可包括第六薄膜晶体管。 在这种情 况下， 上述驱动方法的工作过程如下：
在初始化阶段中：
第二薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体管和第六薄膜晶体管 导通，第三薄膜晶体管截止；将初始电压信号写入驱动薄膜晶体管 T1的栅极、 存储电容第一端、 耦合电容第二端； 第二电源对存储电容的第二端充电； 第 一电源对耦合电容的第一端充电；
在阔值电压补偿和数据电压写入阶段中：
第三薄膜晶体管和第四薄膜晶体管导通， 第二薄膜晶体管、 第五薄膜晶 体管和第六薄膜晶体管截止；将数据电压信号写入到驱动薄膜晶体管 T1的源 极； 存储电容和耦合电容通过驱动薄膜晶体管 T1放电；
在发光阶段中：
第五薄膜晶体管和第六薄膜晶体管导通， 第二薄膜晶体管、 第三薄膜晶 体管和第四薄膜晶体管截止； 驱动薄膜晶体管 T1 为发光二极管提供驱动电 流。
下面结合一个具体实施例对上述驱动方法进行详细描述。 图 7为本公开 实施例 AMOELD像素驱动电路的工作时序图， 其中， 所示 a为初始化阶段， 所示 b为阔值电压补偿和数据电压写入阶段， 所示 c为发光阶段。
在初始化阶段 a中： 如图 8 ( a ) 所示， GN-1、 SI和 S2为高电平， GN为 低电平， 所示 DATA 为数据电压 VDATA， 以初始电压信号为 VDATA为例， VSS<VDATA<VDD , T2、 Τ4、 Τ5和 Τ6导通， Τ3截止。 存储电容 C1连接 T1 的栅极的第一端被充电为 VDATA， 第二端被充电为 VSS， 则存储电容 C1两端 电压差为 VDATA- VSS， 耦合电容 C2第一端为 VDD， 第二端为 VDATA， 耦合电 容 C2两端电压差为 VDD -VDATAO 在阔值电压补偿和数据电压写入阶段 b中： 如图 8 ( b )所示， G^ o S2 为低电平， S1和 GN 为高电平， DATA为数据电压 VDATA， 以初始电压信号 为 VDATA为例， VSS<VDATA<VDD， T3和 T4导通， T2、 Τ5和 Τ6截止。 初始 存储在 C1和 C2上的电压通过 T1放电， 即通过放电 T1漏极从高电平 VDD 下降， 由于 C2的耦合作用， T1的栅极也从 VDATA开始下降。 设 T1漏极电压 变化为 A V， 则 T1栅极的电压变化为 [C2/ ( C1+C2 ) ]* A V。
T1 的漏极放电直至 T1 的栅极电压 VGs < VTH, 即： VDATA- VDATA-[C2/ ( C1+C2 ) ]* A V=VTH， 同时， 为保证 Tl不会因为源漏电压为零而提前截止， 从而失去阔值电压补偿， 则需满足关系式 VDD-VDATA- A V>0。 所以， 只要满 足条件： VDD-VDATA>[ ( C1+C2 ) /C2]* VTH， 即可实现阔值电压补偿。 这样， 存储电容 C1与 T1栅极相连的第一端的电平为 VDATA+VTH， 存储电容 C1的 第二端电平为 Vss， 即存储电容 CI的两端电压差为 VDATA-VSS +VTH。
在发光阶段 c中： 如图 8 ( c )所示， S2为高电平， Sl、 G>^o GN-1为低 电平， T5和 T6导通， T2、 T3和 Τ4截止， T1的栅源电压 VGS=VDATA-VSS + VTH。 因此， T1的漏电流为：
IDS=0.5k* ( VDATA-VSS+VTH-VTH ) 2 = 0.5k* ( VDATA-VSS ) Dl在 Tl漏电 流驱动下发光显示。 同时， Tl的漏电流与阔值电压无关， 可实现对 T1 阔值 电压的补偿。 其中， 所述 k为薄膜晶体管的电流系数。
对于初始电压信号为 VINI的情况， VSS<VINI<VDD， Tl阔值电压的补偿原 理与初始电压信号为 VDATA的情况类似， 在阔值电压补偿和写入阶段， T1的 漏极放电直至 T1的栅极电压 VGS < VTH， 即： V匪- VDATA-[C2/ ( C1+C2 ) ]*△ V=VTH， 同时， 为保证 Tl不会因为源漏电压为零而提前截止， 从而失去阔值 电压补偿， 则需满足关系式 VDD-VDATA- Δ V>0。 所以， 只要满足条件： VDD-VDATA>[ ( C1+C2 ) /C2]* (
Figure imgf000012_0001
)， 即可实现阔值电压补偿。
本公开的实施例还提供一种阵列基板， 包括： 沿列延伸排列的多条数据 线， 沿行延伸排列的多条第一扫描线、 第二扫描线和信号控制线， 以矩阵形 式布置在数据线和扫描线交叉位置处的多个像素； 所述像素包括上文所述的 像素驱动电路。
本公开的实施例还提供一种显示面板， 所述显示面板包括上文所述的阵 列基板。
本公开的实施例还提供了一种显示装置， 所述显示装置包括上文所述的 显示面板。 所述显示装置可为电子纸、 手机、 数码相框等显示设备。
以上所述， 仅为本公开的示例性实施例而已， 并非用于限定本公开的保 脱离本公开的实质和范围。本公开的保护范围以所附权利要求的保护范围 为准。
本申请要求于 2013年 10月 25日递交的中国专利申请第 201310512931.5 号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims

权 利 要 求 书
1、 一种 AMOLED像素驱动电路， 包括： 驱动薄膜晶体管、 存储电容、 有机发光二极管， 其中还包括：
与所述存储电容的第一端连接的耦合电容；
栅极初始电压写入模块，用于将初始电压信号写入所述驱动薄膜晶体管的 栅极、 存储电容的第一端、 耦合电容的第二端；
数据电压写入模块， 用于将数据电压信号写入所述驱动薄膜晶体管的源 极；
初始化模块， 用于初始化所述驱动薄膜晶体管的源极电压；
发光控制模块，用于控制所述有机发光二极管的一端与所述驱动薄膜晶体 管漏极的连接；
饱和放电模块，连接在所述辆合电容的第一端与所述驱动薄膜晶体管的漏 极之间。
2、 根据权利要求 1所述的像素驱动电路， 其中， 所述栅极初始电压写入 模块包括第二薄膜晶体管，所述第二薄膜晶体管的源极与所述存储电容的第一 端、所述辆合电容的第二端以及所述驱动薄膜晶体管的栅极相连， 第二薄膜晶 体管的栅极接上一行栅极信号，所述第二薄膜晶体管的漏极与初始电压信号端 连接。
3、 根据权利要求 2所述的像素驱动电路， 其中， 所述数据电压写入模块 包括第三薄膜晶体管， 第三薄膜晶体管的栅极连接本行栅极信号， 第三薄膜晶 体管的漏极与所述驱动薄膜晶体管的源极连接，第三薄膜晶体管的源极与数据 电压信号端连接。
4、 根据权利要求 3所述的像素驱动电路， 其中， 所述饱和放电模块包括 第四薄膜晶体管， 所述第四薄膜晶体管的漏极与所述辆合电容的第一端相连， 所述第四薄膜晶体管的栅极与第一控制信号线连接，所述第四薄膜晶体管的源 极与所述驱动薄膜晶体管的漏极连接。
5、 根据权利要求 4所述的像素驱动电路， 其中， 所述初始化模块包括第 五薄膜晶体管， 所述第五薄膜晶体管的源极与所述驱动薄膜晶体管的源极连 接， 所述第五薄膜晶体管的栅极与第二控制信号线连接， 所述第五薄膜晶体管 的漏极和所述存储电容的第二端共同连接第二电源。
6、 根据权利要求 5所述的像素驱动电路， 其中， 所述发光控制模块包括 第六薄膜晶体管，所述第六薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连 接， 所述第六薄膜晶体管的栅极与第二控制信号连接； 所述第六薄膜晶体管的 漏极与所述有机发光二极管的所述一端连接，所述有机发光二极管的另一端与 第一电源连接。
7、 根据权利要求 6所述的像素驱动电路， 其中， 所述驱动薄膜晶体管、 所述第二薄膜晶体管、 所述第三薄膜晶体管、 所述第四薄膜晶体管、 所述第五 薄膜晶体管、 所述第六薄膜晶体管为耗尽型 N型薄膜晶体管。
8、 根据权利要求 1-7之一所述的像素驱动电路， 其中， 所述初始电压信 号为数据电压信号。
9、 一种阵列基板， 其中， 包括权利要求 1-8 中任一项所述的像素驱动电 路。
10、 一种 AMOLED像素驱动电路的驱动方法， 该像素驱动电路包括： 驱 动薄膜晶体管、 栅极初始电压写入模块、 数据电压写入模块、 饱和放电模块、 初始化模块、 发光控制模块、 存储电容、 耦合电容、 有机发光二极管； 所述驱 动方法包括下列步骤：
在初始化阶段：
由所述栅极初始电压写入模块将初始电压信号写入所述驱动薄膜晶体管 的栅极、存储电容第一端、耦合电容第二端； 由所述数据电压写入模块将数据 电压信号端与所述驱动薄膜晶体管的源极断开；由所述初始化模块将所述驱动 晶体管的源极与第二电源连通； 由第二电源对所述存储电容的第二端充电； 由 所述发光控制模块将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏 极连通；由所述饱和放电模块将所述辆合电容的第一端与所述驱动薄膜晶体管 的漏极连通；由第一电源通过所述有机发光二极管对所述辆合电容的第一端充 电；
在阔值电压补偿和数据电压写入阶段：
由所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管 的栅极、 存储电容第一端、耦合电容第二端断开； 由所述数据电压写入模块将 数据电压信号端与所述驱动薄膜晶体管的源极连通，将数据电压信号写入所述 驱动薄膜晶体管的源极；由所述初始化模块将所述驱动薄膜晶体管的源极与第 二电源断开；由所述发光控制模块将所述有机发光二极管的所述一端与所述驱 动薄膜晶体管的漏极断开；由所述饱和放电模块将所述辆合电容的第一端与所 述驱动薄膜晶体管的漏极连通；所述存储电容和耦合电容通过所述驱动薄膜晶 体管放电；
在发光阶段：
由所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管 的栅极、 存储电容第一端、耦合电容第二端断开； 由所述数据电压写入模块将 数据电压信号端与所述驱动薄膜晶体管的源极断开；由所述初始化模块将所述 驱动薄膜晶体管的源极与第二电源连通；由所述发光控制模块将所述有机发光 二极管的所述一端与所述驱动薄膜晶体管的漏极连通；由所述饱和放电模块将 所述辆合电容的第一端与所述驱动薄膜晶体管的漏极断开；所述驱动晶体管为 所述有机发光二极管提供驱动电流。
11、 根据如权利要求 10所述的驱动方法， 所述栅极初始电压写入模块包 括第二薄膜晶体管； 所述数据电压写入模块包括第三薄膜晶体管； 所述饱和放 电模块包括第四薄膜晶体管； 所述初始化模块包括第五薄膜晶体管； 所述发光 控制模块包括第六薄膜晶体管； 所述驱动方法包括：
在初始化阶段：
所述第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体 管导通， 所述第三薄膜晶体管截止； 将初始电压信号写入所述驱动薄膜晶体管 的栅极、存储电容第一端、耦合电容第二端； 第二电源对所述存储电容的第二 端充电； 第一电源对所述辆合电容的第一端充电；
在阔值电压补偿和数据电压写入阶段：
第三薄膜晶体管和第四薄膜晶体管导通， 第二薄膜晶体管、第五薄膜晶体 管和第六薄膜晶体管截止； 将数据电压信号写入到所述驱动薄膜晶体管的源 极； 所述存储电容和耦合电容通过所述驱动薄膜晶体管放电；
在发光阶段：
第五薄膜晶体管和第六薄膜晶体管导通， 第二薄膜晶体管、第三薄膜晶体 管和第四薄膜晶体管截止；所述驱动薄膜晶体管为所述发光二极管提供驱动电 n
866丽 OZXD/工：) d Z8S8S0/ST0Z OAV
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102192522B1 (ko) * 2014-08-06 2020-12-18 엘지디스플레이 주식회사 유기 발광 표시 장치
KR102274517B1 (ko) * 2014-11-10 2021-07-09 삼성디스플레이 주식회사 유기전계발광 표시장치
KR102338942B1 (ko) * 2015-06-26 2021-12-14 엘지디스플레이 주식회사 유기발광다이오드 표시장치 및 이의 구동방법
CN105654906B (zh) * 2016-01-26 2018-08-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及显示装置
US11328678B2 (en) * 2017-04-28 2022-05-10 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel, pixel driving circuit, and drving method thereof
CN107123397B (zh) * 2017-06-14 2019-10-25 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路及像素驱动方法
CN107146579B (zh) * 2017-07-06 2018-01-16 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
CN107230451B (zh) * 2017-07-11 2018-01-16 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
CN107657921B (zh) * 2017-11-17 2019-09-24 深圳市华星光电半导体显示技术有限公司 Amoled像素驱动电路及其驱动方法
CN108120915B (zh) * 2017-12-15 2020-05-05 京东方科技集团股份有限公司 应用于显示面板的老化处理方法及老化处理系统
KR102575551B1 (ko) * 2018-04-12 2023-09-08 삼성디스플레이 주식회사 표시 장치
CN109036287B (zh) * 2018-07-19 2020-05-05 武汉华星光电半导体显示技术有限公司 一种像素驱动电路、驱动方法及显示面板
CN109243368B (zh) * 2018-11-13 2021-04-27 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板
CN113168813A (zh) * 2019-01-16 2021-07-23 索尼半导体解决方案公司 电光装置和电子设备
CN111354307B (zh) * 2020-04-09 2022-02-15 武汉天马微电子有限公司 一种像素驱动电路及驱动方法、有机发光显示面板
CN115104148B (zh) * 2020-11-30 2024-04-05 京东方科技集团股份有限公司 像素电路、驱动方法、显示基板和显示装置
US11170719B1 (en) * 2020-12-10 2021-11-09 Sharp Kabushiki Kaisha TFT pixel threshold voltage compensation circuit with a source follower
CN113808536B (zh) * 2021-09-23 2023-09-05 深圳市华星光电半导体显示技术有限公司 显示面板及显示终端
JP2023050791A (ja) * 2021-09-30 2023-04-11 セイコーエプソン株式会社 電気光学装置、電子機器および電気光学装置の駆動方法
CN115376463A (zh) * 2022-08-23 2022-11-22 北京京东方技术开发有限公司 像素电路、驱动方法及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060092148A1 (en) * 2004-10-26 2006-05-04 Seiko Epson Corporation Electro-optical device, method of driving electro-optical device, pixel circuit, and electronic apparatus
EP1857998A1 (en) * 2006-05-19 2007-11-21 TPO Displays Corp. System for displaying image and driving display element method
CN102665321A (zh) * 2011-12-30 2012-09-12 友达光电股份有限公司 发光二极管电路,驱动发光二极管电路的方法及显示器
CN102842283A (zh) * 2012-08-14 2012-12-26 北京大学深圳研究生院 一种像素电路、显示装置及其驱动方法
CN102930822A (zh) * 2012-11-12 2013-02-13 京东方科技集团股份有限公司 像素电路、显示装置和像素电路的驱动方法
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173590B2 (en) * 2004-06-02 2007-02-06 Sony Corporation Pixel circuit, active matrix apparatus and display apparatus
CA2490858A1 (en) * 2004-12-07 2006-06-07 Ignis Innovation Inc. Driving method for compensated voltage-programming of amoled displays
ITMI20070100A1 (it) * 2007-01-24 2008-07-25 St Microelectronics Srl Circuito di pilotaggio di un diodo oled (diodo organico ed emissione di luce), in particolare per applicazione a display di tipo am-oled
KR100962961B1 (ko) 2008-06-17 2010-06-10 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR100986896B1 (ko) * 2008-12-05 2010-10-08 삼성모바일디스플레이주식회사 유기전계발광 표시장치 및 그의 구동방법
KR20100090527A (ko) * 2009-02-06 2010-08-16 삼성모바일디스플레이주식회사 발광 표시 장치 및 발광 표시 장치 구동 방법
JP2010249955A (ja) * 2009-04-13 2010-11-04 Global Oled Technology Llc 表示装置
KR101058110B1 (ko) * 2009-09-16 2011-08-24 삼성모바일디스플레이주식회사 디스플레이 패널의 화소 회로, 그 구동방법, 및 이를 포함하는 유기 발광 표시 장치
KR101681097B1 (ko) * 2010-07-27 2016-12-02 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101674479B1 (ko) * 2010-08-10 2016-11-10 삼성디스플레이 주식회사 유기전계발광 표시장치
TWI433111B (zh) * 2010-12-22 2014-04-01 Univ Nat Taiwan Science Tech 有機發光二極體的畫素單元及具有其之顯示面板
TW201239849A (en) * 2011-03-24 2012-10-01 Hannstar Display Corp Pixel circuit of light emitting diode display and driving method thereof
CN102651192A (zh) * 2011-06-21 2012-08-29 京东方科技集团股份有限公司 有源矩阵有机发光二极体面板及其驱动电路与方法
KR101813215B1 (ko) * 2011-06-30 2018-01-02 삼성디스플레이 주식회사 스테이지 회로 및 이를 이용한 주사 구동부
CN102651197A (zh) * 2011-11-01 2012-08-29 京东方科技集团股份有限公司 有机发光二极管驱动电路、显示面板、显示器及驱动方法
CN103366672A (zh) * 2012-04-10 2013-10-23 东莞万士达液晶显示器有限公司 发光元件驱动电路及像素电路
CN103035201B (zh) * 2012-12-19 2015-08-26 昆山工研院新型平板显示技术中心有限公司 有机发光二极管像素电路、驱动方法及其显示面板
CN103413520B (zh) * 2013-07-30 2015-09-02 京东方科技集团股份有限公司 像素驱动电路、显示装置和像素驱动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060092148A1 (en) * 2004-10-26 2006-05-04 Seiko Epson Corporation Electro-optical device, method of driving electro-optical device, pixel circuit, and electronic apparatus
EP1857998A1 (en) * 2006-05-19 2007-11-21 TPO Displays Corp. System for displaying image and driving display element method
CN102665321A (zh) * 2011-12-30 2012-09-12 友达光电股份有限公司 发光二极管电路,驱动发光二极管电路的方法及显示器
CN102842283A (zh) * 2012-08-14 2012-12-26 北京大学深圳研究生院 一种像素电路、显示装置及其驱动方法
CN102930822A (zh) * 2012-11-12 2013-02-13 京东方科技集团股份有限公司 像素电路、显示装置和像素电路的驱动方法
CN102982767A (zh) * 2012-12-10 2013-03-20 京东方科技集团股份有限公司 一种像素单元驱动电路、驱动方法及显示装置

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