CN104575372B - 一种amoled像素驱动电路及其驱动方法、阵列基板 - Google Patents
一种amoled像素驱动电路及其驱动方法、阵列基板 Download PDFInfo
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Abstract
本发明公开了一种AMOLED像素驱动电路及其驱动方法,电路包括:驱动薄膜晶体管、将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端的栅极初始电压写入模块、将数据电压信号写入所述驱动薄膜晶体管的源极的数据电压写入模块、将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通或断开的饱和放电模块、将所述驱动薄膜晶体管的源极与第二电源连通或断开的初始化模块、将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通或断开的发光控制模块、存储电容、耦合电容和有机发光二极管。本发明还同时公开了一种阵列基板,本发明可实现亚阈饱和截止,补偿驱动TFT阈值电压的目的。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种有源矩阵有机发光二极体(ActiveMatrix Organic Light Emitting Diode,AMOLED)像素驱动电路及其驱动方法、阵列基板。
背景技术
传统AMOLED的基本像素驱动电路结构如图1所示,图1(a)表示N型薄膜晶体管(TFT)构成的AMOLED像素驱动电路,包括:T1、T2两个N型TFT,发光二极管D1和存储电容C1;图1(b)表示P型TFT构成的AMOLED像素驱动电路,包括:T1、T2两个P型TFT,发光二极管D1和存储电容C1。上述电路适用于所有类型的晶体管,包括耗尽型TFT。但该像素驱动电路不具有阈值电压补偿功能,不能解决由于工艺均匀性导致的阈值电压的均一性和有机发光二极管(OLED)驱动发光均一性的问题。
氧化物TFT是大尺寸AMOLED的发展方向,由于氧化物TFT具有耗尽型的特点,即N型阈值电压为负。耗尽型TFT采用传统N型TFT的AMOLED像素驱动电路设计,在采用二极管连接方式补偿阈值电压时,由于阈值电压为负值,TFT进入亚阈饱和截止之前,源漏电压为零而提前截止,从而失去阈值电压补偿功能。
发明内容
有鉴于此,本发明的主要目的在于提供一种AMOLED像素驱动电路及其驱动方法、阵列基板,可实现亚阈饱和截止,补偿驱动TFT阈值电压的目的。
为达到上述目的,本发明的技术方案是这样实现的:
本发明提供了一种AMOLED像素驱动电路,包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;
所述栅极初始电压写入模块,用于将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;
所述数据电压写入模块,用于数据电压信号写入所述驱动薄膜晶体管的源极;
所述初始化模块,用于将所述驱动薄膜晶体管的源极与第二电源连通或断开;
所述发光控制模块,用于将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通或断开;
所述饱和放电模块,用于将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通或断开;
其中,所述存储电容的第二端连接第二电源。
其中,所述栅极初始电压写入模块包括第二薄膜晶体管,所述第二薄膜晶体管的源极与所述存储电容的第一端、所述耦合电容的第二端以及所述驱动薄膜晶体管的栅极相连,第二薄膜晶体管的栅极接上一行栅极信号,所述第二薄膜晶体管的漏极与初始电压信号端连结。
其中,所述数据电压写入模块包括第三薄膜晶体管,第三薄膜晶体管的栅极连接本行栅极信号,第三薄膜晶体管的漏极与所述驱动薄膜晶体管的源极连接,第三薄膜晶体管的源极与数据电压信号端连接。
其中,所述饱和放电模块包括第四薄膜晶体管,所述第四薄膜晶体管的漏极与所述耦合电容的第一端相连,所述第四薄膜晶体管的栅极与第一控制信号线连接,所述第四薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接。
其中,所述初始化模块包括第五薄膜晶体管,所述第五薄膜晶体管的源极与所述驱动薄膜晶体管的源极连接,所述第五薄膜晶体管的栅极与第二控制信号线连接,所述第五薄膜晶体管的漏极和所述存储电容的第二端共同连接第二电源。
其中,所述发光控制模块包括第六薄膜晶体管,所述第六薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接,所述第六薄膜晶体管的栅极与第二控制信号连接;所述第六薄膜晶体管的漏极与所述有机发光二极管的所述一端连接,所述有机发光二极管的另一端与第一电源连接。
优选的,所述驱动薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管为耗尽型N型薄膜晶体管。
优选的,所述初始电压信号为数据电压信号。
本发明还提供了一种阵列基板,包括所述的像素驱动电路。
本发明还提供了AMOLED像素驱动电路的驱动方法,该像素驱动电路包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;所述驱动方法包括:
初始化阶段:
所述栅极初始电压写入模块将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动晶体管的源极与第二电源连通;第二电源对所述存储电容的第二端充电;所述发光控制模块将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通;第一电源通过所述有机发光二极管对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极连通,将数据电压信号写入所述驱动晶体管的源极;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源断开;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极断开;所述饱和放电模块将所述耦合电容的第一端与所述驱动晶体管的漏极连通;所述存储电容和耦合电容通过所述驱动薄膜晶体管放电;
发光阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源连通;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极断开;所述驱动晶体管为所述有机发光二极管提供驱动电流。
其中,所述栅极初始电压写入模块包括第二薄膜晶体管;所述数据电压写入模块包括第三薄膜晶体管;所述饱和放电模块包括第四薄膜晶体管;所述初始化模块包括第五薄膜晶体管;所述发光控制模块包括第六薄膜晶体管;所述驱动方法包括:
初始化阶段具体为:
所述第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管导通,所述第三薄膜晶体管截止;将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;第二电源对所述存储电容的第二端充电;第一电源对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段具体为:
第三薄膜晶体管和第四薄膜晶体管导通,第二薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管截止;将数据电压信号写入到所述驱动薄膜晶体管的源极;所述存储电容和耦合电容通过所述驱动晶体管放电;
发光阶段具体为:
第五薄膜晶体管和第六薄膜晶体管导通,第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管截止;所述驱动薄膜晶体管为所述发光二极管提供驱动电流。
本发明提供的AMOLED像素驱动电路及其驱动方法、阵列基板,所述像素驱动电路,包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;所述栅极初始电压写入模块,用于将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;所述数据电压写入模块,用于将数据电压信号写入所述驱动薄膜晶体管的源极;所述初始化模块,用于将所述驱动薄膜晶体管的源极与第二电源连通或断开;所述发光控制模块,用于将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通或断开;所述饱和放电模块,用于将所述耦合电容的第一端与所述驱动晶体管的漏极连通或断开;其中,所述存储电容的第二端连接第二电源。本发明在放电节点和驱动TFT的栅极之间设置一个耦合电容,改变预充电方式,将放电节点充电至高电平VDD,驱动TFT栅极充电至VDATA或VINI,放电节点放电过程中通过耦合电容同时降低驱动TFT栅极电压,使其低于驱动TFT源级电压,从而实现亚阈饱和截止,驱动TFT的阈值电压得到补偿。
附图说明
图1为传统AMOLED的基本像素驱动电路结构;
图2为N型耗尽TFT的Ids-Vgs特性曲线图;
图3(a)为现有常见的具有阈值电压补偿的AMOLED像素驱动电路结构示意图;
图3(b)为图3(a)所述驱动TFT阈值电压补偿原理示意图;
图4(a)为图3(a)所示电路增强型TFT的阈值电压示意图;
图4(b)为图3(a)所示电路耗尽型TFT的阈值电压补偿失效示意图;
图5为本发明实施例一所述耗尽型TFT的AMOLED像素驱动电路结构图;
图6为本发明实施例二所述耗尽型TFT的AMOLED像素驱动电路结构图;
图7为本发明实施例AMOELD像素驱动电路的工作时序图;
图8(a)为本发明实施例所述AMOELD像素驱动电路在初始化阶段的工作原理图;
图8(b)为本发明实施例所述AMOELD像素驱动电路在阈值电压补偿和数据电压写入阶段的工作原理图;
图8(c)为本发明实施例所述AMOELD像素驱动电路在OLED发光阶段的工作原理图。
具体实施方式
目前,氧化物TFT的器件大都具有耗尽型的特点。图2为N型耗尽TFT的Ids-Vgs特性曲线图。由图2可以看出N型耗尽TFT的最大特点是阈值电压VTH小于0,横坐标为电压,纵坐标为电流。
下面首先对现有常见的具有阈值电压补偿的AMOLED像素驱动电路进行简单介绍,如图3(a)为一种常见的阈值电压补偿的AMOLED像素驱动电路,在电压编程阶段,如图3(b)所示,首先T5和T6截止,切断驱动TFT T1与高电平VDD和低电平VSS的连接,存储电容C1接驱动TFT栅极,T2导通,T3和T4截止,即T1栅极的一端充电至初始电压信号VINI,;然后,关断T2,导通T3和T4,将驱动TFT的栅极与漏极连接组成二极管连接方式进行放电,即最终将存储电容C1两端的电压(即T1的栅源极间电压)放电至驱动TFT亚阈导通状态VDATA+VTH,其中VDATA为数据电压信号。
当驱动TFT为一般增强型特性时,阈值电压为正,如图4(a)所示,存储电容两端电压(即T1的栅源极间电压)可以正常放电至VDATA+VTH,实现阈值电压补偿。但是,当驱动TFT为耗尽型特性时,阈值电压VTH为负,如图4(b)所示,存储电容C1两端电压通过二极管连接的驱动TFT放电时,驱动TFT的源漏电压变为零截止时,依然未放电达到亚阈导通状态,即存储电容两端电压为0,而不是VTH(VTH<0)。因此,像素驱动电路失去阈值电压补偿功能。
本发明实施例的基本思想是:在放电节点和驱动TFT的栅极之间设置一个耦合电容,改变预充电方式,将放电节点充电至高电平VDD,驱动TFT栅极充电至VDATA或VINI,放电节点放电过程中通过耦合电容同时降低驱动TFT栅极电压,使其低于驱动TFT源级电压,从而实现亚阈饱和截止,驱动TFT的阈值电压得到补偿。
这里,所述亚阈饱和截止状态是指:介于导通和截止之间的临界状态,即指VGS=VTH的这个状态,其中VGS是驱动TFT的栅极和源极之间的电压。
本发明提供了一种AMOLED像素驱动电路,包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;
所述栅极初始电压写入模块,用于将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;
所述数据电压写入模块,用于数据电压信号写入所述驱动薄膜晶体管的源极;
所述初始化模块,用于将所述驱动薄膜晶体管的源极与第二电源连通或断开;
所述发光控制模块,用于将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通或断开;
所述饱和放电模块,用于将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通或断开;
其中,所述存储电容的第二端连接第二电源。
其中,所述栅极初始电压写入模块包括第二薄膜晶体管,所述第二薄膜晶体管的源极与所述存储电容的第一端、所述耦合电容的第二端以及所述驱动薄膜晶体管的栅极相连,第二薄膜晶体管的栅极接上一行栅极信号,所述第二薄膜晶体管的漏极与初始电压信号端连结。
其中,所述数据电压写入模块包括第三薄膜晶体管,第三薄膜晶体管的栅极连接本行栅极信号,第三薄膜晶体管的漏极与所述驱动薄膜晶体管的源极连接,第三薄膜晶体管的源极与数据电压信号端连接。
其中,所述饱和放电模块包括第四薄膜晶体管,所述第四薄膜晶体管的漏极与所述耦合电容的第一端相连,所述第四薄膜晶体管的栅极与第一控制信号线连接,所述第四薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接。
其中,所述初始化模块包括第五薄膜晶体管,所述第五薄膜晶体管的源极与所述驱动薄膜晶体管的源极连接,所述第五薄膜晶体管的栅极与第二控制信号线连接,所述第五薄膜晶体管的漏极和所述存储电容的第二端共同连接第二电源。
其中,所述发光控制模块包括第六薄膜晶体管,所述第六薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接,所述第六薄膜晶体管的栅极与第二控制信号连接;所述第六薄膜晶体管的漏极与所述有机发光二极管的所述一端连接,所述有机发光二极管的另一端与第一电源连接。
优选的,所述驱动薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管为耗尽型N型薄膜晶体管。
优选的,所述初始电压信号为数据电压信号。
下面结合附图及具体实施例对本发明作进一步详细说明。
图5为本发明实施例一所述耗尽型TFT的AMOLED像素驱动电路结构图,如图5所示,包括:驱动薄膜晶体管T1、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块;其中,栅极初始电压写入模块包括第二薄膜晶体管T2,T2为栅极初始电压写入TFT,数据电压写入模块包括第三薄膜晶体管T3,T3为数据电压写入TFT,饱和放电模块包括第四薄膜晶体管T4,T4为饱和放电TFT,初始化模块包括第五薄膜晶体管T5,T5为初始化TFT,发光控制模块包括第六薄膜晶体管T6,T6为发光控制TFT,所述驱动薄膜晶体管T1和薄膜晶体管T2~T6为具有耗尽特性的N型TFT;还包括存储电容C1、耦合电容C2,有机发光二极管D1。其中,所示GN-1为上一行栅极(Gate)信号,GN为本行Gate信号,S1为第一控制信号,S2为第二控制信号,VSS为第二电源,VDD为第一电源。本发明实施例所述放电节点即图5中的P点。
具体地,T2的源极与所述存储电容C1的第一端、所述耦合电容C1的第二端以及所述驱动薄膜晶体管T1的栅极相连,T2的栅极接上一行栅极信号GN-1,T2的漏极与初始电压信号端连结,本发明实施例一中的初始电压信号端为数据电压信号端VDATA。
T3的栅极连接本行栅极信号GN,T3的漏极与驱动薄膜晶体管T1的源极连接,T3源极与数据电压信号端VDATA连接。
T4的漏极与所述耦合电容C2的第一端相连,T4的栅极与第一控制信号线S1连接,T4的源极与所述驱动薄膜晶体管T1的漏极连接。
T5的源极与所述驱动薄膜晶体管T1的源极连接,T5的栅极与第二控制信号线S2连接,T5的漏极和所述存储电容C1的第二端共同连接第二电源VSS。
T6的源极与所述驱动薄膜晶体管T1的漏极连接,T6的栅极与第二控制信号S2连接;T6的漏极与所述有机发光二极管的一端连接,所述有机发光二极管的另一端与第一电源VDD连接。
图6为本发明实施例二所述耗尽型TFT的AMOLED像素驱动电路结构图,如图6所示,包括:驱动薄膜晶体管T1、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块;其中,栅极初始电压写入模块包括第二薄膜晶体管T2,T2为栅极初始电压写入TFT,数据电压写入模块包括第三薄膜晶体管T3,T3为数据电压写入TFT,饱和放电模块包括第四薄膜晶体管T4,T4为饱和放电TFT,初始化模块包括第五薄膜晶体管T5,T5为初始化TFT,发光控制模块包括第六薄膜晶体管T6,T6为发光控制TFT,所述驱动薄膜晶体管T1和薄膜晶体管T2~T6为具有耗尽特性的N型TFT;还包括存储电容C1、耦合电容C2,有机发光二极管D1。其中,所示GN-1为上一行栅极(Gate)信号,GN为本行Gate信号,S1为第一控制信号,S2为第二控制信号,VSS为第二电源,VDD为第一电源。图6中的所述P点即为本发明实施例所述的放电节点。
本实施例与实施例一的区别仅在于:所述T2的漏极与初始电压信号端VINI连接其他的连接关系完全相同,此处不再描述。
本发明还提供了AMOLED像素驱动电路的驱动方法,该像素驱动电路包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;所述驱动方法包括:
初始化阶段:
所述栅极初始电压写入模块将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动晶体管的源极与第二电源连通;第二电源对所述存储电容的第二端充电;所述发光控制模块将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通;第一电源通过所述有机发光二极管对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极连通,将数据电压信号写入所述驱动晶体管的源极;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源断开;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极断开;所述饱和放电模块将所述耦合电容的第一端与所述驱动晶体管的漏极连通;所述存储电容和耦合电容通过所述驱动薄膜晶体管放电;
发光阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源连通;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极断开;所述驱动晶体管为所述有机发光二极管提供驱动电流。
其中,所述栅极初始电压写入模块包括第二薄膜晶体管;所述数据电压写入模块包括第三薄膜晶体管;所述饱和放电模块包括第四薄膜晶体管;所述初始化模块包括第五薄膜晶体管;所述发光控制模块包括第六薄膜晶体管;所述驱动方法包括:
初始化阶段具体为:
所述第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管导通,所述第三薄膜晶体管截止;将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;第二电源对所述存储电容的第二端充电;第一电源对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段具体为:
第三薄膜晶体管和第四薄膜晶体管导通,第二薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管截止;将数据电压信号写入到所述驱动薄膜晶体管的源极;所述存储电容和耦合电容通过所述驱动晶体管放电;
发光阶段具体为:
第五薄膜晶体管和第六薄膜晶体管导通,第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管截止;所述驱动薄膜晶体管为所述发光二极管提供驱动电流。
下面结合一个具体实施例对所述驱动方法进行详细描述,图7为本发明实施例AMOELD像素驱动电路的工作时序图,其中,所示a为初始化阶段,所示b为阈值电压补偿和数据电压写入阶段,所示c为发光阶段。具体的,
a)初始化阶段:如图8(a)所示,GN-1、S1和S2为高电平,GN为低电平,所示DATA为数据电压VDATA,以初始电压信号为VDATA为例,,VSS<VDATA<VDD,T2、T4、T5和T6导通,T3截止。存储电容C1接T1的栅极的第一端充电为VDATA,第二端充电为VSS,则存储电容C1两端电压差为VDATA-VSS,耦合电容C2第一端为VDD,第二端为VDATA,耦合电容C2两端电压差为VDD-VDATA。
b)阈值电压补偿和数据电压写入阶段:如图8(b)所示,GN-1和S2为低电平,S1和GN为高电平,DATA为数据电压VDATA,以初始电压信号为VDATA为例,VSS<VDATA<VDD,T3和T4导通,T2、T5和T6截止。初始存储在C1和C2上的电压通过T1放电,即T1漏极从高电平VDD放电下降,由于C2的耦合作用,T1的栅极也从VDATA开始下降。设T1漏极电压变化为△V,则T1栅极的电压变化为[C2/(C1+C2)]*△V。
T1的漏极放电直至T1的栅极电压VGS≤VTH,即:VDATA-VDATA-[C2/(C1+C2)]*△V=VTH,同时,为保证T1不会因为源漏电压为零而提前截止,从而失去阈值电压补偿,则VDD-VDATA-△V>0。所以,只要满足条件:VDD-VDATA>[(C1+C2)/C2]*VTH,即可实现阈值电压补偿。这样,存储电容C1与T1栅极相连的第一端的电平为VDATA+VTH,存储电容C1的第二端电平为VSS,即存储电容C1的两端电压差为VDATA-VSS+VTH。
c)发光阶段:如图8(c)所示,S2为高电平,S1、GN和GN-1为低电平,T5和T6导通,T2、T3和T4截止,T1的栅源电压VGS=VDATA-VSS+VTH。因此,T1的漏电流为:
IDS=0.5k*(VDATA-VSS+VTH-VTH)2=0.5k*(VDATA-VSS)2。D1在T1漏电流驱动下发光显示。同时,T1的漏电流与阈值电压无关,可实现对T1阈值电压的补偿。其中,所述k为薄膜晶体管的电流系数。
对于初始电压信号为VINI的情况,VSS<VINI<VDD,T1阈值电压的补偿原理与初始电压信号为VDATA的情况类似,在阈值电压补偿和写入阶段,T1的漏极放电直至T1的栅极电压VGS≤VTH,即:VINI-VDATA-[C2/(C1+C2)]*△V=VTH,同时,为保证T1不会因为源漏电压为零而提前截止,从而失去阈值电压补偿,则VDD-VDATA-△V>0。所以,只要满足条件:VDD-VDATA>[(C1+C2)/C2]*(VINI-VDATA-VTH),即可实现阈值电压补偿。
本发明还提供了一种阵列基板,包括:沿列延伸排列的多条数据线,沿行延伸排列的多条第一扫面线、第二扫面线和信号控制线,以矩阵形式布置在数据线和扫面线交叉位置处的多个像素;所述像素包括上文所述的像素驱动电路。
本发明还提供了一种显示面板,所述显示面板包括上文所述的阵列基板。
本发明还提供了一种显示装置,所述显示装置包括上文所述的显示面板。所述显示装置可为电子纸、手机、数码相框等显示设备。
以上所述,仅为本发明的较佳实施例而已,并非用于限定本发明的保护范围。
Claims (11)
1.一种AMOLED像素驱动电路,其特征在于,包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;
所述栅极初始电压写入模块,用于将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;
所述数据电压写入模块,用于数据电压信号写入所述驱动薄膜晶体管的源极;
所述初始化模块,用于将所述驱动薄膜晶体管的源极与第二电源连通或断开;
所述发光控制模块,用于将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通或断开;
所述饱和放电模块,用于将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通或断开;
其中,所述存储电容的第二端连接第二电源,所述有机发光二极管的另一端与第一电源连接。
2.根据权利要求1所述的像素驱动电路,其特征在于,所述栅极初始电压写入模块包括第二薄膜晶体管,所述第二薄膜晶体管的源极与所述存储电容的第一端、所述耦合电容的第二端以及所述驱动薄膜晶体管的栅极相连,第二薄膜晶体管的栅极接上一行栅极信号,所述第二薄膜晶体管的漏极与初始电压信号端连结。
3.根据权利要求2所述的像素驱动电路,其特征在于,所述数据电压写入模块包括第三薄膜晶体管,第三薄膜晶体管的栅极连接本行栅极信号,第三薄膜晶体管的漏极与所述驱动薄膜晶体管的源极连接,第三薄膜晶体管的源极与数据电压信号端连接。
4.根据权利要求3所述的像素驱动电路,其特征在于,所述饱和放电模块包括第四薄膜晶体管,所述第四薄膜晶体管的漏极与所述耦合电容的第一端相连,所述第四薄膜晶体管的栅极与第一控制信号线连接,所述第四薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接。
5.根据权利要求4所述的像素驱动电路,其特征在于,所述初始化模块包括第五薄膜晶体管,所述第五薄膜晶体管的源极与所述驱动薄膜晶体管的源极连接,所述第五薄膜晶体管的栅极与第二控制信号线连接,所述第五薄膜晶体管的漏极和所述存储电容的第二端共同连接第二电源。
6.根据权利要求5所述的像素驱动电路,其特征在于,所述发光控制模块包括第六薄膜晶体管,所述第六薄膜晶体管的源极与所述驱动薄膜晶体管的漏极连接,所述第六薄膜晶体管的栅极与第二控制信号连接;所述第六薄膜晶体管的漏极与所述有机发光二极管的所述一端连接。
7.根据权利要求6所述的像素驱动电路,其特征在于,所述驱动薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管为耗尽型N型薄膜晶体管。
8.根据权利要求1所述的像素驱动电路,其特征在于,所述初始电压信号为数据电压信号。
9.一种阵列基板,其特征在于,包括权利要求1-8中任一项所述的像素驱动电路。
10.一种AMOLED像素驱动电路的驱动方法,该像素驱动电路包括:驱动薄膜晶体管、栅极初始电压写入模块、数据电压写入模块、饱和放电模块、初始化模块、发光控制模块、存储电容、耦合电容、有机发光二极管;所述驱动方法包括:
初始化阶段:
所述栅极初始电压写入模块将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动晶体管的源极与第二电源连通;第二电源对所述存储电容的第二端充电;所述发光控制模块将所述有机发光二极管的一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极连通;第一电源通过所述有机发光二极管对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极连通,将数据电压信号写入所述驱动晶体管的源极;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源断开;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极断开;所述饱和放电模块将所述耦合电容的第一端与所述驱动晶体管的漏极连通;所述存储电容和耦合电容通过所述驱动薄膜晶体管放电;
发光阶段:
所述栅极初始电压写入模块将初始电压信号端与所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端断开;所述数据电压写入模块将数据电压信号端与所述驱动薄膜晶体管的源极断开;所述初始化模块将所述驱动薄膜晶体管的源极与第二电源连通;所述发光控制模块将所述有机发光二极管的所述一端与所述驱动薄膜晶体管的漏极连通;所述饱和放电模块将所述耦合电容的第一端与所述驱动薄膜晶体管的漏极断开;所述驱动晶体管为所述有机发光二极管提供驱动电流。
11.根据权利要求10所述的驱动方法,所述栅极初始电压写入模块包括第二薄膜晶体管;所述数据电压写入模块包括第三薄膜晶体管;所述饱和放电模块包括第四薄膜晶体管;所述初始化模块包括第五薄膜晶体管;所述发光控制模块包括第六薄膜晶体管;所述驱动方法包括:
初始化阶段具体为:
所述第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管导通,所述第三薄膜晶体管截止;将初始电压信号写入所述驱动薄膜晶体管的栅极、存储电容第一端、耦合电容第二端;第二电源对所述存储电容的第二端充电;第一电源对所述耦合电容的第一端充电;
阈值电压补偿和数据电压写入阶段具体为:
第三薄膜晶体管和第四薄膜晶体管导通,第二薄膜晶体管、第五薄膜晶体管和第六薄膜晶体管截止;将数据电压信号写入到所述驱动薄膜晶体管的源极;所述存储电容和耦合电容通过所述驱动晶体管放电;
发光阶段具体为:
第五薄膜晶体管和第六薄膜晶体管导通,第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管截止;所述驱动薄膜晶体管为所述发光二极管提供驱动电流。
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