WO2015041189A1 - Procédé de fabrication d'un substrat multicouche de câblage, et dispositif de modélisation tridimensionnelle utilisé pour celui-ci - Google Patents

Procédé de fabrication d'un substrat multicouche de câblage, et dispositif de modélisation tridimensionnelle utilisé pour celui-ci Download PDF

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Publication number
WO2015041189A1
WO2015041189A1 PCT/JP2014/074338 JP2014074338W WO2015041189A1 WO 2015041189 A1 WO2015041189 A1 WO 2015041189A1 JP 2014074338 W JP2014074338 W JP 2014074338W WO 2015041189 A1 WO2015041189 A1 WO 2015041189A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring layer
wiring board
multilayer wiring
insulating material
conductive material
Prior art date
Application number
PCT/JP2014/074338
Other languages
English (en)
Japanese (ja)
Inventor
新井　義之
岩出　卓
Original Assignee
東レエンジニアリング株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 東レエンジニアリング株式会社 filed Critical 東レエンジニアリング株式会社
Publication of WO2015041189A1 publication Critical patent/WO2015041189A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H05K3/125—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/013—Inkjet printing, e.g. for printing insulating material or resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting

Definitions

  • a method of forming a circuit shape by a photolithographic technique is known in a method for manufacturing a wiring board having a circuit made of a conductor such as copper wiring.
  • the circuit on the wiring substrate is formed by applying a photosensitive resist on a metal film formed on the surface of the insulating substrate, exposing and developing through a photomask, and dry etching the exposed film portion.
  • a photosensitive resist on a metal film formed on the surface of the insulating substrate, exposing and developing through a photomask, and dry etching the exposed film portion.
  • the present invention further includes a polishing step of polishing the surface of the wiring layer.
  • the present invention further includes a polishing step of polishing the surface of the wiring layer.
  • the wiring layer forming step is further performed on a support substrate having a flat surface.
  • the curing device is a combination of two types of curing devices, a photocuring device and a thermosetting device.
  • the present invention is a three-dimensional modeling apparatus used for manufacturing a multilayer wiring board in which a wiring layer composed of a conductive portion and an insulating portion is laminated, and discharges either a modeling stage and a conductive material or an insulating material.
  • Nozzle, coating device for applying either conductive material or insulating material, curing device for curing conductive material and insulating material, driving device for driving nozzle, coating device, and curing device And a control device having a function of controlling the modeling stage, the nozzle, the coating device, the curing device, and the driving device.
  • the modeling stage 7 constitutes a modeling space for the multilayer wiring board.
  • the modeling stage 7 includes a modeling table 8 and a driving device 9.
  • the modeling table 8 is composed of a substantially rectangular plate member.
  • the modeling table 8 is configured so that the conductive material and the insulating material can be discharged from the discharge device 2 onto the table.
  • the modeling stage 7 is configured such that the modeling table 8 is moved by the drive device 9 in the Z direction orthogonal to the X direction and the Y direction.
  • step S140 the control device 10 has the same Z coordinate among the calculated spatial coordinates S (X (i), Y (j), Z (k)) (for example, Z (a), where a is a constant).
  • the conductive material and the insulating material are respectively discharged from the conductive material discharge nozzle 3 and the insulating material discharge nozzle 4 to each spatial coordinate S (X (i), Y (j), Z (a)).
  • the control device 10 irradiates a laser beam composed of ultraviolet light from the curing device 5. That is, the control device 10 discharges the conductive material and the insulating material at predetermined positions on the same XY plane, and irradiates the conductive material and the insulating material with ultraviolet light, and the process proceeds to step S150.
  • the control device 10 moves the XY coordinates in step S260 and then proceeds to step S140 (step S440 in FIG. 10).
  • the method for manufacturing a multilayer wiring board according to the present invention includes a wiring layer forming step, a wiring layer laminating step, a one-side terminal forming step, a base material peeling step, and an other-side terminal forming step.
  • a wiring film composed of the conductive portion 13 and the insulating portion 14 in which the conductive material and the insulating material are deposited on the support substrate 12 by the deposition thickness D is formed.
  • a material such as metal, glass, plastic, or the like can be used.
  • a release layer having releasability with respect to the wiring layer is formed on the surface of the support substrate 12, and the releasability of the release layer with respect to the wiring layer is expressed by light irradiation or a chemical solution. May be.
  • FIG. 5 (b) it is formed on the support substrate 12 of the modeling table 8 based on the calculated spatial coordinates S (X (i), Y (j), Z (k)) and the ejection command.
  • a conductive material is discharged by the three-dimensional modeling apparatus 1 onto the conductive portion 13 that has been formed.
  • the insulating material is discharged by the three-dimensional modeling apparatus 1 onto the insulating portion 14 formed on the support substrate 12 of the modeling table 8.
  • the conductive portion 13 in which the conductive material is deposited by the deposition thickness D is formed on the conductive portion 13, and the insulating portion in which the insulating material is deposited by the deposition thickness D on the insulating portion 14.
  • connection terminal 15 made of a conductive material is formed by the three-dimensional modeling apparatus 1.
  • the multilayer wiring board is discharged to a predetermined position on the final wiring layer by the three-dimensional modeling apparatus 1 until the conductive material reaches a predetermined deposition thickness by a deposition thickness D.
  • the conductive portion 13 in which the conductive material is deposited at a predetermined deposition thickness is formed as a connection terminal 15 at a predetermined position on the wiring layer of the final layer.
  • the control device 10 is connected to the polishing device 17 and can control the positions of the driving device 6 in the X and Y directions and the polishing amount.
  • the control device 10 configured as described above controls the polishing device 17 based on the spatial coordinates S (X (i), Y (j), Z (k)) calculated by the spatial coordinate calculation program.
  • the three-dimensional modeling apparatus 1 manufactures an arbitrary modeled object by discharging, depositing, and curing a conductive material and an insulating material that are modeling materials.
  • the three-dimensional modeling apparatus 1 includes a coating device 18.
  • control mode of the three-dimensional modeling apparatus 1 in the third embodiment of the method for manufacturing a multilayer wiring board according to the present invention will be specifically described with reference to FIG.
  • step S ⁇ b> 470 the control device 10, other than the portion where one material of the conductive material and the insulating material is applied in one layer formed on the modeling table 8 of the modeling stage 7 by the coating device 18.
  • the other material of the conductive material and the insulating material is applied to the portion and cured, and the process proceeds to step S390.
  • a polishing step for polishing the surface of the wiring layer may be further included.
  • the multilayer wiring board is formed in each layer from the surface of the support substrate 12 or the immediately polished layer to the polishing position of the polishing device 17 in the three-dimensional modeling apparatus 1.
  • the wiring layer is disposed at a predetermined position equal to the thickness Thn (see FIG. 9A).
  • the surface of the first layer of the multilayer wiring board is polished by the polishing apparatus 17 of the three-dimensional modeling apparatus 1 (see FIG. 9B).
  • the deposition thickness of each layer is maintained within a predetermined range, and the surface roughness of each layer is maintained within a predetermined range (see FIG. 9C).

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　L'invention concerne un procédé de fabrication d'un substrat multicouche de câblage caractérisé en ce que le processus de production peut être simplifié et en ce que le coût de production peut être réduit, et un dispositif de modélisation tridimensionnelle utilisé pour le procédé. Plus particulièrement, un procédé de fabrication d'un substrat multicouche de câblage obtenu en empilant des couches de câblage comportant une partie électriquement conductrice (13) et une partie isolante (14) comporte: une étape de formation de couches de câblage consistant à libérer un matériau électriquement conducteur ou un matériau isolant sur une position prédéterminée tout en effectuant un mouvement de balayage, provoquant l'accumulation du matériau libéré jusqu'à une épaisseur prédéterminée (Thn) et formant une couche de câblage; et une étape d'empilement de couches de câblage consistant à libérer un matériau électriquement conducteur ou un matériau isolant sur une position prédéterminée à la surface de the couche de câblage tout en effectuant un mouvement de balayage, provoquant l'accumulation du matériau libéré jusqu'à une épaisseur prédéterminée (Thn) et formant une couche de câblage supplémentaire.
PCT/JP2014/074338 2013-09-17 2014-09-16 Procédé de fabrication d'un substrat multicouche de câblage, et dispositif de modélisation tridimensionnelle utilisé pour celui-ci WO2015041189A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-192131 2013-09-17
JP2013192131 2013-09-17

Publications (1)

Publication Number Publication Date
WO2015041189A1 true WO2015041189A1 (fr) 2015-03-26

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329244A1 (en) * 2015-05-08 2016-11-10 Winbond Electronics Corp. Stacked Electronic Device and Method for Fabricating the Same
JP2016213464A (ja) * 2015-05-08 2016-12-15 華邦電子股▲ふん▼有限公司 積層パッケージ素子およびその製造方法
WO2016199242A1 (fr) * 2015-06-10 2016-12-15 富士機械製造株式会社 Dispositif de formation de motif de circuit
JP2017143102A (ja) * 2016-02-08 2017-08-17 富士機械製造株式会社 回路パターン形成装置、および回路パターン形成方法
WO2019016920A1 (fr) * 2017-07-20 2019-01-24 株式会社Ｆｕｊｉ Procédé et dispositif de formation de câblage
WO2019058515A1 (fr) * 2017-09-22 2019-03-28 株式会社Ｆｕｊｉ Procédé de formation de couche semi-durcie et dispositif de formation de couche semi-durcie
WO2019123629A1 (fr) * 2017-12-22 2019-06-27 株式会社Ｆｕｊｉ Procédé et dispositif de fabrication d'un dispositif électronique fabriqué de manière additive
JP2019527463A (ja) * 2016-03-26 2019-09-26 ナノ−ディメンション テクノロジーズ，リミテッド ３ｄインクジェット印刷を用いた、シールドされたトラックおよび／または構成要素を有するｐｃｂおよびｆｐｃの製造
CN111107718A (zh) * 2018-10-26 2020-05-05 康达智株式会社 多层基板形成方法以及多层基板形成装置
WO2020255258A1 (fr) * 2019-06-18 2020-12-24 株式会社Ｆｕｊｉ Procédé de fabrication de carte de circuit imprimé et dispositif de fabrication de carte de circuit imprimé
JP7491761B2 (ja) 2020-07-20 2024-05-28 ローランドディー．ジー．株式会社 三次元造形装置および三次元造形装置用の帯電捕集装置
JP7495870B2 (ja) 2020-11-17 2024-06-05 株式会社Fuji 造形方法及び造形装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051567A (ja) * 2001-08-03 2003-02-21 Sony Corp 高周波モジュール用基板装置及びその製造方法、並びに高周波モジュール装置及びその製造方法
JP2007158352A (ja) * 2005-12-07 2007-06-21 Samsung Electro Mech Co Ltd 配線基板の製造方法及び配線基板
JP2007329452A (ja) * 2006-05-09 2007-12-20 Canon Inc 配線モジュール、配線モジュールの製造装置および配線モジュールの製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051567A (ja) * 2001-08-03 2003-02-21 Sony Corp 高周波モジュール用基板装置及びその製造方法、並びに高周波モジュール装置及びその製造方法
JP2007158352A (ja) * 2005-12-07 2007-06-21 Samsung Electro Mech Co Ltd 配線基板の製造方法及び配線基板
JP2007329452A (ja) * 2006-05-09 2007-12-20 Canon Inc 配線モジュール、配線モジュールの製造装置および配線モジュールの製造方法

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329244A1 (en) * 2015-05-08 2016-11-10 Winbond Electronics Corp. Stacked Electronic Device and Method for Fabricating the Same
JP2016213464A (ja) * 2015-05-08 2016-12-15 華邦電子股▲ふん▼有限公司 積層パッケージ素子およびその製造方法
US10483235B2 (en) * 2015-05-08 2019-11-19 Winbond Electronics Corp. Stacked electronic device and method for fabricating the same
JP2016213465A (ja) * 2015-05-08 2016-12-15 華邦電子股▲ふん▼有限公司 積層電子デバイスとその製造方法
JPWO2016199242A1 (ja) * 2015-06-10 2018-03-29 富士機械製造株式会社 回路パターン形成装置
WO2016199242A1 (fr) * 2015-06-10 2016-12-15 富士機械製造株式会社 Dispositif de formation de motif de circuit
JP2017143102A (ja) * 2016-02-08 2017-08-17 富士機械製造株式会社 回路パターン形成装置、および回路パターン形成方法
JP2019527463A (ja) * 2016-03-26 2019-09-26 ナノ−ディメンション テクノロジーズ，リミテッド ３ｄインクジェット印刷を用いた、シールドされたトラックおよび／または構成要素を有するｐｃｂおよびｆｐｃの製造
WO2019016920A1 (fr) * 2017-07-20 2019-01-24 株式会社Ｆｕｊｉ Procédé et dispositif de formation de câblage
JPWO2019016920A1 (ja) * 2017-07-20 2019-12-12 株式会社Ｆｕｊｉ 配線形成方法、および配線形成装置
JP7197489B2 (ja) 2017-09-22 2022-12-27 株式会社Fuji 硬化層と金属配線を有する構造物の形成方法及び構造物形成装置
WO2019058515A1 (fr) * 2017-09-22 2019-03-28 株式会社Ｆｕｊｉ Procédé de formation de couche semi-durcie et dispositif de formation de couche semi-durcie
JPWO2019058515A1 (ja) * 2017-09-22 2019-12-19 株式会社Ｆｕｊｉ 半硬化層の形成方法及び半硬化層形成装置
WO2019123629A1 (fr) * 2017-12-22 2019-06-27 株式会社Ｆｕｊｉ Procédé et dispositif de fabrication d'un dispositif électronique fabriqué de manière additive
JPWO2019123629A1 (ja) * 2017-12-22 2020-10-22 株式会社Ｆｕｊｉ ３次元積層電子デバイスの製造方法及び製造装置
JP7394626B2 (ja) 2017-12-22 2023-12-08 株式会社Fuji ３次元積層電子デバイスの製造方法及び製造装置
CN111107718A (zh) * 2018-10-26 2020-05-05 康达智株式会社 多层基板形成方法以及多层基板形成装置
JP7142781B2 (ja) 2019-06-18 2022-09-27 株式会社Fuji 配線基板の製造方法及び配線基板製造装置
JPWO2020255258A1 (fr) * 2019-06-18 2020-12-24
WO2020255258A1 (fr) * 2019-06-18 2020-12-24 株式会社Ｆｕｊｉ Procédé de fabrication de carte de circuit imprimé et dispositif de fabrication de carte de circuit imprimé
JP7491761B2 (ja) 2020-07-20 2024-05-28 ローランドディー．ジー．株式会社 三次元造形装置および三次元造形装置用の帯電捕集装置
JP7495870B2 (ja) 2020-11-17 2024-06-05 株式会社Fuji 造形方法及び造形装置

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