WO2015025723A1 - 固体撮像素子および電子機器 - Google Patents
固体撮像素子および電子機器 Download PDFInfo
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- WO2015025723A1 WO2015025723A1 PCT/JP2014/070842 JP2014070842W WO2015025723A1 WO 2015025723 A1 WO2015025723 A1 WO 2015025723A1 JP 2014070842 W JP2014070842 W JP 2014070842W WO 2015025723 A1 WO2015025723 A1 WO 2015025723A1
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- semiconductor substrate
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- photoelectric conversion
- state imaging
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Definitions
- the present disclosure relates to a solid-state imaging device suitable for a so-called longitudinal spectroscopic type and an electronic apparatus including the solid-state imaging device.
- CMOS Complementary Metal Oxide Semiconductor
- Patent Document 1 discloses a green photoelectric conversion element in which blue and red photodiodes are stacked in a semiconductor substrate and an organic photoelectric conversion film is used on the light receiving surface side (back surface side, first surface side) of the semiconductor substrate. A provided solid-state imaging device is described.
- Patent Document 1 when the electric charge generated in the green photoelectric conversion element is accumulated in the n-type semiconductor region on the wiring layer side (surface side, second surface side) of the semiconductor substrate through the conductive plug penetrating the semiconductor substrate.
- the conductive plug is important for transferring charges from the photoelectric conversion element on the first surface side of the semiconductor substrate to the second surface side of the semiconductor substrate and improving characteristics such as conversion efficiency. There was still room for discussion about the composition of.
- a first solid-state imaging device includes at least one photoelectric conversion element provided on the first surface side of the semiconductor substrate, and is connected to the at least one photoelectric conversion element.
- a through electrode provided between the first surface and the second surface; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, wherein at least one photoelectric conversion element is interposed through the through electrode.
- the amplifier transistor is connected to the gate and the floating diffusion.
- the electric charge generated in the photoelectric conversion element on the first surface side of the semiconductor substrate is transferred to the second surface side of the semiconductor substrate via the through electrode, and is floating. Accumulated in the diffusion.
- the amplifier transistor modulates the amount of charge generated in the photoelectric conversion element into a voltage.
- a second solid-state imaging device includes a photoelectric conversion element provided on a first surface side of a semiconductor substrate, a first surface and a second surface of the semiconductor substrate that are connected to the photoelectric conversion element. Between the through electrode, a separation groove provided between the penetration electrode and the semiconductor substrate, and a dielectric layer that fills the separation groove and has an insulating property.
- the through electrode and the semiconductor substrate are separated by the separation groove and the dielectric layer, the capacitance generated between the through electrode and the semiconductor substrate. And the characteristics such as conversion efficiency are improved.
- a third solid-state imaging device includes a photoelectric conversion element provided on the first surface side of the semiconductor substrate, a first surface and a second surface of the semiconductor substrate that are connected to the photoelectric conversion element.
- a through electrode provided between the through electrode and the semiconductor substrate, an outer dielectric layer covering the outer surface of the separation groove, and an inner side covering the inner surface of the separation groove A dielectric layer and a cavity provided between the outer dielectric layer and the inner dielectric layer are provided.
- the through electrode and the semiconductor substrate are separated by the separation groove, the outer dielectric layer, the inner dielectric layer, and the cavity.
- the capacitance generated between the two is reduced, and characteristics such as conversion efficiency are improved.
- a first electronic device includes a solid-state imaging element, and the solid-state imaging element includes at least one photoelectric conversion element provided on the first surface side of the semiconductor substrate, and at least one photoelectric conversion element.
- a through electrode connected to the photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate; The two photoelectric conversion elements are connected to the gate of the amplifier transistor and the floating diffusion through the through electrode.
- a second electronic device includes a solid-state imaging element, and the solid-state imaging element is connected to the photoelectric conversion element provided on the first surface side of the semiconductor substrate and the photoelectric conversion element.
- a through electrode provided between the first surface and the second surface of the semiconductor substrate, a separation groove provided between the through electrode and the semiconductor substrate, and a dielectric having an insulating property, filling the separation groove And a layer.
- a third electronic device includes a solid-state imaging element, and the solid-state imaging element is connected to the photoelectric conversion element provided on the first surface side of the semiconductor substrate and the photoelectric conversion element.
- a through electrode provided between the first surface and the second surface of the semiconductor substrate, a separation groove provided between the through electrode and the semiconductor substrate, and an outer dielectric layer covering the outer surface of the separation groove
- an inner dielectric layer covering the inner surface of the separation groove, and a cavity provided between the outer dielectric layer and the inner dielectric layer.
- imaging is performed by the first to third solid-state imaging elements according to the embodiment of the present disclosure.
- the photoelectric conversion element is floating with the gate of the amplifier transistor via the through electrode. I try to connect to the diffusion. Therefore, the charge generated in the photoelectric conversion element on the first surface side of the semiconductor substrate can be satisfactorily transferred to the second surface side of the semiconductor substrate through the through electrode, and the characteristics can be improved.
- the through electrode and the semiconductor substrate are separated by the separation groove and the dielectric layer. I am doing so. Therefore, it is possible to reduce the capacitance generated between the through electrode and the semiconductor substrate and improve characteristics such as conversion efficiency.
- the through electrode and the semiconductor substrate are separated by the separation groove, the outer dielectric layer, the inner side The dielectric layer and the cavity are separated. Therefore, it is possible to reduce the capacitance generated between the through electrode and the semiconductor substrate and improve characteristics such as conversion efficiency.
- FIG. 2 is a plan view illustrating a configuration in which four solid-state imaging devices illustrated in FIG. 1 are arranged. It is sectional drawing showing the manufacturing method of the solid-state image sensor shown in FIG. 1 in order of a process.
- FIG. 4 is a cross-sectional view illustrating a process following FIG. 3.
- FIG. 5 is a cross-sectional view illustrating a process following FIG. 4.
- FIG. 6 is a cross-sectional view illustrating a process following FIG. 5.
- FIG. 7 is a cross-sectional view illustrating a process following FIG. 6.
- FIG. 8 is a cross-sectional diagram illustrating a process following the process in FIG. 7.
- FIG. 11 is a cross-sectional diagram illustrating a process following the process in FIG. 10.
- FIG. 12 is a cross-sectional diagram illustrating a process following the process in FIG. 11.
- FIG. 13 is a cross-sectional diagram illustrating a process following the process in FIG. 12.
- FIG. 14 is a cross-sectional diagram illustrating a process following the process in FIG. 13.
- FIG. 15 is a cross-sectional view illustrating a process following FIG. 14.
- FIG. 16 is a cross-sectional diagram illustrating a process following the process in FIG. 15.
- FIG. 17 is a cross-sectional diagram illustrating a process following the process in FIG. 16.
- FIG. 18 is a cross-sectional diagram illustrating a process following the process in FIG. 17.
- 10 is a cross-sectional view illustrating a configuration of a solid-state imaging element according to Modification 1.
- FIG. It is sectional drawing showing the structure of the solid-state image sensor which concerns on 3rd Embodiment of this indication. It is sectional drawing showing the manufacturing method of the solid-state image sensor shown in FIG. 20 in order of a process.
- FIG. 22 is a cross-sectional diagram illustrating a process following the process in FIG. 21. It is sectional drawing showing the structure of the solid-state image sensor which concerns on 4th Embodiment of this indication.
- FIG. 10 It is sectional drawing showing 1 process of the manufacturing method of the solid-state image sensor shown in FIG. 10 is a cross-sectional view illustrating a configuration of a solid-state imaging element according to Modification 2.
- FIG. It is a functional block diagram of a solid-state imaging device. It is a functional block diagram of the electronic device which concerns on an application example.
- First embodiment solid-state imaging device; example in which a through electrode is made of a semiconductor and a cavity is provided in a separation groove around the through electrode
- Second Embodiment Solid-state imaging device; example in which a through electrode is made of metal and a cavity is provided in a separation groove around the through electrode
- Modification 1 example in which a thermal oxide film is provided on the outer surface of the separation groove
- Third Embodiment Solid-State Image Sensor; Example in which Through Electrode is Constructed of Semiconductor and Separation Groove around Through Electrode is Filled with Dielectric Layer 5.
- Solid-state imaging device an example in which a through electrode is made of metal and a separation groove around the through electrode is filled with a dielectric layer
- Modification 2 Example in which a thermal oxide film is provided on the outer surface of the separation groove
- 7. Whole configuration example of solid-state imaging device
- FIG. 1 illustrates a cross-sectional configuration of a solid-state imaging device 10 according to the first embodiment of the present disclosure.
- the solid-state imaging device 10 constitutes a pixel unit as an imaging pixel region in a solid-state imaging device (described later) such as a CMOS image sensor used in an electronic device such as a digital still camera or a video camera.
- the solid-state imaging device 10 is, for example, a so-called vertical spectroscopic type in which one photoelectric conversion device 20 and two photodiodes PD1 and PD2 are stacked in the thickness direction of the semiconductor substrate 30.
- the photoelectric conversion element 20 is provided on the first surface (back surface) 30 ⁇ / b> A side of the semiconductor substrate 30.
- the photodiodes PD1 and PD2 are provided in the semiconductor substrate 30 and are stacked in the thickness direction of the semiconductor substrate 30.
- the photoelectric conversion element 20 and the photodiodes PD1 and PD2 perform photoelectric conversion by selectively detecting light in different wavelength ranges. Specifically, the photoelectric conversion element 20 acquires a green (G) color signal.
- the photodiodes PD1 and PD2 obtain blue (B) and red (R) color signals, respectively, depending on the difference in absorption coefficient. Thereby, in this solid-state image sensor 10, a plurality of types of color signals can be acquired in one pixel without using a color filter.
- the multilayer wiring 40 has a configuration in which, for example, wiring layers 41, 42, and 43 are stacked in an insulating film 44.
- the first surface 30A side of the semiconductor substrate 30 is represented as the light incident side S1
- the second surface 30B side is represented as the wiring layer side S2.
- the photoelectric conversion element 20 has, for example, a configuration in which a lower transparent electrode 21, a photoelectric conversion film 22, and an upper transparent electrode 23 are stacked in this order from the first surface 30A side of the semiconductor substrate 30. .
- the transparent electrode 21 is separated for each photoelectric conversion element 20.
- the photoelectric conversion film 22 and the transparent electrode 23 are provided as a continuous layer common to the plurality of photoelectric conversion elements 20.
- a film 24 having a fixed charge, an insulating dielectric layer 25, and an interlayer insulating film 26 are provided between the first surface 30 ⁇ / b> A of the semiconductor substrate 30 and the transparent electrode 21, for example.
- a film 24 having a fixed charge, an insulating dielectric layer 25, and an interlayer insulating film 26 are provided.
- a protective film 27 is provided on the transparent electrode 23. Above the protective film 27, an optical member such as a flat film and an on-chip lens (both not shown) are disposed.
- a through electrode 50 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30.
- the photoelectric conversion element 20 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3 through the through electrode 50.
- the charges generated in the photoelectric conversion element 20 on the first surface 30 ⁇ / b> A side of the semiconductor substrate 30 are favorably transferred to the second surface 30 ⁇ / b> B side of the semiconductor substrate 30 through the through electrode 50. It is possible to enhance the characteristics.
- the through electrode 50 has a function as a connector between the photoelectric conversion element 20 and the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3, and serves as a transmission path for charges (here, electrons) generated in the photoelectric conversion element 20. is there.
- the lower end of the through electrode 50 is connected to the connection portion 41 ⁇ / b> A in the wiring layer 41 of the multilayer wiring 40, for example, via the lower first contact 51.
- the connection portion 41A and the gate Gamp of the amplifier transistor AMP are connected by the lower second contact 52.
- the connecting portion 41A and the floating diffusion FD3 are connected by a lower third contact 53.
- the upper end of the through electrode 50 is connected to the lower transparent electrode 21 via the upper contact 54, for example.
- FIG. 2 illustrates a planar configuration of the solid-state imaging device 10 as viewed from the second surface 30B side of the semiconductor substrate 30, and a plurality of (for example, four in FIG. 2) photoelectric conversion elements 20 are arranged in two rows ⁇ An example in which two rows are arranged is shown.
- the through electrode 50 is preferably provided for each of the plurality of photoelectric conversion elements 20. That is, as the transparent electrode 21 below the photoelectric conversion element 20 is separated for each of the plurality of photoelectric conversion elements 20, the through electrode 50 is also provided for each of the plurality of photoelectric conversion elements 20. .
- a reset gate Grst of the reset transistor RST is arranged next to the floating diffusion FD3. As a result, the charge accumulated in the floating diffusion FD3 can be reset by the reset transistor RST.
- FIG. 2 shows only the amplifier transistor AMP and the reset transistor RST that handle charges from the photoelectric conversion element 20.
- the transfer transistors Tr1 and Tr2 related to the photodiodes PD1 and PD2 are appropriately installed in a vacant region.
- the through electrode 50 is made of, for example, the same semiconductor as the semiconductor substrate 30, for example, silicon (Si), and the resistance value is reduced by implanting N-type or P-type impurities (for example, P + in FIG. 1). It is preferable. Further, high-concentration impurity regions (for example, P ++ in FIG. 1) are provided at the upper end portion and the lower end portion of the through electrode 50, and the connection resistance with the upper contact 54 and the connection resistance with the lower first contact 51 are further reduced. It is preferable.
- the outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 are covered with a dielectric layer 25 having insulating properties.
- the dielectric layer 25 includes, for example, an outer dielectric layer 25A that covers the outer surface 61 of the separation groove 60 and an inner dielectric layer 25B that covers the inner surface 62 of the separation groove 60.
- a cavity 70 is preferably provided between the outer dielectric layer 25A and the inner dielectric layer 25B. That is, the separation groove 60 has an annular shape or an annular shape, and the cavity 70 has an annular shape or an annular shape that is concentric with the separation groove 60.
- the through electrode 50 is made of a conductive material such as P + silicon, and the dielectric layer 25 is provided between the through electrode 50 and the semiconductor substrate 30. Since the through electrode 50 penetrates the semiconductor substrate 30 and is connected to the amplifier transistor AMP and the floating diffusion FD3, it is desirable to reduce the capacitance generated between the through electrode 50 and the semiconductor substrate 30. In order to reduce the capacitance, the following three measures can be considered. The first is to reduce the area of the side wall of the through electrode 50. The second is to increase the distance d between the through electrode 50 and the semiconductor substrate 30. The third is to lower the dielectric constant of the insulator between the through electrode 50 and the semiconductor substrate 30.
- the area of the side wall of the first through electrode 50 can be reduced by reducing the thickness of the semiconductor substrate 30 or reducing the diameter of the through electrode 50.
- the regions of the photodiodes PD1 and PD2 may be reduced, and the difficulty of processing the semiconductor substrate 30 may be increased.
- An increase in the distance d between the second through electrode 50 and the semiconductor substrate 30 is a relatively easy response, but leads to an increase in the element area.
- the third correspondence that is, the dielectric constant of the insulator between the through electrode 50 and the semiconductor substrate 30 is lowered. is there. Gases such as hydrogen and nitrogen exist in the cavity 70, but the dielectric constant is lower than that of a solid dielectric such as a TEOS (Tetraethyl orthosilicate) film, and is close to the dielectric constant of a vacuum. Therefore, the capacity between the through electrode 50 and the semiconductor substrate 30 can be dramatically reduced.
- TEOS Tetraethyl orthosilicate
- the size variation of the cavity 70 is preferably as small as possible in the solid-state imaging device 10 or in the wafer, for example, plus or minus 10% or less. This is because the capacitance between the through electrode 50 and the semiconductor substrate 30 is sensitive to the size of the cavity 70.
- impurity regions (N type or P type) of the same conductivity type (N type or P type) as the through electrode 50 are formed in the semiconductor substrate 30 on the outer surface 61 of the separation groove 60.
- P + is preferably provided.
- the film 24 having a fixed charge is provided on the outer surface 61, the inner surface 62 and the bottom surface 63 of the separation groove 60, and the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
- a P-type impurity region (P + in FIG. 1) is provided in the semiconductor substrate 30 on the outer surface 61 of the separation groove 60, and a film having a negative fixed charge is used as the film 24 having a fixed charge. It is preferable to provide it. As a result, dark current can be reduced.
- the through electrode 50 and the separation groove 60 are provided for each photoelectric conversion device 20 in a state of being close to the photodiodes PD1 and PD2 in the semiconductor substrate 30.
- the surface of the through electrode 50 and the separation groove 60 is a surface processed by dry etching or the like, and therefore generally has many defect levels. For this reason, the dark current and white spots of the photodiodes PD1 and PD2 adjacent to the through electrode 50 and the separation groove 60 may increase.
- a P-type impurity region (P + in FIG. 1) is provided in the semiconductor substrate 30 on the outer surface 61 of the separation groove 60, and the film 24 having a fixed charge is negative.
- a film having a fixed charge is provided.
- a hole accumulation (hole accumulation) layer is formed on the outer surface 61 of the separation groove 60 by an electric field induced by the film 24 having a negative fixed charge. The hole accumulation layer suppresses the generation of electrons from the outer surface 61 of the separation groove 60. Further, even when charges (electrons) are generated from the outer surface 61 of the separation groove 60, the generated electrons disappear in the hole accumulation layer in the middle of diffusion, so that the dark current is reduced.
- the photoelectric conversion element 20 photoelectrically converts green light corresponding to a part or all of the wavelength range of 495 nm to 570 nm, for example.
- the transparent electrodes 21 and 23 are made of, for example, a light-transmitting conductive film, and are made of, for example, ITO (indium tin oxide).
- the photoelectric conversion film 22 is an organic film made of an organic photoelectric conversion material that photoelectrically converts light in a selective wavelength range and transmits light in other wavelength ranges.
- the photoelectric conversion film 22 is made of an organic photoelectric conversion material containing, for example, a rhodamine dye, a melocyanine dye, quinacridone, or the like.
- the photoelectric conversion element 20 may be provided with other layers (not shown) such as a base layer, an electron block layer, and a buffer layer.
- the film 24 having a fixed charge may be a film having a positive fixed charge or a film having a negative fixed charge.
- Examples of the material of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide.
- An yttrium, aluminum nitride film, hafnium oxynitride film, or aluminum oxynitride film is also possible.
- the film 24 having a fixed charge may have a structure in which two or more kinds of films are stacked. Thereby, for example, in the case of a film having a negative fixed charge, the function as a hole accumulation layer can be further enhanced.
- the material of the dielectric layer 25 is not particularly limited, but includes, for example, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film.
- the interlayer insulating film 26 is made of, for example, a silicon oxide film.
- the protective film 27 is made of, for example, a silicon nitride film.
- the semiconductor substrate 30 is composed of, for example, an n-type silicon (Si) substrate and has a p-well 31 in a predetermined region. On the second surface 30B of the p-well 31, the above-described vertical transistor Tr1, transfer transistor Tr2, amplifier transistor AMP, reset transistor RST, and the like are provided. In addition, a peripheral circuit (not shown) including a logic circuit or the like is provided in the peripheral portion of the semiconductor substrate 30.
- the photodiodes PD1 and PD2 each have a PN junction in a predetermined region of the semiconductor substrate 30.
- the photodiodes PD1 and PD2 are capable of dispersing light in the vertical direction by utilizing the fact that the wavelength of light absorbed in the silicon substrate varies depending on the incident depth of light.
- the photodiode PD1 selectively detects blue light and accumulates signal charges corresponding to blue light, and is installed at a depth at which blue light can be efficiently photoelectrically converted.
- the photodiode PD2 selectively detects red light and accumulates signal charges corresponding to red, and is installed at a depth at which red light can be efficiently photoelectrically converted.
- blue (B) is a color corresponding to a wavelength range of 450 nm to 495 nm
- red (R) is a color corresponding to a wavelength range of 620 nm to 750 nm, for example, and the photodiodes PD1 and PD2 are It is only necessary to be able to detect light in a part or all of the wavelength region.
- the photodiode PD1 is configured to include, for example, a P + region serving as a hole storage layer and an N region serving as an electron storage layer.
- the photodiode PD2 has, for example, a P + region serving as a hole storage layer and an N region serving as an electron storage layer (having a PNP stack structure).
- the N region of the photodiode PD1 is connected to the vertical transistor Tr1.
- the P + region of the photodiode PD1 is bent along the vertical transistor Tr1 and connected to the P + region of the photodiode PD2.
- the vertical transistor Tr1 is a transfer transistor that transfers signal charges (electrons in the present embodiment) corresponding to blue generated and accumulated in the photodiode PD1 to the floating diffusion FD1. Since the photodiode PD1 is formed at a deep position from the second surface 30B of the semiconductor substrate 30, it is preferable that the transfer transistor of the photodiode PD1 is composed of a vertical transistor Tr1.
- the transfer transistor Tr2 transfers signal charges (electrons in the present embodiment) generated and accumulated in the photodiode PD2 corresponding to red to the floating diffusion FD2, and is configured by, for example, a MOS transistor. .
- the amplifier transistor AMP is a modulation element that modulates the amount of charge generated in the photoelectric conversion element 20 into a voltage, and is composed of, for example, a MOS transistor.
- the reset transistor RST resets the charge transferred from the photoelectric conversion element 20 to the floating diffusion FD3, and is configured by, for example, a MOS transistor.
- the lower first to third contacts 51 to 53 and the upper contact 54 are, for example, doped silicon materials such as PDAS (Phosphorus Doped Amorphous Silicon), or metal materials such as aluminum, tungsten, titanium, cobalt, hafnium, tantalum, and the like. It is comprised by.
- doped silicon materials such as PDAS (Phosphorus Doped Amorphous Silicon)
- metal materials such as aluminum, tungsten, titanium, cobalt, hafnium, tantalum, and the like. It is comprised by.
- the solid-state image sensor 10 can be manufactured as follows, for example.
- 3 to 8 show the manufacturing method of the solid-state imaging device 10 in the order of steps.
- a p-well 31 is formed as a first conductivity type well in the semiconductor substrate 30, and a second conductivity type (for example, N-type) photo is formed in the p-well 31.
- Diodes PD1 and PD2 are formed.
- a P + region is formed in the vicinity of the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
- an impurity region (P + region) penetrating from the first surface 30A to the second surface 30B of the semiconductor substrate 30 is formed in a region where the through electrode 50 and the separation groove 60 are to be formed. Further, high-concentration impurity regions (P ++ regions) are formed in regions where the upper and lower end portions of the through electrode 50 are to be formed.
- the N + region to be the floating diffusions FD1 to FD3 is formed on the second surface 30B of the semiconductor substrate 30, and then the gate insulating film 32, the vertical transistor Tr1, the transfer transistor Tr2, and the amplifier A gate wiring 33 including the gates of the transistor AMP and the reset transistor RST is formed. Thereby, the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST are formed. Further, the multilayer wiring 40 including the lower first to third contacts 51 to 53, the wiring layers 41 to 43 including the connection portion 41A, and the insulating film 44 is formed on the second surface 30B of the semiconductor substrate 30.
- an SOI (Silicon On Insulator) substrate in which a semiconductor substrate 30, a buried oxide film (not shown), and a holding substrate (not shown) are stacked is used.
- the buried oxide film and the holding substrate are bonded to the first surface 30 ⁇ / b> A of the semiconductor substrate 30. After ion implantation, annealing is performed.
- a support substrate (not shown) or another semiconductor substrate or the like is joined to the second surface 30B side (multilayer wiring 40) of the semiconductor substrate 30 and turned upside down. Subsequently, the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the holding substrate, and the first surface 30A of the semiconductor substrate 30 is exposed.
- the above steps can be performed by a technique used in a normal CMOS process such as ion implantation and CVD (Chemical Vapor Deposition).
- the semiconductor substrate 30 is processed from the first surface 30A side by dry etching, for example, to form a ring-shaped or annular separation groove 60.
- the depth of the isolation trench 60 preferably reaches the gate insulating film 32 through the semiconductor substrate 30 from the first surface 30A to the second surface 30B, as indicated by an arrow D60A in FIG. Furthermore, in order to further enhance the insulating effect at the bottom surface 63 of the isolation trench 60, the isolation trench 60 penetrates the semiconductor substrate 30 and the gate insulating film 32 as shown by the arrow D60B in FIG. The insulating film 44 is preferably reached.
- FIG. 5 shows a case where the isolation trench 60 penetrates the semiconductor substrate 30 and the gate insulating film 32.
- the outer surface 61, the inner surface 62 and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30 have, for example, negative fixed charges.
- a film 24 is formed. Two or more types of films may be stacked as the film 24 having a negative fixed charge. Thereby, the function as a hole accumulation layer can be further enhanced.
- the dielectric layer 25 having the outer dielectric layer 25A and the inner dielectric layer 25B is formed as shown in FIG. At this time, the cavity 70 is formed between the outer dielectric layer 25A and the inner dielectric layer 25B in the separation groove 60 by appropriately adjusting the film thickness and film formation conditions of the dielectric layer 25.
- the interlayer insulating film 26 and the upper contact 54 are formed, and the upper contact 54 is connected to the upper end of the through electrode 50.
- the lower transparent electrode 21, the photoelectric conversion film 22, the upper transparent electrode 23, and the protective film 27 are formed.
- an optical member such as a flat film and an on-chip lens (not shown) are disposed.
- the solid-state image sensor 10 shown in FIG. 1 is completed.
- this solid-state imaging device 10 when light enters the photoelectric conversion element 20 via an on-chip lens (not shown), the light passes through the photoelectric conversion element 20, the photodiodes PD1 and PD2 in this order, and passes therethrough. In the process, photoelectric conversion is performed for each color light of green, blue, and red. Hereinafter, the signal acquisition operation for each color will be described.
- the photoelectric conversion element 20 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3 through the through electrode 50. Therefore, electrons in the electron / hole pair generated in the photoelectric conversion element 20 are taken out from the transparent electrode 21 side, transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 50, and transferred to the floating diffusion FD3. Accumulated. At the same time, the charge amount generated in the photoelectric conversion element 20 is modulated into a voltage by the amplifier transistor AMP.
- a reset gate Grst of the reset transistor RST is arranged next to the floating diffusion FD3. Thereby, the electric charge accumulated in the floating diffusion FD3 is reset by the reset transistor RST.
- the photoelectric conversion element 20 is connected not only to the amplifier transistor AMP but also to the floating diffusion FD3 via the through electrode 50, the charge accumulated in the floating diffusion FD3 is easily reset by the reset transistor RST. It becomes possible.
- the photoelectric conversion element 20 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3 via the through electrode 50, and thus the first surface 30A side of the semiconductor substrate 30 is provided.
- the charge generated in the photoelectric conversion element 20 can be satisfactorily transferred to the second surface 30B side of the semiconductor substrate 30 through the through electrode 50, and the characteristics can be improved.
- the through electrode 50 and the semiconductor substrate 30 are separated by the separation groove 60, the outer dielectric layer 25 ⁇ / b> A, the inner dielectric layer 25 ⁇ / b> B, and the cavity 70, it is generated between the through electrode 50 and the semiconductor substrate 30. Capacitance can be reduced, and characteristics such as conversion efficiency can be further improved.
- the reset gate Grst of the reset transistor RST is arranged next to the floating diffusion FD3, the charge accumulated in the floating diffusion FD3 can be easily reset by the reset transistor RST. Therefore, damage to the photoelectric conversion film 22 can be suppressed and reliability can be improved. In addition, resetting in a short time is possible without increasing dark noise.
- FIG. 9 illustrates a cross-sectional configuration of a solid-state imaging element 10A according to the second embodiment of the present disclosure.
- This solid-state imaging device 10A has the same configuration, operation, and effects as those of the first embodiment except that the through electrode 50 is made of a metal or a conductive material. Accordingly, the corresponding components will be described with the same reference numerals.
- this solid-state imaging device 10A is, for example, a so-called longitudinal spectrum in which one photoelectric conversion device 20 and two photodiodes PD1 and PD2 are stacked in the thickness direction of the semiconductor substrate 30.
- the photoelectric conversion element 20 is provided on the first surface (back surface) 30 ⁇ / b> A side of the semiconductor substrate 30.
- the photodiodes PD1 and PD2 are provided in the semiconductor substrate 30 and are stacked in the thickness direction of the semiconductor substrate 30.
- the photoelectric conversion element 20, the photodiodes PD1 and PD2, and the semiconductor substrate 30 are configured in the same manner as in the first embodiment.
- the floating diffusions FD1 to FD3, the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, the reset transistor RST, and the multilayer wiring 40 are configured in the same manner as in the first embodiment.
- the through electrode 50 is provided between the first surface 30A and the second surface 30B of the semiconductor substrate 30 as in the first embodiment.
- the photoelectric conversion element 20 is connected to the gate Gamp of the amplifier transistor AMP and the floating diffusion FD3 through the through electrode 50.
- the charge generated in the photoelectric conversion element 20 on the first surface 30A side of the semiconductor substrate 30 is transferred to the semiconductor substrate 30 via the through electrode 50. It is possible to transfer well to the second surface 30B side and improve the characteristics.
- a floating diffusion FD3 is arranged as in the first embodiment. It is preferable that a reset gate Grst of the reset transistor RST is arranged next to the floating diffusion FD3. As a result, the charge accumulated in the floating diffusion FD3 can be reset by the reset transistor RST.
- the through electrode 50 is made of a metal or a conductive material as described above.
- the resistance value of the through electrode 50 can be further reduced, and the connection resistance between the through electrode 50 and the lower first to third contacts 51 to 53 and the upper contact 54 can be further reduced. Therefore, the electric charge generated in the photoelectric conversion element 20 on the first surface 30A side of the semiconductor substrate 30 is more favorably transferred to the second surface 30B side of the semiconductor substrate 30 via the through electrode 50, and the characteristics are further improved.
- the metal or conductive material constituting the through electrode 50 include aluminum, tungsten, titanium, cobalt, hafnium, and tantalum.
- a separation groove 60 is preferably provided between the through electrode 50 and the semiconductor substrate 30.
- the outer surface 61, the inner surface 62, and the bottom surface 63 of the separation groove 60 are preferably covered with the dielectric layer 25 having an insulating property.
- a cavity 70 is preferably provided between the outer dielectric layer 25A that covers the outer surface 61 of the separation groove and the inner dielectric layer 25B that covers the inner surface 62 of the separation groove 60.
- an impurity region (P + in FIG. 9) is provided in the semiconductor substrate 30 on the outer surface 61 of the separation groove 60, as in the first embodiment. .
- the film 24 having a fixed charge is provided on the outer surface 61, the inner surface 62 and the bottom surface 63 of the separation groove 60, and the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
- a P-type impurity region (P + in FIG. 9) is provided in the semiconductor substrate 30 on the outer surface 61 of the separation groove 60, and a film having a negative fixed charge is used as the film 24 having a fixed charge. It is preferable to provide it. As a result, dark current can be reduced.
- the film 24 having a fixed charge may be a film having a positive fixed charge or a film having a negative fixed charge, as in the first embodiment.
- Examples of the material of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide.
- An yttrium, aluminum nitride film, hafnium oxynitride film, or aluminum oxynitride film is also possible.
- the film 24 having a fixed charge may have a configuration in which two or more kinds of films are stacked, as in the first embodiment. Thereby, for example, in the case of a film having a negative fixed charge, the function as a hole accumulation layer can be further enhanced.
- the material of the dielectric layer 25 is not particularly limited, but includes, for example, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film, as in the first embodiment.
- the lower first to third contacts 51 to 53 and the upper contact 54 are made of a doped silicon material such as PDAS, or aluminum, tungsten, titanium, cobalt, hafnium, tantalum, as in the first embodiment. It is comprised with metal materials, such as.
- This solid-state imaging device 10A can be manufactured as follows, for example.
- a p-type well 31 is formed as a first conductivity type well in the semiconductor substrate 30 by the process shown in FIG.
- Two photodiodes PD1 and PD2 of conductivity type (for example, N type) are formed.
- a P + region is formed in the vicinity of the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
- the through-electrode 50 and the separation groove 60 are formed from the first surface 30 ⁇ / b> A to the second surface 30 ⁇ / b> B through the region where the through-electrode 50 and the separation groove 60 are to be formed, similarly to the first embodiment.
- Impurity regions (P + regions) are formed.
- the through electrode 50 is made of a metal or a conductive material, the high concentration impurity regions (P ++ regions) at the upper end portion and the lower end portion of the through electrode 50 are unnecessary.
- N + regions to be the floating diffusions FD1 to FD3 are formed on the second surface 30B of the semiconductor substrate 30 by the process shown in FIG.
- the gate wiring 33 including the gates of the type transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST is formed.
- the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST are formed.
- the multilayer wiring 40 including the lower first to third contacts 51 to 53, the wiring layers 41 to 43 including the connection portion 41A, and the insulating film 44 is formed on the second surface 30B of the semiconductor substrate 30.
- an SOI substrate is used as in the first embodiment. After ion implantation, annealing is performed.
- a support substrate (not shown) or another semiconductor substrate or the like is joined to the second surface 30B side (multilayer wiring 40) of the semiconductor substrate 30 and turned upside down. Subsequently, the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the holding substrate, and the first surface 30A of the semiconductor substrate 30 is exposed.
- the above steps can be performed by a technique used in a normal CMOS process such as ion implantation and CVD.
- the semiconductor substrate 30 is processed from the first surface 30 ⁇ / b> A side by dry etching, for example, to form an annular or ring-shaped separation groove 60 penetrating the semiconductor substrate 30.
- an insulating film 80 is formed on the outer surface 61 and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30 as shown in FIG.
- a material of the insulating film 80 it is possible to use a SiO film or a SiN film formed by TEOS or ALD.
- the insulating film 80 is retracted by dry etching or the like.
- the metal material film 50 ⁇ / b> A is embedded in the separation groove 60.
- the metal material film 50A is embedded, as shown in FIG. 15, the metal material film 50A is retreated or flattened by dry etching or CMP (Chemical Mechanical Polishing) to form the through electrode 50.
- CMP Chemical Mechanical Polishing
- the insulating film 80 is peeled off as shown in FIG.
- the outer surface 61, the inner surface 62 and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30 have negative fixed charges, for example.
- a film 24 is formed.
- the film 24 having a negative fixed charge two or more kinds of films may be laminated. Thereby, the function as a hole accumulation layer can be further enhanced.
- the dielectric layer 25 is formed as shown in FIG. At this time, the cavity 70 is formed in the separation groove 60 by appropriately adjusting the film thickness and film formation conditions of the dielectric layer 25. Note that the surface of the dielectric layer 25 may be planarized by CMP or the like.
- the interlayer insulating film 26 and the upper contact 54 are formed as shown in FIG. 18, and the upper contact 54 is connected to the upper end of the through electrode 50.
- the lower transparent electrode 21, the photoelectric conversion film 22, the upper transparent electrode 23, and the protective film 27 are formed.
- an optical member such as a flat film and an on-chip lens (not shown) are disposed.
- the solid-state imaging device 10A shown in FIG. 9 is completed.
- the solid-state imaging device 10A when light is incident on the photoelectric conversion element 20 via an on-chip lens (not shown), the light passes through the photoelectric conversion element 20 and the photodiodes PD1 and PD2 in this order, and passes therethrough. In the process, photoelectric conversion is performed for each color light of green, blue, and red, and signals of each color are acquired in the same manner as in the first embodiment.
- the through electrode 50 is made of a metal or a conductive material, the resistance value of the through electrode 50 is reduced and the characteristics are further improved.
- the through electrode 50 is made of a metal or a conductive material, it is possible to reduce the resistance value of the through electrode 50 and further improve the characteristics.
- FIG. 19 illustrates a cross-sectional configuration of a solid-state imaging element 10B according to the first modification.
- a thermal oxide film 34 is provided between the dielectric layer 25 and the through electrode 50 and between the dielectric layer 25 and the semiconductor substrate 30.
- the thermal oxide film 34 can be formed of a silicon oxide film obtained by thermally oxidizing silicon of the semiconductor substrate 30, silicon oxynitride, a high dielectric insulating film, or the like. Except for this, the solid-state imaging device 10B has the same configuration, operation, and effect as the first embodiment.
- the solid-state imaging device 10B can be manufactured in the same manner as in the first embodiment except that the thermal oxide film 34 is provided on the outer side surface 61 and the inner side surface 62 of the separation groove 60.
- FIG. 20 illustrates a cross-sectional configuration of a solid-state imaging element 10C according to the third embodiment of the present disclosure.
- the separation groove 60 is filled with an insulating dielectric layer 25, thereby reducing the capacitance generated between the through electrode 50 and the semiconductor substrate 30, and characteristics such as conversion efficiency. Is further improved.
- the solid-state imaging device 10C has the same configuration, operation, and effect as in the first embodiment.
- the solid-state imaging device 10C can be manufactured as follows, for example.
- 21 and 22 show the manufacturing method of the solid-state imaging device 10C in the order of steps. In addition, the process which overlaps with 1st Embodiment is demonstrated with reference to FIG. 3 thru
- a p-type well 31 is formed as a first conductivity type well in the semiconductor substrate 30 by the process shown in FIG.
- Two photodiodes PD1 and PD2 of conductivity type (for example, N type) are formed.
- a P + region is formed in the vicinity of the first surface 30 ⁇ / b> A of the semiconductor substrate 30.
- the through-electrode 50 and the separation groove 60 are formed through the first surface 30A to the second surface 30B of the semiconductor substrate 30 through the process shown in FIG.
- Impurity regions (P + regions) to be formed are formed.
- high-concentration impurity regions (P ++ regions) are formed in regions where the upper and lower end portions of the through electrode 50 are to be formed.
- the gate insulating film 32 After forming N + regions to be the floating diffusions FD1 to FD3 on the second surface 30B of the semiconductor substrate 30 by the process shown in FIG. 3, the gate insulating film 32, A gate wiring 33 including the gates of the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST is formed. Thereby, the vertical transistor Tr1, the transfer transistor Tr2, the amplifier transistor AMP, and the reset transistor RST are formed. Further, the multilayer wiring 40 including the lower first to third contacts 51 to 53, the wiring layers 41 to 43 including the connection portion 41A, and the insulating film 44 is formed on the second surface 30B of the semiconductor substrate 30.
- an SOI substrate is used as in the first embodiment. After ion implantation, annealing is performed.
- a supporting substrate (not shown) or another semiconductor substrate is bonded to the second surface 30B side (multilayer wiring 40) of the semiconductor substrate 30 by the process shown in FIG. And flip upside down. Subsequently, the semiconductor substrate 30 is separated from the buried oxide film of the SOI substrate and the holding substrate, and the first surface 30A of the semiconductor substrate 30 is exposed.
- the above steps can be performed by a technique used in a normal CMOS process such as ion implantation and CVD.
- the semiconductor substrate 30 is processed from the first surface 30A side by dry etching, for example, by the process shown in FIG.
- the separation groove 60, the outer surface 61, the inner surface 62 and the bottom surface 63 of the separation groove 60, and the first surface 30 ⁇ / b> A of the semiconductor substrate 30 are formed by the process shown in FIG. 6, as in the first embodiment. Then, for example, a film 24 having a negative fixed charge is formed. As the film 24 having a negative fixed charge, two or more kinds of films may be laminated. Thereby, the function as a hole accumulation layer can be further enhanced.
- the separation groove 60 is filled with the dielectric layer 25 as shown in FIG.
- the interlayer insulating film 26 and the upper contact 54 are formed, and the upper contact 54 is connected to the upper end of the through electrode 50.
- a lower transparent electrode 21 a photoelectric conversion film 22, an upper transparent electrode 23, and a protective film 27 are formed.
- an optical member such as a flat film and an on-chip lens (not shown) are disposed.
- the solid-state imaging device 10C shown in FIG. 20 is completed.
- FIG. 23 illustrates a cross-sectional configuration of a solid-state imaging element 10D according to the fourth embodiment of the present disclosure.
- the isolation groove 60 is filled with an insulating dielectric layer 25, thereby reducing the capacitance generated between the through electrode 50 and the semiconductor substrate 30, and characteristics such as conversion efficiency. Is further improved.
- the solid-state imaging element 10D has the same configuration, operation, and effect as the second embodiment.
- This solid-state imaging device 10D can be manufactured in the same manner as in the second embodiment except that the separation groove 60 is embedded in the dielectric layer 25 as shown in FIG.
- FIG. 25 illustrates a cross-sectional configuration of a solid-state imaging element 10E according to Modification 2.
- a thermal oxide film 34 similar to that of the first modification is provided between the dielectric layer 25 and the through electrode 50 and between the dielectric layer 25 and the semiconductor substrate 30.
- the thermal oxide film 34 can be formed of a silicon oxide film obtained by thermally oxidizing silicon of the semiconductor substrate 30, silicon oxynitride, a high dielectric insulating film, or the like.
- the solid-state imaging device 10E has the same configuration, operation, and effect as in the third embodiment.
- the solid-state imaging device 10E can be manufactured in the same manner as in the third embodiment except that the thermal oxide film 34 is provided on the outer side surface 61 and the inner side surface 62 of the separation groove 60.
- FIG. 26 illustrates the overall configuration of a solid-state imaging device including the solid-state imaging elements 10 and 10A to 10E described in the above embodiment as the pixel unit 110.
- the solid-state imaging device 1 is a CMOS image sensor, for example, and includes a pixel unit 110 as an imaging pixel region, and a circuit unit including a row scanning unit 131, a horizontal selection unit 133, a column scanning unit 134, and a system control unit 132, for example. 130.
- the circuit unit 130 may be provided in a peripheral region of the pixel unit 110 or may be provided so as to be stacked with the pixel unit 110 (in a region facing the pixel unit 110).
- the pixel unit 110 includes, for example, a plurality of pixels PXL that are two-dimensionally arranged in a matrix.
- a pixel drive line Lread (specifically, a row selection line and a reset control line) is wired for each pixel row, and a vertical signal line Lsig is wired for each pixel column.
- the pixel drive line Lread transmits a drive signal for reading a signal from the pixel.
- One end of the pixel drive line Lread is connected to an output end corresponding to each row of the row scanning unit 131.
- the row scanning unit 131 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel PXL of the pixel unit 110, for example, in units of rows.
- a signal output from each pixel PXL in the pixel row selected and scanned by the row scanning unit 131 is supplied to the horizontal selection unit 133 through each of the vertical signal lines Lsig.
- the horizontal selection unit 133 is configured by an amplifier, a horizontal selection switch, and the like provided for each vertical signal line Lsig.
- the column scanning unit 134 includes a shift register, an address decoder, and the like, and drives the horizontal selection switches in the horizontal selection unit 133 in order while scanning. By the selective scanning by the column scanning unit 134, the signal of each pixel PXL transmitted through each of the vertical signal lines Lsig is sequentially transmitted to the horizontal signal line 135 and output through the horizontal signal line 135.
- the system control unit 132 receives a clock given from the outside, data for instructing an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1.
- the system control unit 132 further includes a timing generator that generates various timing signals.
- the row scanning unit 131, the horizontal selection unit 133, the column scanning unit 134, and the like are based on the various timing signals generated by the timing generator. Drive control is performed.
- FIG. 27 shows a schematic configuration of the electronic apparatus 2 (camera) as an example.
- the electronic device 2 is, for example, a video camera capable of shooting a still image or a moving image.
- the electronic device 2 is a solid-state imaging device 1, an optical system (imaging lens) 310, a shutter device 311, the solid-state imaging device 1 and the shutter device 311.
- a drive unit 313 including the circuit unit 130), a signal processing unit 312, a user interface 314, and a monitor 315.
- the optical system 310 guides image light (incident light) from a subject to the pixel unit 110 of the solid-state imaging device 1.
- the optical system 310 may be composed of a plurality of optical lenses.
- the shutter device 311 controls the light irradiation period and the light shielding period for the solid-state imaging device 1.
- the drive unit 313 controls the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 311.
- the signal processing unit 312 performs various types of signal processing on the signal output from the solid-state imaging device 1.
- the video signal Dout after the signal processing is output to the monitor 315.
- the video signal Dout may be stored in a storage medium such as a memory.
- the user interface 314 can specify a shooting scene (dynamic range specification, wavelength (terahertz, visible, infrared, ultraviolet, X-ray, etc.) specification, and the like (input signal from the user interface 314). Is sent to the drive unit 313, and based on this, the solid-state imaging device 1 performs desired imaging.
- a shooting scene dynamic range specification, wavelength (terahertz, visible, infrared, ultraviolet, X-ray, etc.) specification, and the like
- the pixel circuit of the solid-state imaging device 10 may have a three-transistor configuration including a total of three transistors including a transfer transistor, an amplifier transistor, and a reset transistor, or may have a four-transistor configuration in which a selection transistor is added.
- the backside illumination type solid-state imaging device 10 has been described as an example, but the present disclosure can be applied to a frontside illumination type.
- solid-state imaging device 10 and the solid-state imaging device 1 of the above-described embodiment may not include all the components described in the above-described embodiments, and conversely may include other components. .
- this technique can also take the following structures.
- At least one photoelectric conversion element provided on the first surface side of the semiconductor substrate; A through electrode connected to the at least one photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; An amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate; The at least one photoelectric conversion element is connected to the gate of the amplifier transistor and the floating diffusion through the through electrode.
- a reset transistor including a reset gate on the second surface of the semiconductor substrate; The solid-state imaging device according to (1), wherein the reset gate is provided next to the floating diffusion.
- the at least one photoelectric conversion element includes a plurality of photoelectric conversion elements, The through electrode is provided for each of the plurality of photoelectric conversion elements.
- the through electrode is made of a semiconductor into which an N-type or P-type impurity is implanted, The solid-state imaging device according to (4), wherein an impurity region having the same conductivity type as that of the through electrode is provided in the semiconductor substrate on an outer surface of the separation groove.
- the through electrode is made of a metal or a conductive material.
- the outer surface of the separation groove is covered with an outer dielectric layer
- the inner surface of the separation groove is covered with an inner dielectric layer
- the solid-state imaging device according to any one of (4) to (6) wherein a cavity is provided between the outer dielectric layer and the inner dielectric layer.
- the solid-state imaging device according to any one of (4) to (8) wherein a film having a fixed charge is provided on an outer surface, an inner surface, and a bottom surface of the separation groove and on the first surface of the semiconductor substrate. .
- a photoelectric conversion element provided on the first surface side of the semiconductor substrate;
- a through electrode connected to the photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate;
- a separation groove provided between the through electrode and the semiconductor substrate;
- a solid-state imaging device comprising: a dielectric layer filling the separation groove and having an insulating property.
- a photoelectric conversion element provided on the first surface side of the semiconductor substrate; A through electrode connected to the photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; A separation groove provided between the through electrode and the semiconductor substrate; An outer dielectric layer covering the outer surface of the separation groove; An inner dielectric layer covering the inner surface of the separation groove; A solid-state imaging device comprising: a cavity provided between the outer dielectric layer and the inner dielectric layer.
- a solid-state image sensor is At least one photoelectric conversion element provided on the first surface side of the semiconductor substrate; A through electrode connected to the at least one photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; An amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate; The electronic device wherein the at least one photoelectric conversion element is connected to the gate of the amplifier transistor and the floating diffusion through the through electrode.
- a solid-state image sensor is A photoelectric conversion element provided on the first surface side of the semiconductor substrate; A through electrode connected to the photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; A separation groove provided between the through electrode and the semiconductor substrate; An electronic device comprising: a dielectric layer filling the separation groove and having an insulating property.
- a solid-state image sensor is A photoelectric conversion element provided on the first surface side of the semiconductor substrate; A through electrode connected to the photoelectric conversion element and provided between the first surface and the second surface of the semiconductor substrate; A separation groove provided between the through electrode and the semiconductor substrate; An outer dielectric layer covering the outer surface of the separation groove; An inner dielectric layer covering the inner surface of the separation groove; An electronic device comprising: a cavity provided between the outer dielectric layer and the inner dielectric layer.
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Abstract
Description
1.第1の実施の形態(固体撮像素子;貫通電極を半導体により構成し、貫通電極の周囲の分離溝内に空洞を設ける例)
2.第2の実施の形態(固体撮像素子;貫通電極を金属により構成し、貫通電極の周囲の分離溝内に空洞を設ける例)
3.変形例1(分離溝の外側面に熱酸化膜を設ける例)
4.第3の実施の形態(固体撮像素子;貫通電極を半導体により構成し、貫通電極の周囲の分離溝を誘電体層で充填する例)
5.第4の実施の形態(固体撮像素子;貫通電極を金属により構成し、貫通電極の周囲の分離溝を誘電体層で充填する例)
6.変形例2(分離溝の外側面に熱酸化膜を設ける例)
7.固体撮像装置の全体構成例
8.適用例(電子機器の例)
図1は、本開示の第1の実施の形態に係る固体撮像素子10の断面構成を表したものである。この固体撮像素子10は、例えばデジタルスチルカメラ,ビデオカメラ等の電子機器に用いられるCMOSイメージセンサなどの固体撮像装置(後述)において撮像画素領域としての画素部を構成するものである。
光電変換素子20へ入射した光のうち、まず、緑色光が、光電変換素子20において選択的に検出(吸収)され、光電変換される。
続いて、光電変換素子20を透過した光のうち、青色光はフォトダイオードPD1、赤色光はフォトダイオードPD2において、それぞれ順に吸収され、光電変換される。フォトダイオードPD1では、入射した青色光に対応した電子がフォトダイオードPD1のN領域に蓄積され、蓄積された電子は、縦型トランジスタTr1によりフローティングディフュージョンFD1へと転送される。同様に、フォトダイオードPD2では、入射した赤色光に対応した電子がフォトダイオードPD2のN領域に蓄積され、蓄積された電子は、転送トランジスタTr2によりフローティングディフュージョンFD2へと転送される。
図9は、本開示の第2の実施の形態に係る固体撮像素子10Aの断面構成を表したものである。この固体撮像素子10Aは、貫通電極50を金属または導電性材料により構成したことを除いては、上記第1の実施の形態と同様の構成、作用および効果を有している。よって、対応する構成要素には同一の符号を付して説明する。
図19は、変形例1に係る固体撮像素子10Bの断面構成を表したものである。この固体撮像素子10Bは、誘電体層25と貫通電極50との間、および誘電体層25と半導体基板30との間に、熱酸化膜34を設けたものである。熱酸化膜34は、半導体基板30のシリコンを熱酸化させた酸化シリコン膜、酸化窒化シリコン、高誘電体絶縁膜などにより構成することが可能である。このことを除いては、この固体撮像素子10Bは、上記第1の実施の形態と同様の構成、作用および効果を有している。また、この固体撮像素子10Bは、分離溝60の外側面61および内側面62に熱酸化膜34を設けることを除いては、第1の実施の形態と同様にして製造することができる。
図20は、本開示の第3の実施の形態に係る固体撮像素子10Cの断面構成を表したものである。この固体撮像素子10Cは、分離溝60を、絶縁性を有する誘電体層25で充填することにより、貫通電極50と半導体基板30との間に生じる静電容量を低減し、変換効率などの特性を更に向上させるようにしたものである。このことを除いては、この固体撮像素子10Cは、上記第1の実施の形態と同様の構成、作用および効果を有している。
図23は、本開示の第4の実施の形態に係る固体撮像素子10Dの断面構成を表したものである。この固体撮像素子10Dは、分離溝60を、絶縁性を有する誘電体層25で充填することにより、貫通電極50と半導体基板30との間に生じる静電容量を低減し、変換効率などの特性を更に向上させるようにしたものである。このことを除いては、この固体撮像素子10Dは、上記第2の実施の形態と同様の構成、作用および効果を有している。
図25は、変形例2に係る固体撮像素子10Eの断面構成を表したものである。この固体撮像素子10Eは、誘電体層25と貫通電極50との間、および誘電体層25と半導体基板30との間に、変形例1と同様の熱酸化膜34を設けたものである。熱酸化膜34は、変形例1と同様に、半導体基板30のシリコンを熱酸化させた酸化シリコン膜、酸化窒化シリコン、高誘電体絶縁膜などにより構成することが可能である。このことを除いては、この固体撮像素子10Eは、上記第3の実施の形態と同様の構成、作用および効果を有している。また、この固体撮像素子10Eは、分離溝60の外側面61および内側面62に熱酸化膜34を設けることを除いては、第3の実施の形態と同様にして製造することができる。
図26は、上記実施の形態において説明した固体撮像素子10,10A~10Eを画素部110として備えた固体撮像装置の全体構成を表したものである。この固体撮像装置1は、例えばCMOSイメージセンサであり、撮像画素領域としての画素部110を有すると共に、例えば行走査部131、水平選択部133、列走査部134およびシステム制御部132からなる回路部130を有している。回路部130は、画素部110の周辺領域に設けられていてもよいし、画素部110と積層されて(画素部110に対向する領域に)設けられていてもよい。
上記実施の形態等の固体撮像装置は、例えばデジタルスチルカメラやビデオカメラ等のカメラシステムや、撮像機能を有する携帯電話など、撮像機能を備えたあらゆるタイプの電子機器に適用することができる。図27に、その一例として、電子機器2(カメラ)の概略構成を示す。この電子機器2は、例えば静止画または動画を撮影可能なビデオカメラであり、例えば、固体撮像装置1と、光学系(撮像レンズ)310と、シャッタ装置311と、固体撮像装置1およびシャッタ装置311を駆動する駆動部313(上記回路部130を含む)と、信号処理部312と、ユーザインターフェイス314と、モニタ315とを有する。
(1)
半導体基板の第1面側に設けられた少なくとも一つの光電変換素子と、
前記少なくとも一つの光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記半導体基板の前記第2面に設けられたアンプトランジスタおよびフローティングディフュージョンと
を有し、
前記少なくとも一つの光電変換素子は、前記貫通電極を介して、前記アンプトランジスタのゲートと前記フローティングディフュージョンとに接続されている
固体撮像素子。
(2)
前記半導体基板の前記第2面に、リセットゲートを含むリセットトランジスタを有し、
前記リセットゲートは、前記フローティングディフュージョンの隣に設けられている
前記(1)記載の固体撮像素子。
(3)
前記少なくとも一つの光電変換素子は、複数の光電変換素子を含み、
前記貫通電極は、前記複数の光電変換素子の各々ごとに設けられている
前記(1)または(2)記載の固体撮像素子。
(4)
前記貫通電極は、前記半導体基板を貫通すると共に、分離溝により前記半導体基板と分離されている
前記(1)ないし(3)のいずれかに記載の固体撮像素子。
(5)
前記貫通電極は、N型またはP型の不純物が注入された半導体により構成され、
前記分離溝の外側面の前記半導体基板内に、前記貫通電極と同じ導電型の不純物領域が設けられている
前記(4)記載の固体撮像素子。
(6)
前記貫通電極は、金属または導電性材料により構成されている
前記(4)記載の固体撮像素子。
(7)
前記分離溝は、絶縁性を有する誘電体層により充填されている
前記(4)ないし(6)のいずれかに記載の固体撮像素子。
(8)
前記分離溝の外側面は、外側誘電体層により被覆され、
前記分離溝の内側面は、内側誘電体層により被覆され、
前記外側誘電体層と前記内側誘電体層との間に、空洞が設けられている
前記(4)ないし(6)のいずれかに記載の固体撮像素子。
(9)
前記分離溝の外側面、内側面および底面と、前記半導体基板の前記第1面に、固定電荷を有する膜が設けられている
前記(4)ないし(8)のいずれかに記載の固体撮像素子。
(10)
前記半導体基板内に設けられた1または複数のフォトダイオードを有する
前記(1)ないし(9)のいずれかに記載の固体撮像素子。
(11)
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝を充填し、絶縁性を有する誘電体層と
を備えた固体撮像素子。
(12)
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝の外側面を被覆する外側誘電体層と、
前記分離溝の内側面を被覆する内側誘電体層と、
前記外側誘電体層と前記内側誘電体層との間に設けられた空洞と
を備えた固体撮像素子。
(13)
固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた少なくとも一つの光電変換素子と、
前記少なくとも一つの光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記半導体基板の前記第2面に設けられたアンプトランジスタおよびフローティングディフュージョンと
を有し、
前記少なくとも一つの光電変換素子は、前記貫通電極を介して、前記アンプトランジスタのゲートと前記フローティングディフュージョンとに接続されている
電子機器。
(14)
固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝を充填し、絶縁性を有する誘電体層と
を備えた電子機器。
(15)
固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝の外側面を被覆する外側誘電体層と、
前記分離溝の内側面を被覆する内側誘電体層と、
前記外側誘電体層と前記内側誘電体層との間に設けられた空洞と
を備えた電子機器。
Claims (15)
- 半導体基板の第1面側に設けられた少なくとも一つの光電変換素子と、
前記少なくとも一つの光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記半導体基板の前記第2面に設けられたアンプトランジスタおよびフローティングディフュージョンと
を有し、
前記少なくとも一つの光電変換素子は、前記貫通電極を介して、前記アンプトランジスタのゲートと前記フローティングディフュージョンとに接続されている
固体撮像素子。 - 前記半導体基板の前記第2面に、リセットゲートを含むリセットトランジスタを有し、
前記リセットゲートは、前記フローティングディフュージョンの隣に設けられている
請求項1記載の固体撮像素子。 - 前記少なくとも一つの光電変換素子は、複数の光電変換素子を含み、
前記貫通電極は、前記複数の光電変換素子の各々ごとに設けられている
請求項1記載の固体撮像素子。 - 前記貫通電極は、前記半導体基板を貫通すると共に、分離溝により前記半導体基板と分離されている
請求項1記載の固体撮像素子。 - 前記貫通電極は、N型またはP型の不純物が注入された半導体により構成され、
前記分離溝の外側面の前記半導体基板内に、前記貫通電極と同じ導電型の不純物領域が設けられている
請求項4記載の固体撮像素子。 - 前記貫通電極は、金属または導電性材料により構成されている
請求項4記載の固体撮像素子。 - 前記分離溝は、絶縁性を有する誘電体層により充填されている
請求項4記載の固体撮像素子。 - 前記分離溝の外側面は、外側誘電体層により被覆され、
前記分離溝の内側面は、内側誘電体層により被覆され、
前記外側誘電体層と前記内側誘電体層との間に、空洞が設けられている
請求項4記載の固体撮像素子。 - 前記分離溝の外側面、内側面および底面と、前記半導体基板の前記第1面に、固定電荷を有する膜が設けられている
請求項4記載の固体撮像素子。 - 前記半導体基板内に設けられた1または複数のフォトダイオードを有する
請求項1記載の固体撮像素子。 - 半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝を充填し、絶縁性を有する誘電体層と
を備えた固体撮像素子。 - 半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝の外側面を被覆する外側誘電体層と、
前記分離溝の内側面を被覆する内側誘電体層と、
前記外側誘電体層と前記内側誘電体層との間に設けられた空洞と
を備えた固体撮像素子。 - 固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた少なくとも一つの光電変換素子と、
前記少なくとも一つの光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記半導体基板の前記第2面に設けられたアンプトランジスタおよびフローティングディフュージョンと
を有し、
前記少なくとも一つの光電変換素子は、前記貫通電極を介して、前記アンプトランジスタのゲートと前記フローティングディフュージョンとに接続されている
電子機器。 - 固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝を充填し、絶縁性を有する誘電体層と
を備えた電子機器。 - 固体撮像素子を有し、
前記固体撮像素子は、
半導体基板の第1面側に設けられた光電変換素子と、
前記光電変換素子に接続され、前記半導体基板の前記第1面と第2面との間に設けられた貫通電極と、
前記貫通電極と前記半導体基板との間に設けられた分離溝と、
前記分離溝の外側面を被覆する外側誘電体層と、
前記分離溝の内側面を被覆する内側誘電体層と、
前記外側誘電体層と前記内側誘電体層との間に設けられた空洞と
を備えた電子機器。
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US11094730B2 (en) | 2021-08-17 |
CN105409002B (zh) | 2019-03-08 |
KR102349538B1 (ko) | 2022-01-12 |
KR102482051B1 (ko) | 2022-12-28 |
US20200176501A1 (en) | 2020-06-04 |
KR102576328B1 (ko) | 2023-09-08 |
US20240096922A1 (en) | 2024-03-21 |
KR20230003400A (ko) | 2023-01-05 |
CN110047856A (zh) | 2019-07-23 |
CN110047856B (zh) | 2022-11-18 |
US20180006073A1 (en) | 2018-01-04 |
CN116705814A (zh) | 2023-09-05 |
JP2015038931A (ja) | 2015-02-26 |
US11862655B2 (en) | 2024-01-02 |
CN110047857B (zh) | 2022-11-18 |
JP6079502B2 (ja) | 2017-02-15 |
CN116705815A (zh) | 2023-09-05 |
CN110047857A (zh) | 2019-07-23 |
KR20220005597A (ko) | 2022-01-13 |
US10529765B2 (en) | 2020-01-07 |
KR20230132617A (ko) | 2023-09-15 |
CN110010549A (zh) | 2019-07-12 |
US20160204156A1 (en) | 2016-07-14 |
US9698188B2 (en) | 2017-07-04 |
CN105409002A (zh) | 2016-03-16 |
CN110010549B (zh) | 2023-06-20 |
US20210408098A1 (en) | 2021-12-30 |
KR20160045054A (ko) | 2016-04-26 |
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