WO2014192229A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014192229A1
WO2014192229A1 PCT/JP2014/002407 JP2014002407W WO2014192229A1 WO 2014192229 A1 WO2014192229 A1 WO 2014192229A1 JP 2014002407 W JP2014002407 W JP 2014002407W WO 2014192229 A1 WO2014192229 A1 WO 2014192229A1
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Prior art keywords
layer
buffer layer
buffer
sublayer
layers
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Ceased
Application number
PCT/JP2014/002407
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English (en)
French (fr)
Japanese (ja)
Inventor
洋志 鹿内
憲 佐藤
博一 後藤
篠宮　勝
慶太郎 土屋
和徳 萩本
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Application filed by Sanken Electric Co Ltd, Shin Etsu Handotai Co Ltd filed Critical Sanken Electric Co Ltd
Priority to CN201480031054.2A priority Critical patent/CN105247665B/zh
Priority to US14/891,942 priority patent/US9401420B2/en
Publication of WO2014192229A1 publication Critical patent/WO2014192229A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having a nitride semiconductor layer.
  • the nitride semiconductor layer is generally formed on an inexpensive silicon substrate or sapphire substrate.
  • the lattice constants of these substrates and the nitride semiconductor layers are greatly different, and the thermal expansion coefficients are also different. Therefore, large strain energy is generated in the nitride semiconductor layer formed by epitaxial growth on the substrate. As a result, the nitride semiconductor layer is likely to generate cracks and crystal quality.
  • a semiconductor wafer having a buffer layer of Patent Document 1 is shown in FIG.
  • the buffer layer 3 is provided between the silicon substrate 2 and the active layer 4, and the buffer layer 3 is formed on the first multilayer structure buffer region 5 and the first multilayer structure buffer region 5.
  • the first multilayer structure buffer region 5 and the second multilayer structure buffer region 5 ′ are composed of a sub multilayer structure buffer region 6 and a first single layer structure made of GaN and thinner than the second single layer structure buffer region 8. It has a multilayer structure in which the buffer region 7 is repeatedly stacked.
  • the sub-multilayer structure buffer region 6 has a multilayer structure in which a first layer made of AlN and a second layer made of GaN are repeatedly stacked.
  • a first layer is formed of a nitride semiconductor containing aluminum at a first ratio, and a second layer, a first single-layer structure buffer region 7, and a second single-layer structure buffer are formed. It is disclosed that the warpage of the semiconductor wafer is reduced by making the proportion of aluminum in the region 8 (including zero) smaller than the first proportion.
  • the present inventors have found that there are the following problems. That is, when the buffer layer is composed of a multilayer buffer in which AlN / GaN of a certain thickness is repeated, and the GaN layer of the multilayer buffer layer is thickened, cracks occur in the buffer layer and the active layer, and thermal expansion with the substrate There is a problem that the warp cannot be adjusted by the coefficient difference. Conversely, when the GaN layer constituting the buffer layer is thinned, there is a problem that the leakage current in the buffer layer increases. Further, when the buffer layer has an AlN / GaN superlattice structure, there is a problem of warping as the total thickness of the buffer layer is increased.
  • the present invention has been made in view of the above problems, and provides a semiconductor device capable of suppressing leakage and suppressing the leakage and improving the flatness of the upper surface of the active layer while reducing the stress applied to the buffer layer. With the goal.
  • the present invention provides a silicon-based substrate, a first layer provided on the silicon-based substrate, containing an Al composition, and a second layer containing less Al than the first layer.
  • First buffer layers alternately stacked, a third layer provided on the first buffer layer and containing an Al composition, and a fourth layer containing less Al than the third layer.
  • a second buffer layer in which layers are alternately stacked, a fifth layer provided on the second buffer layer and containing an Al composition, and a sixth layer containing less Al than the fifth layer.
  • a third buffer layer alternately stacked with the second buffer layer, and as a whole, the second buffer layer contains more Al than the first buffer layer and the third buffer layer.
  • a semiconductor device is provided.
  • the central layer of the buffer layer contains more Al than the upper layer of the buffer layer (third buffer layer) and the lower layer of the buffer layer (first buffer layer).
  • lattice relaxation occurs more in the center of the buffer layer, and the stress applied to the buffer layer can be reduced.
  • the leakage current can be reduced by making the central layer (second buffer layer) of the buffer layer a multilayer structure including a layer containing Al composition (third layer) and increasing the aluminum composition of the entire buffer layer. Can do.
  • the central layer (second buffer layer) of the buffer layer a multilayer structure including a layer containing the Al composition (third layer)
  • the flatness of the upper surface of the buffer layer can be improved, Thereby, the flatness of the upper surface of the active layer can be improved.
  • the semiconductor device further includes an active layer provided on the third buffer layer, and the first layer includes a first sublayer including an Al composition, and Al content from the first sublayer.
  • the second sub-layer is formed repeatedly, and the fifth layer includes a third sub-layer containing an Al composition and a fourth sub-layer containing less Al than the third sub-layer.
  • the second sub-layer and the fourth sub-layer have a thickness less than a critical film thickness, and the second layer includes the first sub-layer and the first sub-layer.
  • the sublayer has less Al content and is thicker than the second sublayer, and the sixth layer has less Al content than the fourth sublayer and is thicker than the fourth sublayer.
  • the fourth layer is thicker than the second sublayer and the fourth sublayer, and the second layer and the fourth sublayer. Thinner than the layer of the are those having a critical film thickness or a thickness of the fourth layer, it is preferable that the second transposition than the layer and the sixth layer of those often.
  • the fourth layer included in the central layer of the buffer layer is changed from the second sub layer included in the lower layer of the buffer layer and the fourth sub layer included in the upper layer of the buffer layer.
  • lattice relaxation is likely to occur in the fourth layer included in the central layer of the buffer layer, thereby increasing the width of stress control and forming the entire buffer layer thicker. can do.
  • the second sublayer, the second layer, the fourth layer, the fourth sublayer, and the sixth layer may be GaN.
  • the above materials can be suitably used.
  • the first sublayer, the third layer, and the third sublayer may be AlN.
  • the above materials can be suitably used.
  • the content of Al in the plurality of the third layers is reduced as it is closer to the third buffer layer.
  • the difference in the Al composition ratio between the third layer and the fourth layer adjacent to each other is made smaller as it is closer to the active layer.
  • the effect of improving the crystallinity can be made larger than the stress relaxation effect.
  • the upper surface side of the second buffer layer with respect to the third layer disposed at the center of the second buffer layer is preferable to reduce the Al content as compared with the third layer disposed on the lower surface side.
  • the difference in Al composition ratio between the third layer and the fourth layer adjacent to each other is reduced at the central portion, so that the stress relaxation effect is exerted on the lower side and the upper side.
  • the effect of improving the crystallinity can be made larger than the stress relaxation effect at the central portion.
  • the present invention it is possible to provide a semiconductor device capable of reducing the stress applied to the buffer layer, suppressing leakage, and improving the flatness of the upper surface of the active layer.
  • the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
  • the upper surface of the active layer is formed by unevenness on the upper surface of the buffer layer. The unevenness is transferred to the surface of the active layer, causing a problem in the flatness of the upper surface of the active layer, resulting in variations in electrical characteristics of the semiconductor device and deterioration of characteristics.
  • the buffer layer is thickened by inserting a single-layer buffer region made of thick GaN at the center of the buffer layer, the buffer layer warps due to the difference in thermal expansion coefficient between the buffer layer and the substrate in the film forming apparatus.
  • the stress of the substrate and the layer on the substrate is not sufficiently adjusted, and warping and cracking may occur.
  • the present inventors have intensively studied a semiconductor device that can improve the flatness of the upper surface of the active layer while reducing the stress applied to the buffer layer.
  • the central layer (second buffer layer) of the buffer layer contains more Al than the upper layer (third buffer layer) and the lower layer (first buffer layer) of the buffer layer.
  • the central layer of the buffer layer (second buffer layer) a multilayer structure including a layer containing Al composition (third layer)
  • stress applied to the buffer layer can be reduced and leakage current can be reduced.
  • the present inventors have found that the flatness of the upper surface of the active layer can be improved.
  • FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor device of the present invention.
  • a semiconductor device 11 of the present invention shown in FIG. 1 includes a silicon substrate 12, a buffer layer 13 provided on the silicon substrate 12, an active layer 14 provided on the buffer layer 13, and an active layer 14.
  • the first electrode 24, the second electrode 26, and the control electrode 28 are provided.
  • the silicon-based substrate 12 is a substrate made of, for example, Si or SiC.
  • the buffer layer 13 includes a first buffer layer 15, a second buffer layer 20 provided on the first buffer layer 15, and a third buffer layer 15 a provided on the second buffer layer 20.
  • the first buffer layer 15 is formed by alternately laminating a first layer 16 containing an Al composition and a second layer 17 containing less Al than the first layer 16.
  • the second buffer layer 20 is formed by alternately laminating third layers 18a containing an Al composition and fourth layers 18b containing less Al than the third layers 18a.
  • the third buffer layer 15a is formed by alternately stacking fifth layers 16a containing an Al composition and sixth layers 17a containing less Al than the fifth layer 16a.
  • the active layer 14 further includes a channel layer 141 and a barrier layer 142 provided on the channel layer 141.
  • the first electrode 24 and the second electrode 26 are arranged so that current flows from the first electrode 24 to the second electrode 26 through the two-dimensional electron gas 22 formed in the channel layer 141. ing.
  • the current flowing between the first electrode 24 and the second electrode 26 can be controlled by the potential applied to the control electrode 28.
  • the second buffer layer 20, which is the central layer of the buffer layer 13, as a whole contains more Al than the first buffer layer 15 and the third buffer layer 15 a.
  • large lattice relaxation occurs at the center of the buffer layer 13, and the stress applied to the buffer layer 13 can be reduced.
  • the second buffer layer 20, which is the central layer of the buffer layer 13 has a multilayer structure including a layer containing the Al composition (the third layer 18 a), and the aluminum composition of the entire buffer layer 13 is increased, so that The current can be reduced.
  • the flatness of the upper surface of the buffer layer is improved by forming the second buffer layer 20, which is the central layer of the buffer layer 13, into a multilayer structure including a layer containing the Al composition (third layer 18 a). Thereby, the flatness of the upper surface of the active layer can be improved.
  • the first layer 16 includes a first sublayer 16 ′ containing an Al composition and a second sublayer 16 ′′ containing less Al than the first sublayer 16 ′. Can be formed repeatedly.
  • the fifth layer 16a includes a third sub-layer 16a ′ containing an Al composition and a fourth sub-layer 16a containing less Al than the third sub-layer. "Can be repeatedly formed.
  • the second sublayer 16 ′′ and the fourth sublayer 16a ′′ have a thickness less than the critical film thickness (if the film thickness is greater than this, misfit dislocations can be reliably generated). be able to.
  • the fourth layer 18b is preferably 3.5 nm to 200 nm. Within this range, misfit dislocations can surely occur.
  • the fourth layer 18b is more preferably 5 nm to 50 nm. Within this range, misfit dislocations can be generated more reliably.
  • each layer of the buffer layer 13 has the above-described film thickness relationship, lattice relaxation (misfit dislocation) is likely to occur in the fourth layer included in the central layer of the buffer layer.
  • the width of the stress control is further widened, and the entire buffer layer can be formed thicker.
  • the second sublayer 16 ′′, the second layer 17, the fourth layer 18b, the fourth sublayer 16a ′′, and the sixth layer 17a are, for example, GaN.
  • the first sublayer 16 ′, the third layer 18a, and the third sublayer 16a ′ are, for example, AlN.
  • the content of Al in the third layer 18a constituting the second buffer layer 20 is reduced as it is closer to the third buffer layer 15a, that is, closer to the active layer 14.
  • the difference in the Al composition ratio between the third layer 18a and the fourth layer 18b adjacent to each other is closer to the third buffer layer 15a, that is, the active layer 14
  • the upper surface side and the lower surface of the second buffer layer with respect to the third layer disposed in the central portion of the second buffer layer 20 are preferable to reduce the Al content as compared with the third layer disposed on the side.
  • the difference in Al composition ratio between the third layer 18a and the fourth layer 18b adjacent to each other is reduced in the central portion, so that the stress relaxation is performed on the lower side and the upper side. The effect can be increased, and the effect of improving the crystallinity can be increased more than the stress relaxation effect in the central portion.
  • the first buffer layer 15 constituting the buffer layer 13 is formed on the silicon substrate 12. Specifically, the first layer formed by alternately growing the first sublayer 16 ′ made of AlN and the second sublayer 16 ′′ made of GaN by MOVPE (metal organic chemical vapor deposition). 16 and the second layer 17 made of GaN are alternately grown to form the first buffer layer 15.
  • the film thickness of the first sublayer 16 ′ is, for example, 3 to 7 nm
  • the film thickness of the second sublayer 16 ′′ is, for example, 2 to 5 nm
  • the film thickness of the second layer 17 is, for example, 100 It is ⁇ 500 nm, preferably 100 to 300 nm.
  • the number of the first layers 16 and the second layers 17 that are repeatedly formed can be, for example, 4 to 7, and the first sublayer 16 ′ and the second sublayer 16 ′′ that are repeatedly formed The number can be, for example, 1-15.
  • the second buffer layer 20 constituting the buffer layer 13 is formed on the first buffer layer 15.
  • the second buffer layer 20 is formed by alternately growing the third layer 18a made of AlN and the fourth layer 18b made of GaN by the MOVPE method.
  • the film thickness of the third layer 18a is, for example, 3 to 7 nm
  • the film thickness of the fourth layer 18b is, for example, 3.5 to 200 nm.
  • the number of the third layers 18a and the fourth layers 18b that are repeatedly formed can be 10 to 100, for example.
  • a third buffer layer 15 a constituting the buffer layer 13 is formed on the second buffer layer 20.
  • the fifth layer 16a formed by alternately growing the third sublayer 16a ′ made of AlN and the fourth sublayer 16a ′′ made of GaN by the MOVPE method, and the first layer made of GaN.
  • Six layers 17a are alternately grown to form a third buffer layer 15a.
  • the film thickness of the third sublayer 16a ′ is, for example, 3 to 7 nm
  • the film thickness of the fourth sublayer 16a ′′ is, for example, 2 to 5 nm
  • the film thickness of the sixth layer 17a is, for example, 100 It is ⁇ 500 nm, preferably 100 to 300 nm.
  • the number of the fifth layers 16a and the sixth layers 17a formed repeatedly can be, for example, 4 to 7, and the number of the third sublayer 16a ′ and the fourth sublayer 16a ′′ formed repeatedly can be increased.
  • the number can be, for example, 1-15. Note that the crystallinity is improved when the number of the third sublayer 16a ′ and the number of the fourth sublayer 16a ′′ is smaller than the number of the first sublayer 16 ′ and the second sublayer 16 ′′. Can do.
  • the active layer 14 is formed on the buffer layer 13. Specifically, a channel layer 141 made of GaN and a barrier layer 142 made of AlGaN are sequentially grown on the buffer layer 13 by MOVPE.
  • the film thickness of the channel layer 141 is, for example, 1000 to 4000 nm
  • the film thickness of the barrier layer 142 is, for example, 10 to 50 nm.
  • the first electrode 24, the second electrode 26, and the control electrode 28 are formed on the active layer 14.
  • the first electrode 24 and the second electrode 26 can be formed of, for example, a Ti / Al laminated film
  • the control electrode 28 can be formed of, for example, a lower layer film made of a metal oxide such as SiO or SiN, and Ni, Au, or Mo. , Pt, or other metal layer.
  • the semiconductor device shown in FIG. 1 can be obtained by the manufacturing method described above.
  • Example 1 A semiconductor device as shown in FIG. 1 was manufactured by the manufacturing method described above.
  • the first layer 16 has a stacked structure as shown in FIG. 2, and the fifth layer 16a has a stacked structure as shown in FIG.
  • the first sublayer 16 ′, the third layer 18a, and the third sublayer 16a ′ are made of AlN, and the second sublayer 16 ′′, the second layer 17, the fourth layer 18b, The fourth sublayer 16a ′′ is made of GaN.
  • Example 1 A semiconductor device was manufactured in the same manner as in Example 1. However, the second buffer layer 20 has a single layer structure made of GaN.
  • the semiconductor device of Example 1 can reduce the stress applied to the buffer layer, suppress leakage, and improve the flatness of the upper surface of the active layer.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

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  • Condensed Matter Physics & Semiconductors (AREA)
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PCT/JP2014/002407 2013-05-31 2014-05-02 半導体装置 Ceased WO2014192229A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201480031054.2A CN105247665B (zh) 2013-05-31 2014-05-02 半导体装置
US14/891,942 US9401420B2 (en) 2013-05-31 2014-05-02 Semiconductor device

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JP2013-116030 2013-05-31
JP2013116030A JP6029538B2 (ja) 2013-05-31 2013-05-31 半導体装置

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WO (1) WO2014192229A1 (enExample)

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JP6615075B2 (ja) 2016-09-15 2019-12-04 サンケン電気株式会社 半導体デバイス用基板、半導体デバイス、及び、半導体デバイス用基板の製造方法
CN112820773B (zh) * 2019-11-18 2024-05-07 联华电子股份有限公司 一种高电子迁移率晶体管
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